| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.18 | 95.58 | 94.06 | 95.46 | 94.88 | 97.53 | 99.58 |
| T399 | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.232982621 | Jul 12 07:25:12 PM PDT 24 | Jul 12 08:46:46 PM PDT 24 | 30434979144 ps | ||
| T2763 | /workspace/coverage/cover_reg_top/42.xbar_random.2049668078 | Jul 12 07:30:40 PM PDT 24 | Jul 12 07:31:16 PM PDT 24 | 347363725 ps | ||
| T2764 | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.563175732 | Jul 12 07:37:50 PM PDT 24 | Jul 12 07:42:00 PM PDT 24 | 15495019496 ps | ||
| T2765 | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.2875101846 | Jul 12 07:33:17 PM PDT 24 | Jul 12 07:36:03 PM PDT 24 | 542056957 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.1743394693 | Jul 12 07:26:11 PM PDT 24 | Jul 12 07:28:04 PM PDT 24 | 10084739273 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/87.xbar_stress_all.308350991 | Jul 12 07:37:45 PM PDT 24 | Jul 12 07:39:11 PM PDT 24 | 2005908522 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.4024639913 | Jul 12 07:28:10 PM PDT 24 | Jul 12 07:32:54 PM PDT 24 | 2678629841 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.284556083 | Jul 12 07:33:58 PM PDT 24 | Jul 12 07:38:10 PM PDT 24 | 13994500246 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.1974600311 | Jul 12 07:32:30 PM PDT 24 | Jul 12 07:34:00 PM PDT 24 | 7363459948 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.73293548 | Jul 12 07:39:22 PM PDT 24 | Jul 12 07:41:01 PM PDT 24 | 5306891870 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.134576151 | Jul 12 07:26:03 PM PDT 24 | Jul 12 08:42:14 PM PDT 24 | 29319619574 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/89.xbar_smoke.326532127 | Jul 12 07:37:49 PM PDT 24 | Jul 12 07:37:58 PM PDT 24 | 41698772 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.1484619320 | Jul 12 07:36:00 PM PDT 24 | Jul 12 07:37:02 PM PDT 24 | 248231205 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.3354480156 | Jul 12 07:32:18 PM PDT 24 | Jul 12 07:46:56 PM PDT 24 | 48673678368 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.174639058 | Jul 12 07:36:26 PM PDT 24 | Jul 12 07:40:44 PM PDT 24 | 3079186350 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/99.xbar_random.2221756060 | Jul 12 07:39:34 PM PDT 24 | Jul 12 07:40:14 PM PDT 24 | 911231184 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/6.xbar_error_random.277003383 | Jul 12 07:24:18 PM PDT 24 | Jul 12 07:24:55 PM PDT 24 | 492042675 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.2148765841 | Jul 12 07:29:01 PM PDT 24 | Jul 12 07:30:56 PM PDT 24 | 219724247 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.162682291 | Jul 12 07:33:42 PM PDT 24 | Jul 12 07:54:38 PM PDT 24 | 105651208915 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.2173823044 | Jul 12 07:38:24 PM PDT 24 | Jul 12 07:40:06 PM PDT 24 | 5576983018 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.844414663 | Jul 12 07:34:39 PM PDT 24 | Jul 12 07:34:50 PM PDT 24 | 140783259 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/19.xbar_smoke.1207305549 | Jul 12 07:26:37 PM PDT 24 | Jul 12 07:26:46 PM PDT 24 | 44078766 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.1304376214 | Jul 12 07:33:07 PM PDT 24 | Jul 12 07:41:18 PM PDT 24 | 28799348637 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.563510929 | Jul 12 07:31:00 PM PDT 24 | Jul 12 07:31:41 PM PDT 24 | 281397841 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/34.xbar_same_source.2656746785 | Jul 12 07:29:11 PM PDT 24 | Jul 12 07:29:48 PM PDT 24 | 396744145 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.247762838 | Jul 12 07:31:27 PM PDT 24 | Jul 12 07:32:06 PM PDT 24 | 333839249 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.934766029 | Jul 12 07:28:42 PM PDT 24 | Jul 12 08:07:10 PM PDT 24 | 128472056715 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.2980953954 | Jul 12 07:36:03 PM PDT 24 | Jul 12 07:52:18 PM PDT 24 | 54765265873 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.3186731655 | Jul 12 07:33:20 PM PDT 24 | Jul 12 07:34:13 PM PDT 24 | 487900614 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.3911430216 | Jul 12 07:35:38 PM PDT 24 | Jul 12 07:36:16 PM PDT 24 | 306270719 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.2237713321 | Jul 12 07:31:47 PM PDT 24 | Jul 12 07:40:02 PM PDT 24 | 6868305078 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1931301049 | Jul 12 07:26:04 PM PDT 24 | Jul 12 07:27:38 PM PDT 24 | 5004286316 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.2420073363 | Jul 12 07:34:43 PM PDT 24 | Jul 12 07:37:44 PM PDT 24 | 17813711450 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/83.xbar_smoke.1770712488 | Jul 12 07:36:54 PM PDT 24 | Jul 12 07:37:05 PM PDT 24 | 225509544 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.2907927303 | Jul 12 07:32:44 PM PDT 24 | Jul 12 07:33:49 PM PDT 24 | 168598113 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/88.xbar_smoke.68032404 | Jul 12 07:37:38 PM PDT 24 | Jul 12 07:37:46 PM PDT 24 | 50180886 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.3897034216 | Jul 12 07:28:44 PM PDT 24 | Jul 12 07:29:40 PM PDT 24 | 777819049 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.749968815 | Jul 12 07:23:11 PM PDT 24 | Jul 12 07:23:50 PM PDT 24 | 987834696 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.4123832670 | Jul 12 07:37:29 PM PDT 24 | Jul 12 07:39:40 PM PDT 24 | 7414786847 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.3781155721 | Jul 12 07:27:15 PM PDT 24 | Jul 12 07:27:30 PM PDT 24 | 227280868 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/81.xbar_error_random.4268028566 | Jul 12 07:36:29 PM PDT 24 | Jul 12 07:37:28 PM PDT 24 | 1561450124 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2219776766 | Jul 12 07:23:09 PM PDT 24 | Jul 12 07:23:36 PM PDT 24 | 568434003 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.2560209635 | Jul 12 07:30:25 PM PDT 24 | Jul 12 07:32:15 PM PDT 24 | 9039105946 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.4030619110 | Jul 12 07:23:19 PM PDT 24 | Jul 12 08:07:57 PM PDT 24 | 131197538520 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.2404596323 | Jul 12 07:31:00 PM PDT 24 | Jul 12 07:33:00 PM PDT 24 | 9720180787 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.236524531 | Jul 12 07:32:21 PM PDT 24 | Jul 12 07:34:00 PM PDT 24 | 8859636831 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.2956396886 | Jul 12 07:24:35 PM PDT 24 | Jul 12 07:26:13 PM PDT 24 | 9163956494 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.1128483586 | Jul 12 07:36:44 PM PDT 24 | Jul 12 07:45:50 PM PDT 24 | 7805430637 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/38.xbar_error_random.1344287722 | Jul 12 07:30:07 PM PDT 24 | Jul 12 07:31:36 PM PDT 24 | 2221160421 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.243307180 | Jul 12 07:28:57 PM PDT 24 | Jul 12 07:32:33 PM PDT 24 | 13144259322 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.3310316761 | Jul 12 07:33:03 PM PDT 24 | Jul 12 07:34:27 PM PDT 24 | 4489569640 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.1579152584 | Jul 12 07:32:40 PM PDT 24 | Jul 12 07:53:03 PM PDT 24 | 107420978328 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.3137588647 | Jul 12 07:30:29 PM PDT 24 | Jul 12 07:42:59 PM PDT 24 | 67411423824 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/94.xbar_random.4285091258 | Jul 12 07:38:37 PM PDT 24 | Jul 12 07:39:18 PM PDT 24 | 422028782 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.1434316790 | Jul 12 07:38:48 PM PDT 24 | Jul 12 07:39:09 PM PDT 24 | 193001597 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.1632899510 | Jul 12 07:38:48 PM PDT 24 | Jul 12 07:40:39 PM PDT 24 | 6228295202 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/28.chip_tl_errors.4115155086 | Jul 12 07:28:08 PM PDT 24 | Jul 12 07:32:13 PM PDT 24 | 3368988412 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1879133021 | Jul 12 07:37:55 PM PDT 24 | Jul 12 07:46:53 PM PDT 24 | 4189466114 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/74.xbar_error_random.3768306794 | Jul 12 07:35:49 PM PDT 24 | Jul 12 07:36:23 PM PDT 24 | 319000726 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/22.xbar_smoke.1927179485 | Jul 12 07:27:16 PM PDT 24 | Jul 12 07:27:26 PM PDT 24 | 42238863 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/81.xbar_random.2149543548 | Jul 12 07:36:29 PM PDT 24 | Jul 12 07:37:12 PM PDT 24 | 416366931 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.4201385400 | Jul 12 07:23:46 PM PDT 24 | Jul 12 07:26:20 PM PDT 24 | 608636769 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.3623652094 | Jul 12 07:29:26 PM PDT 24 | Jul 12 07:30:30 PM PDT 24 | 1267584498 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.3126943194 | Jul 12 07:31:39 PM PDT 24 | Jul 12 07:33:02 PM PDT 24 | 4376989708 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/42.xbar_error_random.3360422184 | Jul 12 07:30:39 PM PDT 24 | Jul 12 07:31:06 PM PDT 24 | 575659918 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/10.xbar_smoke.3122288523 | Jul 12 07:25:07 PM PDT 24 | Jul 12 07:25:19 PM PDT 24 | 201202197 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.3501783952 | Jul 12 07:27:48 PM PDT 24 | Jul 12 07:47:42 PM PDT 24 | 95835067729 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.2812964518 | Jul 12 07:26:01 PM PDT 24 | Jul 12 07:42:32 PM PDT 24 | 90911662262 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/46.xbar_random.3053467859 | Jul 12 07:31:14 PM PDT 24 | Jul 12 07:32:39 PM PDT 24 | 2282857705 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.2172522323 | Jul 12 07:29:45 PM PDT 24 | Jul 12 07:48:41 PM PDT 24 | 100047065564 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.2175276109 | Jul 12 07:28:43 PM PDT 24 | Jul 12 07:29:43 PM PDT 24 | 1204942526 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.2452776137 | Jul 12 07:37:17 PM PDT 24 | Jul 12 07:52:08 PM PDT 24 | 44705321901 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.746763953 | Jul 12 07:32:00 PM PDT 24 | Jul 12 07:35:13 PM PDT 24 | 3921358825 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.86379066 | Jul 12 07:23:57 PM PDT 24 | Jul 12 07:24:13 PM PDT 24 | 286312920 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/47.xbar_random.2167958354 | Jul 12 07:31:27 PM PDT 24 | Jul 12 07:31:48 PM PDT 24 | 174250164 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.1032228010 | Jul 12 07:33:04 PM PDT 24 | Jul 12 07:39:05 PM PDT 24 | 3055823911 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.4177360387 | Jul 12 07:28:03 PM PDT 24 | Jul 12 07:28:44 PM PDT 24 | 330118495 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.1889992682 | Jul 12 07:36:18 PM PDT 24 | Jul 12 07:36:27 PM PDT 24 | 42956044 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.619155342 | Jul 12 07:25:10 PM PDT 24 | Jul 12 07:37:18 PM PDT 24 | 13853536713 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.3063203746 | Jul 12 07:29:06 PM PDT 24 | Jul 12 07:31:21 PM PDT 24 | 3141563452 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.4245333420 | Jul 12 07:34:58 PM PDT 24 | Jul 12 07:36:17 PM PDT 24 | 987839208 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/46.xbar_smoke.4004951013 | Jul 12 07:31:15 PM PDT 24 | Jul 12 07:31:29 PM PDT 24 | 168400076 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/90.xbar_random.4056632482 | Jul 12 07:38:05 PM PDT 24 | Jul 12 07:38:58 PM PDT 24 | 1174076929 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.598755 | Jul 12 07:34:06 PM PDT 24 | Jul 12 07:40:50 PM PDT 24 | 3861519489 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/8.xbar_smoke.3726278536 | Jul 12 07:24:54 PM PDT 24 | Jul 12 07:25:05 PM PDT 24 | 131231463 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/86.xbar_smoke.1401420260 | Jul 12 07:37:17 PM PDT 24 | Jul 12 07:37:27 PM PDT 24 | 218646294 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.1153831937 | Jul 12 07:26:53 PM PDT 24 | Jul 12 07:30:36 PM PDT 24 | 2490580132 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/93.xbar_stress_all.3506148645 | Jul 12 07:38:36 PM PDT 24 | Jul 12 07:42:45 PM PDT 24 | 2578778869 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.3740076325 | Jul 12 07:29:11 PM PDT 24 | Jul 12 07:30:36 PM PDT 24 | 5003065525 ps | ||
| T584 | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.153860324 | Jul 12 07:31:13 PM PDT 24 | Jul 12 07:33:49 PM PDT 24 | 1998996224 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/5.xbar_smoke.248357655 | Jul 12 07:24:04 PM PDT 24 | Jul 12 07:24:11 PM PDT 24 | 46568260 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.3558666227 | Jul 12 07:33:23 PM PDT 24 | Jul 12 07:34:02 PM PDT 24 | 498927510 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.1384549798 | Jul 12 07:24:05 PM PDT 24 | Jul 12 07:24:53 PM PDT 24 | 532871810 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/63.xbar_random.4039251150 | Jul 12 07:33:54 PM PDT 24 | Jul 12 07:34:14 PM PDT 24 | 383061549 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.494996313 | Jul 12 07:30:28 PM PDT 24 | Jul 12 07:46:45 PM PDT 24 | 88703793719 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.1851201363 | Jul 12 07:31:36 PM PDT 24 | Jul 12 07:32:42 PM PDT 24 | 696747353 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3292930307 | Jul 12 07:25:42 PM PDT 24 | Jul 12 07:27:14 PM PDT 24 | 300607588 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1929678481 | Jul 12 07:37:16 PM PDT 24 | Jul 12 07:37:27 PM PDT 24 | 177461996 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.1996174046 | Jul 12 07:39:25 PM PDT 24 | Jul 12 07:54:43 PM PDT 24 | 7861188346 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.239697952 | Jul 12 07:29:12 PM PDT 24 | Jul 12 07:31:13 PM PDT 24 | 6777074178 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.3124639466 | Jul 12 07:35:40 PM PDT 24 | Jul 12 07:39:19 PM PDT 24 | 3006720989 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.2280616679 | Jul 12 07:26:01 PM PDT 24 | Jul 12 07:42:10 PM PDT 24 | 53771722769 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/31.xbar_smoke.2804330902 | Jul 12 07:28:42 PM PDT 24 | Jul 12 07:28:58 PM PDT 24 | 189410838 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/13.xbar_random.1062675114 | Jul 12 07:25:40 PM PDT 24 | Jul 12 07:26:14 PM PDT 24 | 798952820 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.4015651219 | Jul 12 07:36:16 PM PDT 24 | Jul 12 07:36:27 PM PDT 24 | 39593397 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.2124018504 | Jul 12 07:34:08 PM PDT 24 | Jul 12 07:35:27 PM PDT 24 | 6845648531 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.4122101884 | Jul 12 07:39:02 PM PDT 24 | Jul 12 07:40:25 PM PDT 24 | 4407172043 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.921765491 | Jul 12 07:35:29 PM PDT 24 | Jul 12 07:38:35 PM PDT 24 | 16597129643 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.415051973 | Jul 12 07:35:24 PM PDT 24 | Jul 12 07:35:42 PM PDT 24 | 98268821 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.661808578 | Jul 12 07:30:59 PM PDT 24 | Jul 12 07:43:51 PM PDT 24 | 68249209008 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/24.xbar_stress_all.4083242420 | Jul 12 07:27:45 PM PDT 24 | Jul 12 07:36:20 PM PDT 24 | 14453320526 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.3710372710 | Jul 12 07:38:03 PM PDT 24 | Jul 12 07:38:37 PM PDT 24 | 183165650 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/51.xbar_error_random.503879096 | Jul 12 07:32:06 PM PDT 24 | Jul 12 07:32:42 PM PDT 24 | 456357372 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.3354606236 | Jul 12 07:34:41 PM PDT 24 | Jul 12 07:46:42 PM PDT 24 | 38144526777 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.1285288241 | Jul 12 07:27:01 PM PDT 24 | Jul 12 07:27:46 PM PDT 24 | 464035631 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.3997001430 | Jul 12 07:24:08 PM PDT 24 | Jul 12 07:50:59 PM PDT 24 | 95071453871 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/65.xbar_smoke.3030325586 | Jul 12 07:34:08 PM PDT 24 | Jul 12 07:34:17 PM PDT 24 | 42265577 ps | ||
| T2878 | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.3882763027 | Jul 12 07:32:22 PM PDT 24 | Jul 12 07:32:34 PM PDT 24 | 43393092 ps | ||
| T2879 | /workspace/coverage/cover_reg_top/2.xbar_stress_all.3469696063 | Jul 12 07:23:38 PM PDT 24 | Jul 12 07:31:31 PM PDT 24 | 12123865041 ps | ||
| T2880 | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.826084083 | Jul 12 07:30:44 PM PDT 24 | Jul 12 07:31:02 PM PDT 24 | 61994366 ps | ||
| T2881 | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.312332212 | Jul 12 07:25:55 PM PDT 24 | Jul 12 07:27:37 PM PDT 24 | 229616698 ps | ||
| T2882 | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.764936610 | Jul 12 07:30:06 PM PDT 24 | Jul 12 07:31:13 PM PDT 24 | 4916889440 ps | ||
| T2883 | /workspace/coverage/cover_reg_top/66.xbar_error_random.1634445364 | Jul 12 07:34:24 PM PDT 24 | Jul 12 07:35:54 PM PDT 24 | 2372041344 ps | ||
| T2884 | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.2415065419 | Jul 12 07:30:27 PM PDT 24 | Jul 12 07:33:10 PM PDT 24 | 1599913508 ps | ||
| T2885 | /workspace/coverage/cover_reg_top/50.xbar_same_source.4091048941 | Jul 12 07:32:02 PM PDT 24 | Jul 12 07:32:40 PM PDT 24 | 430632698 ps | ||
| T2886 | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.17613243 | Jul 12 07:32:31 PM PDT 24 | Jul 12 07:33:03 PM PDT 24 | 266948477 ps | ||
| T2887 | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.1104599436 | Jul 12 07:35:53 PM PDT 24 | Jul 12 07:37:32 PM PDT 24 | 8392342495 ps | ||
| T2888 | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.1651977768 | Jul 12 07:35:14 PM PDT 24 | Jul 12 07:36:49 PM PDT 24 | 8147425542 ps | ||
| T2889 | /workspace/coverage/cover_reg_top/7.chip_csr_rw.4267438826 | Jul 12 07:24:55 PM PDT 24 | Jul 12 07:29:00 PM PDT 24 | 3836816150 ps | ||
| T2890 | /workspace/coverage/cover_reg_top/61.xbar_error_random.1883843 | Jul 12 07:33:36 PM PDT 24 | Jul 12 07:34:20 PM PDT 24 | 1272244548 ps | ||
| T2891 | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.3325294047 | Jul 12 07:35:48 PM PDT 24 | Jul 12 07:36:17 PM PDT 24 | 264269596 ps | ||
| T2892 | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.90608906 | Jul 12 07:38:01 PM PDT 24 | Jul 12 07:38:12 PM PDT 24 | 59569508 ps | ||
| T2893 | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.119803101 | Jul 12 07:27:32 PM PDT 24 | Jul 12 07:48:56 PM PDT 24 | 102600575298 ps | ||
| T2894 | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.2483689054 | Jul 12 07:32:46 PM PDT 24 | Jul 12 07:41:46 PM PDT 24 | 31204517555 ps | ||
| T2895 | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.885960815 | Jul 12 07:38:31 PM PDT 24 | Jul 12 07:39:38 PM PDT 24 | 5759652010 ps | ||
| T2896 | /workspace/coverage/cover_reg_top/21.xbar_random.1073582436 | Jul 12 07:27:08 PM PDT 24 | Jul 12 07:28:04 PM PDT 24 | 580717550 ps | ||
| T2897 | /workspace/coverage/cover_reg_top/54.xbar_random.4107352546 | Jul 12 07:32:29 PM PDT 24 | Jul 12 07:33:25 PM PDT 24 | 560555782 ps | ||
| T2898 | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.1656154306 | Jul 12 07:31:14 PM PDT 24 | Jul 12 08:10:24 PM PDT 24 | 135759822304 ps | ||
| T2899 | /workspace/coverage/cover_reg_top/22.xbar_error_random.1382380244 | Jul 12 07:27:18 PM PDT 24 | Jul 12 07:27:46 PM PDT 24 | 680764665 ps | ||
| T2900 | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.3275834983 | Jul 12 07:25:53 PM PDT 24 | Jul 12 07:28:29 PM PDT 24 | 4632148079 ps | ||
| T2901 | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.663097447 | Jul 12 07:23:48 PM PDT 24 | Jul 12 07:40:41 PM PDT 24 | 55817178625 ps | ||
| T2902 | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.4010104703 | Jul 12 07:31:27 PM PDT 24 | Jul 12 07:31:36 PM PDT 24 | 14983734 ps | ||
| T38 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.471062255 | Jul 12 08:16:51 PM PDT 24 | Jul 12 08:21:42 PM PDT 24 | 4281297124 ps | ||
| T39 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.267002418 | Jul 12 08:16:46 PM PDT 24 | Jul 12 08:21:55 PM PDT 24 | 5409166960 ps | ||
| T40 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3343712073 | Jul 12 08:16:59 PM PDT 24 | Jul 12 08:21:22 PM PDT 24 | 5014866168 ps | ||
| T194 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1393735202 | Jul 12 08:17:03 PM PDT 24 | Jul 12 08:22:33 PM PDT 24 | 4351169236 ps | ||
| T195 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.951468340 | Jul 12 08:17:19 PM PDT 24 | Jul 12 08:23:27 PM PDT 24 | 4526240454 ps | ||
| T196 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2895609645 | Jul 12 08:16:53 PM PDT 24 | Jul 12 08:22:07 PM PDT 24 | 5392556090 ps | ||
| T197 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.4208654570 | Jul 12 08:16:56 PM PDT 24 | Jul 12 08:22:23 PM PDT 24 | 4334104908 ps | ||
| T198 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1600151890 | Jul 12 08:16:52 PM PDT 24 | Jul 12 08:22:12 PM PDT 24 | 5763991608 ps | ||
| T199 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1764504416 | Jul 12 08:16:59 PM PDT 24 | Jul 12 08:22:54 PM PDT 24 | 6128850880 ps | ||
| T200 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.60541837 | Jul 12 08:16:47 PM PDT 24 | Jul 12 08:21:21 PM PDT 24 | 5333348844 ps |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.1634210053 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4219088630 ps |
| CPU time | 467.16 seconds |
| Started | Jul 12 08:22:00 PM PDT 24 |
| Finished | Jul 12 08:29:48 PM PDT 24 |
| Peak memory | 649932 kb |
| Host | smart-efa9c5da-e885-44cd-a0ee-b23dc7e8b346 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1634210053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.1634210053 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.1210072667 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 12833582307 ps |
| CPU time | 1610.52 seconds |
| Started | Jul 12 07:52:58 PM PDT 24 |
| Finished | Jul 12 08:19:50 PM PDT 24 |
| Peak memory | 608404 kb |
| Host | smart-b8d21da6-f20a-46d4-b2e3-c191de7fcdf7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210072667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.1210072667 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.142761164 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 14205363728 ps |
| CPU time | 571.39 seconds |
| Started | Jul 12 07:39:33 PM PDT 24 |
| Finished | Jul 12 07:49:06 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-231b9f7f-f652-4eb9-bf38-60fa51672763 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142761164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.142761164 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.2992458296 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 6204367832 ps |
| CPU time | 1118.82 seconds |
| Started | Jul 12 08:12:02 PM PDT 24 |
| Finished | Jul 12 08:30:42 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-9111ff91-0d4f-40ac-81f1-ae626adda077 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992458296 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.2992458296 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.471062255 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4281297124 ps |
| CPU time | 290.31 seconds |
| Started | Jul 12 08:16:51 PM PDT 24 |
| Finished | Jul 12 08:21:42 PM PDT 24 |
| Peak memory | 643384 kb |
| Host | smart-41bc57fe-64bf-4e8f-8f83-b2fc69ccde3a |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471062255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 6.chip_padctrl_attributes.471062255 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.710900658 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 124356720870 ps |
| CPU time | 2411.63 seconds |
| Started | Jul 12 07:32:30 PM PDT 24 |
| Finished | Jul 12 08:12:50 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-c30bb629-2955-4f73-a8ef-ddcb9ea5bf1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710900658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_d evice_slow_rsp.710900658 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.2236866118 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 33083222941 ps |
| CPU time | 4333.8 seconds |
| Started | Jul 12 07:24:55 PM PDT 24 |
| Finished | Jul 12 08:37:13 PM PDT 24 |
| Peak memory | 593156 kb |
| Host | smart-4c0ea79f-cebb-46e2-945e-beed70d1400a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236866118 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.2236866118 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2628405547 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 7864462060 ps |
| CPU time | 1386.51 seconds |
| Started | Jul 12 08:10:23 PM PDT 24 |
| Finished | Jul 12 08:33:30 PM PDT 24 |
| Peak memory | 608688 kb |
| Host | smart-fce788a1-32b6-4067-a9f2-a0ac424ffd92 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26284 05547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.2628405547 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2636604056 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 25098563120 ps |
| CPU time | 5848.71 seconds |
| Started | Jul 12 07:55:05 PM PDT 24 |
| Finished | Jul 12 09:32:35 PM PDT 24 |
| Peak memory | 610704 kb |
| Host | smart-90e0ec0a-ba2e-46c7-ab57-449b5742aed1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2636604056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2636604056 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1360448263 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 118110096868 ps |
| CPU time | 2299.52 seconds |
| Started | Jul 12 07:31:00 PM PDT 24 |
| Finished | Jul 12 08:09:29 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-e57e72e8-94c3-480b-b6a8-155cc01d9da5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360448263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.1360448263 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.2979036745 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 94378920358 ps |
| CPU time | 1903.67 seconds |
| Started | Jul 12 07:27:59 PM PDT 24 |
| Finished | Jul 12 07:59:50 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-56b56295-e7cf-4e27-923c-92f274274b41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979036745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_ device_slow_rsp.2979036745 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2069852657 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 125195456529 ps |
| CPU time | 2302.9 seconds |
| Started | Jul 12 07:25:16 PM PDT 24 |
| Finished | Jul 12 08:03:43 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-bb822114-10be-4828-806c-ef7f7adc79d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069852657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.2069852657 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.132614749 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 49232220300 ps |
| CPU time | 5124 seconds |
| Started | Jul 12 08:05:40 PM PDT 24 |
| Finished | Jul 12 09:31:07 PM PDT 24 |
| Peak memory | 616124 kb |
| Host | smart-2265c2e2-4765-48b4-a311-7de7e4fc7efb |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132614749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_prod.132614749 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.3104938033 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 82861952393 ps |
| CPU time | 1678.95 seconds |
| Started | Jul 12 07:33:30 PM PDT 24 |
| Finished | Jul 12 08:01:32 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-e21bd86d-d1b6-4e97-8fff-1531dc8b11ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104938033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_ device_slow_rsp.3104938033 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.2194073495 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 2844588088 ps |
| CPU time | 261.82 seconds |
| Started | Jul 12 08:07:47 PM PDT 24 |
| Finished | Jul 12 08:12:10 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-99554675-5dc3-4fc6-880e-5bc8ae465d88 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194073495 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.2194073495 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.886032772 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3282825040 ps |
| CPU time | 332.17 seconds |
| Started | Jul 12 07:53:13 PM PDT 24 |
| Finished | Jul 12 07:58:46 PM PDT 24 |
| Peak memory | 609620 kb |
| Host | smart-db09ed0d-3657-4038-b3b4-e2808cc4817d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8860 32772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.886032772 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.216276808 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 5289179016 ps |
| CPU time | 1099.38 seconds |
| Started | Jul 12 08:13:33 PM PDT 24 |
| Finished | Jul 12 08:31:54 PM PDT 24 |
| Peak memory | 610584 kb |
| Host | smart-04e37ead-bdef-44c9-acb3-ed70718be503 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216276808 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_20.216276808 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.537534659 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 3133868650 ps |
| CPU time | 223.06 seconds |
| Started | Jul 12 07:48:42 PM PDT 24 |
| Finished | Jul 12 07:52:26 PM PDT 24 |
| Peak memory | 609668 kb |
| Host | smart-130430f2-ef3f-4f8e-9009-944fd2dd5e1b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=537534659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.537534659 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.4152201949 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4481141300 ps |
| CPU time | 537.19 seconds |
| Started | Jul 12 08:05:34 PM PDT 24 |
| Finished | Jul 12 08:14:32 PM PDT 24 |
| Peak memory | 610412 kb |
| Host | smart-fa36b58a-c60d-45b4-a189-3de1e53d16ac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152201949 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_gpio.4152201949 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1962265774 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5803257584 ps |
| CPU time | 1171.86 seconds |
| Started | Jul 12 07:59:22 PM PDT 24 |
| Finished | Jul 12 08:18:54 PM PDT 24 |
| Peak memory | 611428 kb |
| Host | smart-253e9516-7794-4ffb-acde-079e43e827db |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1962265774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.1962265774 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.1615370892 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 4668810335 ps |
| CPU time | 271.78 seconds |
| Started | Jul 12 07:25:45 PM PDT 24 |
| Finished | Jul 12 07:30:21 PM PDT 24 |
| Peak memory | 599632 kb |
| Host | smart-7355dec3-7b2d-4fb7-a37f-5b4e7a58e22b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615370892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.1615370892 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.2752145033 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 4287921051 ps |
| CPU time | 343.02 seconds |
| Started | Jul 12 07:35:43 PM PDT 24 |
| Finished | Jul 12 07:41:30 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-5234fcc4-ddf9-4488-acd9-4f6f4eeee2e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752145033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.2752145033 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2825966618 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 21927746078 ps |
| CPU time | 1814.9 seconds |
| Started | Jul 12 07:53:09 PM PDT 24 |
| Finished | Jul 12 08:23:24 PM PDT 24 |
| Peak memory | 611160 kb |
| Host | smart-6f6b6bba-99ac-42a1-903b-5e9b656ee314 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2825966618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2825966618 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.1676092458 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 3607905842 ps |
| CPU time | 526.55 seconds |
| Started | Jul 12 08:13:47 PM PDT 24 |
| Finished | Jul 12 08:22:35 PM PDT 24 |
| Peak memory | 610272 kb |
| Host | smart-1d9e810c-cb6d-4155-b56c-567e2aa7c65c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676092458 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.1676092458 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.1879485538 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 25461981539 ps |
| CPU time | 481.88 seconds |
| Started | Jul 12 07:34:40 PM PDT 24 |
| Finished | Jul 12 07:42:46 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-f697ab3c-bc67-4d57-9cba-2fd6a598e0b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879485538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.1879485538 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.3271881845 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 8240288883 ps |
| CPU time | 793.42 seconds |
| Started | Jul 12 07:24:11 PM PDT 24 |
| Finished | Jul 12 07:37:26 PM PDT 24 |
| Peak memory | 576988 kb |
| Host | smart-fc5f8d40-95fc-4c39-b3fd-5f3f3191e270 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271881845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.3271881845 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.393104498 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 7897854819 ps |
| CPU time | 318.39 seconds |
| Started | Jul 12 07:23:31 PM PDT 24 |
| Finished | Jul 12 07:28:53 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-10ee9919-42ce-46ac-ace1-9ac9c8123799 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393104498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.393104498 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3758683259 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3105873937 ps |
| CPU time | 121.9 seconds |
| Started | Jul 12 07:55:57 PM PDT 24 |
| Finished | Jul 12 07:57:59 PM PDT 24 |
| Peak memory | 620564 kb |
| Host | smart-0571a75c-caed-4cfa-aee0-b53c1da17cfd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37586832 59 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.3758683259 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.3826848593 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 88178867544 ps |
| CPU time | 1715.55 seconds |
| Started | Jul 12 07:31:51 PM PDT 24 |
| Finished | Jul 12 08:00:34 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-a9136acc-e46b-494d-bab1-9febee1cd2ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826848593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.3826848593 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.972344709 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 3417778660 ps |
| CPU time | 410.27 seconds |
| Started | Jul 12 08:22:40 PM PDT 24 |
| Finished | Jul 12 08:29:31 PM PDT 24 |
| Peak memory | 649508 kb |
| Host | smart-f74da26b-fbbd-4807-9392-22675f91b6d0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972344709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_s w_alert_handler_lpg_sleep_mode_alerts.972344709 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.4081155565 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 2856840240 ps |
| CPU time | 320.96 seconds |
| Started | Jul 12 07:47:01 PM PDT 24 |
| Finished | Jul 12 07:52:24 PM PDT 24 |
| Peak memory | 613436 kb |
| Host | smart-aefdd4ba-e2cd-4465-b7bd-427b1a740720 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081155565 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.4081155565 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.913634285 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 4771894222 ps |
| CPU time | 388.71 seconds |
| Started | Jul 12 07:50:52 PM PDT 24 |
| Finished | Jul 12 07:57:22 PM PDT 24 |
| Peak memory | 609696 kb |
| Host | smart-6ebe3fd6-f19e-4452-a1f3-c059b4915269 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91363428 5 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.913634285 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1476683756 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 2950294158 ps |
| CPU time | 400.3 seconds |
| Started | Jul 12 07:50:49 PM PDT 24 |
| Finished | Jul 12 07:57:30 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-050260b6-5673-4e60-a12b-06e2dd278261 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476 683756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.1476683756 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.80652506 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 21559587778 ps |
| CPU time | 2834.2 seconds |
| Started | Jul 12 07:41:35 PM PDT 24 |
| Finished | Jul 12 08:28:51 PM PDT 24 |
| Peak memory | 608440 kb |
| Host | smart-6f40c855-8d42-4348-80df-4d6c66d0a20c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80652506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_jtag_csr_rw.80652506 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.3334777852 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 5215361300 ps |
| CPU time | 456.29 seconds |
| Started | Jul 12 07:27:49 PM PDT 24 |
| Finished | Jul 12 07:35:33 PM PDT 24 |
| Peak memory | 598776 kb |
| Host | smart-4f53ffe0-24aa-4bfa-8a07-aa61b866f95e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334777852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.3334777852 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3772452306 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 42384110740 ps |
| CPU time | 5046.18 seconds |
| Started | Jul 12 08:04:37 PM PDT 24 |
| Finished | Jul 12 09:28:44 PM PDT 24 |
| Peak memory | 620268 kb |
| Host | smart-2cbb4302-9693-4224-824a-3c06fc178f57 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3772452306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.3772452306 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.3679826219 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 38850743072 ps |
| CPU time | 407.62 seconds |
| Started | Jul 12 07:34:54 PM PDT 24 |
| Finished | Jul 12 07:41:44 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-414b4102-a027-43ff-befc-76206b9ed391 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679826219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.3679826219 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2615813702 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 11978072368 ps |
| CPU time | 1359.33 seconds |
| Started | Jul 12 07:58:17 PM PDT 24 |
| Finished | Jul 12 08:20:58 PM PDT 24 |
| Peak memory | 611336 kb |
| Host | smart-904d088e-eb3a-439e-9f54-7705b739ecb2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615813702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.2615813702 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2116103519 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4081204659 ps |
| CPU time | 535.4 seconds |
| Started | Jul 12 07:50:48 PM PDT 24 |
| Finished | Jul 12 07:59:45 PM PDT 24 |
| Peak memory | 610960 kb |
| Host | smart-f8255a7f-900d-4b3c-bde9-b52b0714e6c5 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116103519 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2116103519 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3935877725 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 5298582488 ps |
| CPU time | 478.49 seconds |
| Started | Jul 12 07:48:02 PM PDT 24 |
| Finished | Jul 12 07:56:02 PM PDT 24 |
| Peak memory | 611284 kb |
| Host | smart-6c18b0fc-a702-4e80-9889-b7c766e9fe03 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3935877725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.3935877725 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.2650674435 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 6684108160 ps |
| CPU time | 1993.09 seconds |
| Started | Jul 12 08:09:33 PM PDT 24 |
| Finished | Jul 12 08:42:48 PM PDT 24 |
| Peak memory | 610856 kb |
| Host | smart-01206d06-285f-4693-a6ee-b3e2788179aa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650674435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.2650674435 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1042455692 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3185043851 ps |
| CPU time | 337.71 seconds |
| Started | Jul 12 08:02:39 PM PDT 24 |
| Finished | Jul 12 08:08:17 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-fc178574-776e-4ce1-942e-e6222a06bb96 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042 455692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.1042455692 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3074523326 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 5053164154 ps |
| CPU time | 561.51 seconds |
| Started | Jul 12 07:47:35 PM PDT 24 |
| Finished | Jul 12 07:56:58 PM PDT 24 |
| Peak memory | 625276 kb |
| Host | smart-55266f42-a707-4288-96a6-0e1329fe1bad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074523326 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.3074523326 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.1488443485 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 24219977950 ps |
| CPU time | 2343.53 seconds |
| Started | Jul 12 07:46:46 PM PDT 24 |
| Finished | Jul 12 08:25:52 PM PDT 24 |
| Peak memory | 613756 kb |
| Host | smart-53b5c7fa-a5e6-4505-93a2-5455acee8fec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488443485 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.1488443485 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.992258870 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 11369004818 ps |
| CPU time | 620.95 seconds |
| Started | Jul 12 07:27:30 PM PDT 24 |
| Finished | Jul 12 07:37:54 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-902f1521-49b6-4348-bfb8-39732a4a4194 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992258870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_ with_rand_reset.992258870 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.3178596149 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 5544971386 ps |
| CPU time | 560.48 seconds |
| Started | Jul 12 08:23:15 PM PDT 24 |
| Finished | Jul 12 08:32:36 PM PDT 24 |
| Peak memory | 650152 kb |
| Host | smart-f18bcc12-6754-4210-9ac6-3992cdaf71b2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3178596149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.3178596149 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3458703327 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 6935768679 ps |
| CPU time | 666.82 seconds |
| Started | Jul 12 08:08:40 PM PDT 24 |
| Finished | Jul 12 08:19:48 PM PDT 24 |
| Peak memory | 611688 kb |
| Host | smart-8ca92f56-d561-4699-bc9b-520f866c94bc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458703327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.3458703327 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.22397447 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 4721843868 ps |
| CPU time | 566.63 seconds |
| Started | Jul 12 08:19:40 PM PDT 24 |
| Finished | Jul 12 08:29:09 PM PDT 24 |
| Peak memory | 650180 kb |
| Host | smart-50b452a8-084d-4696-b7c5-20a611ef81b2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 22397447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.22397447 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.3449946178 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 5059191330 ps |
| CPU time | 431.36 seconds |
| Started | Jul 12 07:26:10 PM PDT 24 |
| Finished | Jul 12 07:33:24 PM PDT 24 |
| Peak memory | 603696 kb |
| Host | smart-694ba08c-9ae4-462a-b37b-c5c1490f9bbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449946178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.3449946178 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3596714528 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 7414930666 ps |
| CPU time | 405.1 seconds |
| Started | Jul 12 07:23:09 PM PDT 24 |
| Finished | Jul 12 07:29:57 PM PDT 24 |
| Peak memory | 660716 kb |
| Host | smart-7df4b3d1-b381-45bc-b947-f00edf13f10c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596714528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.3596714528 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.2457236426 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 6403788158 ps |
| CPU time | 578.23 seconds |
| Started | Jul 12 08:21:28 PM PDT 24 |
| Finished | Jul 12 08:31:07 PM PDT 24 |
| Peak memory | 650548 kb |
| Host | smart-eda0e0ee-1cf1-4d7e-ae3a-ac6337b9b865 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2457236426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.2457236426 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.1956939193 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 5037886800 ps |
| CPU time | 574.54 seconds |
| Started | Jul 12 08:19:24 PM PDT 24 |
| Finished | Jul 12 08:29:00 PM PDT 24 |
| Peak memory | 650408 kb |
| Host | smart-03d2156c-3fd5-47b7-a5f6-18c6d7ede02d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1956939193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.1956939193 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.3087147173 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 4108959880 ps |
| CPU time | 626.2 seconds |
| Started | Jul 12 08:17:50 PM PDT 24 |
| Finished | Jul 12 08:28:17 PM PDT 24 |
| Peak memory | 649876 kb |
| Host | smart-069ae381-d6ef-4560-9db4-702a67190802 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3087147173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.3087147173 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.2933384438 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 5709827512 ps |
| CPU time | 805.82 seconds |
| Started | Jul 12 08:14:19 PM PDT 24 |
| Finished | Jul 12 08:27:46 PM PDT 24 |
| Peak memory | 611312 kb |
| Host | smart-80dbac0d-35ea-49a2-8360-666b1bb1350e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2933384438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.2933384438 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.3348172258 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 11134922380 ps |
| CPU time | 642.52 seconds |
| Started | Jul 12 07:37:44 PM PDT 24 |
| Finished | Jul 12 07:48:29 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-4b38f720-2a37-4849-9e3e-31cd92988253 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348172258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_rand_reset.3348172258 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.3360792480 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3330382544 ps |
| CPU time | 313.38 seconds |
| Started | Jul 12 07:47:13 PM PDT 24 |
| Finished | Jul 12 07:52:28 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-21ae7712-e38d-4923-8d4e-33fed4a7cb7c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360792480 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.3360792480 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.1854956877 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 6676341688 ps |
| CPU time | 1403.41 seconds |
| Started | Jul 12 07:49:33 PM PDT 24 |
| Finished | Jul 12 08:12:57 PM PDT 24 |
| Peak memory | 609676 kb |
| Host | smart-f661d8ae-6771-4d51-96a4-1dd9243cfa9c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854956877 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.1854956877 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1884294601 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 77797070157 ps |
| CPU time | 13823.5 seconds |
| Started | Jul 12 07:47:48 PM PDT 24 |
| Finished | Jul 12 11:38:15 PM PDT 24 |
| Peak memory | 634412 kb |
| Host | smart-4beefedf-2607-4458-9079-2c691f30d1ae |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1884294601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.1884294601 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.134257652 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 8801103576 ps |
| CPU time | 406.22 seconds |
| Started | Jul 12 07:30:44 PM PDT 24 |
| Finished | Jul 12 07:37:38 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-d2d06685-4f9c-4ae2-a50b-be4436c30e7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134257652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_ with_rand_reset.134257652 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.473929318 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 8561764784 ps |
| CPU time | 979.56 seconds |
| Started | Jul 12 07:54:14 PM PDT 24 |
| Finished | Jul 12 08:10:35 PM PDT 24 |
| Peak memory | 611028 kb |
| Host | smart-9094eb33-11ec-4ba1-8552-3a10069fd01f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47392931 8 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.473929318 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.569520905 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 4511497698 ps |
| CPU time | 397.67 seconds |
| Started | Jul 12 07:47:39 PM PDT 24 |
| Finished | Jul 12 07:54:17 PM PDT 24 |
| Peak memory | 609552 kb |
| Host | smart-ca3d38d6-5d4d-4494-85e7-d08dea3487f5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56 9520905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.569520905 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2643397722 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 8925561457 ps |
| CPU time | 1506.76 seconds |
| Started | Jul 12 08:14:56 PM PDT 24 |
| Finished | Jul 12 08:40:04 PM PDT 24 |
| Peak memory | 625104 kb |
| Host | smart-f042ca3f-ce43-43d7-be5f-7be6f4e9ab2c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643397722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.2643397722 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_rma.2407203732 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 4200498396 ps |
| CPU time | 336.13 seconds |
| Started | Jul 12 08:16:33 PM PDT 24 |
| Finished | Jul 12 08:22:10 PM PDT 24 |
| Peak memory | 621364 kb |
| Host | smart-cc7b4c70-5395-448d-9094-8742e76876d2 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407203732 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.2407203732 |
| Directory | /workspace/3.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.2354613178 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3593232552 ps |
| CPU time | 274.82 seconds |
| Started | Jul 12 07:58:06 PM PDT 24 |
| Finished | Jul 12 08:02:41 PM PDT 24 |
| Peak memory | 609480 kb |
| Host | smart-10133cce-1e1f-4834-a3c1-9c9d14618848 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354613178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.2354613178 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.1916701154 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 2941579385 ps |
| CPU time | 312.07 seconds |
| Started | Jul 12 07:36:29 PM PDT 24 |
| Finished | Jul 12 07:41:45 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-2994d8fc-918e-4696-9f6e-beb7135f3227 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916701154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.1916701154 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.546681241 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 5024988776 ps |
| CPU time | 493.1 seconds |
| Started | Jul 12 07:23:47 PM PDT 24 |
| Finished | Jul 12 07:32:03 PM PDT 24 |
| Peak memory | 599020 kb |
| Host | smart-a1bb8506-e298-4e4f-a1ad-2b170de7a2cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546681241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.546681241 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.1416533670 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 20745425680 ps |
| CPU time | 772.01 seconds |
| Started | Jul 12 07:31:38 PM PDT 24 |
| Finished | Jul 12 07:44:37 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-45343144-bb14-491d-b71c-87241851f815 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416533670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1416533670 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.3975120283 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 20294973050 ps |
| CPU time | 2237.4 seconds |
| Started | Jul 12 08:03:21 PM PDT 24 |
| Finished | Jul 12 08:40:40 PM PDT 24 |
| Peak memory | 608440 kb |
| Host | smart-e02faed3-7eea-497c-8d7e-7e0a04790ebe |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975120283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.3975120283 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3877348691 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 3660556194 ps |
| CPU time | 622.23 seconds |
| Started | Jul 12 07:46:31 PM PDT 24 |
| Finished | Jul 12 07:56:54 PM PDT 24 |
| Peak memory | 609664 kb |
| Host | smart-7216cf50-9f78-4b93-9e74-f57ca5c7ae4f |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387734 8691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.3877348691 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.1947010862 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 101087148 ps |
| CPU time | 13.66 seconds |
| Started | Jul 12 07:30:44 PM PDT 24 |
| Finished | Jul 12 07:31:07 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-0e34bcaf-937a-4621-8195-b50937bcfbe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947010862 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add r.1947010862 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.502333636 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 43459511289 ps |
| CPU time | 5674.34 seconds |
| Started | Jul 12 07:48:10 PM PDT 24 |
| Finished | Jul 12 09:22:47 PM PDT 24 |
| Peak memory | 625168 kb |
| Host | smart-38cccc83-69f2-4e29-8ce4-b780f0b88de5 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=502333636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.502333636 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1696636437 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 50716286177 ps |
| CPU time | 5292.1 seconds |
| Started | Jul 12 07:58:38 PM PDT 24 |
| Finished | Jul 12 09:26:52 PM PDT 24 |
| Peak memory | 624304 kb |
| Host | smart-9ad4b50f-a3b5-4a80-ae95-6d43a91a9abd |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696636437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_lc_walkthrough_prod.1696636437 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.590832687 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 7952071688 ps |
| CPU time | 1679 seconds |
| Started | Jul 12 07:47:30 PM PDT 24 |
| Finished | Jul 12 08:15:30 PM PDT 24 |
| Peak memory | 619168 kb |
| Host | smart-da33dcff-3817-4746-ac79-1901c06d914d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=590832687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.590832687 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.839194722 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 6031703930 ps |
| CPU time | 635.52 seconds |
| Started | Jul 12 07:24:30 PM PDT 24 |
| Finished | Jul 12 07:35:07 PM PDT 24 |
| Peak memory | 598984 kb |
| Host | smart-f9419f39-5d1c-48cb-9506-91c54f254b81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839194722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.839194722 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.1964542206 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 4582980040 ps |
| CPU time | 987.36 seconds |
| Started | Jul 12 07:52:47 PM PDT 24 |
| Finished | Jul 12 08:09:16 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-f850cbfb-f84c-40ad-a6a1-7b24f40ab639 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964542206 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.1964542206 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2304654361 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 5213063831 ps |
| CPU time | 467.7 seconds |
| Started | Jul 12 07:25:52 PM PDT 24 |
| Finished | Jul 12 07:33:41 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-1f7bceea-cbb8-4b3a-91d1-57d0984ba890 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304654361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.2304654361 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.330130614 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5423605000 ps |
| CPU time | 519.23 seconds |
| Started | Jul 12 07:48:16 PM PDT 24 |
| Finished | Jul 12 07:56:57 PM PDT 24 |
| Peak memory | 611048 kb |
| Host | smart-4ab54acb-f618-4012-80ad-36e866062f9f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330130614 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.330130614 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.677175212 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 6043472244 ps |
| CPU time | 1212.98 seconds |
| Started | Jul 12 07:59:09 PM PDT 24 |
| Finished | Jul 12 08:19:23 PM PDT 24 |
| Peak memory | 610568 kb |
| Host | smart-9463d8a9-4e64-4671-b60f-0fcd320038bd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677175212 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_plic_all_irqs_0.677175212 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1905725481 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 18516409484 ps |
| CPU time | 641.97 seconds |
| Started | Jul 12 07:47:48 PM PDT 24 |
| Finished | Jul 12 07:58:32 PM PDT 24 |
| Peak memory | 619544 kb |
| Host | smart-6d4b7bda-6985-4133-a160-e5859cb6426f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1905725481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1905725481 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.914018388 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2543356200 ps |
| CPU time | 299.33 seconds |
| Started | Jul 12 07:57:06 PM PDT 24 |
| Finished | Jul 12 08:02:07 PM PDT 24 |
| Peak memory | 610716 kb |
| Host | smart-79154e70-fe66-43f6-a425-62c5aa6cae40 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914018388 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.914018388 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.4208654570 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 4334104908 ps |
| CPU time | 326.86 seconds |
| Started | Jul 12 08:16:56 PM PDT 24 |
| Finished | Jul 12 08:22:23 PM PDT 24 |
| Peak memory | 643416 kb |
| Host | smart-441bda8a-d78b-4884-a632-010c922474f9 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208654570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.4208654570 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2968579806 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 7958847288 ps |
| CPU time | 1404.46 seconds |
| Started | Jul 12 08:09:45 PM PDT 24 |
| Finished | Jul 12 08:33:10 PM PDT 24 |
| Peak memory | 618164 kb |
| Host | smart-1f14e0bc-4945-4bce-840d-f36f6b84c862 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2968579806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.2968579806 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3062165636 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 17057360473 ps |
| CPU time | 1901.03 seconds |
| Started | Jul 12 07:25:56 PM PDT 24 |
| Finished | Jul 12 07:57:39 PM PDT 24 |
| Peak memory | 593088 kb |
| Host | smart-81fa400f-9eac-4365-ab0c-207f0ff87b47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062165636 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.3062165636 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.2452404843 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 5950245542 ps |
| CPU time | 273.71 seconds |
| Started | Jul 12 07:27:43 PM PDT 24 |
| Finished | Jul 12 07:32:20 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-0cfea338-dd1b-43d5-a834-13a0b0322538 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452404843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al l_with_reset_error.2452404843 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.3680972823 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 627995497 ps |
| CPU time | 203.84 seconds |
| Started | Jul 12 07:38:35 PM PDT 24 |
| Finished | Jul 12 07:42:02 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-97a80428-4e80-4af5-b0c9-919e9139c349 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680972823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.3680972823 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2799468219 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 5419527800 ps |
| CPU time | 499.46 seconds |
| Started | Jul 12 08:09:29 PM PDT 24 |
| Finished | Jul 12 08:17:50 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-d20a6986-b50c-454a-8234-02e329b7fe0c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27994682 19 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.2799468219 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2320622452 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2922163104 ps |
| CPU time | 245.12 seconds |
| Started | Jul 12 07:47:46 PM PDT 24 |
| Finished | Jul 12 07:51:52 PM PDT 24 |
| Peak memory | 623080 kb |
| Host | smart-e594df75-cc27-412d-b80a-088186cb02f0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320622452 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.2320622452 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.2664548406 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 4558808361 ps |
| CPU time | 345.27 seconds |
| Started | Jul 12 07:25:25 PM PDT 24 |
| Finished | Jul 12 07:31:12 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-18c42846-8d04-4755-914c-4d0078ec129e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664548406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2664548406 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.954231469 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 44936221756 ps |
| CPU time | 5462.6 seconds |
| Started | Jul 12 07:53:01 PM PDT 24 |
| Finished | Jul 12 09:24:05 PM PDT 24 |
| Peak memory | 622184 kb |
| Host | smart-a48f4625-d546-4326-a720-366df23802fc |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=954231469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.954231469 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.3743573463 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 9209630780 ps |
| CPU time | 1660.18 seconds |
| Started | Jul 12 07:53:02 PM PDT 24 |
| Finished | Jul 12 08:20:43 PM PDT 24 |
| Peak memory | 619340 kb |
| Host | smart-d309f122-2d29-4559-91aa-078909ecd616 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3743573463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.3743573463 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.2474884401 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 850792561 ps |
| CPU time | 189.84 seconds |
| Started | Jul 12 07:35:30 PM PDT 24 |
| Finished | Jul 12 07:38:44 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-1be55827-27eb-481c-9f54-b45411650cd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474884401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.2474884401 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.608274991 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 4254596740 ps |
| CPU time | 708.01 seconds |
| Started | Jul 12 07:53:59 PM PDT 24 |
| Finished | Jul 12 08:05:49 PM PDT 24 |
| Peak memory | 613216 kb |
| Host | smart-23155953-6db8-4342-81ca-5c43b3f8a589 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608274991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_fast_rma.608274991 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2727239133 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 14215039763 ps |
| CPU time | 3600.05 seconds |
| Started | Jul 12 07:53:54 PM PDT 24 |
| Finished | Jul 12 08:53:56 PM PDT 24 |
| Peak memory | 611888 kb |
| Host | smart-f1b79d53-a514-4349-abeb-9518f3550377 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727239133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_ shutdown_exception_c.2727239133 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2681992752 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 25108687220 ps |
| CPU time | 1893.79 seconds |
| Started | Jul 12 07:49:07 PM PDT 24 |
| Finished | Jul 12 08:20:42 PM PDT 24 |
| Peak memory | 614384 kb |
| Host | smart-652d71d6-0b4c-42a1-8bfb-2ead0c5d0672 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26819927 52 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.2681992752 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.4054161023 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 5076922404 ps |
| CPU time | 484.35 seconds |
| Started | Jul 12 07:23:03 PM PDT 24 |
| Finished | Jul 12 07:31:09 PM PDT 24 |
| Peak memory | 599608 kb |
| Host | smart-b2fae9dc-5888-4bab-b5f3-7c8bbaa0fe7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054161023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.4054161023 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.48264788 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 5764456116 ps |
| CPU time | 202.18 seconds |
| Started | Jul 12 07:31:48 PM PDT 24 |
| Finished | Jul 12 07:35:17 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-2e1264d5-c1b4-47df-8e7e-7dfd743c9efd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48264788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.48264788 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.171406116 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 4492733000 ps |
| CPU time | 502.44 seconds |
| Started | Jul 12 07:50:56 PM PDT 24 |
| Finished | Jul 12 07:59:20 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-2db96171-3d49-4f36-b6af-13c546accdd4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171406116 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_10.171406116 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.4022705276 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 11571279017 ps |
| CPU time | 634.72 seconds |
| Started | Jul 12 07:32:42 PM PDT 24 |
| Finished | Jul 12 07:43:22 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-7e5d4ae8-8fab-4835-a1c5-2791de8d3621 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022705276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_rand_reset.4022705276 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2478249488 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 5076618046 ps |
| CPU time | 573.41 seconds |
| Started | Jul 12 07:50:24 PM PDT 24 |
| Finished | Jul 12 07:59:59 PM PDT 24 |
| Peak memory | 610864 kb |
| Host | smart-ccf24106-2cd9-45e9-b680-597babc289db |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2478249488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2478249488 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.3115354506 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 5241819424 ps |
| CPU time | 1062.1 seconds |
| Started | Jul 12 07:59:34 PM PDT 24 |
| Finished | Jul 12 08:17:17 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-f0738eca-b9ca-4683-9bbe-982660fa627c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3115354506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.3115354506 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1999119182 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 4212632676 ps |
| CPU time | 531.08 seconds |
| Started | Jul 12 07:51:56 PM PDT 24 |
| Finished | Jul 12 08:00:48 PM PDT 24 |
| Peak memory | 623640 kb |
| Host | smart-c6a68843-cbb3-4fc6-9143-bd107b5347f8 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199911 9182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1999119182 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3818391738 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 30904333555 ps |
| CPU time | 4107.1 seconds |
| Started | Jul 12 07:25:11 PM PDT 24 |
| Finished | Jul 12 08:33:41 PM PDT 24 |
| Peak memory | 593624 kb |
| Host | smart-e16919c7-a91a-4833-8ee2-b63ed33079d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818391738 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.3818391738 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_rma.2174447466 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 4891080840 ps |
| CPU time | 409.23 seconds |
| Started | Jul 12 07:51:05 PM PDT 24 |
| Finished | Jul 12 07:57:57 PM PDT 24 |
| Peak memory | 621420 kb |
| Host | smart-1c72a411-c02a-4dc3-8bae-8d1117ccc551 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174447466 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.2174447466 |
| Directory | /workspace/0.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.2114643718 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 17223248992 ps |
| CPU time | 718.29 seconds |
| Started | Jul 12 07:36:13 PM PDT 24 |
| Finished | Jul 12 07:48:16 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-444c70d0-8e9b-4955-bd9f-013b8836d4c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114643718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.2114643718 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.2071444362 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 4076840800 ps |
| CPU time | 518.73 seconds |
| Started | Jul 12 07:59:38 PM PDT 24 |
| Finished | Jul 12 08:08:18 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-6c9544d4-f277-4acf-8ad7-281acb7d6b34 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071444362 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_10.2071444362 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.386985081 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 38324442509 ps |
| CPU time | 2965.72 seconds |
| Started | Jul 12 07:55:50 PM PDT 24 |
| Finished | Jul 12 08:45:17 PM PDT 24 |
| Peak memory | 611796 kb |
| Host | smart-226fef57-7684-4d3f-810c-4b7803acd3ff |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386985081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.386985081 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.1382915148 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 31847371426 ps |
| CPU time | 6683.4 seconds |
| Started | Jul 12 07:49:11 PM PDT 24 |
| Finished | Jul 12 09:40:36 PM PDT 24 |
| Peak memory | 610528 kb |
| Host | smart-0cdf2204-6812-4607-8384-f5f0dd37f28c |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1382915148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.1382915148 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3712068277 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 4855312960 ps |
| CPU time | 220.6 seconds |
| Started | Jul 12 07:23:32 PM PDT 24 |
| Finished | Jul 12 07:27:16 PM PDT 24 |
| Peak memory | 660324 kb |
| Host | smart-c7ec111e-9aab-43a4-95ce-6f3dd458bb72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712068277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r eset.3712068277 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3810499427 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 6222174081 ps |
| CPU time | 976.83 seconds |
| Started | Jul 12 07:49:36 PM PDT 24 |
| Finished | Jul 12 08:05:54 PM PDT 24 |
| Peak memory | 611464 kb |
| Host | smart-2cefd06e-36da-4d3f-b343-3050ecff8cb5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810499427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.3810499427 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.3718834395 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 2055108178 ps |
| CPU time | 92.62 seconds |
| Started | Jul 12 07:25:27 PM PDT 24 |
| Finished | Jul 12 07:27:02 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-0472e9f9-ef06-44f7-b59f-5693128cec1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718834395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .3718834395 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.2736974787 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 4951251324 ps |
| CPU time | 828.89 seconds |
| Started | Jul 12 08:03:02 PM PDT 24 |
| Finished | Jul 12 08:16:52 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-8597cd6b-6eee-46d6-8505-30e8808a9a69 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736974787 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.2736974787 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.2138735333 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 5383387496 ps |
| CPU time | 550.43 seconds |
| Started | Jul 12 08:14:54 PM PDT 24 |
| Finished | Jul 12 08:24:06 PM PDT 24 |
| Peak memory | 650532 kb |
| Host | smart-daa66bb1-fa95-4b55-9e1e-4b09878743ba |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2138735333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.2138735333 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.4285732240 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2448594339 ps |
| CPU time | 135.89 seconds |
| Started | Jul 12 08:07:20 PM PDT 24 |
| Finished | Jul 12 08:09:37 PM PDT 24 |
| Peak memory | 622468 kb |
| Host | smart-9199a4ac-be07-4180-b749-4e2e12a52ccb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285732240 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.4285732240 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2043664317 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 6855488518 ps |
| CPU time | 651.17 seconds |
| Started | Jul 12 08:17:03 PM PDT 24 |
| Finished | Jul 12 08:27:55 PM PDT 24 |
| Peak memory | 621720 kb |
| Host | smart-b4872fd5-e3b1-4335-8679-16f57d800f55 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043664317 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.2043664317 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.4225426296 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 2963272152 ps |
| CPU time | 298.16 seconds |
| Started | Jul 12 08:04:06 PM PDT 24 |
| Finished | Jul 12 08:09:06 PM PDT 24 |
| Peak memory | 610808 kb |
| Host | smart-8537d474-e184-445c-83c5-8a4cfb0c5dc2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225426296 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.4225426296 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2267068216 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 1793646977 ps |
| CPU time | 323.9 seconds |
| Started | Jul 12 07:23:10 PM PDT 24 |
| Finished | Jul 12 07:28:37 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-99eb0ace-c498-4459-90cf-bc86f4a7e8bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267068216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.2267068216 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.580827372 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 4982865710 ps |
| CPU time | 397.53 seconds |
| Started | Jul 12 07:23:40 PM PDT 24 |
| Finished | Jul 12 07:30:19 PM PDT 24 |
| Peak memory | 603640 kb |
| Host | smart-a75b7d46-f67a-4df2-8ba0-55f98b58d0d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580827372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.580827372 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.4028372996 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 617986535 ps |
| CPU time | 166.79 seconds |
| Started | Jul 12 07:29:44 PM PDT 24 |
| Finished | Jul 12 07:32:38 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-ce6a8a44-0369-4394-a4ed-8902505f9b32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028372996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.4028372996 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.3653720405 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 19956708577 ps |
| CPU time | 922.39 seconds |
| Started | Jul 12 07:31:37 PM PDT 24 |
| Finished | Jul 12 07:47:06 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-2aafd2d4-2444-4968-a42c-c0a2fd6004a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653720405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.3653720405 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3860149754 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 3953976124 ps |
| CPU time | 348.05 seconds |
| Started | Jul 12 07:48:37 PM PDT 24 |
| Finished | Jul 12 07:54:26 PM PDT 24 |
| Peak memory | 648668 kb |
| Host | smart-5da3f410-94a9-42fd-9d8a-3df0b8bde95a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860149754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.3860149754 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.32596240 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 4990812992 ps |
| CPU time | 581.27 seconds |
| Started | Jul 12 07:46:37 PM PDT 24 |
| Finished | Jul 12 07:56:19 PM PDT 24 |
| Peak memory | 650252 kb |
| Host | smart-26219238-93e8-44e4-b379-b9b6ad15a975 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 32596240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.32596240 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.128260189 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 3512054312 ps |
| CPU time | 484.88 seconds |
| Started | Jul 12 07:56:36 PM PDT 24 |
| Finished | Jul 12 08:04:43 PM PDT 24 |
| Peak memory | 648928 kb |
| Host | smart-db245ca2-994b-4240-8b57-3f50ae4a9df1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128260189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _alert_handler_lpg_sleep_mode_alerts.128260189 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.2749153695 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 4389921824 ps |
| CPU time | 726.41 seconds |
| Started | Jul 12 07:52:17 PM PDT 24 |
| Finished | Jul 12 08:04:25 PM PDT 24 |
| Peak memory | 650000 kb |
| Host | smart-ae0bbb95-8aaf-483b-8864-eef499be1338 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2749153695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.2749153695 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.4086662918 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 3632374388 ps |
| CPU time | 416.77 seconds |
| Started | Jul 12 08:18:28 PM PDT 24 |
| Finished | Jul 12 08:25:26 PM PDT 24 |
| Peak memory | 648912 kb |
| Host | smart-5706c713-8df8-42b7-9bf1-33fddd5829c5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086662918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4086662918 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.186342973 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 6314483496 ps |
| CPU time | 718.13 seconds |
| Started | Jul 12 08:17:33 PM PDT 24 |
| Finished | Jul 12 08:29:32 PM PDT 24 |
| Peak memory | 650480 kb |
| Host | smart-0240b8fd-00bf-4965-90bd-a2ea90925888 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 186342973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.186342973 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.807709232 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 4400490196 ps |
| CPU time | 411.37 seconds |
| Started | Jul 12 08:18:23 PM PDT 24 |
| Finished | Jul 12 08:25:16 PM PDT 24 |
| Peak memory | 648904 kb |
| Host | smart-7d9c591e-bcfe-4475-b642-a3e8551c9767 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807709232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_s w_alert_handler_lpg_sleep_mode_alerts.807709232 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.2413990576 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 4612744152 ps |
| CPU time | 581.65 seconds |
| Started | Jul 12 08:18:09 PM PDT 24 |
| Finished | Jul 12 08:27:51 PM PDT 24 |
| Peak memory | 650588 kb |
| Host | smart-369be802-5dd6-46df-b7d3-c59ca8e3665d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2413990576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.2413990576 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.612054184 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 3669873240 ps |
| CPU time | 457.36 seconds |
| Started | Jul 12 08:18:24 PM PDT 24 |
| Finished | Jul 12 08:26:02 PM PDT 24 |
| Peak memory | 648912 kb |
| Host | smart-22201edb-bc77-4c91-b1ab-4475ede92c2a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612054184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_s w_alert_handler_lpg_sleep_mode_alerts.612054184 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.3377941587 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 5183766896 ps |
| CPU time | 638.96 seconds |
| Started | Jul 12 08:16:53 PM PDT 24 |
| Finished | Jul 12 08:27:33 PM PDT 24 |
| Peak memory | 650088 kb |
| Host | smart-ee4f6289-31f3-47f1-81b6-66c6a8cae423 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3377941587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.3377941587 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3242364019 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 4211295920 ps |
| CPU time | 536.79 seconds |
| Started | Jul 12 08:17:33 PM PDT 24 |
| Finished | Jul 12 08:26:31 PM PDT 24 |
| Peak memory | 648580 kb |
| Host | smart-215bf1c1-4e35-4fc7-b41d-6da359396392 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242364019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3242364019 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3967765152 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3783101546 ps |
| CPU time | 403.83 seconds |
| Started | Jul 12 08:16:53 PM PDT 24 |
| Finished | Jul 12 08:23:39 PM PDT 24 |
| Peak memory | 649036 kb |
| Host | smart-416eec56-8898-46a0-9c07-2ed9d8437dc2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967765152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3967765152 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.3815220837 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 4602704890 ps |
| CPU time | 614.93 seconds |
| Started | Jul 12 08:17:53 PM PDT 24 |
| Finished | Jul 12 08:28:09 PM PDT 24 |
| Peak memory | 650132 kb |
| Host | smart-ef14f391-90d3-4a6e-ad2d-16348dd214a6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3815220837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.3815220837 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3387096326 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 3323878310 ps |
| CPU time | 407.07 seconds |
| Started | Jul 12 08:18:03 PM PDT 24 |
| Finished | Jul 12 08:24:51 PM PDT 24 |
| Peak memory | 648756 kb |
| Host | smart-c544d8c1-7bd2-4230-b386-6b94a9a86766 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387096326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3387096326 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.1402255201 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 4785388964 ps |
| CPU time | 817.12 seconds |
| Started | Jul 12 08:17:56 PM PDT 24 |
| Finished | Jul 12 08:31:34 PM PDT 24 |
| Peak memory | 650164 kb |
| Host | smart-cf28c7e8-e6ee-4eff-8f0c-3e7c5a109cd6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1402255201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.1402255201 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.347609213 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 4015804770 ps |
| CPU time | 551.24 seconds |
| Started | Jul 12 08:17:46 PM PDT 24 |
| Finished | Jul 12 08:26:59 PM PDT 24 |
| Peak memory | 649652 kb |
| Host | smart-f3681b70-d472-4f56-b791-ac8e382509f2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 347609213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.347609213 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2712922121 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 3807237632 ps |
| CPU time | 461.08 seconds |
| Started | Jul 12 08:19:15 PM PDT 24 |
| Finished | Jul 12 08:26:57 PM PDT 24 |
| Peak memory | 648916 kb |
| Host | smart-13f23d58-504a-4d0a-aa2b-cf82c0855be8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712922121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2712922121 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.2343317002 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 4463022500 ps |
| CPU time | 920.08 seconds |
| Started | Jul 12 08:17:01 PM PDT 24 |
| Finished | Jul 12 08:32:23 PM PDT 24 |
| Peak memory | 650116 kb |
| Host | smart-2664d8bb-0216-48f4-87a0-dd809a6604df |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2343317002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.2343317002 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2271603504 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 3702169260 ps |
| CPU time | 391.93 seconds |
| Started | Jul 12 08:18:37 PM PDT 24 |
| Finished | Jul 12 08:25:10 PM PDT 24 |
| Peak memory | 649080 kb |
| Host | smart-26de4d79-b0b8-4293-86fb-0a888528d56f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271603504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2271603504 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2217034729 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 4334624968 ps |
| CPU time | 406.6 seconds |
| Started | Jul 12 08:17:56 PM PDT 24 |
| Finished | Jul 12 08:24:43 PM PDT 24 |
| Peak memory | 649092 kb |
| Host | smart-496b35b2-ed6d-4c2d-83e9-21cb0217164a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217034729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2217034729 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.3336171285 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 4369584080 ps |
| CPU time | 612.55 seconds |
| Started | Jul 12 08:17:22 PM PDT 24 |
| Finished | Jul 12 08:27:36 PM PDT 24 |
| Peak memory | 650156 kb |
| Host | smart-cb4ff233-54e0-4bf3-ae2b-7ad4c0aa9e1a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3336171285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.3336171285 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1448344509 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 3914420868 ps |
| CPU time | 423.2 seconds |
| Started | Jul 12 08:18:36 PM PDT 24 |
| Finished | Jul 12 08:25:40 PM PDT 24 |
| Peak memory | 648856 kb |
| Host | smart-4053383a-a2b5-4f4e-ac6e-f2432fe33a7e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448344509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1448344509 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.100395513 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 4732400216 ps |
| CPU time | 602.68 seconds |
| Started | Jul 12 08:19:33 PM PDT 24 |
| Finished | Jul 12 08:29:37 PM PDT 24 |
| Peak memory | 649972 kb |
| Host | smart-4458b5c9-fb34-4611-ae80-a587a9235b3e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 100395513 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.100395513 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.962681821 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 3750620200 ps |
| CPU time | 454.4 seconds |
| Started | Jul 12 08:19:53 PM PDT 24 |
| Finished | Jul 12 08:27:28 PM PDT 24 |
| Peak memory | 648888 kb |
| Host | smart-adb57255-a17b-4dac-9b84-e2b59e34f252 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962681821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_s w_alert_handler_lpg_sleep_mode_alerts.962681821 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.452108901 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 4423409600 ps |
| CPU time | 550.73 seconds |
| Started | Jul 12 08:20:09 PM PDT 24 |
| Finished | Jul 12 08:29:21 PM PDT 24 |
| Peak memory | 649492 kb |
| Host | smart-e4fe736a-68e6-4e7a-8564-92ae654bb2a2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452108901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_s w_alert_handler_lpg_sleep_mode_alerts.452108901 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.3962939947 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 6378126872 ps |
| CPU time | 721.61 seconds |
| Started | Jul 12 08:18:48 PM PDT 24 |
| Finished | Jul 12 08:30:51 PM PDT 24 |
| Peak memory | 650232 kb |
| Host | smart-73746984-7968-47a0-814e-3fd83b9bdaf3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3962939947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.3962939947 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.3038551334 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 4580285236 ps |
| CPU time | 661.52 seconds |
| Started | Jul 12 08:18:48 PM PDT 24 |
| Finished | Jul 12 08:29:50 PM PDT 24 |
| Peak memory | 650436 kb |
| Host | smart-89effb24-e4aa-41d8-ab18-8c2b229ae234 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3038551334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.3038551334 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.703595386 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 3890920102 ps |
| CPU time | 357.64 seconds |
| Started | Jul 12 08:20:00 PM PDT 24 |
| Finished | Jul 12 08:25:59 PM PDT 24 |
| Peak memory | 649208 kb |
| Host | smart-9b2e7239-cd8d-4cf8-8e73-c57dc2fbbaa5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703595386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_s w_alert_handler_lpg_sleep_mode_alerts.703595386 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.4106774188 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 4627890534 ps |
| CPU time | 892.63 seconds |
| Started | Jul 12 08:19:09 PM PDT 24 |
| Finished | Jul 12 08:34:03 PM PDT 24 |
| Peak memory | 649896 kb |
| Host | smart-9c2a0957-e34f-4136-9254-b1cb5327e22f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4106774188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.4106774188 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.3241105855 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 5899988728 ps |
| CPU time | 759.63 seconds |
| Started | Jul 12 08:18:48 PM PDT 24 |
| Finished | Jul 12 08:31:28 PM PDT 24 |
| Peak memory | 650292 kb |
| Host | smart-99a2102e-3b7f-4705-81f5-9812764840e0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3241105855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.3241105855 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1411217309 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 4476679900 ps |
| CPU time | 443 seconds |
| Started | Jul 12 08:14:32 PM PDT 24 |
| Finished | Jul 12 08:21:55 PM PDT 24 |
| Peak memory | 648976 kb |
| Host | smart-064f98a2-fd7e-4a77-b70e-6f4c011452fa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411217309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.1411217309 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.2319395692 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 5250335186 ps |
| CPU time | 737.42 seconds |
| Started | Jul 12 08:15:18 PM PDT 24 |
| Finished | Jul 12 08:27:37 PM PDT 24 |
| Peak memory | 650044 kb |
| Host | smart-6dca575f-fcd6-46fd-b2b6-487d3bbe9e44 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2319395692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.2319395692 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3771414271 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 3996046600 ps |
| CPU time | 409.6 seconds |
| Started | Jul 12 08:21:02 PM PDT 24 |
| Finished | Jul 12 08:27:53 PM PDT 24 |
| Peak memory | 648608 kb |
| Host | smart-66fa35ca-24f7-460f-aa3c-507d96a6f129 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771414271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3771414271 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.3305558160 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 4860162640 ps |
| CPU time | 552.81 seconds |
| Started | Jul 12 08:18:45 PM PDT 24 |
| Finished | Jul 12 08:27:59 PM PDT 24 |
| Peak memory | 650148 kb |
| Host | smart-d48b385e-d898-4495-a883-da621462fed8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3305558160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.3305558160 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.446523786 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 3665779200 ps |
| CPU time | 462.71 seconds |
| Started | Jul 12 08:19:46 PM PDT 24 |
| Finished | Jul 12 08:27:29 PM PDT 24 |
| Peak memory | 648680 kb |
| Host | smart-0636b391-b555-4191-8728-44f4748c4ad7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446523786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_s w_alert_handler_lpg_sleep_mode_alerts.446523786 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.3866310504 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 4781685352 ps |
| CPU time | 633.27 seconds |
| Started | Jul 12 08:18:26 PM PDT 24 |
| Finished | Jul 12 08:29:00 PM PDT 24 |
| Peak memory | 650176 kb |
| Host | smart-1935970c-84d3-4bb0-aa94-24f2d2f4bef9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3866310504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.3866310504 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2524322360 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 3876416180 ps |
| CPU time | 382.36 seconds |
| Started | Jul 12 08:21:11 PM PDT 24 |
| Finished | Jul 12 08:27:34 PM PDT 24 |
| Peak memory | 648884 kb |
| Host | smart-3bb6b5e7-6c80-42e1-8172-472b1a1f84f0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524322360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2524322360 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.2734676252 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 5208051382 ps |
| CPU time | 616.04 seconds |
| Started | Jul 12 08:22:13 PM PDT 24 |
| Finished | Jul 12 08:32:31 PM PDT 24 |
| Peak memory | 650044 kb |
| Host | smart-cfddac0c-3681-4ae2-92b1-838a1e45b299 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2734676252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.2734676252 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3342976189 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 3340034660 ps |
| CPU time | 456.96 seconds |
| Started | Jul 12 08:18:52 PM PDT 24 |
| Finished | Jul 12 08:26:29 PM PDT 24 |
| Peak memory | 649144 kb |
| Host | smart-b7fe2bdb-309c-4bda-9276-0f8e42232722 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342976189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3342976189 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.3796421840 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 5440157454 ps |
| CPU time | 719.04 seconds |
| Started | Jul 12 08:20:08 PM PDT 24 |
| Finished | Jul 12 08:32:08 PM PDT 24 |
| Peak memory | 650240 kb |
| Host | smart-b49c55f5-8816-4b8e-ae1d-916b2496aa03 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3796421840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.3796421840 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.1336935591 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 6121948264 ps |
| CPU time | 466.17 seconds |
| Started | Jul 12 08:18:57 PM PDT 24 |
| Finished | Jul 12 08:26:44 PM PDT 24 |
| Peak memory | 649380 kb |
| Host | smart-dfeea832-dc2e-4fde-93f5-4db86fb1f092 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1336935591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.1336935591 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.914496318 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 4092553424 ps |
| CPU time | 352.05 seconds |
| Started | Jul 12 08:20:22 PM PDT 24 |
| Finished | Jul 12 08:26:16 PM PDT 24 |
| Peak memory | 648896 kb |
| Host | smart-13ac2753-1b0f-4ace-8bd4-71fa348dd83a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914496318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_s w_alert_handler_lpg_sleep_mode_alerts.914496318 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.695919168 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 4178812872 ps |
| CPU time | 391.47 seconds |
| Started | Jul 12 08:20:16 PM PDT 24 |
| Finished | Jul 12 08:26:48 PM PDT 24 |
| Peak memory | 649004 kb |
| Host | smart-de9c111d-ce6b-4cc4-90f4-7aeb0e4acb85 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695919168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_s w_alert_handler_lpg_sleep_mode_alerts.695919168 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2427517866 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 3525323840 ps |
| CPU time | 438.72 seconds |
| Started | Jul 12 08:19:19 PM PDT 24 |
| Finished | Jul 12 08:26:39 PM PDT 24 |
| Peak memory | 648572 kb |
| Host | smart-d885f669-2d21-4412-9613-2d6f439496ff |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427517866 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2427517866 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.1553818659 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 6089311950 ps |
| CPU time | 728.11 seconds |
| Started | Jul 12 08:20:17 PM PDT 24 |
| Finished | Jul 12 08:32:26 PM PDT 24 |
| Peak memory | 650368 kb |
| Host | smart-90becf9f-1788-4241-bd3b-a503148c2492 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1553818659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.1553818659 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.3147528244 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 4662630232 ps |
| CPU time | 664.03 seconds |
| Started | Jul 12 08:20:31 PM PDT 24 |
| Finished | Jul 12 08:31:37 PM PDT 24 |
| Peak memory | 650224 kb |
| Host | smart-7ccd5f97-7802-4683-9524-ace87c3584f3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3147528244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.3147528244 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.4174256890 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 3848885410 ps |
| CPU time | 365.42 seconds |
| Started | Jul 12 08:21:42 PM PDT 24 |
| Finished | Jul 12 08:27:48 PM PDT 24 |
| Peak memory | 648880 kb |
| Host | smart-d9fa42e5-175c-4080-bde2-25be70dd7210 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174256890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4174256890 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.3019183392 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 5063160976 ps |
| CPU time | 564.6 seconds |
| Started | Jul 12 08:20:09 PM PDT 24 |
| Finished | Jul 12 08:29:35 PM PDT 24 |
| Peak memory | 649904 kb |
| Host | smart-2dfbda4d-74a4-457e-bb31-34856e40da33 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3019183392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.3019183392 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.4075769684 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 3651143934 ps |
| CPU time | 434.23 seconds |
| Started | Jul 12 08:20:39 PM PDT 24 |
| Finished | Jul 12 08:27:54 PM PDT 24 |
| Peak memory | 648844 kb |
| Host | smart-ce2d94f0-93ee-4dcd-a0cb-6c71aec90c18 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075769684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4075769684 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.1373426571 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 5086760040 ps |
| CPU time | 580.07 seconds |
| Started | Jul 12 08:20:40 PM PDT 24 |
| Finished | Jul 12 08:30:20 PM PDT 24 |
| Peak memory | 651152 kb |
| Host | smart-5a469f9b-ed4f-41da-894c-c19a1332a112 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1373426571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.1373426571 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.2356167904 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 5417561352 ps |
| CPU time | 697.9 seconds |
| Started | Jul 12 08:20:20 PM PDT 24 |
| Finished | Jul 12 08:31:59 PM PDT 24 |
| Peak memory | 650312 kb |
| Host | smart-887b2d08-22d8-462a-9716-ba7b34d2531a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2356167904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.2356167904 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3323226715 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 3575927892 ps |
| CPU time | 553.1 seconds |
| Started | Jul 12 08:22:19 PM PDT 24 |
| Finished | Jul 12 08:31:33 PM PDT 24 |
| Peak memory | 648832 kb |
| Host | smart-ca7c8c7c-45a6-431e-ad2f-b2de99757e8a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323226715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3323226715 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.966463189 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 5223440170 ps |
| CPU time | 467.09 seconds |
| Started | Jul 12 08:21:00 PM PDT 24 |
| Finished | Jul 12 08:28:48 PM PDT 24 |
| Peak memory | 650120 kb |
| Host | smart-3da32e76-422e-4836-a86b-f548bae0d557 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 966463189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.966463189 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.460522359 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 3374394568 ps |
| CPU time | 340.92 seconds |
| Started | Jul 12 08:15:50 PM PDT 24 |
| Finished | Jul 12 08:21:33 PM PDT 24 |
| Peak memory | 648980 kb |
| Host | smart-3054407f-61bb-477d-a99f-4ee7d3932fd8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460522359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw _alert_handler_lpg_sleep_mode_alerts.460522359 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.1338177319 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 5094944960 ps |
| CPU time | 660.28 seconds |
| Started | Jul 12 08:22:15 PM PDT 24 |
| Finished | Jul 12 08:33:17 PM PDT 24 |
| Peak memory | 650272 kb |
| Host | smart-7b25e6a1-3b03-4407-827a-ce88a004a8e1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1338177319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.1338177319 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.2663869312 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 4047533036 ps |
| CPU time | 456.18 seconds |
| Started | Jul 12 08:21:16 PM PDT 24 |
| Finished | Jul 12 08:28:54 PM PDT 24 |
| Peak memory | 649872 kb |
| Host | smart-98855150-8a0b-48e1-91a0-23297de07e95 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2663869312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.2663869312 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2624492094 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 4104816092 ps |
| CPU time | 439.65 seconds |
| Started | Jul 12 08:22:30 PM PDT 24 |
| Finished | Jul 12 08:29:51 PM PDT 24 |
| Peak memory | 649016 kb |
| Host | smart-605d6119-ebee-4585-80c1-40424785481a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624492094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2624492094 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.945971018 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 5611715904 ps |
| CPU time | 709.23 seconds |
| Started | Jul 12 08:17:33 PM PDT 24 |
| Finished | Jul 12 08:29:25 PM PDT 24 |
| Peak memory | 650096 kb |
| Host | smart-504fb90c-c915-488d-8a8c-242f1181af64 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 945971018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.945971018 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.3272076440 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 4798594080 ps |
| CPU time | 578.28 seconds |
| Started | Jul 12 08:22:41 PM PDT 24 |
| Finished | Jul 12 08:32:21 PM PDT 24 |
| Peak memory | 650420 kb |
| Host | smart-4f7ca56e-2310-458b-ac55-cae90e403841 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3272076440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.3272076440 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.105118148 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 4834076610 ps |
| CPU time | 559.5 seconds |
| Started | Jul 12 08:22:30 PM PDT 24 |
| Finished | Jul 12 08:31:50 PM PDT 24 |
| Peak memory | 650232 kb |
| Host | smart-33624e7f-cf7a-412e-9540-53c6e51dfec4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 105118148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.105118148 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1024824148 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 3923140600 ps |
| CPU time | 485.77 seconds |
| Started | Jul 12 08:18:38 PM PDT 24 |
| Finished | Jul 12 08:26:44 PM PDT 24 |
| Peak memory | 648808 kb |
| Host | smart-ff18fab9-0006-4903-80d2-2adba3504627 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024824148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.1024824148 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.3355189084 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 6219432500 ps |
| CPU time | 579.53 seconds |
| Started | Jul 12 08:23:09 PM PDT 24 |
| Finished | Jul 12 08:32:49 PM PDT 24 |
| Peak memory | 650088 kb |
| Host | smart-49461d82-a5f4-406d-b30e-5618e52759c0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3355189084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.3355189084 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.4189655877 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 3940701784 ps |
| CPU time | 334.98 seconds |
| Started | Jul 12 08:23:44 PM PDT 24 |
| Finished | Jul 12 08:29:19 PM PDT 24 |
| Peak memory | 648736 kb |
| Host | smart-79ed178e-ffa9-4731-ac08-4b2066219bd8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189655877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4189655877 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.3298967282 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 6510499314 ps |
| CPU time | 618.34 seconds |
| Started | Jul 12 08:26:28 PM PDT 24 |
| Finished | Jul 12 08:36:47 PM PDT 24 |
| Peak memory | 649940 kb |
| Host | smart-e6cb2021-5b18-4cf2-898c-a9556ff54f54 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3298967282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.3298967282 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.544605562 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 4650484606 ps |
| CPU time | 544.12 seconds |
| Started | Jul 12 08:26:14 PM PDT 24 |
| Finished | Jul 12 08:35:19 PM PDT 24 |
| Peak memory | 650020 kb |
| Host | smart-3b61b85e-ec6a-4fe2-8dc8-508ee605826b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 544605562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.544605562 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3900272035 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 8562170349 ps |
| CPU time | 1172.69 seconds |
| Started | Jul 12 07:49:11 PM PDT 24 |
| Finished | Jul 12 08:08:45 PM PDT 24 |
| Peak memory | 610808 kb |
| Host | smart-d1e959f4-cc74-48ff-b7e3-ac62b48174c2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900272035 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.3900272035 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.3561604897 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 5405858600 ps |
| CPU time | 448.19 seconds |
| Started | Jul 12 07:23:17 PM PDT 24 |
| Finished | Jul 12 07:30:48 PM PDT 24 |
| Peak memory | 603736 kb |
| Host | smart-72e6675f-b1a4-43be-9cf6-5caf645e283f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561604897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.3561604897 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.868295376 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3906847678 ps |
| CPU time | 473.1 seconds |
| Started | Jul 12 07:47:58 PM PDT 24 |
| Finished | Jul 12 07:55:52 PM PDT 24 |
| Peak memory | 610444 kb |
| Host | smart-8b1ee386-bb19-4475-b94b-3ee7d209d2ac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868295376 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.chip_sw_gpio.868295376 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3738345092 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 4071081212 ps |
| CPU time | 389.3 seconds |
| Started | Jul 12 07:49:25 PM PDT 24 |
| Finished | Jul 12 07:55:55 PM PDT 24 |
| Peak memory | 609020 kb |
| Host | smart-c569ec9a-f67a-4ed2-8815-2f52a98d7291 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738345092 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.3738345092 |
| Directory | /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3543835641 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 5933921860 ps |
| CPU time | 499.78 seconds |
| Started | Jul 12 07:52:07 PM PDT 24 |
| Finished | Jul 12 08:00:28 PM PDT 24 |
| Peak memory | 611140 kb |
| Host | smart-f95c915e-629e-4fae-bec0-bdf8c1b4e566 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3543835641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3543835641 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3951074203 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 13348739072 ps |
| CPU time | 1937.63 seconds |
| Started | Jul 12 07:47:56 PM PDT 24 |
| Finished | Jul 12 08:20:14 PM PDT 24 |
| Peak memory | 611396 kb |
| Host | smart-970e53dd-2239-4644-a7ed-c75ef0babf2c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3951074203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.3951074203 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.139839804 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 6561222382 ps |
| CPU time | 1332.43 seconds |
| Started | Jul 12 07:49:42 PM PDT 24 |
| Finished | Jul 12 08:11:55 PM PDT 24 |
| Peak memory | 610800 kb |
| Host | smart-a2c13334-4cad-4da8-8997-26b0c396acac |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=139839804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.139839804 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1767998427 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 7166956729 ps |
| CPU time | 524.3 seconds |
| Started | Jul 12 07:49:51 PM PDT 24 |
| Finished | Jul 12 07:58:36 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-d84ddd7a-4c89-4169-9822-7583c9795edb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767998427 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.1767998427 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2348077028 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 5511184587 ps |
| CPU time | 746.05 seconds |
| Started | Jul 12 07:52:49 PM PDT 24 |
| Finished | Jul 12 08:05:17 PM PDT 24 |
| Peak memory | 624248 kb |
| Host | smart-ea7b7c35-74c9-4301-914a-6af005ab1971 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348077028 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.2348077028 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3306325716 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 67913026167 ps |
| CPU time | 10548.7 seconds |
| Started | Jul 12 07:50:44 PM PDT 24 |
| Finished | Jul 12 10:46:34 PM PDT 24 |
| Peak memory | 610908 kb |
| Host | smart-b8a86255-2eb0-4a87-b0a3-2a99e64f3e25 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3306325716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.3306325716 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.2605672251 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 10884489728 ps |
| CPU time | 1203.69 seconds |
| Started | Jul 12 07:52:21 PM PDT 24 |
| Finished | Jul 12 08:12:25 PM PDT 24 |
| Peak memory | 621404 kb |
| Host | smart-7eb971b6-4bb6-44c2-9d00-01669b5123bc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2605672251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.2605672251 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.3921744848 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 4068736608 ps |
| CPU time | 445.9 seconds |
| Started | Jul 12 07:49:05 PM PDT 24 |
| Finished | Jul 12 07:56:32 PM PDT 24 |
| Peak memory | 610208 kb |
| Host | smart-75425cdc-761f-4139-9b3f-16c9fcae6f46 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921744848 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.3921744848 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2491994450 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 4008856508 ps |
| CPU time | 612.29 seconds |
| Started | Jul 12 07:47:33 PM PDT 24 |
| Finished | Jul 12 07:57:46 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-fcbe9f38-1507-4aeb-bff2-9c899b8b73f7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491994450 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.2491994450 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.3127319119 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 2998524572 ps |
| CPU time | 537.92 seconds |
| Started | Jul 12 07:48:18 PM PDT 24 |
| Finished | Jul 12 07:57:17 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-9bf46e66-1a19-4e07-a9f7-6ba640ea13fe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127319119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.3127319119 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.1483577353 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 3006495496 ps |
| CPU time | 334.46 seconds |
| Started | Jul 12 07:52:30 PM PDT 24 |
| Finished | Jul 12 07:58:06 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-a19ef9a2-d274-4393-b260-c2b25fe82c40 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483577353 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.1483577353 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.4189875666 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 5354798996 ps |
| CPU time | 510.43 seconds |
| Started | Jul 12 07:49:15 PM PDT 24 |
| Finished | Jul 12 07:57:46 PM PDT 24 |
| Peak memory | 610888 kb |
| Host | smart-dd88876b-84b3-4ae2-bd45-e7e7a7d598d9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4189875666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.4189875666 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3389976966 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 48472942020 ps |
| CPU time | 5842.46 seconds |
| Started | Jul 12 07:48:51 PM PDT 24 |
| Finished | Jul 12 09:26:17 PM PDT 24 |
| Peak memory | 620620 kb |
| Host | smart-72b7cae2-9cb8-4136-8b47-e8c5c3cd4bca |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389976966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_dev.3389976966 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1533147444 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 15996492672 ps |
| CPU time | 2071.4 seconds |
| Started | Jul 12 07:23:05 PM PDT 24 |
| Finished | Jul 12 07:57:38 PM PDT 24 |
| Peak memory | 593156 kb |
| Host | smart-7a10b42f-4c8e-4c92-8388-22bc99ceeb01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533147444 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.1533147444 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1101991047 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 6846038036 ps |
| CPU time | 119.04 seconds |
| Started | Jul 12 07:23:22 PM PDT 24 |
| Finished | Jul 12 07:25:23 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-53d8aef0-0d3e-4b01-845b-e740310a28e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101991047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1101991047 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.4276608318 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 12300860235 ps |
| CPU time | 441.53 seconds |
| Started | Jul 12 07:26:10 PM PDT 24 |
| Finished | Jul 12 07:33:34 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-bf8ed9a4-852f-43ac-9770-8e6386c2e092 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276608318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.4276608318 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.2778681034 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 3574614483 ps |
| CPU time | 311.02 seconds |
| Started | Jul 12 07:26:48 PM PDT 24 |
| Finished | Jul 12 07:32:02 PM PDT 24 |
| Peak memory | 599588 kb |
| Host | smart-9786b4c9-6381-43bb-a805-43bf02444ad9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778681034 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.2778681034 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.1598106058 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 17883467339 ps |
| CPU time | 681.99 seconds |
| Started | Jul 12 07:30:45 PM PDT 24 |
| Finished | Jul 12 07:42:16 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-c7a86e65-2069-4bb4-8784-713bb29c4d97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598106058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1598106058 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.2363665917 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 9954829326 ps |
| CPU time | 361.69 seconds |
| Started | Jul 12 07:30:59 PM PDT 24 |
| Finished | Jul 12 07:37:10 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-18768389-afd2-44dd-b04b-b129dcf66d2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363665917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2363665917 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.153860324 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 1998996224 ps |
| CPU time | 150.51 seconds |
| Started | Jul 12 07:31:13 PM PDT 24 |
| Finished | Jul 12 07:33:49 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-f5d6ff8a-f034-48c0-8beb-fabbf6de1685 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153860324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.153860324 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.4198949436 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 10327391330 ps |
| CPU time | 325.61 seconds |
| Started | Jul 12 07:37:26 PM PDT 24 |
| Finished | Jul 12 07:42:58 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-29f0f718-066b-4e84-b8fd-123d50b01b9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198949436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.4198949436 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.2145479259 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 14415691547 ps |
| CPU time | 745.57 seconds |
| Started | Jul 12 07:38:14 PM PDT 24 |
| Finished | Jul 12 07:50:45 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-a51ac67b-322f-4c56-bc43-a31da8725b7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145479259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.2145479259 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.99044864 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 4144467838 ps |
| CPU time | 676.77 seconds |
| Started | Jul 12 07:49:19 PM PDT 24 |
| Finished | Jul 12 08:00:38 PM PDT 24 |
| Peak memory | 610584 kb |
| Host | smart-d5c4b9b3-e53d-40b9-8c5a-5f680708cfad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99044864 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.99044864 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1089163297 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 7250127292 ps |
| CPU time | 413.56 seconds |
| Started | Jul 12 07:50:08 PM PDT 24 |
| Finished | Jul 12 07:57:03 PM PDT 24 |
| Peak memory | 610744 kb |
| Host | smart-0e84e30d-89b3-42cc-8941-64bb031caae8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089163297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1089163297 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.932197332 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 4905254314 ps |
| CPU time | 831.39 seconds |
| Started | Jul 12 07:49:30 PM PDT 24 |
| Finished | Jul 12 08:03:22 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-075118f2-e191-4036-900a-e40c77b36286 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93219 7332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.932197332 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3623784233 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3793482032 ps |
| CPU time | 490.49 seconds |
| Started | Jul 12 07:59:59 PM PDT 24 |
| Finished | Jul 12 08:08:10 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-dea86003-2a57-48aa-9f2c-1ac5028095a9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623784233 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.3623784233 |
| Directory | /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3648847390 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 12390377100 ps |
| CPU time | 1888.8 seconds |
| Started | Jul 12 07:55:23 PM PDT 24 |
| Finished | Jul 12 08:26:55 PM PDT 24 |
| Peak memory | 611428 kb |
| Host | smart-0f74d9c7-2611-4c21-a8d3-fdce481c24c8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3648847390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.3648847390 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_rma.3985236777 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 3831201857 ps |
| CPU time | 320.26 seconds |
| Started | Jul 12 08:00:41 PM PDT 24 |
| Finished | Jul 12 08:06:02 PM PDT 24 |
| Peak memory | 621408 kb |
| Host | smart-d9a393ca-acd4-44aa-9a83-3475b3328ee7 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985236777 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.3985236777 |
| Directory | /workspace/1.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3458264116 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 4736309240 ps |
| CPU time | 890.75 seconds |
| Started | Jul 12 07:47:07 PM PDT 24 |
| Finished | Jul 12 08:01:59 PM PDT 24 |
| Peak memory | 609892 kb |
| Host | smart-5925a736-9c0d-4bd4-9b55-7f8a7a4c89cb |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458264116 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.3458264116 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.1854733209 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 3899577416 ps |
| CPU time | 679.12 seconds |
| Started | Jul 12 07:50:20 PM PDT 24 |
| Finished | Jul 12 08:01:40 PM PDT 24 |
| Peak memory | 609412 kb |
| Host | smart-b750827a-323c-48ce-911f-676bb9580477 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854733209 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.1854733209 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3118694652 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 5553166336 ps |
| CPU time | 264.48 seconds |
| Started | Jul 12 07:23:47 PM PDT 24 |
| Finished | Jul 12 07:28:14 PM PDT 24 |
| Peak memory | 661524 kb |
| Host | smart-f226f530-d15c-46e1-bb13-b338056bf182 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118694652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.3118694652 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1026241942 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 7534212488 ps |
| CPU time | 1781.98 seconds |
| Started | Jul 12 07:49:21 PM PDT 24 |
| Finished | Jul 12 08:19:04 PM PDT 24 |
| Peak memory | 611492 kb |
| Host | smart-cdccdbe3-02cd-4473-a1ac-641bdda184a8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102624 1942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.1026241942 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2533921783 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 11400775720 ps |
| CPU time | 3016.57 seconds |
| Started | Jul 12 07:50:18 PM PDT 24 |
| Finished | Jul 12 08:40:36 PM PDT 24 |
| Peak memory | 610304 kb |
| Host | smart-ea44e845-f32c-44a9-b330-070c39d05921 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25339 21783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.2533921783 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2482134635 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 17208326024 ps |
| CPU time | 3641.38 seconds |
| Started | Jul 12 07:51:22 PM PDT 24 |
| Finished | Jul 12 08:52:06 PM PDT 24 |
| Peak memory | 610900 kb |
| Host | smart-6591196c-1697-4a4e-8a73-3aaf585c952c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2482134635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.2482134635 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2399179147 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 2772644306 ps |
| CPU time | 236.59 seconds |
| Started | Jul 12 07:53:07 PM PDT 24 |
| Finished | Jul 12 07:57:04 PM PDT 24 |
| Peak memory | 608996 kb |
| Host | smart-aa04ad5c-9855-4245-b8a4-25547e9dab18 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399179147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.2399179147 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.759000605 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 2186094737 ps |
| CPU time | 108.54 seconds |
| Started | Jul 12 07:56:01 PM PDT 24 |
| Finished | Jul 12 07:57:50 PM PDT 24 |
| Peak memory | 622464 kb |
| Host | smart-edef2665-ac8b-4848-9a09-7e44a5e08ea7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759000605 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.759000605 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3841197678 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 30699080912 ps |
| CPU time | 3613.93 seconds |
| Started | Jul 12 07:23:02 PM PDT 24 |
| Finished | Jul 12 08:23:17 PM PDT 24 |
| Peak memory | 592216 kb |
| Host | smart-0d9f2717-3b41-40ef-a22d-72d85077e1d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841197678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.3841197678 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.2903215676 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 3745369728 ps |
| CPU time | 358.98 seconds |
| Started | Jul 12 07:23:13 PM PDT 24 |
| Finished | Jul 12 07:29:15 PM PDT 24 |
| Peak memory | 598676 kb |
| Host | smart-33eb6e79-a74e-4c92-8c96-cee8adcee4b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903215676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.2903215676 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3137536808 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 7252794883 ps |
| CPU time | 286.82 seconds |
| Started | Jul 12 07:23:06 PM PDT 24 |
| Finished | Jul 12 07:27:54 PM PDT 24 |
| Peak memory | 590464 kb |
| Host | smart-6c90da65-5453-47e3-ac92-f2bdae7d76e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137536808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.3137536808 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3363075783 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 16154821441 ps |
| CPU time | 707.24 seconds |
| Started | Jul 12 07:23:10 PM PDT 24 |
| Finished | Jul 12 07:35:00 PM PDT 24 |
| Peak memory | 591188 kb |
| Host | smart-9ddf68cc-019b-432c-a7e4-b7ee73329cc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363075783 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.3363075783 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.3319386740 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 354310626 ps |
| CPU time | 26.25 seconds |
| Started | Jul 12 07:23:13 PM PDT 24 |
| Finished | Jul 12 07:23:42 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-abbbbcfb-91a1-4927-ab06-1b19e0aef73d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319386740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 3319386740 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.4280970084 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 140666367084 ps |
| CPU time | 2554.84 seconds |
| Started | Jul 12 07:23:12 PM PDT 24 |
| Finished | Jul 12 08:05:50 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-0fc3a023-0baa-4a88-9cee-52b7c75ebe46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280970084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.4280970084 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2219776766 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 568434003 ps |
| CPU time | 24.66 seconds |
| Started | Jul 12 07:23:09 PM PDT 24 |
| Finished | Jul 12 07:23:36 PM PDT 24 |
| Peak memory | 575208 kb |
| Host | smart-c3cce0bd-a3ad-4849-b29a-f48510c4c4aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219776766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .2219776766 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.2321349555 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 2245660941 ps |
| CPU time | 81.1 seconds |
| Started | Jul 12 07:23:06 PM PDT 24 |
| Finished | Jul 12 07:24:28 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-d003118c-a453-4a88-8149-020718b8c178 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321349555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2321349555 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.1301862924 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 244337268 ps |
| CPU time | 21.64 seconds |
| Started | Jul 12 07:23:11 PM PDT 24 |
| Finished | Jul 12 07:23:36 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-e3ff5311-f234-433d-8bdb-b2303a54ed14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301862924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.1301862924 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3913176792 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 9782568528 ps |
| CPU time | 105.95 seconds |
| Started | Jul 12 07:23:12 PM PDT 24 |
| Finished | Jul 12 07:25:01 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-95de0d4a-3750-4c71-829e-028a12f142a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913176792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3913176792 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.2792463165 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 24246424288 ps |
| CPU time | 439.41 seconds |
| Started | Jul 12 07:23:10 PM PDT 24 |
| Finished | Jul 12 07:30:33 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-5c432d65-5b11-4bcb-8a36-a23f55f8eeb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792463165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2792463165 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2637743502 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 33290563 ps |
| CPU time | 5.81 seconds |
| Started | Jul 12 07:23:09 PM PDT 24 |
| Finished | Jul 12 07:23:17 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-305a7876-3449-4aaa-b65e-27b180af8eee |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637743502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.2637743502 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.3933077613 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 2654130255 ps |
| CPU time | 75.26 seconds |
| Started | Jul 12 07:23:09 PM PDT 24 |
| Finished | Jul 12 07:24:27 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-3fe4d337-f601-4786-b8cd-dd5a873b060b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933077613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.3933077613 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.427005163 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 181117781 ps |
| CPU time | 8.28 seconds |
| Started | Jul 12 07:23:11 PM PDT 24 |
| Finished | Jul 12 07:23:22 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-7c39fcda-fd2e-4ad2-a5b8-1568cdffac26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427005163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.427005163 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3231528880 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 7594954197 ps |
| CPU time | 87.39 seconds |
| Started | Jul 12 07:23:12 PM PDT 24 |
| Finished | Jul 12 07:24:43 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-cb8ff2cc-4cf3-4520-80e6-dca0f77abe85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231528880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3231528880 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.586447872 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 4480349243 ps |
| CPU time | 76.09 seconds |
| Started | Jul 12 07:23:12 PM PDT 24 |
| Finished | Jul 12 07:24:31 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-9d797163-adcf-4c67-8072-23f8d957b248 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586447872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.586447872 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3478607877 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 43687767 ps |
| CPU time | 5.94 seconds |
| Started | Jul 12 07:23:10 PM PDT 24 |
| Finished | Jul 12 07:23:18 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-041e4c9b-2b7d-4663-8de2-9937e69d864d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478607877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .3478607877 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.1853515785 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 2171422664 ps |
| CPU time | 199.87 seconds |
| Started | Jul 12 07:23:11 PM PDT 24 |
| Finished | Jul 12 07:26:34 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-a091b5d1-6623-4e79-989f-db4403ce04ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853515785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1853515785 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.749968815 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 987834696 ps |
| CPU time | 35.95 seconds |
| Started | Jul 12 07:23:11 PM PDT 24 |
| Finished | Jul 12 07:23:50 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-c0f5918a-41c7-4120-9749-dbf4ee0150c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749968815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.749968815 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2692788073 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 11187798116 ps |
| CPU time | 696.24 seconds |
| Started | Jul 12 07:23:09 PM PDT 24 |
| Finished | Jul 12 07:34:47 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-117ef434-97f5-47f1-9c56-d0d862943af3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692788073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_rand_reset.2692788073 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1831883407 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 477848339 ps |
| CPU time | 22.24 seconds |
| Started | Jul 12 07:23:15 PM PDT 24 |
| Finished | Jul 12 07:23:39 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-db701d55-5584-4625-a228-1a1024a7b28f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831883407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1831883407 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2605787230 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 33063368350 ps |
| CPU time | 6315.6 seconds |
| Started | Jul 12 07:23:12 PM PDT 24 |
| Finished | Jul 12 09:08:31 PM PDT 24 |
| Peak memory | 593852 kb |
| Host | smart-95b0fd3b-7dd8-48b0-9796-047eda1e29ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605787230 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.chip_csr_aliasing.2605787230 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2661135723 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 68096166442 ps |
| CPU time | 6993.62 seconds |
| Started | Jul 12 07:23:15 PM PDT 24 |
| Finished | Jul 12 09:19:51 PM PDT 24 |
| Peak memory | 592544 kb |
| Host | smart-e2367728-01e0-441a-944e-b90fde4b12a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661135723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.2661135723 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.1424156975 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 4121792174 ps |
| CPU time | 351.34 seconds |
| Started | Jul 12 07:23:33 PM PDT 24 |
| Finished | Jul 12 07:29:28 PM PDT 24 |
| Peak memory | 596764 kb |
| Host | smart-2ea3d183-4511-4480-9398-37f044dd0913 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424156975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.1424156975 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2689518054 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 3395679692 ps |
| CPU time | 136.95 seconds |
| Started | Jul 12 07:23:18 PM PDT 24 |
| Finished | Jul 12 07:25:37 PM PDT 24 |
| Peak memory | 589740 kb |
| Host | smart-90ff6c10-e5de-4027-9bcb-6ba74b2e399d |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689518054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.2689518054 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2116404601 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 7947635289 ps |
| CPU time | 335.87 seconds |
| Started | Jul 12 07:23:20 PM PDT 24 |
| Finished | Jul 12 07:28:58 PM PDT 24 |
| Peak memory | 591272 kb |
| Host | smart-10bfcdbc-ee0e-4a55-98ff-d706cbc66b75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116404601 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.2116404601 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1585753832 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 14841555044 ps |
| CPU time | 1583.93 seconds |
| Started | Jul 12 07:23:10 PM PDT 24 |
| Finished | Jul 12 07:49:36 PM PDT 24 |
| Peak memory | 592748 kb |
| Host | smart-ca39b17e-8756-4571-8753-ffdfe8f91d34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585753832 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.1585753832 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.4203659102 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 1028586246 ps |
| CPU time | 68.49 seconds |
| Started | Jul 12 07:23:19 PM PDT 24 |
| Finished | Jul 12 07:24:30 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-f372c4d2-9f5c-4156-95a4-ce06c30783b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203659102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device. 4203659102 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.4030619110 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 131197538520 ps |
| CPU time | 2676.31 seconds |
| Started | Jul 12 07:23:19 PM PDT 24 |
| Finished | Jul 12 08:07:57 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-95a1ccfc-0f68-4705-a0dd-d4ca3ee71f7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030619110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.4030619110 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1849093753 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 1437244813 ps |
| CPU time | 53.33 seconds |
| Started | Jul 12 07:23:21 PM PDT 24 |
| Finished | Jul 12 07:24:16 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-075543ea-70d4-4dff-9149-0be6260b3301 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849093753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr .1849093753 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.3425950739 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 426586163 ps |
| CPU time | 33.15 seconds |
| Started | Jul 12 07:23:20 PM PDT 24 |
| Finished | Jul 12 07:23:55 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-a4c209ea-dbef-468c-af64-439b8fd1b636 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425950739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.3425950739 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.3991435528 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 1631721236 ps |
| CPU time | 63.78 seconds |
| Started | Jul 12 07:23:18 PM PDT 24 |
| Finished | Jul 12 07:24:24 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-a7e8dc9c-9db8-443e-8273-d388db78e8c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991435528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.3991435528 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.621702502 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 79729741071 ps |
| CPU time | 910.94 seconds |
| Started | Jul 12 07:23:22 PM PDT 24 |
| Finished | Jul 12 07:38:35 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-6fd91912-76c8-4e5c-95c3-f118d36a215d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621702502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.621702502 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1680203745 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 40037676198 ps |
| CPU time | 716.1 seconds |
| Started | Jul 12 07:23:21 PM PDT 24 |
| Finished | Jul 12 07:35:19 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-da9744c4-9d6e-4e05-8a48-eb601310a7b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680203745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1680203745 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.620996248 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 289194756 ps |
| CPU time | 24.48 seconds |
| Started | Jul 12 07:23:18 PM PDT 24 |
| Finished | Jul 12 07:23:45 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-ffec210b-afec-4b16-80bd-7224bb00d8e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620996248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delay s.620996248 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.2681781677 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 2450604849 ps |
| CPU time | 67.72 seconds |
| Started | Jul 12 07:23:27 PM PDT 24 |
| Finished | Jul 12 07:24:37 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-8f4eef79-fc2f-4e0b-9c27-e0f3531283ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681781677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2681781677 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.2979862430 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 234087212 ps |
| CPU time | 10.5 seconds |
| Started | Jul 12 07:23:17 PM PDT 24 |
| Finished | Jul 12 07:23:30 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-3fc9727f-9a5a-4fb5-a6ba-7d23718fdc76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979862430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2979862430 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2512354205 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 7189470608 ps |
| CPU time | 83.47 seconds |
| Started | Jul 12 07:23:19 PM PDT 24 |
| Finished | Jul 12 07:24:44 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-d02ea789-c0b1-4d97-8a94-d7b2b59db937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512354205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2512354205 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1355766871 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 39135215 ps |
| CPU time | 5.62 seconds |
| Started | Jul 12 07:23:25 PM PDT 24 |
| Finished | Jul 12 07:23:33 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-64b42054-e2ec-415b-b3fe-3f5f474bd1b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355766871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays .1355766871 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1509423724 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 4997817880 ps |
| CPU time | 178.04 seconds |
| Started | Jul 12 07:23:30 PM PDT 24 |
| Finished | Jul 12 07:26:32 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-6107292f-0275-4a10-9612-f53fda221819 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509423724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1509423724 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2126655400 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 388104647 ps |
| CPU time | 90.14 seconds |
| Started | Jul 12 07:23:30 PM PDT 24 |
| Finished | Jul 12 07:25:05 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-b5a0d240-415c-4238-b681-f8b1e719c7d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126655400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.2126655400 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2665978002 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 9063416520 ps |
| CPU time | 418.2 seconds |
| Started | Jul 12 07:23:32 PM PDT 24 |
| Finished | Jul 12 07:30:34 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-c05ed3ee-55d6-48a6-baa9-6951cb7e6f65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665978002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all _with_reset_error.2665978002 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.269919302 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 1192952895 ps |
| CPU time | 51.9 seconds |
| Started | Jul 12 07:23:25 PM PDT 24 |
| Finished | Jul 12 07:24:18 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-4c7e0953-07f6-4301-8363-9475298a2a74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269919302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.269919302 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.2365614190 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 4065047343 ps |
| CPU time | 327.92 seconds |
| Started | Jul 12 07:25:11 PM PDT 24 |
| Finished | Jul 12 07:30:41 PM PDT 24 |
| Peak memory | 598292 kb |
| Host | smart-a0e8c95d-95db-4e73-a880-872baf7439a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365614190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.2365614190 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.232982621 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 30434979144 ps |
| CPU time | 4890.91 seconds |
| Started | Jul 12 07:25:12 PM PDT 24 |
| Finished | Jul 12 08:46:46 PM PDT 24 |
| Peak memory | 592696 kb |
| Host | smart-8829d404-e179-4b88-bc96-3474c2165347 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232982621 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 10.chip_same_csr_outstanding.232982621 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.2664599239 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 3345777360 ps |
| CPU time | 207.97 seconds |
| Started | Jul 12 07:25:08 PM PDT 24 |
| Finished | Jul 12 07:28:38 PM PDT 24 |
| Peak memory | 598652 kb |
| Host | smart-72e3410e-b98d-4077-be62-161ef47f8566 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664599239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.2664599239 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.1528751681 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 2330317333 ps |
| CPU time | 107.78 seconds |
| Started | Jul 12 07:25:11 PM PDT 24 |
| Finished | Jul 12 07:27:01 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-2d60181a-b6d1-4db8-8d22-cac9a009126c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528751681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .1528751681 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3681665895 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 299995205 ps |
| CPU time | 28.46 seconds |
| Started | Jul 12 07:25:12 PM PDT 24 |
| Finished | Jul 12 07:25:44 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-4f469442-be1e-46fb-97e2-99a611455860 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681665895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add r.3681665895 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.711900039 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 941366573 ps |
| CPU time | 34.38 seconds |
| Started | Jul 12 07:25:08 PM PDT 24 |
| Finished | Jul 12 07:25:45 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-a0c1c6b9-0b09-4c2a-95ea-8c44d80902bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711900039 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.711900039 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.1168553958 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 704027379 ps |
| CPU time | 23.79 seconds |
| Started | Jul 12 07:25:17 PM PDT 24 |
| Finished | Jul 12 07:25:45 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-b6ea5a6f-48f6-4cf1-8aa4-c7a68dace8c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168553958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.1168553958 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3914230659 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 33033559254 ps |
| CPU time | 399.17 seconds |
| Started | Jul 12 07:25:09 PM PDT 24 |
| Finished | Jul 12 07:31:50 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-d411ef3f-52f9-4794-af56-3028a4837937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914230659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3914230659 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.4161829956 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 47080628283 ps |
| CPU time | 823.73 seconds |
| Started | Jul 12 07:25:11 PM PDT 24 |
| Finished | Jul 12 07:38:58 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-6c663f6d-37c3-451d-954f-f51e40f4a8db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161829956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.4161829956 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1092324990 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 169239036 ps |
| CPU time | 15.84 seconds |
| Started | Jul 12 07:25:15 PM PDT 24 |
| Finished | Jul 12 07:25:34 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-6d21d26d-9d43-4843-b675-f498834046e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092324990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_del ays.1092324990 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.2705459935 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 501959037 ps |
| CPU time | 37.37 seconds |
| Started | Jul 12 07:25:09 PM PDT 24 |
| Finished | Jul 12 07:25:49 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-632c2bda-3fca-4ab6-be75-7189c4b589a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705459935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2705459935 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.3122288523 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 201202197 ps |
| CPU time | 9.87 seconds |
| Started | Jul 12 07:25:07 PM PDT 24 |
| Finished | Jul 12 07:25:19 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-febdc4a8-fe2f-4927-9cc8-1c44da7d8311 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122288523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3122288523 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3193606519 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 10417969895 ps |
| CPU time | 117.79 seconds |
| Started | Jul 12 07:25:12 PM PDT 24 |
| Finished | Jul 12 07:27:13 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-75af8df5-fcf5-4fa9-b2f4-de416f3ae09a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193606519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3193606519 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1730812085 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 4990809086 ps |
| CPU time | 92.08 seconds |
| Started | Jul 12 07:25:11 PM PDT 24 |
| Finished | Jul 12 07:26:45 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-55de0f9f-5ef4-4bc2-8363-140d4d6e43cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730812085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.1730812085 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.394884176 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 51774336 ps |
| CPU time | 6.71 seconds |
| Started | Jul 12 07:25:07 PM PDT 24 |
| Finished | Jul 12 07:25:16 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-c9f42e58-9fe9-43ec-8246-33b183447586 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394884176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays .394884176 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.2271561831 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 3789912720 ps |
| CPU time | 320.22 seconds |
| Started | Jul 12 07:25:12 PM PDT 24 |
| Finished | Jul 12 07:30:35 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-c0001c55-fe1a-4dfa-8ffc-1b1fe7eafa85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271561831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2271561831 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.701583003 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 2339079679 ps |
| CPU time | 175.19 seconds |
| Started | Jul 12 07:25:07 PM PDT 24 |
| Finished | Jul 12 07:28:05 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-103b4eb0-5e8b-448c-b562-f99702e5bdcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701583003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.701583003 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.619155342 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 13853536713 ps |
| CPU time | 726 seconds |
| Started | Jul 12 07:25:10 PM PDT 24 |
| Finished | Jul 12 07:37:18 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-c273487d-52b1-4243-b6e6-2d66fd767bb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619155342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_ with_rand_reset.619155342 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.953746440 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 5136015527 ps |
| CPU time | 269.73 seconds |
| Started | Jul 12 07:25:09 PM PDT 24 |
| Finished | Jul 12 07:29:41 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-cc1ad32e-7d27-49ad-88c3-96afc708f9ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953746440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_reset_error.953746440 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1222029449 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 16443189 ps |
| CPU time | 4.99 seconds |
| Started | Jul 12 07:25:08 PM PDT 24 |
| Finished | Jul 12 07:25:15 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-ed01c741-7bb1-409d-9247-20aacea130d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222029449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1222029449 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.3902792 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 6200515676 ps |
| CPU time | 743.39 seconds |
| Started | Jul 12 07:25:16 PM PDT 24 |
| Finished | Jul 12 07:37:42 PM PDT 24 |
| Peak memory | 598492 kb |
| Host | smart-ee139c05-4d7d-448f-896f-230e11a9074c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.3902792 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.1885283737 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 4169846798 ps |
| CPU time | 290.04 seconds |
| Started | Jul 12 07:25:17 PM PDT 24 |
| Finished | Jul 12 07:30:11 PM PDT 24 |
| Peak memory | 603732 kb |
| Host | smart-18dee6c2-1fcd-4b39-80e9-a0f7de327dbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885283737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.1885283737 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.1803639354 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 1298764646 ps |
| CPU time | 53.15 seconds |
| Started | Jul 12 07:25:17 PM PDT 24 |
| Finished | Jul 12 07:26:14 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-11166f72-8112-45d1-8d94-00521af73d8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803639354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device .1803639354 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3660122502 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 119486679008 ps |
| CPU time | 2208.45 seconds |
| Started | Jul 12 07:25:16 PM PDT 24 |
| Finished | Jul 12 08:02:08 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-912813ef-778d-4a30-9204-e8ed32921b78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660122502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.3660122502 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.951742951 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 202402179 ps |
| CPU time | 22.47 seconds |
| Started | Jul 12 07:25:24 PM PDT 24 |
| Finished | Jul 12 07:25:49 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-2ecc82b6-dde1-4dba-a2a0-2e501614bc6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951742951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr .951742951 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.1443352441 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 481391609 ps |
| CPU time | 17.97 seconds |
| Started | Jul 12 07:25:17 PM PDT 24 |
| Finished | Jul 12 07:25:39 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-60bae361-e50a-4741-9c2a-27556c40ba0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443352441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1443352441 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.1396181130 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 658988651 ps |
| CPU time | 25.45 seconds |
| Started | Jul 12 07:25:21 PM PDT 24 |
| Finished | Jul 12 07:25:49 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-295a73d8-b492-4a21-be5e-9d5fe3fc4d83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396181130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.1396181130 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3663707150 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 29773891761 ps |
| CPU time | 339.63 seconds |
| Started | Jul 12 07:25:47 PM PDT 24 |
| Finished | Jul 12 07:31:30 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-b9737f02-5ef5-4fa1-a860-02a8efc9d458 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663707150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3663707150 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3976358661 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 18288280492 ps |
| CPU time | 317.93 seconds |
| Started | Jul 12 07:25:17 PM PDT 24 |
| Finished | Jul 12 07:30:38 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-3fe856be-3939-4d19-9b0d-48232d670897 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976358661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3976358661 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2404823806 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 329205879 ps |
| CPU time | 32.45 seconds |
| Started | Jul 12 07:25:16 PM PDT 24 |
| Finished | Jul 12 07:25:51 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-2ea65ef2-7ca2-443d-9cb5-29fa850f4f5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404823806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.2404823806 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.3958584479 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 2465696969 ps |
| CPU time | 71.75 seconds |
| Started | Jul 12 07:25:24 PM PDT 24 |
| Finished | Jul 12 07:26:37 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-ec38b886-72b7-460b-ac64-6d1a71391267 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958584479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3958584479 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.2503120742 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 247817735 ps |
| CPU time | 9.87 seconds |
| Started | Jul 12 07:25:18 PM PDT 24 |
| Finished | Jul 12 07:25:32 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-499a850a-108a-456e-88db-00fb453b8022 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503120742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.2503120742 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.3193053034 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 9440738356 ps |
| CPU time | 106.04 seconds |
| Started | Jul 12 07:25:30 PM PDT 24 |
| Finished | Jul 12 07:27:18 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-a865c36e-8840-4a11-aaba-302c6cc30d4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193053034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3193053034 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.857411160 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 6270985874 ps |
| CPU time | 106.74 seconds |
| Started | Jul 12 07:25:17 PM PDT 24 |
| Finished | Jul 12 07:27:07 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-d759ebe5-637f-4d5d-a11d-6dd92c07fbbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857411160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.857411160 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3691950248 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 52710033 ps |
| CPU time | 6.84 seconds |
| Started | Jul 12 07:25:17 PM PDT 24 |
| Finished | Jul 12 07:25:28 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-7f6e747f-b1e9-4357-9d7c-62768062fc57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691950248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.3691950248 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1856708765 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 1758472083 ps |
| CPU time | 121.14 seconds |
| Started | Jul 12 07:25:25 PM PDT 24 |
| Finished | Jul 12 07:27:28 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-ad53b329-35f9-44dd-9126-f59db1dc8cf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856708765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1856708765 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3756715794 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 2866078657 ps |
| CPU time | 401.01 seconds |
| Started | Jul 12 07:25:16 PM PDT 24 |
| Finished | Jul 12 07:32:00 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-b5657e9e-13b9-4f1c-bbb1-06789e3f6668 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756715794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.3756715794 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2709828744 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 48946566 ps |
| CPU time | 38.01 seconds |
| Started | Jul 12 07:25:30 PM PDT 24 |
| Finished | Jul 12 07:26:10 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-34c9b843-2d10-43bb-b4f5-1115455ec4a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709828744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.2709828744 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.649372342 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 392781396 ps |
| CPU time | 16.18 seconds |
| Started | Jul 12 07:25:29 PM PDT 24 |
| Finished | Jul 12 07:25:48 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-ba85aa91-6987-4f6d-96f9-f4fb67de8e1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649372342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.649372342 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.402861408 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 3843952552 ps |
| CPU time | 332.29 seconds |
| Started | Jul 12 07:25:26 PM PDT 24 |
| Finished | Jul 12 07:31:00 PM PDT 24 |
| Peak memory | 598252 kb |
| Host | smart-c31dfde0-a231-411a-bb0a-c6bc817c4e2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402861408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.402861408 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.600890514 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 31743657238 ps |
| CPU time | 4795.54 seconds |
| Started | Jul 12 07:25:29 PM PDT 24 |
| Finished | Jul 12 08:45:27 PM PDT 24 |
| Peak memory | 593140 kb |
| Host | smart-d7872c80-8a49-4a72-b8ef-7bb9a2687230 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600890514 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 12.chip_same_csr_outstanding.600890514 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.3335408615 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 4032551552 ps |
| CPU time | 272.27 seconds |
| Started | Jul 12 07:25:18 PM PDT 24 |
| Finished | Jul 12 07:29:54 PM PDT 24 |
| Peak memory | 603720 kb |
| Host | smart-d88eba40-a8a4-4151-99ff-0de8153bd47a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335408615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.3335408615 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3450663178 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 68102333531 ps |
| CPU time | 1145.41 seconds |
| Started | Jul 12 07:25:26 PM PDT 24 |
| Finished | Jul 12 07:44:34 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-c062da89-5f5b-4f92-b38c-60c52a905f03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450663178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.3450663178 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.853128899 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 213682848 ps |
| CPU time | 23.52 seconds |
| Started | Jul 12 07:25:26 PM PDT 24 |
| Finished | Jul 12 07:25:52 PM PDT 24 |
| Peak memory | 575148 kb |
| Host | smart-76a63821-5835-48ca-abd1-9d160977ed6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853128899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr .853128899 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.1652061872 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 2165657058 ps |
| CPU time | 75.38 seconds |
| Started | Jul 12 07:25:28 PM PDT 24 |
| Finished | Jul 12 07:26:46 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-af606fe9-b4d5-4530-9b83-bfabf41e2902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652061872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1652061872 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.2037152224 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 448881752 ps |
| CPU time | 40.66 seconds |
| Started | Jul 12 07:25:17 PM PDT 24 |
| Finished | Jul 12 07:26:02 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-ffa2132a-07af-4e56-a59a-acd9432b2dba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037152224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.2037152224 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2889505961 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 25672551839 ps |
| CPU time | 294.52 seconds |
| Started | Jul 12 07:25:26 PM PDT 24 |
| Finished | Jul 12 07:30:23 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-92dee760-dd73-4fe6-bd76-368cc13f9222 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889505961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2889505961 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3153298989 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 39608091118 ps |
| CPU time | 685.47 seconds |
| Started | Jul 12 07:25:29 PM PDT 24 |
| Finished | Jul 12 07:36:57 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-f8815a1a-b09d-4b24-8b55-31731b0bbf14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153298989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3153298989 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2697120551 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 135620443 ps |
| CPU time | 12.68 seconds |
| Started | Jul 12 07:25:29 PM PDT 24 |
| Finished | Jul 12 07:25:44 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-7b9ed484-4ef3-46de-bd13-ceeb5bbf92d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697120551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del ays.2697120551 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.967099922 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 163226396 ps |
| CPU time | 15.18 seconds |
| Started | Jul 12 07:25:29 PM PDT 24 |
| Finished | Jul 12 07:25:47 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-91fcca2f-8053-4058-a064-bc90ec0c8f7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967099922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.967099922 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.879745718 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 219991093 ps |
| CPU time | 9.47 seconds |
| Started | Jul 12 07:25:20 PM PDT 24 |
| Finished | Jul 12 07:25:33 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-279c6775-6416-4aa3-82c0-01619c40d12b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879745718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.879745718 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2966785883 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 8178596414 ps |
| CPU time | 90.01 seconds |
| Started | Jul 12 07:25:15 PM PDT 24 |
| Finished | Jul 12 07:26:48 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-85176061-3f9e-46cf-b996-4be8752b235c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966785883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2966785883 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2430729721 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 4237653335 ps |
| CPU time | 74.86 seconds |
| Started | Jul 12 07:25:18 PM PDT 24 |
| Finished | Jul 12 07:26:36 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-90bcd8e6-6996-4323-a145-a11c3e971367 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430729721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2430729721 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.767764933 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 48201816 ps |
| CPU time | 6.31 seconds |
| Started | Jul 12 07:25:29 PM PDT 24 |
| Finished | Jul 12 07:25:38 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-de1c0ea7-7a5e-4b8f-9693-b80f44d2fb61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767764933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays .767764933 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.2075888004 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 14655986924 ps |
| CPU time | 563.47 seconds |
| Started | Jul 12 07:25:27 PM PDT 24 |
| Finished | Jul 12 07:34:53 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-fa4ea743-c415-4ef3-8f43-28302b4a1951 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075888004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2075888004 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1991115646 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 2029266424 ps |
| CPU time | 147.64 seconds |
| Started | Jul 12 07:25:26 PM PDT 24 |
| Finished | Jul 12 07:27:56 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-006caed4-07eb-4762-a56a-638addf1f055 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991115646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1991115646 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3846871675 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2374508073 ps |
| CPU time | 348.77 seconds |
| Started | Jul 12 07:25:27 PM PDT 24 |
| Finished | Jul 12 07:31:18 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-75c2d989-7780-4293-bfb2-2bf613eb8e6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846871675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.3846871675 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1801513373 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 5193173949 ps |
| CPU time | 245.72 seconds |
| Started | Jul 12 07:25:28 PM PDT 24 |
| Finished | Jul 12 07:29:36 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-37b7b2d0-2364-4fc0-a2a7-bd8005aaffec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801513373 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.1801513373 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2005101142 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 285586723 ps |
| CPU time | 32.99 seconds |
| Started | Jul 12 07:25:29 PM PDT 24 |
| Finished | Jul 12 07:26:04 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-c32ee8db-8933-4567-91d7-718da05e8fd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005101142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2005101142 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.2609937561 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 3653074978 ps |
| CPU time | 290.05 seconds |
| Started | Jul 12 07:25:47 PM PDT 24 |
| Finished | Jul 12 07:30:41 PM PDT 24 |
| Peak memory | 596808 kb |
| Host | smart-6d136df8-4e59-45e7-a343-4f4c2267634d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609937561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.2609937561 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.122799533 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 16585488364 ps |
| CPU time | 2371.19 seconds |
| Started | Jul 12 07:25:25 PM PDT 24 |
| Finished | Jul 12 08:04:59 PM PDT 24 |
| Peak memory | 593156 kb |
| Host | smart-604588a0-86fa-462d-936b-5af0431a8fa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122799533 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 13.chip_same_csr_outstanding.122799533 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.2058159106 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 3289839160 ps |
| CPU time | 93.9 seconds |
| Started | Jul 12 07:25:26 PM PDT 24 |
| Finished | Jul 12 07:27:02 PM PDT 24 |
| Peak memory | 598636 kb |
| Host | smart-27b7f6b3-57c9-4a3c-a158-7efabd5d69e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058159106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.2058159106 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.2967854572 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 943761179 ps |
| CPU time | 62.25 seconds |
| Started | Jul 12 07:25:44 PM PDT 24 |
| Finished | Jul 12 07:26:51 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-436137c5-4a1d-47fa-91e2-41ee47f6f250 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967854572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device .2967854572 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.386016566 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 46670303230 ps |
| CPU time | 862.58 seconds |
| Started | Jul 12 07:33:48 PM PDT 24 |
| Finished | Jul 12 07:48:11 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-8ecc1888-4f28-45de-ad3e-b5075772fea2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386016566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_d evice_slow_rsp.386016566 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.4143339641 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 130410644 ps |
| CPU time | 15.04 seconds |
| Started | Jul 12 07:25:42 PM PDT 24 |
| Finished | Jul 12 07:26:01 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-21901910-2fce-4653-8ad4-10ccb8211bbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143339641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.4143339641 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.1209997966 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 580867762 ps |
| CPU time | 46.97 seconds |
| Started | Jul 12 07:25:41 PM PDT 24 |
| Finished | Jul 12 07:26:32 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-cf80970a-bd54-4f75-a867-10ab8d76a26f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209997966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1209997966 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.1062675114 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 798952820 ps |
| CPU time | 31.91 seconds |
| Started | Jul 12 07:25:40 PM PDT 24 |
| Finished | Jul 12 07:26:14 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-94080ecc-f01b-416f-b7c9-5a7a3db6875d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062675114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.1062675114 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1055862779 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 15960809068 ps |
| CPU time | 178.99 seconds |
| Started | Jul 12 07:25:45 PM PDT 24 |
| Finished | Jul 12 07:28:48 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-22c1eddf-7ed2-49ad-8d20-93deb96bfa9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055862779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.1055862779 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3917566374 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 61582980422 ps |
| CPU time | 1071.66 seconds |
| Started | Jul 12 07:25:44 PM PDT 24 |
| Finished | Jul 12 07:43:41 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-fc075aef-f548-4fbe-ae75-e921868475a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917566374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.3917566374 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3875016237 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 192805617 ps |
| CPU time | 17.62 seconds |
| Started | Jul 12 07:25:43 PM PDT 24 |
| Finished | Jul 12 07:26:05 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-e722a6a1-be88-4ff8-9636-74f58750a77b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875016237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.3875016237 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.2638602246 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 2740850718 ps |
| CPU time | 76.76 seconds |
| Started | Jul 12 07:25:41 PM PDT 24 |
| Finished | Jul 12 07:27:01 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-1ea27880-c0d0-4246-a878-827984209850 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638602246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2638602246 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.658671649 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 41660040 ps |
| CPU time | 6.28 seconds |
| Started | Jul 12 07:25:28 PM PDT 24 |
| Finished | Jul 12 07:25:37 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-c3c9cb3e-f97e-4ee2-9d3d-cf04fb16ce4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658671649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.658671649 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3961613004 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 7436514737 ps |
| CPU time | 81.01 seconds |
| Started | Jul 12 07:25:42 PM PDT 24 |
| Finished | Jul 12 07:27:06 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-d452dcd6-1c06-487b-938c-554548fe9452 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961613004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3961613004 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.4181908302 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 6927033597 ps |
| CPU time | 119.53 seconds |
| Started | Jul 12 07:25:42 PM PDT 24 |
| Finished | Jul 12 07:27:46 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-57b193c7-44fd-4511-954f-14d2f475c03e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181908302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.4181908302 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.628588845 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 47842439 ps |
| CPU time | 6.69 seconds |
| Started | Jul 12 07:25:47 PM PDT 24 |
| Finished | Jul 12 07:25:57 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-c864d78b-e50d-4581-a50f-9e354f5e838e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628588845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays .628588845 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.3124208978 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1117247366 ps |
| CPU time | 90.08 seconds |
| Started | Jul 12 07:25:42 PM PDT 24 |
| Finished | Jul 12 07:27:16 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-fda04e1d-ba1e-4e5b-b7ae-5cfbfdbfade3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124208978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3124208978 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.2219603469 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 3561666862 ps |
| CPU time | 252.34 seconds |
| Started | Jul 12 07:25:44 PM PDT 24 |
| Finished | Jul 12 07:30:01 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-6466bff9-e408-4451-b1d8-a8ac96fe6532 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219603469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2219603469 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3292930307 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 300607588 ps |
| CPU time | 87.38 seconds |
| Started | Jul 12 07:25:42 PM PDT 24 |
| Finished | Jul 12 07:27:14 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-a2c11b02-e68a-46d5-a20a-396452370f81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292930307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.3292930307 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3378677924 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 6032207252 ps |
| CPU time | 374.98 seconds |
| Started | Jul 12 07:27:37 PM PDT 24 |
| Finished | Jul 12 07:33:56 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-793d5b13-5898-49f3-b559-e371d86587c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378677924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.3378677924 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.3601562001 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 156306178 ps |
| CPU time | 9.46 seconds |
| Started | Jul 12 07:25:42 PM PDT 24 |
| Finished | Jul 12 07:25:56 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-f142cc01-2864-4c3e-ba92-568377fe93b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601562001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3601562001 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.3702208613 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 5987487848 ps |
| CPU time | 607.34 seconds |
| Started | Jul 12 07:25:55 PM PDT 24 |
| Finished | Jul 12 07:36:04 PM PDT 24 |
| Peak memory | 598116 kb |
| Host | smart-ea6e50c8-0056-466e-a0e5-447389ab296a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702208613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.3702208613 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.969649237 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 17230353187 ps |
| CPU time | 2068.29 seconds |
| Started | Jul 12 07:25:46 PM PDT 24 |
| Finished | Jul 12 08:00:19 PM PDT 24 |
| Peak memory | 593064 kb |
| Host | smart-8faadd0f-b5c4-43eb-b2c7-d5e94859697d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969649237 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 14.chip_same_csr_outstanding.969649237 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.3710509396 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 2345366893 ps |
| CPU time | 98.91 seconds |
| Started | Jul 12 07:25:45 PM PDT 24 |
| Finished | Jul 12 07:27:29 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-f54af3ca-67dd-4a00-9514-f8281df61483 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710509396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device .3710509396 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1648568976 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 79949675565 ps |
| CPU time | 1558.47 seconds |
| Started | Jul 12 07:25:53 PM PDT 24 |
| Finished | Jul 12 07:51:53 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-d3f5d591-4182-4dc9-bed0-56b493da7367 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648568976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.1648568976 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3919673268 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 71695667 ps |
| CPU time | 6.44 seconds |
| Started | Jul 12 07:25:56 PM PDT 24 |
| Finished | Jul 12 07:26:04 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-8daa2ef3-1aec-409b-8885-afa30bb63e2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919673268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add r.3919673268 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.2610463746 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 598312613 ps |
| CPU time | 22.96 seconds |
| Started | Jul 12 07:25:58 PM PDT 24 |
| Finished | Jul 12 07:26:22 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-361129e3-4ce0-4372-9b62-1d068ebb0c7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610463746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2610463746 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.3716940359 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 1329347406 ps |
| CPU time | 50.93 seconds |
| Started | Jul 12 07:25:41 PM PDT 24 |
| Finished | Jul 12 07:26:35 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-f1e84cda-cabe-4a62-ac9d-f579d2baf584 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716940359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.3716940359 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.1962055588 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 66827522750 ps |
| CPU time | 746.04 seconds |
| Started | Jul 12 07:25:44 PM PDT 24 |
| Finished | Jul 12 07:38:15 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-22ae7290-9577-4e29-86fa-c6a5dd9e3b4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962055588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.1962055588 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.3503545977 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 51842578746 ps |
| CPU time | 857.23 seconds |
| Started | Jul 12 07:25:42 PM PDT 24 |
| Finished | Jul 12 07:40:04 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-ed168c14-abee-4605-a031-a35213b3b97c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503545977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3503545977 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.1226947407 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 550427850 ps |
| CPU time | 46.81 seconds |
| Started | Jul 12 07:25:43 PM PDT 24 |
| Finished | Jul 12 07:26:34 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-3cd80ecc-771e-455d-a45d-42843fab4553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226947407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del ays.1226947407 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.1325336590 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 405334602 ps |
| CPU time | 30.52 seconds |
| Started | Jul 12 07:25:54 PM PDT 24 |
| Finished | Jul 12 07:26:26 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-ed28d42e-d7fb-42ac-88f5-9b80c8b48f7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325336590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1325336590 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.3617695187 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 51099634 ps |
| CPU time | 6.91 seconds |
| Started | Jul 12 07:25:40 PM PDT 24 |
| Finished | Jul 12 07:25:49 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-89fa7721-5120-4277-91c7-f380454b669d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617695187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3617695187 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.2875469396 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 5539314753 ps |
| CPU time | 57.84 seconds |
| Started | Jul 12 07:25:42 PM PDT 24 |
| Finished | Jul 12 07:26:44 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-cc306a18-186c-43a8-a27f-7bfb5ff006a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875469396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2875469396 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.4006820557 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 7039085946 ps |
| CPU time | 133.97 seconds |
| Started | Jul 12 07:25:44 PM PDT 24 |
| Finished | Jul 12 07:28:02 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-6c447066-70e2-4552-8b3a-0e9884c741e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006820557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.4006820557 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3070617914 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 47466331 ps |
| CPU time | 6.39 seconds |
| Started | Jul 12 07:25:43 PM PDT 24 |
| Finished | Jul 12 07:25:54 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-e06b20ec-7ba9-41dc-b7ad-cc5b0058175d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070617914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.3070617914 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.570677994 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 2198354407 ps |
| CPU time | 234.27 seconds |
| Started | Jul 12 07:25:54 PM PDT 24 |
| Finished | Jul 12 07:29:50 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-ce6a044b-0907-4802-82a3-2e1962c534fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570677994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.570677994 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.3275834983 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 4632148079 ps |
| CPU time | 154.36 seconds |
| Started | Jul 12 07:25:53 PM PDT 24 |
| Finished | Jul 12 07:28:29 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-c3a76a1b-edd9-4e42-baef-e7b67e8a12b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275834983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3275834983 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1722712538 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 3519798194 ps |
| CPU time | 215.05 seconds |
| Started | Jul 12 07:25:54 PM PDT 24 |
| Finished | Jul 12 07:29:30 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-65cb2d9b-59d0-496f-95d6-3a7d70480a83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722712538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.1722712538 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.1476696764 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 1358152892 ps |
| CPU time | 58.83 seconds |
| Started | Jul 12 07:25:52 PM PDT 24 |
| Finished | Jul 12 07:26:53 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-5a86668d-9cf1-4173-b8fc-dcdac4aff3d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476696764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1476696764 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.3772864477 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 3915301176 ps |
| CPU time | 320.36 seconds |
| Started | Jul 12 07:26:14 PM PDT 24 |
| Finished | Jul 12 07:31:39 PM PDT 24 |
| Peak memory | 597144 kb |
| Host | smart-9209ce19-1658-45b4-8a02-90c95008c000 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772864477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.3772864477 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.3661869771 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 3661599185 ps |
| CPU time | 155.28 seconds |
| Started | Jul 12 07:25:54 PM PDT 24 |
| Finished | Jul 12 07:28:31 PM PDT 24 |
| Peak memory | 603680 kb |
| Host | smart-2fcc52e9-661c-492b-bb29-45be8dcedb3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661869771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.3661869771 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.1365367006 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 1393238983 ps |
| CPU time | 62.35 seconds |
| Started | Jul 12 07:25:54 PM PDT 24 |
| Finished | Jul 12 07:26:59 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-9252086b-3b09-46b2-8ec7-2f61e37c4905 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365367006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device .1365367006 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3403127133 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 59652866370 ps |
| CPU time | 1075.39 seconds |
| Started | Jul 12 07:26:01 PM PDT 24 |
| Finished | Jul 12 07:43:58 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-1bccdfb4-3429-49e4-b152-dfa193f289cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403127133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_ device_slow_rsp.3403127133 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.3810668387 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 351683004 ps |
| CPU time | 37.11 seconds |
| Started | Jul 12 07:25:52 PM PDT 24 |
| Finished | Jul 12 07:26:30 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-b8911a2f-c9f7-472a-be56-4af564afde47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810668387 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.3810668387 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.3460806811 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 623323056 ps |
| CPU time | 46.88 seconds |
| Started | Jul 12 07:25:57 PM PDT 24 |
| Finished | Jul 12 07:26:45 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-394142a1-d6fd-4637-a8db-83b32e5d9d5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460806811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3460806811 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.3986103868 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 309171889 ps |
| CPU time | 24.34 seconds |
| Started | Jul 12 07:25:54 PM PDT 24 |
| Finished | Jul 12 07:26:20 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-a2f3ac66-de1a-436f-ab93-85face692c9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986103868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.3986103868 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.2812964518 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 90911662262 ps |
| CPU time | 989.42 seconds |
| Started | Jul 12 07:26:01 PM PDT 24 |
| Finished | Jul 12 07:42:32 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-2e92e0d7-098f-4125-b032-d2c4036f4661 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812964518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2812964518 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.2280616679 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 53771722769 ps |
| CPU time | 967.45 seconds |
| Started | Jul 12 07:26:01 PM PDT 24 |
| Finished | Jul 12 07:42:10 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-e4f366d8-240c-4b9f-91ed-fe323cb4df68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280616679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.2280616679 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.2521064454 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 478956598 ps |
| CPU time | 44.31 seconds |
| Started | Jul 12 07:25:55 PM PDT 24 |
| Finished | Jul 12 07:26:41 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-34ed1618-5ae6-451a-9a64-ee1aba8a15f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521064454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del ays.2521064454 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.2394486253 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 400282486 ps |
| CPU time | 32.39 seconds |
| Started | Jul 12 07:25:52 PM PDT 24 |
| Finished | Jul 12 07:26:26 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-7f445106-8dd1-489c-acfa-bd7cf542b1fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394486253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2394486253 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.31790786 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 43598268 ps |
| CPU time | 6.5 seconds |
| Started | Jul 12 07:25:54 PM PDT 24 |
| Finished | Jul 12 07:26:02 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-fc4d0355-974c-4f08-8d2d-2f2eaa95147f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31790786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.31790786 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.1978187901 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 5954638807 ps |
| CPU time | 69.2 seconds |
| Started | Jul 12 07:25:48 PM PDT 24 |
| Finished | Jul 12 07:27:00 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-5d62b01a-1960-4316-a4d7-60e98d9edcf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978187901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1978187901 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.1214865409 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 5109876995 ps |
| CPU time | 89.15 seconds |
| Started | Jul 12 07:25:58 PM PDT 24 |
| Finished | Jul 12 07:27:28 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-d421dab8-713e-4391-97c8-d48ae50b229e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214865409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1214865409 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.782902113 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 42895192 ps |
| CPU time | 5.82 seconds |
| Started | Jul 12 07:25:58 PM PDT 24 |
| Finished | Jul 12 07:26:05 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-51869cf6-6b09-40d3-9444-2ab38afb41c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782902113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays .782902113 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.1013393861 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 7025004457 ps |
| CPU time | 253.09 seconds |
| Started | Jul 12 07:25:59 PM PDT 24 |
| Finished | Jul 12 07:30:13 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-27d50225-c07c-4fcb-ab3e-b1d56dbeacdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013393861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1013393861 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.841672775 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 7212777936 ps |
| CPU time | 247.06 seconds |
| Started | Jul 12 07:25:53 PM PDT 24 |
| Finished | Jul 12 07:30:02 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-edeb316c-8042-4e65-a6cb-eb9d749a1571 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841672775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.841672775 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2542059878 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 10110303147 ps |
| CPU time | 452.06 seconds |
| Started | Jul 12 07:25:54 PM PDT 24 |
| Finished | Jul 12 07:33:27 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-545a3257-4aa8-4bb4-9454-7675ba32d874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542059878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_rand_reset.2542059878 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.312332212 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 229616698 ps |
| CPU time | 100.07 seconds |
| Started | Jul 12 07:25:55 PM PDT 24 |
| Finished | Jul 12 07:27:37 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-980d6cf4-e204-446f-8f5b-6ff0a38cd9f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312332212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_reset_error.312332212 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.413408924 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 284253586 ps |
| CPU time | 31.22 seconds |
| Started | Jul 12 07:25:56 PM PDT 24 |
| Finished | Jul 12 07:26:28 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-90cd05c6-ef50-4f72-a2b7-577a546c2e17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413408924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.413408924 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.4243421757 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 5887334500 ps |
| CPU time | 620.29 seconds |
| Started | Jul 12 07:26:15 PM PDT 24 |
| Finished | Jul 12 07:36:40 PM PDT 24 |
| Peak memory | 598732 kb |
| Host | smart-aecae1a0-fbee-459a-a65f-c7720ce27d7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243421757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.4243421757 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.2195824731 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 17303391361 ps |
| CPU time | 2515.69 seconds |
| Started | Jul 12 07:26:07 PM PDT 24 |
| Finished | Jul 12 08:08:05 PM PDT 24 |
| Peak memory | 593108 kb |
| Host | smart-106ca503-66dc-415a-93ad-cd76a1215f6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195824731 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.2195824731 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.2002998031 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 2498029353 ps |
| CPU time | 106.1 seconds |
| Started | Jul 12 07:26:15 PM PDT 24 |
| Finished | Jul 12 07:28:05 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-5869b95f-c771-45c9-9a47-9d122df0fc04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002998031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device .2002998031 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.2128873625 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 79797651987 ps |
| CPU time | 1307.85 seconds |
| Started | Jul 12 07:26:12 PM PDT 24 |
| Finished | Jul 12 07:48:05 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-699795d5-48b0-4e2d-b2c7-575708951334 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128873625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.2128873625 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.2294158549 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 87706028 ps |
| CPU time | 10.61 seconds |
| Started | Jul 12 07:26:09 PM PDT 24 |
| Finished | Jul 12 07:26:22 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-64676009-7bab-47bd-8234-1b611840fb75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294158549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add r.2294158549 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.3496861527 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 1291547558 ps |
| CPU time | 44.1 seconds |
| Started | Jul 12 07:26:07 PM PDT 24 |
| Finished | Jul 12 07:26:54 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-f9e053e5-4851-42e3-8aee-3502c23f15ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496861527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3496861527 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.4192598025 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2397352531 ps |
| CPU time | 98.32 seconds |
| Started | Jul 12 07:26:11 PM PDT 24 |
| Finished | Jul 12 07:27:55 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-7d20b4f8-8408-451f-95d4-b715857e730b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192598025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.4192598025 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.3578176211 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 27500935796 ps |
| CPU time | 304.16 seconds |
| Started | Jul 12 07:26:14 PM PDT 24 |
| Finished | Jul 12 07:31:23 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-e5fd627b-91ee-4fcb-8ec6-a27232b11e2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578176211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3578176211 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.3830898902 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 13925914251 ps |
| CPU time | 236.18 seconds |
| Started | Jul 12 07:26:05 PM PDT 24 |
| Finished | Jul 12 07:30:03 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-998ec3a5-d581-40f6-837b-18f47e8a97b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830898902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3830898902 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.4115667052 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 133003838 ps |
| CPU time | 13.89 seconds |
| Started | Jul 12 07:26:07 PM PDT 24 |
| Finished | Jul 12 07:26:23 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-d2c4483d-464d-488d-a22a-ba00afa2fc0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115667052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.4115667052 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.184857504 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 694090500 ps |
| CPU time | 23.75 seconds |
| Started | Jul 12 07:26:04 PM PDT 24 |
| Finished | Jul 12 07:26:30 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-aa3d196f-5fab-4aef-8cc2-8b43f86639de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184857504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.184857504 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.2887414977 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 37631884 ps |
| CPU time | 5.74 seconds |
| Started | Jul 12 07:26:06 PM PDT 24 |
| Finished | Jul 12 07:26:14 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-49fe60f7-c177-4ad7-b769-3b71308ac28e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887414977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2887414977 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.1743394693 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 10084739273 ps |
| CPU time | 108.48 seconds |
| Started | Jul 12 07:26:11 PM PDT 24 |
| Finished | Jul 12 07:28:04 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-79e4b753-1929-4291-b654-d021ebe0a5e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743394693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1743394693 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1931301049 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 5004286316 ps |
| CPU time | 92.25 seconds |
| Started | Jul 12 07:26:04 PM PDT 24 |
| Finished | Jul 12 07:27:38 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-992b385f-2265-4782-87ab-6037a1d67ea0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931301049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1931301049 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.834028816 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 42215189 ps |
| CPU time | 6.04 seconds |
| Started | Jul 12 07:26:05 PM PDT 24 |
| Finished | Jul 12 07:26:13 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-62df0f57-1454-4b8f-b390-1bfff8b06938 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834028816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays .834028816 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.4209446798 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 2367320449 ps |
| CPU time | 88.49 seconds |
| Started | Jul 12 07:26:09 PM PDT 24 |
| Finished | Jul 12 07:27:40 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-8406372c-f314-4304-9476-66aacd27f2ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209446798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.4209446798 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.3954158605 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 2217794904 ps |
| CPU time | 147.85 seconds |
| Started | Jul 12 07:26:04 PM PDT 24 |
| Finished | Jul 12 07:28:34 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-980a3a3d-fc52-4270-9445-bc8c54fd65ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954158605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_rand_reset.3954158605 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1590292637 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 94406970 ps |
| CPU time | 22.88 seconds |
| Started | Jul 12 07:26:07 PM PDT 24 |
| Finished | Jul 12 07:26:33 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-8bc32308-d223-4d02-a2eb-4ecb32b8cb28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590292637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.1590292637 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.3397886965 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 513881011 ps |
| CPU time | 23.96 seconds |
| Started | Jul 12 07:26:50 PM PDT 24 |
| Finished | Jul 12 07:27:17 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-6248407d-8163-4a8b-84dd-bd89436627c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397886965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3397886965 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.2048631134 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 4474462068 ps |
| CPU time | 332.83 seconds |
| Started | Jul 12 07:26:13 PM PDT 24 |
| Finished | Jul 12 07:31:51 PM PDT 24 |
| Peak memory | 597140 kb |
| Host | smart-fc711b38-c1ee-4c4f-a800-c26d5c027b9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048631134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.2048631134 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.134576151 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 29319619574 ps |
| CPU time | 4568.51 seconds |
| Started | Jul 12 07:26:03 PM PDT 24 |
| Finished | Jul 12 08:42:14 PM PDT 24 |
| Peak memory | 593120 kb |
| Host | smart-e4636e20-979f-4adb-90ee-58a7d0b2c88f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134576151 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 17.chip_same_csr_outstanding.134576151 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.1242102783 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 3710652698 ps |
| CPU time | 223.03 seconds |
| Started | Jul 12 07:26:05 PM PDT 24 |
| Finished | Jul 12 07:29:51 PM PDT 24 |
| Peak memory | 598684 kb |
| Host | smart-8ea916a6-feb5-49de-8cdf-8cce5c038ee1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242102783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.1242102783 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.3259977753 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 2512460337 ps |
| CPU time | 113.31 seconds |
| Started | Jul 12 07:26:14 PM PDT 24 |
| Finished | Jul 12 07:28:12 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-53fe5f18-e08c-46df-b7e2-50a3cdec1cff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259977753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .3259977753 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1602081122 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 64190839896 ps |
| CPU time | 1213.39 seconds |
| Started | Jul 12 07:26:17 PM PDT 24 |
| Finished | Jul 12 07:46:34 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-bc2e749e-bf7c-4b13-a0ce-9673f771c2cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602081122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_ device_slow_rsp.1602081122 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.3345815172 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 245825879 ps |
| CPU time | 12.42 seconds |
| Started | Jul 12 07:26:13 PM PDT 24 |
| Finished | Jul 12 07:26:30 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-db055bac-8638-4f54-add0-7a17cfedb54e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345815172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.3345815172 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.1795891539 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 504395082 ps |
| CPU time | 36.28 seconds |
| Started | Jul 12 07:26:17 PM PDT 24 |
| Finished | Jul 12 07:26:57 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-fef61aff-c4e6-4144-9037-9eec61a67c34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795891539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1795891539 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.2432558179 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 299021648 ps |
| CPU time | 30.74 seconds |
| Started | Jul 12 07:26:02 PM PDT 24 |
| Finished | Jul 12 07:26:35 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-cf9bf47b-3d07-433b-9671-54d681c4d594 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432558179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.2432558179 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.661994872 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 33766833461 ps |
| CPU time | 373.51 seconds |
| Started | Jul 12 07:26:15 PM PDT 24 |
| Finished | Jul 12 07:32:32 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-1f4cbd59-d882-485f-ac65-b662bba2167a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661994872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.661994872 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.718635756 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 12517554130 ps |
| CPU time | 215.51 seconds |
| Started | Jul 12 07:26:12 PM PDT 24 |
| Finished | Jul 12 07:29:52 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-a06f1190-ec92-4545-a402-643273124ebe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718635756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.718635756 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.2177270059 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 79827492 ps |
| CPU time | 9.89 seconds |
| Started | Jul 12 07:26:17 PM PDT 24 |
| Finished | Jul 12 07:26:31 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-77556fd0-673b-4200-bef2-e6027c92e3b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177270059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del ays.2177270059 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.3868150984 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1589580379 ps |
| CPU time | 49.18 seconds |
| Started | Jul 12 07:26:16 PM PDT 24 |
| Finished | Jul 12 07:27:09 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-dc063947-07d8-46c6-8b25-df295cc6399b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868150984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3868150984 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.230289353 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 232683941 ps |
| CPU time | 9.89 seconds |
| Started | Jul 12 07:28:26 PM PDT 24 |
| Finished | Jul 12 07:28:46 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-d872f148-e92f-415a-aa8c-1c1fdcd7ffdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230289353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.230289353 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.2082138815 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 5365564703 ps |
| CPU time | 58.32 seconds |
| Started | Jul 12 07:26:02 PM PDT 24 |
| Finished | Jul 12 07:27:02 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-835c761d-b88b-4b8e-b057-b7faa64fab7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082138815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2082138815 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.3804310122 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 5722406378 ps |
| CPU time | 107.24 seconds |
| Started | Jul 12 07:26:03 PM PDT 24 |
| Finished | Jul 12 07:27:52 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-2ac66ec0-03f8-4f55-ade5-5dbfdb92b93f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804310122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3804310122 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.368198499 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 41257699 ps |
| CPU time | 5.74 seconds |
| Started | Jul 12 07:26:06 PM PDT 24 |
| Finished | Jul 12 07:26:14 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-1c03de6f-9ff4-44d7-9e23-7c19dafcea1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368198499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays .368198499 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.3524901340 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 3995657490 ps |
| CPU time | 164.13 seconds |
| Started | Jul 12 07:26:16 PM PDT 24 |
| Finished | Jul 12 07:29:04 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-fe9eed04-477a-4a06-a3d8-b0a4d6199dfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524901340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3524901340 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.2121561114 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1225767964 ps |
| CPU time | 87.68 seconds |
| Started | Jul 12 07:26:15 PM PDT 24 |
| Finished | Jul 12 07:27:47 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-2d0d8557-8f2d-4bfb-893b-a3149c15d11e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121561114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2121561114 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.1394802571 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 626610255 ps |
| CPU time | 278.81 seconds |
| Started | Jul 12 07:26:13 PM PDT 24 |
| Finished | Jul 12 07:30:57 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-bc642076-00c9-4e44-a608-3ddf90ed29d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394802571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_rand_reset.1394802571 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.4105844340 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 1395052383 ps |
| CPU time | 168.69 seconds |
| Started | Jul 12 07:26:15 PM PDT 24 |
| Finished | Jul 12 07:29:08 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-b904a737-ab6e-4a72-86d4-c4989cec1aa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105844340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_al l_with_reset_error.4105844340 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.178658076 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 26575752 ps |
| CPU time | 5.83 seconds |
| Started | Jul 12 07:26:12 PM PDT 24 |
| Finished | Jul 12 07:26:23 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-2adc0337-9448-45ce-b13d-dc4cd6e0aafb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178658076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.178658076 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.2210176123 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 4921801455 ps |
| CPU time | 466.9 seconds |
| Started | Jul 12 07:26:38 PM PDT 24 |
| Finished | Jul 12 07:34:29 PM PDT 24 |
| Peak memory | 599184 kb |
| Host | smart-0c5fe416-47bb-488a-a864-73005800af89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210176123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.2210176123 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.3297566097 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 16645707774 ps |
| CPU time | 2002.17 seconds |
| Started | Jul 12 07:26:13 PM PDT 24 |
| Finished | Jul 12 07:59:41 PM PDT 24 |
| Peak memory | 593024 kb |
| Host | smart-51c75dae-5c53-447c-aa42-aa26682127a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297566097 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.3297566097 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.1235453240 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 4131994228 ps |
| CPU time | 389.1 seconds |
| Started | Jul 12 07:26:17 PM PDT 24 |
| Finished | Jul 12 07:32:50 PM PDT 24 |
| Peak memory | 598640 kb |
| Host | smart-b0b28156-41f0-4668-95f8-94448b780767 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235453240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.1235453240 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.3461857676 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 619167241 ps |
| CPU time | 29.88 seconds |
| Started | Jul 12 07:26:22 PM PDT 24 |
| Finished | Jul 12 07:26:55 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-f1da9540-0a47-4179-a352-ff792d53744e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461857676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .3461857676 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3795508136 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 95886528259 ps |
| CPU time | 1760.01 seconds |
| Started | Jul 12 07:26:25 PM PDT 24 |
| Finished | Jul 12 07:55:47 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-ae4d447e-4578-4cc3-9bbe-c0eb7094578c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795508136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.3795508136 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.1732938902 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 307962257 ps |
| CPU time | 16.72 seconds |
| Started | Jul 12 07:26:25 PM PDT 24 |
| Finished | Jul 12 07:26:44 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-0e33f935-bf74-47ae-9540-d7731a6a58a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732938902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add r.1732938902 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.433347809 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 2342535351 ps |
| CPU time | 74.52 seconds |
| Started | Jul 12 07:26:25 PM PDT 24 |
| Finished | Jul 12 07:27:42 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-1a6485cf-5dcf-49bb-bfe9-43e7cbfaa76c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433347809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.433347809 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.274347028 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 2127865016 ps |
| CPU time | 81.29 seconds |
| Started | Jul 12 07:26:23 PM PDT 24 |
| Finished | Jul 12 07:27:47 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-ba005273-247a-4552-a19a-ffd2f8a8604b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274347028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.274347028 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.2996547770 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 104776500147 ps |
| CPU time | 1196.8 seconds |
| Started | Jul 12 07:26:24 PM PDT 24 |
| Finished | Jul 12 07:46:24 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-c5453168-cd52-4fa2-acd8-7f01b259262b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996547770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2996547770 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.611469818 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 20433776905 ps |
| CPU time | 374.65 seconds |
| Started | Jul 12 07:26:23 PM PDT 24 |
| Finished | Jul 12 07:32:41 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-ebf68fff-6b31-40df-8ba7-7c8461acfa69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611469818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.611469818 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.3112124650 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 319858282 ps |
| CPU time | 25.96 seconds |
| Started | Jul 12 07:26:23 PM PDT 24 |
| Finished | Jul 12 07:26:51 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-0b3a3a34-d973-47d0-9121-5c98ce3ce274 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112124650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.3112124650 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.1222141321 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 1231454936 ps |
| CPU time | 31.86 seconds |
| Started | Jul 12 07:26:24 PM PDT 24 |
| Finished | Jul 12 07:26:59 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-07350495-caef-475c-b749-e89fa6aa83e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222141321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1222141321 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.3442003812 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 190372098 ps |
| CPU time | 8.73 seconds |
| Started | Jul 12 07:26:25 PM PDT 24 |
| Finished | Jul 12 07:26:36 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-171d3a8a-4e23-4afc-aab1-64b81bdfd03f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442003812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3442003812 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.3443230928 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 5335574128 ps |
| CPU time | 61.68 seconds |
| Started | Jul 12 07:26:26 PM PDT 24 |
| Finished | Jul 12 07:27:30 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-2f6f5a96-8f83-4e3a-948c-8b95f74e097c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443230928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3443230928 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.1884871360 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 6762247310 ps |
| CPU time | 114.94 seconds |
| Started | Jul 12 07:26:25 PM PDT 24 |
| Finished | Jul 12 07:28:22 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-921a1bc9-fbd8-4b44-b674-a669b73c5797 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884871360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1884871360 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.97899525 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 55642081 ps |
| CPU time | 6.58 seconds |
| Started | Jul 12 07:26:24 PM PDT 24 |
| Finished | Jul 12 07:26:34 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-0776a370-1b24-4f77-aa37-c43ab3c3ca7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97899525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.97899525 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.2506317617 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 571735887 ps |
| CPU time | 61.36 seconds |
| Started | Jul 12 07:26:25 PM PDT 24 |
| Finished | Jul 12 07:27:29 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-25162c69-ac4e-4c3f-8a0b-19c0deb588b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506317617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2506317617 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.3434954002 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 12434755899 ps |
| CPU time | 418.17 seconds |
| Started | Jul 12 07:26:26 PM PDT 24 |
| Finished | Jul 12 07:33:26 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-a2b3a7f1-33f1-4643-9c7c-cac81ae53ae6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434954002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3434954002 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1819047143 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 251033693 ps |
| CPU time | 121.27 seconds |
| Started | Jul 12 07:26:25 PM PDT 24 |
| Finished | Jul 12 07:28:28 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-16d1a02c-feae-4c4b-a785-a29149220f20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819047143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.1819047143 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.52106448 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 6811548 ps |
| CPU time | 6.88 seconds |
| Started | Jul 12 07:26:37 PM PDT 24 |
| Finished | Jul 12 07:26:47 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-e0fcd07f-ef67-4be2-9c30-48cea7fed25a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52106448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_ with_reset_error.52106448 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.4217867824 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 1470429150 ps |
| CPU time | 60.2 seconds |
| Started | Jul 12 07:26:21 PM PDT 24 |
| Finished | Jul 12 07:27:25 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-4b80debc-5a41-4551-b2d8-d3a005adb1c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217867824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.4217867824 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.2543991568 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 4984669481 ps |
| CPU time | 403.16 seconds |
| Started | Jul 12 07:26:42 PM PDT 24 |
| Finished | Jul 12 07:33:29 PM PDT 24 |
| Peak memory | 598352 kb |
| Host | smart-2ee5ba6b-dee2-47d8-9c3e-dd79086c75f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543991568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.2543991568 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.273063921 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 16104638213 ps |
| CPU time | 2311.32 seconds |
| Started | Jul 12 07:26:34 PM PDT 24 |
| Finished | Jul 12 08:05:10 PM PDT 24 |
| Peak memory | 592976 kb |
| Host | smart-371bc28e-bd97-4036-9713-7ae4ad75162e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273063921 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 19.chip_same_csr_outstanding.273063921 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.63159284 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 3610452015 ps |
| CPU time | 196.35 seconds |
| Started | Jul 12 07:26:33 PM PDT 24 |
| Finished | Jul 12 07:29:54 PM PDT 24 |
| Peak memory | 603652 kb |
| Host | smart-8e557a36-405e-4f3b-8bfb-7139f0e600f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63159284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.63159284 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.3074680011 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 522888193 ps |
| CPU time | 50.07 seconds |
| Started | Jul 12 07:26:34 PM PDT 24 |
| Finished | Jul 12 07:27:29 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-ec2e9496-d671-4ced-95a2-ecf4f3255d1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074680011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device .3074680011 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.4222669740 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 171838684867 ps |
| CPU time | 3026.88 seconds |
| Started | Jul 12 07:26:49 PM PDT 24 |
| Finished | Jul 12 08:17:18 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-c1e32374-de9b-4ace-b875-143be2d01518 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222669740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_ device_slow_rsp.4222669740 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.1633712206 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 38843312 ps |
| CPU time | 6.53 seconds |
| Started | Jul 12 07:26:43 PM PDT 24 |
| Finished | Jul 12 07:26:53 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-a8c26f7d-8e28-490e-ba27-5db442f6a3f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633712206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add r.1633712206 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.1971642995 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 38898006 ps |
| CPU time | 5.96 seconds |
| Started | Jul 12 07:26:40 PM PDT 24 |
| Finished | Jul 12 07:26:50 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-eaaabfb2-7c7b-4643-9968-ae47f8cb8373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971642995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1971642995 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.581459388 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 518651159 ps |
| CPU time | 19.88 seconds |
| Started | Jul 12 07:26:34 PM PDT 24 |
| Finished | Jul 12 07:26:59 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-7645758a-9c75-45d2-9323-dd7a17c1cafa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581459388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.581459388 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.1172389715 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 23521218224 ps |
| CPU time | 253.34 seconds |
| Started | Jul 12 07:26:35 PM PDT 24 |
| Finished | Jul 12 07:30:53 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-58d731f3-0908-47e1-86c8-d90a099dd674 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172389715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1172389715 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.2601108373 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 42892422563 ps |
| CPU time | 724.02 seconds |
| Started | Jul 12 07:26:33 PM PDT 24 |
| Finished | Jul 12 07:38:42 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-a95fc7ac-1f81-4347-978e-1d256a25a718 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601108373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2601108373 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.1736933270 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 206599511 ps |
| CPU time | 20.42 seconds |
| Started | Jul 12 07:26:33 PM PDT 24 |
| Finished | Jul 12 07:26:58 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-cccdcb78-d4d7-447e-9701-1c504e48ec0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736933270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del ays.1736933270 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.201535089 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 429739497 ps |
| CPU time | 29.07 seconds |
| Started | Jul 12 07:26:42 PM PDT 24 |
| Finished | Jul 12 07:27:14 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-6efa069f-24f7-4b2f-b2a2-f059cb66a84c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201535089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.201535089 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.1207305549 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 44078766 ps |
| CPU time | 5.72 seconds |
| Started | Jul 12 07:26:37 PM PDT 24 |
| Finished | Jul 12 07:26:46 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-a4bcfda8-5dba-427a-963e-9e4cbb5d0d14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207305549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1207305549 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.4155408431 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 7301984228 ps |
| CPU time | 75.96 seconds |
| Started | Jul 12 07:26:35 PM PDT 24 |
| Finished | Jul 12 07:27:55 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-6cbbcbc6-6251-4611-9aed-4cf0f3f23287 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155408431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.4155408431 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.628424453 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 5058449220 ps |
| CPU time | 85.95 seconds |
| Started | Jul 12 07:26:32 PM PDT 24 |
| Finished | Jul 12 07:28:03 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-fbac64c3-9121-439f-8db7-11c463eba1d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628424453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.628424453 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.2316192682 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 44459525 ps |
| CPU time | 6.78 seconds |
| Started | Jul 12 07:26:32 PM PDT 24 |
| Finished | Jul 12 07:26:44 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-514b51c8-33c1-455f-bcce-80c5313f9854 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316192682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.2316192682 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.2586918933 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 475396726 ps |
| CPU time | 49.32 seconds |
| Started | Jul 12 07:26:41 PM PDT 24 |
| Finished | Jul 12 07:27:34 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-bb0414d9-f48c-491e-a806-583f5f7b2d6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586918933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2586918933 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.3529252332 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 7600846480 ps |
| CPU time | 283.04 seconds |
| Started | Jul 12 07:26:43 PM PDT 24 |
| Finished | Jul 12 07:31:30 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-d2a245fc-428c-4efd-b3aa-146954bb402a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529252332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3529252332 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.408134133 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 3162906679 ps |
| CPU time | 494.15 seconds |
| Started | Jul 12 07:26:47 PM PDT 24 |
| Finished | Jul 12 07:35:04 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-b1529527-d356-481d-a15a-e63c2b3b5082 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408134133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_ with_rand_reset.408134133 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3251302805 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 139833091 ps |
| CPU time | 18.31 seconds |
| Started | Jul 12 07:26:42 PM PDT 24 |
| Finished | Jul 12 07:27:04 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-28cdfb35-cb30-42d3-a158-1b23a8006303 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251302805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.3251302805 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.3859581683 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 90720115 ps |
| CPU time | 11.38 seconds |
| Started | Jul 12 07:26:48 PM PDT 24 |
| Finished | Jul 12 07:27:02 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-f332ef1c-1a74-4183-87c2-564e8970a0f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859581683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3859581683 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.1872428624 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 56166884738 ps |
| CPU time | 9924.6 seconds |
| Started | Jul 12 07:23:32 PM PDT 24 |
| Finished | Jul 12 10:09:01 PM PDT 24 |
| Peak memory | 640568 kb |
| Host | smart-d99fcfab-98fb-4113-8abf-c7703e82ac16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872428624 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.chip_csr_aliasing.1872428624 |
| Directory | /workspace/2.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.506538120 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 7875587770 ps |
| CPU time | 803.43 seconds |
| Started | Jul 12 07:23:30 PM PDT 24 |
| Finished | Jul 12 07:36:57 PM PDT 24 |
| Peak memory | 593040 kb |
| Host | smart-b680271d-146f-46bb-a808-2b31b3fd7a57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506538120 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.506538120 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3409568652 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 5272576476 ps |
| CPU time | 215.21 seconds |
| Started | Jul 12 07:23:41 PM PDT 24 |
| Finished | Jul 12 07:27:18 PM PDT 24 |
| Peak memory | 660436 kb |
| Host | smart-75d6ed22-8b4e-4757-aebb-947bcdbe8d2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409568652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.3409568652 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.2716253805 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 5840508970 ps |
| CPU time | 628.31 seconds |
| Started | Jul 12 07:23:40 PM PDT 24 |
| Finished | Jul 12 07:34:11 PM PDT 24 |
| Peak memory | 598276 kb |
| Host | smart-ecf37533-a502-468d-a2c8-ad501a6f1e4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716253805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.2716253805 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.1709808795 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 3389175320 ps |
| CPU time | 120.93 seconds |
| Started | Jul 12 07:23:30 PM PDT 24 |
| Finished | Jul 12 07:25:35 PM PDT 24 |
| Peak memory | 589464 kb |
| Host | smart-d43df44c-25e6-43d3-8126-04ef9fba1f91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709808795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.1709808795 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.1858221943 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 11565067654 ps |
| CPU time | 504.61 seconds |
| Started | Jul 12 07:23:30 PM PDT 24 |
| Finished | Jul 12 07:31:59 PM PDT 24 |
| Peak memory | 591240 kb |
| Host | smart-c1b50328-3b78-48a2-8253-947d5ccef957 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858221943 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.1858221943 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.2926536836 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 28871292278 ps |
| CPU time | 4564.38 seconds |
| Started | Jul 12 07:23:29 PM PDT 24 |
| Finished | Jul 12 08:39:38 PM PDT 24 |
| Peak memory | 593488 kb |
| Host | smart-0c2c062f-959f-4b2a-a37c-090079296cb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926536836 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.2926536836 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.3018558626 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 3808439818 ps |
| CPU time | 277.94 seconds |
| Started | Jul 12 07:23:31 PM PDT 24 |
| Finished | Jul 12 07:28:12 PM PDT 24 |
| Peak memory | 603688 kb |
| Host | smart-9afac604-c3ef-4b20-9c83-bb2a0ffce29c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018558626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.3018558626 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.4053151847 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 742460785 ps |
| CPU time | 55.96 seconds |
| Started | Jul 12 07:23:31 PM PDT 24 |
| Finished | Jul 12 07:24:31 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-165f1dac-0d47-4722-b60c-e43e1b49a3eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053151847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device. 4053151847 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2920101848 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 84593008092 ps |
| CPU time | 1470.32 seconds |
| Started | Jul 12 07:23:41 PM PDT 24 |
| Finished | Jul 12 07:48:13 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-79a6f04a-5a33-42e8-9675-cd35b1691520 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920101848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.2920101848 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.4138414754 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 573048222 ps |
| CPU time | 24.94 seconds |
| Started | Jul 12 07:23:40 PM PDT 24 |
| Finished | Jul 12 07:24:07 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-44dfdfe2-55e5-4ef6-906d-9ea2d1800462 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138414754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .4138414754 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.1495921473 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 173467884 ps |
| CPU time | 9.46 seconds |
| Started | Jul 12 07:23:39 PM PDT 24 |
| Finished | Jul 12 07:23:50 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-1e5f3b08-2a1d-4d1d-9159-7b7966786b05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495921473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1495921473 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.1238090162 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 1483743025 ps |
| CPU time | 49.57 seconds |
| Started | Jul 12 07:23:29 PM PDT 24 |
| Finished | Jul 12 07:24:23 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-d1ccb9e7-7bc2-41d0-849a-d3ae4cce594d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238090162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.1238090162 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.3988250878 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 80042912158 ps |
| CPU time | 872.51 seconds |
| Started | Jul 12 07:23:33 PM PDT 24 |
| Finished | Jul 12 07:38:09 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-1a09ae14-b2c1-44be-ba69-e2af1a14652a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988250878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3988250878 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.498429226 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 35706745916 ps |
| CPU time | 590.45 seconds |
| Started | Jul 12 07:23:32 PM PDT 24 |
| Finished | Jul 12 07:33:26 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-1b5be4bb-cb22-4bd3-b9ba-ede8ba401e95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498429226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.498429226 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.4196986454 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 200384080 ps |
| CPU time | 18.68 seconds |
| Started | Jul 12 07:23:33 PM PDT 24 |
| Finished | Jul 12 07:23:55 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-f681aaf8-c9ef-4b6d-8fbd-01c198267fa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196986454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.4196986454 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.1870642100 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 170375761 ps |
| CPU time | 13.24 seconds |
| Started | Jul 12 07:23:37 PM PDT 24 |
| Finished | Jul 12 07:23:51 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-a94ebfe9-8967-4518-9036-735cd4a85b50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870642100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1870642100 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.753038600 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 42385041 ps |
| CPU time | 6.35 seconds |
| Started | Jul 12 07:23:28 PM PDT 24 |
| Finished | Jul 12 07:23:38 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-acdd24bd-f0a8-4fa3-9d06-04a533f83e97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753038600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.753038600 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.660960867 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 5763100332 ps |
| CPU time | 61.3 seconds |
| Started | Jul 12 07:23:31 PM PDT 24 |
| Finished | Jul 12 07:24:37 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-63bacead-efb2-4b9c-bf01-52bd9e5f3f2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660960867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.660960867 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.1166826696 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 3520088584 ps |
| CPU time | 61.3 seconds |
| Started | Jul 12 07:23:31 PM PDT 24 |
| Finished | Jul 12 07:24:36 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-f6319e1f-b774-4c63-97cb-0786926c6631 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166826696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1166826696 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.1716229340 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 50055030 ps |
| CPU time | 6.3 seconds |
| Started | Jul 12 07:23:30 PM PDT 24 |
| Finished | Jul 12 07:23:41 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-0d56e3d9-eac6-4186-9ea9-92c27bf92321 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716229340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .1716229340 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.3469696063 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 12123865041 ps |
| CPU time | 471.58 seconds |
| Started | Jul 12 07:23:38 PM PDT 24 |
| Finished | Jul 12 07:31:31 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-8aed23d0-c482-446f-b51b-0c2b1bf596e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469696063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3469696063 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.3074087797 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 4894613058 ps |
| CPU time | 359.82 seconds |
| Started | Jul 12 07:23:39 PM PDT 24 |
| Finished | Jul 12 07:29:40 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-9ab15b2e-24d6-4ced-9675-24d7be0e5ef7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074087797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3074087797 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.4230665527 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 4635173730 ps |
| CPU time | 325.39 seconds |
| Started | Jul 12 07:23:42 PM PDT 24 |
| Finished | Jul 12 07:29:09 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-8ec0e206-1c20-4f3e-9de3-a3205b9b1ba0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230665527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_rand_reset.4230665527 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.1249664600 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 139558095 ps |
| CPU time | 69.1 seconds |
| Started | Jul 12 07:23:41 PM PDT 24 |
| Finished | Jul 12 07:24:52 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-7f688bdc-38c9-4451-884d-5f442300c087 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249664600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.1249664600 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.3560116793 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 143240463 ps |
| CPU time | 18.16 seconds |
| Started | Jul 12 07:23:40 PM PDT 24 |
| Finished | Jul 12 07:24:00 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-ba469b1a-26a4-414f-96dd-36666717389e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560116793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3560116793 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.3403776845 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 2251195111 ps |
| CPU time | 102.32 seconds |
| Started | Jul 12 07:26:44 PM PDT 24 |
| Finished | Jul 12 07:28:30 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-34fa396d-34bd-4963-809c-a95c9fe5541c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403776845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .3403776845 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.2601097204 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 30672437657 ps |
| CPU time | 527.85 seconds |
| Started | Jul 12 07:26:52 PM PDT 24 |
| Finished | Jul 12 07:35:43 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-2262bd8f-a8f1-448b-bb48-1066045a5a2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601097204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_ device_slow_rsp.2601097204 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.1855310040 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 1014764594 ps |
| CPU time | 46.2 seconds |
| Started | Jul 12 07:26:52 PM PDT 24 |
| Finished | Jul 12 07:27:42 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-ae2d9f26-244a-4787-8fc4-7e9fd18f7b31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855310040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.1855310040 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.3694761131 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 1426505541 ps |
| CPU time | 52.54 seconds |
| Started | Jul 12 07:26:52 PM PDT 24 |
| Finished | Jul 12 07:27:47 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-65e16f6e-d372-44fc-8e10-9043a514d10f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694761131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3694761131 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.2152925499 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 1085742725 ps |
| CPU time | 43.87 seconds |
| Started | Jul 12 07:26:47 PM PDT 24 |
| Finished | Jul 12 07:27:33 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-0857a343-3166-4792-97b2-681691a12f65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152925499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.2152925499 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.1244543732 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 50156980602 ps |
| CPU time | 564.89 seconds |
| Started | Jul 12 07:26:46 PM PDT 24 |
| Finished | Jul 12 07:36:13 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-09297576-6a17-4904-974a-c3375b72ad15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244543732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1244543732 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.3240466712 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 10246419928 ps |
| CPU time | 182.52 seconds |
| Started | Jul 12 07:26:45 PM PDT 24 |
| Finished | Jul 12 07:29:50 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-b7591004-f26d-45d1-9717-7e2452cc0789 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240466712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3240466712 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.3488171113 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 278639389 ps |
| CPU time | 25.67 seconds |
| Started | Jul 12 07:26:41 PM PDT 24 |
| Finished | Jul 12 07:27:10 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-a6b16cb0-da3f-4080-996f-78c6408a6d7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488171113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.3488171113 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.2746915450 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 154367245 ps |
| CPU time | 13.27 seconds |
| Started | Jul 12 07:26:52 PM PDT 24 |
| Finished | Jul 12 07:27:08 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-5b66684b-6d2f-4c0c-b251-934ba9a03e7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746915450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2746915450 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.1135776445 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 188517788 ps |
| CPU time | 9.15 seconds |
| Started | Jul 12 07:26:41 PM PDT 24 |
| Finished | Jul 12 07:26:54 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-3bb90621-6d6f-403a-b045-05b050df34ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135776445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1135776445 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.2515060230 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 4580048477 ps |
| CPU time | 49.38 seconds |
| Started | Jul 12 07:26:48 PM PDT 24 |
| Finished | Jul 12 07:27:40 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-6d70c4da-1d54-4783-be0f-4cc0dbc152b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515060230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2515060230 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.1169196757 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 4974298242 ps |
| CPU time | 87.41 seconds |
| Started | Jul 12 07:26:48 PM PDT 24 |
| Finished | Jul 12 07:28:18 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-66aca5ea-dd4f-4ad8-bf4a-64a91e47985f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169196757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1169196757 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.4208283195 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 51660641 ps |
| CPU time | 6.35 seconds |
| Started | Jul 12 07:26:42 PM PDT 24 |
| Finished | Jul 12 07:26:51 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-6c96675e-c91d-45b2-874e-12029a70507d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208283195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.4208283195 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.158665434 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 9275007540 ps |
| CPU time | 359.7 seconds |
| Started | Jul 12 07:26:52 PM PDT 24 |
| Finished | Jul 12 07:32:55 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-445be5c3-2253-4e43-94e8-16a410645cd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158665434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.158665434 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.1153831937 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 2490580132 ps |
| CPU time | 219.89 seconds |
| Started | Jul 12 07:26:53 PM PDT 24 |
| Finished | Jul 12 07:30:36 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-e5130d48-0fcc-4dc7-a0b7-2653e0fc5c85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153831937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1153831937 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.4142813289 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 278437699 ps |
| CPU time | 82.05 seconds |
| Started | Jul 12 07:26:51 PM PDT 24 |
| Finished | Jul 12 07:28:16 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-ff73aff4-3db6-4c5b-a500-478cffc36a95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142813289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_rand_reset.4142813289 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.3235003715 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 8011287828 ps |
| CPU time | 361.55 seconds |
| Started | Jul 12 07:26:54 PM PDT 24 |
| Finished | Jul 12 07:32:59 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-ef7164e6-753f-43db-832a-6df90588fcd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235003715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al l_with_reset_error.3235003715 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.1626017117 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 839015314 ps |
| CPU time | 39.03 seconds |
| Started | Jul 12 07:26:51 PM PDT 24 |
| Finished | Jul 12 07:27:34 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-b70fadd8-84f4-45f8-b73f-a69fbb34f5e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626017117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1626017117 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.1084750754 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 3523458738 ps |
| CPU time | 198.02 seconds |
| Started | Jul 12 07:26:51 PM PDT 24 |
| Finished | Jul 12 07:30:13 PM PDT 24 |
| Peak memory | 603644 kb |
| Host | smart-9902f501-3a90-4e5b-8309-7fd77ddb8d1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084750754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.1084750754 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.2362008834 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 2785689315 ps |
| CPU time | 115.62 seconds |
| Started | Jul 12 07:27:17 PM PDT 24 |
| Finished | Jul 12 07:29:16 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-856f7e07-c967-4744-a460-dd10cf3a6091 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362008834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device .2362008834 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.1941477399 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 77178494017 ps |
| CPU time | 1360.93 seconds |
| Started | Jul 12 07:27:03 PM PDT 24 |
| Finished | Jul 12 07:49:46 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-d42837ee-582f-498e-b477-84afb5ff4ba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941477399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.1941477399 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.1352391641 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 121952135 ps |
| CPU time | 16.32 seconds |
| Started | Jul 12 07:27:04 PM PDT 24 |
| Finished | Jul 12 07:27:23 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-8536265b-a21b-403c-97c4-bfa680022cc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352391641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.1352391641 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.154589506 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 452628984 ps |
| CPU time | 35.87 seconds |
| Started | Jul 12 07:27:01 PM PDT 24 |
| Finished | Jul 12 07:27:38 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-8a7684e5-1397-4715-ad58-9fc92fd21049 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154589506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.154589506 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.1073582436 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 580717550 ps |
| CPU time | 54 seconds |
| Started | Jul 12 07:27:08 PM PDT 24 |
| Finished | Jul 12 07:28:04 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-070623b1-cad8-47f4-8cf6-ac43dc70541e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073582436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.1073582436 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.845657560 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 29924038827 ps |
| CPU time | 337.95 seconds |
| Started | Jul 12 07:27:05 PM PDT 24 |
| Finished | Jul 12 07:32:45 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-1860541a-ba8e-441c-8444-8635b76a887d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845657560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.845657560 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.3710754941 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 55396893257 ps |
| CPU time | 1036.26 seconds |
| Started | Jul 12 07:27:11 PM PDT 24 |
| Finished | Jul 12 07:44:31 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-2722e761-a2bf-48da-8dc2-5dfb0b5c6714 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710754941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3710754941 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.1285288241 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 464035631 ps |
| CPU time | 43.21 seconds |
| Started | Jul 12 07:27:01 PM PDT 24 |
| Finished | Jul 12 07:27:46 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-22b95fdf-8a8c-4624-a4e0-42ecbbf9ec5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285288241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del ays.1285288241 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.1300304878 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 549539101 ps |
| CPU time | 18.05 seconds |
| Started | Jul 12 07:27:05 PM PDT 24 |
| Finished | Jul 12 07:27:26 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-a8f1afb5-171c-460a-aaf0-808f1e388a1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300304878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1300304878 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.80760752 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 198629352 ps |
| CPU time | 8.88 seconds |
| Started | Jul 12 07:26:53 PM PDT 24 |
| Finished | Jul 12 07:27:05 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-70042d8e-92ed-48cc-b3c0-0cd5f6f18c09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80760752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.80760752 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.3540596446 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 8254072333 ps |
| CPU time | 98.52 seconds |
| Started | Jul 12 07:26:53 PM PDT 24 |
| Finished | Jul 12 07:28:35 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-07caae9e-3539-4d76-b644-2082b138c004 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540596446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3540596446 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.3562996300 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 5548858046 ps |
| CPU time | 99.37 seconds |
| Started | Jul 12 07:26:53 PM PDT 24 |
| Finished | Jul 12 07:28:36 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-d601e883-b377-4b1d-ad4f-90096f2b1393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562996300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3562996300 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.709319810 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 49631648 ps |
| CPU time | 7.02 seconds |
| Started | Jul 12 07:27:21 PM PDT 24 |
| Finished | Jul 12 07:27:32 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-02a4599b-246a-415f-b5f9-80b1eaa0de88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709319810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays .709319810 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.3883118807 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1545080504 ps |
| CPU time | 136.83 seconds |
| Started | Jul 12 07:27:16 PM PDT 24 |
| Finished | Jul 12 07:29:36 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-7a8ea9fc-b5a1-4b82-bf34-4f67b0a3f1ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883118807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3883118807 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.3761922955 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 10884434286 ps |
| CPU time | 357.02 seconds |
| Started | Jul 12 07:27:05 PM PDT 24 |
| Finished | Jul 12 07:33:04 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-a9b7d858-587b-46d4-942d-2989ba831a85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761922955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3761922955 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.2293686791 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 68872814 ps |
| CPU time | 10.24 seconds |
| Started | Jul 12 07:27:01 PM PDT 24 |
| Finished | Jul 12 07:27:13 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-89129e7c-7827-45f7-aee2-165d445ecae8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293686791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.2293686791 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.1419874321 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 4925031291 ps |
| CPU time | 546.07 seconds |
| Started | Jul 12 07:27:00 PM PDT 24 |
| Finished | Jul 12 07:36:07 PM PDT 24 |
| Peak memory | 582516 kb |
| Host | smart-9f71215c-9341-4dac-8879-889ad7f15c16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419874321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al l_with_reset_error.1419874321 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.3781155721 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 227280868 ps |
| CPU time | 11.57 seconds |
| Started | Jul 12 07:27:15 PM PDT 24 |
| Finished | Jul 12 07:27:30 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-363ffa40-3968-489c-a3ea-69ac07a812ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781155721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3781155721 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.642597028 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 3598151462 ps |
| CPU time | 160.17 seconds |
| Started | Jul 12 07:27:10 PM PDT 24 |
| Finished | Jul 12 07:29:53 PM PDT 24 |
| Peak memory | 603652 kb |
| Host | smart-52492842-77a2-485a-a3ca-16aee5826033 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642597028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.642597028 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.320465097 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 669118736 ps |
| CPU time | 52.14 seconds |
| Started | Jul 12 07:27:12 PM PDT 24 |
| Finished | Jul 12 07:28:09 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-bd2f1955-4b6b-4f6b-a378-14638dc396cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320465097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device. 320465097 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.2500492055 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 11118333889 ps |
| CPU time | 195.68 seconds |
| Started | Jul 12 07:27:17 PM PDT 24 |
| Finished | Jul 12 07:30:36 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-8d1b0f43-7f61-4bd9-99ee-752b9b00d774 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500492055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.2500492055 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.4031675462 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 417271577 ps |
| CPU time | 19.77 seconds |
| Started | Jul 12 07:27:11 PM PDT 24 |
| Finished | Jul 12 07:27:35 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-172ddecc-82ed-478e-9efd-ba36fd4864b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031675462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add r.4031675462 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.1382380244 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 680764665 ps |
| CPU time | 25.05 seconds |
| Started | Jul 12 07:27:18 PM PDT 24 |
| Finished | Jul 12 07:27:46 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-e58a8fe0-f9cb-43d8-a116-1179c34ec354 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382380244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1382380244 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.829993239 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 34073091 ps |
| CPU time | 6.15 seconds |
| Started | Jul 12 07:27:11 PM PDT 24 |
| Finished | Jul 12 07:27:21 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-55d76504-9ebc-4db9-be5b-4b6949544d94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829993239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.829993239 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.2339865942 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 61935377162 ps |
| CPU time | 664.21 seconds |
| Started | Jul 12 07:27:16 PM PDT 24 |
| Finished | Jul 12 07:38:24 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-f6bf8e3e-20e8-4fdf-b91c-abd2af32873f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339865942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2339865942 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.2130747681 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 57356409316 ps |
| CPU time | 864.71 seconds |
| Started | Jul 12 07:27:10 PM PDT 24 |
| Finished | Jul 12 07:41:37 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-81f49f32-6993-4e25-91a9-dd5bc9e6f3c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130747681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2130747681 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.3919644078 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 550602558 ps |
| CPU time | 45.34 seconds |
| Started | Jul 12 07:27:16 PM PDT 24 |
| Finished | Jul 12 07:28:05 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-004e33e8-45c3-4ba7-a101-65f6d3a815e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919644078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.3919644078 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.3830998829 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 79259299 ps |
| CPU time | 9.3 seconds |
| Started | Jul 12 07:27:10 PM PDT 24 |
| Finished | Jul 12 07:27:23 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-7c106924-5f1f-4518-a762-156ac7a0de60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830998829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3830998829 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.1927179485 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 42238863 ps |
| CPU time | 6.05 seconds |
| Started | Jul 12 07:27:16 PM PDT 24 |
| Finished | Jul 12 07:27:26 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-88486d19-9ce4-49bd-87dc-5aacfa7d921e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927179485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1927179485 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.4231514206 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 6663941960 ps |
| CPU time | 75.97 seconds |
| Started | Jul 12 07:27:19 PM PDT 24 |
| Finished | Jul 12 07:28:38 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-b3faa233-0d07-4f9c-aff5-138049b1e5ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231514206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.4231514206 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.4219786675 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 4738921517 ps |
| CPU time | 82.61 seconds |
| Started | Jul 12 07:27:14 PM PDT 24 |
| Finished | Jul 12 07:28:41 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-0f36c267-9837-45ce-8654-b619559a2b32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219786675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.4219786675 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.1040917527 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 39070349 ps |
| CPU time | 6.09 seconds |
| Started | Jul 12 07:27:12 PM PDT 24 |
| Finished | Jul 12 07:27:22 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-b4ec6f5a-65e2-4b67-8cde-808af9eb5a74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040917527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.1040917527 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.2024765521 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 2192722379 ps |
| CPU time | 181.72 seconds |
| Started | Jul 12 07:27:12 PM PDT 24 |
| Finished | Jul 12 07:30:18 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-e2bbd30d-f00d-45b2-b7ae-5e9c54e6fadc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024765521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2024765521 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.3764842508 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 7055754477 ps |
| CPU time | 226.32 seconds |
| Started | Jul 12 07:27:30 PM PDT 24 |
| Finished | Jul 12 07:31:20 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-8a906e12-c40e-4ddf-bcfb-c48eea476c69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764842508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3764842508 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.1605799732 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 2238756386 ps |
| CPU time | 166.29 seconds |
| Started | Jul 12 07:27:30 PM PDT 24 |
| Finished | Jul 12 07:30:20 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-37a638d4-e54f-4b9f-9ae1-d99f6075aadd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605799732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.1605799732 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.2453436302 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 1166128955 ps |
| CPU time | 50.48 seconds |
| Started | Jul 12 07:27:10 PM PDT 24 |
| Finished | Jul 12 07:28:03 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-65643c69-a68b-41ed-9777-b19c1f318d00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453436302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2453436302 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.526502310 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 2643094119 ps |
| CPU time | 102.52 seconds |
| Started | Jul 12 07:27:29 PM PDT 24 |
| Finished | Jul 12 07:29:16 PM PDT 24 |
| Peak memory | 599564 kb |
| Host | smart-95aca531-1a63-451a-b75c-30fc4cc7da53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526502310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.526502310 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.701737160 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 1990437150 ps |
| CPU time | 81.36 seconds |
| Started | Jul 12 07:27:39 PM PDT 24 |
| Finished | Jul 12 07:29:03 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-bfa1e0cb-8cf8-4a9e-ad84-0229de4b8df1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701737160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device. 701737160 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.4101852140 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 20589055199 ps |
| CPU time | 370.45 seconds |
| Started | Jul 12 07:27:40 PM PDT 24 |
| Finished | Jul 12 07:33:53 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-d5a05005-7163-47e5-a407-0b5cfe7de565 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101852140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_ device_slow_rsp.4101852140 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.1467375331 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 381855884 ps |
| CPU time | 18.28 seconds |
| Started | Jul 12 07:27:40 PM PDT 24 |
| Finished | Jul 12 07:28:01 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-e00b4950-0d69-4eb7-83c4-761d4909e476 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467375331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.1467375331 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.1078947472 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 559627178 ps |
| CPU time | 23.52 seconds |
| Started | Jul 12 07:27:42 PM PDT 24 |
| Finished | Jul 12 07:28:09 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-2ff9d58c-6883-485a-9902-a1f792a34db6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078947472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1078947472 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.154435442 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 2595172636 ps |
| CPU time | 83.44 seconds |
| Started | Jul 12 07:27:30 PM PDT 24 |
| Finished | Jul 12 07:28:57 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-808b3665-0f7a-4c8d-ba02-a2efd8c0122d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154435442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.154435442 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.119803101 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 102600575298 ps |
| CPU time | 1280.33 seconds |
| Started | Jul 12 07:27:32 PM PDT 24 |
| Finished | Jul 12 07:48:56 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-5b1fda2f-5496-442c-959f-c05f26785c89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119803101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.119803101 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.3276996410 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 53011735381 ps |
| CPU time | 943.11 seconds |
| Started | Jul 12 07:27:32 PM PDT 24 |
| Finished | Jul 12 07:43:18 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-e22c33b8-3259-43ca-abbb-813a78b60efe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276996410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3276996410 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.3955185968 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 275552118 ps |
| CPU time | 23.09 seconds |
| Started | Jul 12 07:27:29 PM PDT 24 |
| Finished | Jul 12 07:27:56 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-d8ea6d44-1839-46ab-9ae5-794f32845f51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955185968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.3955185968 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.2628516108 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 402471144 ps |
| CPU time | 14.8 seconds |
| Started | Jul 12 07:28:34 PM PDT 24 |
| Finished | Jul 12 07:28:59 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-533e06ae-e35c-420e-aa41-89fb3b23ab2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628516108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2628516108 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.4078712922 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 41271290 ps |
| CPU time | 6.06 seconds |
| Started | Jul 12 07:27:30 PM PDT 24 |
| Finished | Jul 12 07:27:40 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-df22962f-64ee-4c5c-9713-15b2f2ece099 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078712922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.4078712922 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.1003215338 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 9482810940 ps |
| CPU time | 101.24 seconds |
| Started | Jul 12 07:27:29 PM PDT 24 |
| Finished | Jul 12 07:29:14 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-ad857284-9f4c-4e2e-a9b1-89f4afae4339 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003215338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1003215338 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.3987941184 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 5484024315 ps |
| CPU time | 94.4 seconds |
| Started | Jul 12 07:27:29 PM PDT 24 |
| Finished | Jul 12 07:29:07 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-7821a203-0b6b-44ab-b34b-7e664c627a76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987941184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3987941184 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.568365095 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 47247537 ps |
| CPU time | 6.27 seconds |
| Started | Jul 12 07:27:31 PM PDT 24 |
| Finished | Jul 12 07:27:40 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-757080aa-e6dc-446d-b3a7-af5756be348c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568365095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays .568365095 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.2226759068 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 5663719066 ps |
| CPU time | 206.86 seconds |
| Started | Jul 12 07:27:40 PM PDT 24 |
| Finished | Jul 12 07:31:10 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-8ee3e1e9-07a4-4b74-a609-513ab4c7efee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226759068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2226759068 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.1850804086 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 7814532113 ps |
| CPU time | 285.33 seconds |
| Started | Jul 12 07:27:40 PM PDT 24 |
| Finished | Jul 12 07:32:28 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-51b0ffb9-6e41-4040-96d7-fc3e21153c11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850804086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1850804086 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.3594839317 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 88195157 ps |
| CPU time | 26.54 seconds |
| Started | Jul 12 07:27:43 PM PDT 24 |
| Finished | Jul 12 07:28:12 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-f4cf8db5-4f65-4f9f-8dca-cf5ffb968c0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594839317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_rand_reset.3594839317 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.3969069323 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 70235801 ps |
| CPU time | 14.6 seconds |
| Started | Jul 12 07:27:41 PM PDT 24 |
| Finished | Jul 12 07:27:58 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-b15d5fe0-172a-4517-acb0-e1f65e0cd08a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969069323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.3969069323 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.1678362420 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 154217129 ps |
| CPU time | 21.78 seconds |
| Started | Jul 12 07:27:42 PM PDT 24 |
| Finished | Jul 12 07:28:07 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-9991dd64-bdf0-4c69-ac90-1c3f3b36adfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678362420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1678362420 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.2608735438 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 2861617352 ps |
| CPU time | 97.8 seconds |
| Started | Jul 12 07:27:41 PM PDT 24 |
| Finished | Jul 12 07:29:21 PM PDT 24 |
| Peak memory | 598504 kb |
| Host | smart-ab2f0f75-4297-40fe-93e5-190d2c589ee5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608735438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.2608735438 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.213271484 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 3602843346 ps |
| CPU time | 147.44 seconds |
| Started | Jul 12 07:27:43 PM PDT 24 |
| Finished | Jul 12 07:30:14 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-f10fe9a4-8190-42ba-847f-f7c50de92b0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213271484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device. 213271484 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.2260381290 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 71980954839 ps |
| CPU time | 1232.86 seconds |
| Started | Jul 12 07:27:48 PM PDT 24 |
| Finished | Jul 12 07:48:28 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-cdf6e8d3-2cba-4cdc-aa4e-418f4ccfe0de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260381290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.2260381290 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.1965723587 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 86640927 ps |
| CPU time | 11.54 seconds |
| Started | Jul 12 07:27:44 PM PDT 24 |
| Finished | Jul 12 07:27:59 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-2660b703-263c-4e1f-95e1-83aece6478c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965723587 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.1965723587 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.973889650 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 198226163 ps |
| CPU time | 17.63 seconds |
| Started | Jul 12 07:27:45 PM PDT 24 |
| Finished | Jul 12 07:28:06 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-e03ffa0d-ac79-44d2-9a12-808b09391c2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973889650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.973889650 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.235117408 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 1059846802 ps |
| CPU time | 39.09 seconds |
| Started | Jul 12 07:27:45 PM PDT 24 |
| Finished | Jul 12 07:28:28 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-a3843d70-049d-4e75-a535-eb72c1aa6b3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235117408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.235117408 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.1251488385 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 36419145812 ps |
| CPU time | 409.73 seconds |
| Started | Jul 12 07:27:43 PM PDT 24 |
| Finished | Jul 12 07:34:37 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-8b5313ed-92b9-4390-9e19-e22f7caf41af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251488385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1251488385 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.2829811218 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 46618246024 ps |
| CPU time | 820.59 seconds |
| Started | Jul 12 07:27:47 PM PDT 24 |
| Finished | Jul 12 07:41:35 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-d80ffc4e-0806-4da2-8592-69b09a0a6067 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829811218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2829811218 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.2658451471 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 423071083 ps |
| CPU time | 40.32 seconds |
| Started | Jul 12 07:27:49 PM PDT 24 |
| Finished | Jul 12 07:28:36 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-a801748f-9150-43ab-be9b-6d89883f605e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658451471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.2658451471 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.2034670954 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 2256142504 ps |
| CPU time | 64.84 seconds |
| Started | Jul 12 07:27:44 PM PDT 24 |
| Finished | Jul 12 07:28:52 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-43b89e77-60fb-44ad-bd39-c3697b680b67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034670954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.2034670954 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.3285167036 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 40808326 ps |
| CPU time | 5.9 seconds |
| Started | Jul 12 07:27:39 PM PDT 24 |
| Finished | Jul 12 07:27:48 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-3f5aaad9-ac50-4088-ad4a-6ae554fcf6c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285167036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3285167036 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.2713725663 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 7531834103 ps |
| CPU time | 90.82 seconds |
| Started | Jul 12 07:27:48 PM PDT 24 |
| Finished | Jul 12 07:29:27 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-5b772083-0907-49c9-bd2e-b981136368bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713725663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2713725663 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.1928381002 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 5902981745 ps |
| CPU time | 98.21 seconds |
| Started | Jul 12 07:27:50 PM PDT 24 |
| Finished | Jul 12 07:29:36 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-ad8628d0-010d-4727-8f5c-1e4a4f4e7b60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928381002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1928381002 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.363228172 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 44680548 ps |
| CPU time | 6.44 seconds |
| Started | Jul 12 07:27:41 PM PDT 24 |
| Finished | Jul 12 07:27:50 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-dd410b5f-dd78-428b-bf5b-1cb6b3cd21d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363228172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays .363228172 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.4083242420 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 14453320526 ps |
| CPU time | 511.01 seconds |
| Started | Jul 12 07:27:45 PM PDT 24 |
| Finished | Jul 12 07:36:20 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-561590b0-a0ab-41a6-8202-8497818ea6d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083242420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.4083242420 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.2379168307 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 10739759045 ps |
| CPU time | 410.83 seconds |
| Started | Jul 12 07:27:43 PM PDT 24 |
| Finished | Jul 12 07:34:37 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-99e0b106-fe8f-4742-9785-67b64b16e6d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379168307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2379168307 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.2347021334 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 5589292768 ps |
| CPU time | 214.87 seconds |
| Started | Jul 12 07:27:47 PM PDT 24 |
| Finished | Jul 12 07:31:29 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-9885ec0f-f252-4809-ad09-ad2aa9fe04c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347021334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_rand_reset.2347021334 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.1580804095 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 839624130 ps |
| CPU time | 40.06 seconds |
| Started | Jul 12 07:27:45 PM PDT 24 |
| Finished | Jul 12 07:28:30 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-973f952b-1f7b-4b51-89f7-2919aedbd294 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580804095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1580804095 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.2890033400 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 841452738 ps |
| CPU time | 70.83 seconds |
| Started | Jul 12 07:27:46 PM PDT 24 |
| Finished | Jul 12 07:29:04 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-f075dab0-e1f6-4bda-a580-f16bf53ca1d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890033400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device .2890033400 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.476266635 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 36493299331 ps |
| CPU time | 682.35 seconds |
| Started | Jul 12 07:27:48 PM PDT 24 |
| Finished | Jul 12 07:39:18 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-097aae05-e817-4136-ad1c-5ab16985a895 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476266635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_d evice_slow_rsp.476266635 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.2454151624 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 773113378 ps |
| CPU time | 27.61 seconds |
| Started | Jul 12 07:27:50 PM PDT 24 |
| Finished | Jul 12 07:28:26 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-a6f36438-f299-4299-8e91-35adadf79413 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454151624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.2454151624 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.2821987552 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 892158891 ps |
| CPU time | 28.98 seconds |
| Started | Jul 12 07:27:51 PM PDT 24 |
| Finished | Jul 12 07:28:28 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-68b4c0ac-2d06-4165-95d9-5b6b153a0af5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821987552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2821987552 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.564815054 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 1879781259 ps |
| CPU time | 74.95 seconds |
| Started | Jul 12 07:27:48 PM PDT 24 |
| Finished | Jul 12 07:29:11 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-8c071468-1a65-4fd0-a057-ca76a445e232 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564815054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.564815054 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.3501783952 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 95835067729 ps |
| CPU time | 1186.12 seconds |
| Started | Jul 12 07:27:48 PM PDT 24 |
| Finished | Jul 12 07:47:42 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-9544fbdc-15c3-4f24-a226-b95eba9caa86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501783952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3501783952 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.3041729808 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 67944841908 ps |
| CPU time | 1232.14 seconds |
| Started | Jul 12 07:27:45 PM PDT 24 |
| Finished | Jul 12 07:48:22 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-5b662668-124c-4987-b61b-1d9f5730a44d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041729808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3041729808 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.2215832568 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 37439756 ps |
| CPU time | 6.48 seconds |
| Started | Jul 12 07:27:47 PM PDT 24 |
| Finished | Jul 12 07:28:01 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-d4cfc71e-23bd-4b90-be5d-2de98bd14e00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215832568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del ays.2215832568 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.3645865972 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1209139917 ps |
| CPU time | 36.65 seconds |
| Started | Jul 12 07:27:48 PM PDT 24 |
| Finished | Jul 12 07:28:31 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-e497d89a-b4f8-4ff6-9227-700a12b6421b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645865972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3645865972 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.1043018688 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 43589986 ps |
| CPU time | 6.06 seconds |
| Started | Jul 12 07:27:44 PM PDT 24 |
| Finished | Jul 12 07:27:54 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-5bab98ad-2bd4-471c-a777-192291983e52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043018688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1043018688 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.3452197317 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 6768527685 ps |
| CPU time | 74.61 seconds |
| Started | Jul 12 07:27:47 PM PDT 24 |
| Finished | Jul 12 07:29:08 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-9f8aaa12-671e-45d1-8481-0452e6ec4dd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452197317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3452197317 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.2269687574 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 4020777742 ps |
| CPU time | 77.09 seconds |
| Started | Jul 12 07:27:47 PM PDT 24 |
| Finished | Jul 12 07:29:11 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-f72fb2c8-52cd-40ae-84d5-e9ce2c3cb952 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269687574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2269687574 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.2475689602 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 51053191 ps |
| CPU time | 6.4 seconds |
| Started | Jul 12 07:27:48 PM PDT 24 |
| Finished | Jul 12 07:28:02 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-75cf35fd-385e-4ec6-8732-6d1822de133c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475689602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay s.2475689602 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.2077675545 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 6518324170 ps |
| CPU time | 242.08 seconds |
| Started | Jul 12 07:27:48 PM PDT 24 |
| Finished | Jul 12 07:31:58 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-bcfe04aa-4fd3-4c17-8304-ca69e6c61d66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077675545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2077675545 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.2464904634 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 4808254241 ps |
| CPU time | 169.72 seconds |
| Started | Jul 12 07:27:48 PM PDT 24 |
| Finished | Jul 12 07:30:46 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-9d2e2f42-5a76-455e-ac48-cf1b6f8fb5b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464904634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2464904634 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1893346021 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 574677613 ps |
| CPU time | 204.33 seconds |
| Started | Jul 12 07:27:47 PM PDT 24 |
| Finished | Jul 12 07:31:18 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-04c7efcb-488d-4f89-9f4c-c727dd2d06e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893346021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.1893346021 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.3247780105 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 544632208 ps |
| CPU time | 159.82 seconds |
| Started | Jul 12 07:27:47 PM PDT 24 |
| Finished | Jul 12 07:30:33 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-74bfbefa-b04a-452b-800e-9dae11505b4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247780105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.3247780105 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.3621426960 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 89511126 ps |
| CPU time | 11.87 seconds |
| Started | Jul 12 07:27:52 PM PDT 24 |
| Finished | Jul 12 07:28:12 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-3dccb7d9-64e7-46f7-a226-8acdc6519b98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621426960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3621426960 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.3543342722 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 3268059519 ps |
| CPU time | 180.58 seconds |
| Started | Jul 12 07:27:48 PM PDT 24 |
| Finished | Jul 12 07:30:56 PM PDT 24 |
| Peak memory | 603736 kb |
| Host | smart-820104a1-15c0-4dfe-9e06-2fa1156818f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543342722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.3543342722 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.2859243275 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 1435044278 ps |
| CPU time | 73.08 seconds |
| Started | Jul 12 07:27:57 PM PDT 24 |
| Finished | Jul 12 07:29:17 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-0a26705f-b618-4ede-bb7f-a528813e8d9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859243275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .2859243275 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.4177360387 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 330118495 ps |
| CPU time | 33.12 seconds |
| Started | Jul 12 07:28:03 PM PDT 24 |
| Finished | Jul 12 07:28:44 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-a72aa031-fac2-4ccb-9d7a-28313f430139 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177360387 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.4177360387 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.2665579010 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 155354927 ps |
| CPU time | 15.92 seconds |
| Started | Jul 12 07:28:00 PM PDT 24 |
| Finished | Jul 12 07:28:23 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-163ba54b-f38e-4ce3-ad6a-be0540bb833f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665579010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2665579010 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.493914585 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 213347381 ps |
| CPU time | 18.66 seconds |
| Started | Jul 12 07:27:57 PM PDT 24 |
| Finished | Jul 12 07:28:22 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-2e3e621c-1182-4c1d-974b-6c2f8f133211 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493914585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.493914585 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.1635539290 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 61918303931 ps |
| CPU time | 705.5 seconds |
| Started | Jul 12 07:27:58 PM PDT 24 |
| Finished | Jul 12 07:39:51 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-b4184b18-5288-46f4-8c7d-9e22b94876e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635539290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1635539290 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.4004337388 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 67939899125 ps |
| CPU time | 1122.68 seconds |
| Started | Jul 12 07:28:00 PM PDT 24 |
| Finished | Jul 12 07:46:50 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-4b536273-bdbc-4482-827d-e546bbb43239 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004337388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.4004337388 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.4241992142 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 458532870 ps |
| CPU time | 41.26 seconds |
| Started | Jul 12 07:27:58 PM PDT 24 |
| Finished | Jul 12 07:28:47 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-aa642356-5aa6-4c72-9c6d-99a477e5ffe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241992142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.4241992142 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.280341652 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 351511166 ps |
| CPU time | 28.05 seconds |
| Started | Jul 12 07:27:59 PM PDT 24 |
| Finished | Jul 12 07:28:34 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-a29f95cb-77be-4e96-81f8-0067bca40b00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280341652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.280341652 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.121064953 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 218442725 ps |
| CPU time | 10.05 seconds |
| Started | Jul 12 07:27:50 PM PDT 24 |
| Finished | Jul 12 07:28:08 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-52d0769d-433e-448c-886f-0081387b5fe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121064953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.121064953 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.1981469698 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 9344555967 ps |
| CPU time | 105.9 seconds |
| Started | Jul 12 07:27:48 PM PDT 24 |
| Finished | Jul 12 07:29:42 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-93a380ff-d081-4ebc-b83e-f5f16c013742 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981469698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1981469698 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.2683151075 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 4843350901 ps |
| CPU time | 84.64 seconds |
| Started | Jul 12 07:27:50 PM PDT 24 |
| Finished | Jul 12 07:29:23 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-97612a33-15d3-49af-acd3-d6ba0be59911 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683151075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.2683151075 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.1108347780 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 49237365 ps |
| CPU time | 6.75 seconds |
| Started | Jul 12 07:27:47 PM PDT 24 |
| Finished | Jul 12 07:28:01 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-6b020f6e-5782-48ed-95c3-2875995004ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108347780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.1108347780 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.3296025473 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 576585394 ps |
| CPU time | 22.05 seconds |
| Started | Jul 12 07:27:58 PM PDT 24 |
| Finished | Jul 12 07:28:27 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-8c4dd365-bd49-46dc-851d-feed7431b5ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296025473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3296025473 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.1598496747 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 12355272199 ps |
| CPU time | 460.34 seconds |
| Started | Jul 12 07:28:00 PM PDT 24 |
| Finished | Jul 12 07:35:49 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-e21ad1da-1ebb-4820-a65b-c20848f1f27e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598496747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1598496747 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.2004935649 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 306176676 ps |
| CPU time | 131.99 seconds |
| Started | Jul 12 07:28:00 PM PDT 24 |
| Finished | Jul 12 07:30:19 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-54c47c53-fa95-47c2-b1b8-c2d5d7f34f26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004935649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.2004935649 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.581880671 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 1246403745 ps |
| CPU time | 152.36 seconds |
| Started | Jul 12 07:28:02 PM PDT 24 |
| Finished | Jul 12 07:30:42 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-41a7d1fe-8bf7-40ab-976c-eeeac8d91aae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581880671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_reset_error.581880671 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.2846886004 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 1339361147 ps |
| CPU time | 53.95 seconds |
| Started | Jul 12 07:27:59 PM PDT 24 |
| Finished | Jul 12 07:29:01 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-ce1c6946-3781-400c-be72-fa9c4fb20b5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846886004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2846886004 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.474278039 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 3003099512 ps |
| CPU time | 181.19 seconds |
| Started | Jul 12 07:27:58 PM PDT 24 |
| Finished | Jul 12 07:31:07 PM PDT 24 |
| Peak memory | 603608 kb |
| Host | smart-0e55d971-d76f-4a9c-aedc-8e011e3edde6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474278039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.474278039 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.1598527761 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 544166828 ps |
| CPU time | 37.74 seconds |
| Started | Jul 12 07:28:03 PM PDT 24 |
| Finished | Jul 12 07:28:49 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-88cd2475-ab8c-49da-8fcb-a1f65946e8c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598527761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device .1598527761 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.3088681569 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 81087272030 ps |
| CPU time | 1554.72 seconds |
| Started | Jul 12 07:28:03 PM PDT 24 |
| Finished | Jul 12 07:54:06 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-b91bbaa9-bf9d-49a4-a5da-8b99f3687cdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088681569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.3088681569 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.2504071224 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 406068200 ps |
| CPU time | 16.31 seconds |
| Started | Jul 12 07:28:06 PM PDT 24 |
| Finished | Jul 12 07:28:31 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-ec6f0a59-c3f0-41a9-b697-a0d6abd8a621 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504071224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.2504071224 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.429707245 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 1491107418 ps |
| CPU time | 50.16 seconds |
| Started | Jul 12 07:28:12 PM PDT 24 |
| Finished | Jul 12 07:29:11 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-853e7907-5dac-4e51-a8ce-03ff9c967ffa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429707245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.429707245 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.3581945787 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 390514850 ps |
| CPU time | 36.08 seconds |
| Started | Jul 12 07:27:59 PM PDT 24 |
| Finished | Jul 12 07:28:42 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-6f9148af-6161-4772-8468-6a09d8e3041f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581945787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.3581945787 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.1275715193 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 52338002193 ps |
| CPU time | 566.18 seconds |
| Started | Jul 12 07:28:04 PM PDT 24 |
| Finished | Jul 12 07:37:38 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-8cb77d60-f206-4c39-b8b8-264f38c969d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275715193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1275715193 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.1360521275 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 65821610783 ps |
| CPU time | 1252.23 seconds |
| Started | Jul 12 07:28:03 PM PDT 24 |
| Finished | Jul 12 07:49:04 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-3f14b54d-5db6-4485-a2e5-1f0bc58fa80e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360521275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1360521275 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.4203944100 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 94184025 ps |
| CPU time | 11.69 seconds |
| Started | Jul 12 07:27:57 PM PDT 24 |
| Finished | Jul 12 07:28:16 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-d22b7aad-ffbf-48c1-afdb-3b455200b0be |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203944100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del ays.4203944100 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.2672453494 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 217417955 ps |
| CPU time | 17.13 seconds |
| Started | Jul 12 07:28:03 PM PDT 24 |
| Finished | Jul 12 07:28:28 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-ff196fd0-8a52-44d1-8217-c0946d78be72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672453494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2672453494 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.3816967266 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 151055050 ps |
| CPU time | 8.17 seconds |
| Started | Jul 12 07:27:59 PM PDT 24 |
| Finished | Jul 12 07:28:15 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-32e79e5c-b07d-4638-a4ca-1ed0a7506ded |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816967266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3816967266 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.2512187745 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 7981109989 ps |
| CPU time | 86.25 seconds |
| Started | Jul 12 07:28:00 PM PDT 24 |
| Finished | Jul 12 07:29:34 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-dc681ce6-182f-4d1f-a461-d38127814880 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512187745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2512187745 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.2341016048 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 4944884993 ps |
| CPU time | 83.56 seconds |
| Started | Jul 12 07:28:01 PM PDT 24 |
| Finished | Jul 12 07:29:32 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-554be4cb-fc86-456b-9d8d-8ae0ac4b5988 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341016048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2341016048 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.3918052929 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 56134088 ps |
| CPU time | 6.97 seconds |
| Started | Jul 12 07:28:03 PM PDT 24 |
| Finished | Jul 12 07:28:18 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-aeab805c-69c4-4deb-9654-f2e0a48d7688 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918052929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.3918052929 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.3323689854 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 4548826982 ps |
| CPU time | 321.08 seconds |
| Started | Jul 12 07:28:06 PM PDT 24 |
| Finished | Jul 12 07:33:36 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-c23ec8c8-f8bc-4717-adfb-12ed8caae4fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323689854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3323689854 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.2300655986 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 2630581944 ps |
| CPU time | 217.2 seconds |
| Started | Jul 12 07:28:13 PM PDT 24 |
| Finished | Jul 12 07:31:59 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-8e696ab1-d6db-497f-9dd1-6b60d585a1ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300655986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2300655986 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.1654593524 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 654618422 ps |
| CPU time | 289.83 seconds |
| Started | Jul 12 07:28:12 PM PDT 24 |
| Finished | Jul 12 07:33:10 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-d3379f05-dfbc-45f8-8de6-7ebab63772eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654593524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_rand_reset.1654593524 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.4024639913 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 2678629841 ps |
| CPU time | 275.12 seconds |
| Started | Jul 12 07:28:10 PM PDT 24 |
| Finished | Jul 12 07:32:54 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-a9d88493-6287-4ca3-824f-7466ec113290 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024639913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.4024639913 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.1268438444 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 297998218 ps |
| CPU time | 36.36 seconds |
| Started | Jul 12 07:28:12 PM PDT 24 |
| Finished | Jul 12 07:28:58 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-5a785de1-17b4-4943-9938-ae9bdfe9378e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268438444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1268438444 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.4115155086 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 3368988412 ps |
| CPU time | 235.92 seconds |
| Started | Jul 12 07:28:08 PM PDT 24 |
| Finished | Jul 12 07:32:13 PM PDT 24 |
| Peak memory | 603764 kb |
| Host | smart-f8da878a-52fd-4c42-9de8-bba1c533fb75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115155086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.4115155086 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.3156965389 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 3870741478 ps |
| CPU time | 147.48 seconds |
| Started | Jul 12 07:28:08 PM PDT 24 |
| Finished | Jul 12 07:30:44 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-b55cb5fc-3712-461d-b9c1-ba2998831684 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156965389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device .3156965389 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.3229500305 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 92712692818 ps |
| CPU time | 1712.59 seconds |
| Started | Jul 12 07:28:11 PM PDT 24 |
| Finished | Jul 12 07:56:52 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-602d7a05-69e9-4229-8a75-a53248d7c01b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229500305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.3229500305 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.567829098 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 1322661961 ps |
| CPU time | 49.02 seconds |
| Started | Jul 12 07:28:21 PM PDT 24 |
| Finished | Jul 12 07:29:20 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-e71789c1-5cda-4dd5-98d6-387e178ba6ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567829098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr .567829098 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.4048048824 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 531778376 ps |
| CPU time | 19.86 seconds |
| Started | Jul 12 07:28:12 PM PDT 24 |
| Finished | Jul 12 07:28:41 PM PDT 24 |
| Peak memory | 575176 kb |
| Host | smart-1747458f-7d71-4a2b-bed3-a217856be970 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048048824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.4048048824 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.2924448634 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 149330198 ps |
| CPU time | 14.42 seconds |
| Started | Jul 12 07:28:08 PM PDT 24 |
| Finished | Jul 12 07:28:31 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-a1f56627-c93c-4b0a-be96-ffdb746545b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924448634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.2924448634 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.267324799 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 77058217756 ps |
| CPU time | 811.17 seconds |
| Started | Jul 12 07:28:10 PM PDT 24 |
| Finished | Jul 12 07:41:50 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-3f2a5336-b655-4517-b1b1-cffd1f102bbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267324799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.267324799 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.3491622779 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 47266712649 ps |
| CPU time | 816.34 seconds |
| Started | Jul 12 07:28:05 PM PDT 24 |
| Finished | Jul 12 07:41:49 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-d18b6e30-deca-495b-be1e-1c2226361a4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491622779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3491622779 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.2010997289 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 230800700 ps |
| CPU time | 20.51 seconds |
| Started | Jul 12 07:35:22 PM PDT 24 |
| Finished | Jul 12 07:35:46 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-bc264a39-d1b9-45dc-9972-3c7ac0be220c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010997289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del ays.2010997289 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.1943390693 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 1443704086 ps |
| CPU time | 45.19 seconds |
| Started | Jul 12 07:28:12 PM PDT 24 |
| Finished | Jul 12 07:29:07 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-1d4fcd51-08c0-420e-873d-8df5d7458214 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943390693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1943390693 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.3948691943 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 173682003 ps |
| CPU time | 8.51 seconds |
| Started | Jul 12 07:28:12 PM PDT 24 |
| Finished | Jul 12 07:28:30 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-0cbeb777-da2f-43f2-b247-4c85684fe067 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948691943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3948691943 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.3698731136 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 8435363206 ps |
| CPU time | 91.41 seconds |
| Started | Jul 12 07:28:08 PM PDT 24 |
| Finished | Jul 12 07:29:48 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-14fb48e3-9741-4d3b-948d-4120403a1d5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698731136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3698731136 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.1292776873 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 3946697078 ps |
| CPU time | 63.22 seconds |
| Started | Jul 12 07:28:07 PM PDT 24 |
| Finished | Jul 12 07:29:20 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-83044af2-ba20-4fc2-96f6-99e2ba93eec5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292776873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1292776873 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1038184030 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 48072326 ps |
| CPU time | 6.22 seconds |
| Started | Jul 12 07:28:07 PM PDT 24 |
| Finished | Jul 12 07:28:23 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-05665ddc-5d80-4d05-9811-f4f11563a0ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038184030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.1038184030 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.2543445368 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 9501333664 ps |
| CPU time | 320.82 seconds |
| Started | Jul 12 07:28:16 PM PDT 24 |
| Finished | Jul 12 07:33:45 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-e7a3a8dd-e6bb-4d84-b203-d5c98e835244 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543445368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2543445368 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.2915545189 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 11287411422 ps |
| CPU time | 369.26 seconds |
| Started | Jul 12 07:28:17 PM PDT 24 |
| Finished | Jul 12 07:34:34 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-84cf3b4c-c19f-4c3e-8e61-ab1ecebd2261 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915545189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2915545189 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1692317236 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 2501210872 ps |
| CPU time | 277.38 seconds |
| Started | Jul 12 07:28:16 PM PDT 24 |
| Finished | Jul 12 07:33:01 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-54690617-66a0-4e1a-bb82-c35f83d7f085 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692317236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.1692317236 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.4171373682 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 4310982833 ps |
| CPU time | 214.95 seconds |
| Started | Jul 12 07:28:19 PM PDT 24 |
| Finished | Jul 12 07:32:02 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-181ec949-3b4b-4c3d-a5ba-780ec8a49d29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171373682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al l_with_reset_error.4171373682 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.234800294 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 251243253 ps |
| CPU time | 30.68 seconds |
| Started | Jul 12 07:28:15 PM PDT 24 |
| Finished | Jul 12 07:28:54 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-bb501b66-5ac0-4665-9201-1c4384bfcd50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234800294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.234800294 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.14999818 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 2517947903 ps |
| CPU time | 149.14 seconds |
| Started | Jul 12 07:28:18 PM PDT 24 |
| Finished | Jul 12 07:30:56 PM PDT 24 |
| Peak memory | 603744 kb |
| Host | smart-8931d868-2f9d-4a95-aba3-429fc4189a9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14999818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.14999818 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.3911754292 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 877814374 ps |
| CPU time | 39.92 seconds |
| Started | Jul 12 07:28:25 PM PDT 24 |
| Finished | Jul 12 07:29:16 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-1e5afd38-851b-4b4a-bc8f-33d32a7d6473 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911754292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .3911754292 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.555704793 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 9169849457 ps |
| CPU time | 156.85 seconds |
| Started | Jul 12 07:28:23 PM PDT 24 |
| Finished | Jul 12 07:31:10 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-21df48ff-1a82-4a34-8c2d-6e6e639abd2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555704793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_d evice_slow_rsp.555704793 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.2891798412 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 189756473 ps |
| CPU time | 10.74 seconds |
| Started | Jul 12 07:28:28 PM PDT 24 |
| Finished | Jul 12 07:28:50 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-d446826e-0dcf-4595-8391-c11c4c326bbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891798412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.2891798412 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.3413666194 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 708145749 ps |
| CPU time | 29.15 seconds |
| Started | Jul 12 07:28:24 PM PDT 24 |
| Finished | Jul 12 07:29:03 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-abfd8f9f-568e-463a-b8b5-5e9b9ee4e212 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413666194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3413666194 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.953621673 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 458361157 ps |
| CPU time | 39.31 seconds |
| Started | Jul 12 07:29:33 PM PDT 24 |
| Finished | Jul 12 07:30:24 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-23fa668d-6988-49d8-a13e-d5679cdb197d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953621673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.953621673 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.811342661 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 85081203804 ps |
| CPU time | 895.76 seconds |
| Started | Jul 12 07:28:30 PM PDT 24 |
| Finished | Jul 12 07:43:37 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-ba510135-dfe0-4551-96e7-c721d38fc87d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811342661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.811342661 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.1589427799 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 13022915324 ps |
| CPU time | 220.61 seconds |
| Started | Jul 12 07:28:30 PM PDT 24 |
| Finished | Jul 12 07:32:21 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-11ea5cad-4ddb-47bb-8fd0-daf15741138a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589427799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1589427799 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.3367656259 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 368261607 ps |
| CPU time | 33.72 seconds |
| Started | Jul 12 07:28:31 PM PDT 24 |
| Finished | Jul 12 07:29:15 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-cea77738-fa4c-4c80-b12a-d40dd7243ec4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367656259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.3367656259 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.1934512742 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 272688503 ps |
| CPU time | 22.36 seconds |
| Started | Jul 12 07:28:29 PM PDT 24 |
| Finished | Jul 12 07:29:02 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-b11a89f7-6ae0-445f-914e-648a1838dd66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934512742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1934512742 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.3555302076 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 141065356 ps |
| CPU time | 7.55 seconds |
| Started | Jul 12 07:28:15 PM PDT 24 |
| Finished | Jul 12 07:28:30 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-2b5f76c3-22ff-442c-bd36-b23f56c95b51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555302076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3555302076 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.4199323047 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 6364466458 ps |
| CPU time | 67.56 seconds |
| Started | Jul 12 07:28:16 PM PDT 24 |
| Finished | Jul 12 07:29:32 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-eed33249-f055-4929-90a1-84c82bb46e27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199323047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.4199323047 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.3519138138 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 5587138434 ps |
| CPU time | 99.32 seconds |
| Started | Jul 12 07:28:22 PM PDT 24 |
| Finished | Jul 12 07:30:11 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-b32d56e2-311d-48c3-af3b-ae4676eca290 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519138138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3519138138 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.2154221438 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 52043376 ps |
| CPU time | 6.42 seconds |
| Started | Jul 12 07:28:15 PM PDT 24 |
| Finished | Jul 12 07:28:29 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-7e26d080-4572-40c9-9435-400952ca1f6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154221438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.2154221438 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.585508674 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 1465904063 ps |
| CPU time | 60.9 seconds |
| Started | Jul 12 07:28:23 PM PDT 24 |
| Finished | Jul 12 07:29:34 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-c2cef850-7810-464b-b11a-b320c3e82bc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585508674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.585508674 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.485943875 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 7455101834 ps |
| CPU time | 214.54 seconds |
| Started | Jul 12 07:28:22 PM PDT 24 |
| Finished | Jul 12 07:32:06 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-3b608f39-3784-4050-9649-1b4b2fab233c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485943875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.485943875 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.3411606523 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 7852635269 ps |
| CPU time | 347.34 seconds |
| Started | Jul 12 07:28:30 PM PDT 24 |
| Finished | Jul 12 07:34:28 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-c98d28f0-4659-40f2-b76c-7c9452b3ec11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411606523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.3411606523 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.680534909 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 2476486240 ps |
| CPU time | 350.37 seconds |
| Started | Jul 12 07:28:29 PM PDT 24 |
| Finished | Jul 12 07:34:31 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-741dc902-24a7-43e4-9bbd-e0c75e0a9cfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680534909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_reset_error.680534909 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.676433341 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 744721052 ps |
| CPU time | 33.82 seconds |
| Started | Jul 12 07:28:22 PM PDT 24 |
| Finished | Jul 12 07:29:06 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-180d5f9d-6b39-4e3c-9618-67929f08a23e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676433341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.676433341 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.3189501891 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 28128045473 ps |
| CPU time | 5810.41 seconds |
| Started | Jul 12 07:23:48 PM PDT 24 |
| Finished | Jul 12 09:00:42 PM PDT 24 |
| Peak memory | 593456 kb |
| Host | smart-f4a0f250-ab70-4a73-a649-483b89c33e35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189501891 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.chip_csr_aliasing.3189501891 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.4141507471 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 6563930568 ps |
| CPU time | 723.02 seconds |
| Started | Jul 12 07:23:38 PM PDT 24 |
| Finished | Jul 12 07:35:43 PM PDT 24 |
| Peak memory | 590436 kb |
| Host | smart-f66a2b87-f344-4fda-ba1b-d5726556129e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141507471 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.4141507471 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.3845592867 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 34335351208 ps |
| CPU time | 4879.97 seconds |
| Started | Jul 12 07:23:38 PM PDT 24 |
| Finished | Jul 12 08:44:59 PM PDT 24 |
| Peak memory | 593504 kb |
| Host | smart-8fb453cf-9ded-4ec9-b3b2-a7abaea9158a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845592867 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.3845592867 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.3368962784 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 344695125 ps |
| CPU time | 30.99 seconds |
| Started | Jul 12 07:23:42 PM PDT 24 |
| Finished | Jul 12 07:24:15 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-49f3b942-267d-400b-9eea-4d2c771712ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368962784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 3368962784 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3475553401 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 112903273532 ps |
| CPU time | 2172.63 seconds |
| Started | Jul 12 07:23:46 PM PDT 24 |
| Finished | Jul 12 08:00:01 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-a7fc06c4-c538-4f8a-879c-092d400636ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475553401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d evice_slow_rsp.3475553401 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.2909266864 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 1049977084 ps |
| CPU time | 37.44 seconds |
| Started | Jul 12 07:23:48 PM PDT 24 |
| Finished | Jul 12 07:24:29 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-92ec310b-4afb-4e3e-806a-7aaaff019aa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909266864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .2909266864 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.2333171264 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 137069625 ps |
| CPU time | 13.24 seconds |
| Started | Jul 12 07:23:47 PM PDT 24 |
| Finished | Jul 12 07:24:04 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-e378f928-e28e-44ba-9f26-967c24c54655 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333171264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2333171264 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.3906952640 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 96006530 ps |
| CPU time | 12.34 seconds |
| Started | Jul 12 07:23:43 PM PDT 24 |
| Finished | Jul 12 07:23:56 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-916d1d45-ce05-436b-95ce-7d877fa62db7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906952640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.3906952640 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.172001949 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 83155056100 ps |
| CPU time | 872.06 seconds |
| Started | Jul 12 07:23:40 PM PDT 24 |
| Finished | Jul 12 07:38:15 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-afe6c09a-c821-43b9-b1f2-ab7f2a1c4242 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172001949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.172001949 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.663097447 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 55817178625 ps |
| CPU time | 1009.7 seconds |
| Started | Jul 12 07:23:48 PM PDT 24 |
| Finished | Jul 12 07:40:41 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-df2bc7b9-3d6a-414a-b3e3-eceefa93fde8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663097447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.663097447 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.3823422333 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 569071384 ps |
| CPU time | 51.55 seconds |
| Started | Jul 12 07:23:40 PM PDT 24 |
| Finished | Jul 12 07:24:34 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-e108df5e-2e0b-4aaf-b2a5-737604e6229a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823422333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela ys.3823422333 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.4122287926 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 987354415 ps |
| CPU time | 29.87 seconds |
| Started | Jul 12 07:23:49 PM PDT 24 |
| Finished | Jul 12 07:24:22 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-4161e860-6eb7-4ea5-a674-b4237a4b68c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122287926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.4122287926 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.3580156841 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 222644497 ps |
| CPU time | 10.32 seconds |
| Started | Jul 12 07:23:40 PM PDT 24 |
| Finished | Jul 12 07:23:52 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-d57b0771-09d2-423b-bf42-df58b2848ce3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580156841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3580156841 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.1301802962 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 8259941983 ps |
| CPU time | 88.84 seconds |
| Started | Jul 12 07:23:48 PM PDT 24 |
| Finished | Jul 12 07:25:21 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-2554ed9e-c6da-4853-9421-aceaf4e59ae7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301802962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1301802962 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2625181649 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 3868191946 ps |
| CPU time | 66.12 seconds |
| Started | Jul 12 07:23:41 PM PDT 24 |
| Finished | Jul 12 07:24:49 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-1a543cad-48d1-4d2f-b288-30afd4cf5acc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625181649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2625181649 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.1794526224 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 50125005 ps |
| CPU time | 6.88 seconds |
| Started | Jul 12 07:23:49 PM PDT 24 |
| Finished | Jul 12 07:23:59 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-e9064f2d-e646-4302-931a-ed763d579339 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794526224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .1794526224 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.3046344523 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 3242845285 ps |
| CPU time | 106.95 seconds |
| Started | Jul 12 07:23:46 PM PDT 24 |
| Finished | Jul 12 07:25:35 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-68d21833-a466-4ad1-8bf3-4f7264dc8c57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046344523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3046344523 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.3219478634 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 4476187432 ps |
| CPU time | 332.04 seconds |
| Started | Jul 12 07:23:46 PM PDT 24 |
| Finished | Jul 12 07:29:21 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-dfecc5cf-9e1c-4944-b33f-7117ca2332ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219478634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3219478634 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.1567809229 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 254056035 ps |
| CPU time | 77.33 seconds |
| Started | Jul 12 07:23:44 PM PDT 24 |
| Finished | Jul 12 07:25:02 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-e9b7afaf-e2a0-4326-b397-abae61ba0a02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567809229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.1567809229 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.4201385400 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 608636769 ps |
| CPU time | 151.92 seconds |
| Started | Jul 12 07:23:46 PM PDT 24 |
| Finished | Jul 12 07:26:20 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-5fa9fb80-440e-4cb6-9c15-d429e78d1510 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201385400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.4201385400 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.1369107456 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 354068837 ps |
| CPU time | 20.99 seconds |
| Started | Jul 12 07:23:47 PM PDT 24 |
| Finished | Jul 12 07:24:10 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-2b6775d0-b255-4ea7-a7a9-45cb5855b56d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369107456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1369107456 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.3398253580 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 662775263 ps |
| CPU time | 50.11 seconds |
| Started | Jul 12 07:28:33 PM PDT 24 |
| Finished | Jul 12 07:29:33 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-1d885cb1-3cce-461a-8e54-67055ef07536 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398253580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device .3398253580 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2004614577 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 88849494964 ps |
| CPU time | 1606.93 seconds |
| Started | Jul 12 07:28:36 PM PDT 24 |
| Finished | Jul 12 07:55:32 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-86db0311-c940-4790-8591-5fc101cbed86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004614577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.2004614577 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.3492325322 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 403410415 ps |
| CPU time | 18.35 seconds |
| Started | Jul 12 07:28:36 PM PDT 24 |
| Finished | Jul 12 07:29:03 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-ba70f735-f51e-4c77-bd1d-983f470ade27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492325322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.3492325322 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.969207700 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 1676564834 ps |
| CPU time | 56.94 seconds |
| Started | Jul 12 07:28:32 PM PDT 24 |
| Finished | Jul 12 07:29:39 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-eb35dfb5-4be3-4d88-9c8f-0aa9fb68bedf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969207700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.969207700 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.2475896380 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 869997678 ps |
| CPU time | 32.61 seconds |
| Started | Jul 12 07:28:33 PM PDT 24 |
| Finished | Jul 12 07:29:15 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-3d291210-b064-4076-8e76-46da5af4d815 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475896380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.2475896380 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.2554327457 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 69983277609 ps |
| CPU time | 836.16 seconds |
| Started | Jul 12 07:28:31 PM PDT 24 |
| Finished | Jul 12 07:42:37 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-af70ee6f-bcfe-4315-b97c-4042e59ea8ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554327457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2554327457 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.451016229 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 56363714765 ps |
| CPU time | 958.1 seconds |
| Started | Jul 12 07:28:33 PM PDT 24 |
| Finished | Jul 12 07:44:41 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-0f646c63-54a6-4c73-abda-59a7ccf4da55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451016229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.451016229 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.806851538 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 353705441 ps |
| CPU time | 34.53 seconds |
| Started | Jul 12 07:28:34 PM PDT 24 |
| Finished | Jul 12 07:29:18 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-70817d26-6294-409e-bd11-f101c1e4aeaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806851538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_dela ys.806851538 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.3072499836 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 271069672 ps |
| CPU time | 19.93 seconds |
| Started | Jul 12 07:28:34 PM PDT 24 |
| Finished | Jul 12 07:29:04 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-fdab8b0b-b8af-4ff6-bbe8-4f45688a9f66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072499836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3072499836 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.454369167 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 40562347 ps |
| CPU time | 6.2 seconds |
| Started | Jul 12 07:28:30 PM PDT 24 |
| Finished | Jul 12 07:28:47 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-babde62b-a514-4753-8cb1-29c9954b3d92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454369167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.454369167 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.3069067492 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 9518115406 ps |
| CPU time | 106.96 seconds |
| Started | Jul 12 07:28:33 PM PDT 24 |
| Finished | Jul 12 07:30:30 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-01193833-7894-440f-a088-99a898fc4792 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069067492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3069067492 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.608162217 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 4255374597 ps |
| CPU time | 73.52 seconds |
| Started | Jul 12 07:28:34 PM PDT 24 |
| Finished | Jul 12 07:29:57 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-054d343d-0cb5-468e-af61-5146894325d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608162217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.608162217 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.24078278 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 42092212 ps |
| CPU time | 6.11 seconds |
| Started | Jul 12 07:28:34 PM PDT 24 |
| Finished | Jul 12 07:28:50 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-b73749d4-4714-440b-b70c-9b2c1c566daf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24078278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.24078278 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.4279973202 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 5455459423 ps |
| CPU time | 237.55 seconds |
| Started | Jul 12 07:28:33 PM PDT 24 |
| Finished | Jul 12 07:32:40 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-792e7ea7-cdfb-4e81-9ec3-0834b2b66ba5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279973202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.4279973202 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.3677276784 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 6824148953 ps |
| CPU time | 235.83 seconds |
| Started | Jul 12 07:28:48 PM PDT 24 |
| Finished | Jul 12 07:32:47 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-8cf51b93-afdd-40a0-ad20-9938df906b2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677276784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3677276784 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1879133021 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 4189466114 ps |
| CPU time | 535.69 seconds |
| Started | Jul 12 07:37:55 PM PDT 24 |
| Finished | Jul 12 07:46:53 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-68c7e0be-56cd-4b48-b0ea-29c3bf3b5eed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879133021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.1879133021 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1007194713 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 12582809 ps |
| CPU time | 12.78 seconds |
| Started | Jul 12 07:28:44 PM PDT 24 |
| Finished | Jul 12 07:29:02 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-a56ed0e4-d2f4-46f4-bbc8-8d756b031fa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007194713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.1007194713 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.1722844738 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 129075470 ps |
| CPU time | 15.9 seconds |
| Started | Jul 12 07:28:34 PM PDT 24 |
| Finished | Jul 12 07:29:00 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-d17c94f1-cf54-4d86-83be-5a82ab06f020 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722844738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1722844738 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.3897034216 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 777819049 ps |
| CPU time | 51.19 seconds |
| Started | Jul 12 07:28:44 PM PDT 24 |
| Finished | Jul 12 07:29:40 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-16e2e283-0c86-417f-bc01-c9856c6b6ee3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897034216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .3897034216 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.934766029 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 128472056715 ps |
| CPU time | 2302.12 seconds |
| Started | Jul 12 07:28:42 PM PDT 24 |
| Finished | Jul 12 08:07:10 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-dd37c640-841b-41c5-8db7-021dc78c6997 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934766029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_d evice_slow_rsp.934766029 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.292538551 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 198079853 ps |
| CPU time | 9.91 seconds |
| Started | Jul 12 07:28:42 PM PDT 24 |
| Finished | Jul 12 07:28:58 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-d7ce85b1-0dde-4f8a-a541-b85cdb7e89d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292538551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr .292538551 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.1803665336 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 25695284 ps |
| CPU time | 5.48 seconds |
| Started | Jul 12 07:28:43 PM PDT 24 |
| Finished | Jul 12 07:28:54 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-b45eb51f-2372-474f-a6f3-7ef86479a9a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803665336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1803665336 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.1796004599 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 517664043 ps |
| CPU time | 47 seconds |
| Started | Jul 12 07:28:45 PM PDT 24 |
| Finished | Jul 12 07:29:37 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-55d3d745-7f28-4515-ab58-137da52c2819 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796004599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.1796004599 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.4152279614 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 23825238052 ps |
| CPU time | 285.35 seconds |
| Started | Jul 12 07:28:44 PM PDT 24 |
| Finished | Jul 12 07:33:35 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-be41c4fa-515d-4163-beb5-10d9da479ac5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152279614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.4152279614 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.1375890135 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 7628394374 ps |
| CPU time | 130.21 seconds |
| Started | Jul 12 07:28:43 PM PDT 24 |
| Finished | Jul 12 07:30:59 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-a23da2bd-4443-422c-bece-f8d705dc62a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375890135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1375890135 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.351977692 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 587928054 ps |
| CPU time | 48.04 seconds |
| Started | Jul 12 07:28:42 PM PDT 24 |
| Finished | Jul 12 07:29:36 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-fb936ce4-878b-4532-b346-2065d55f4e2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351977692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_dela ys.351977692 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.2192672355 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 297709236 ps |
| CPU time | 23.93 seconds |
| Started | Jul 12 07:28:45 PM PDT 24 |
| Finished | Jul 12 07:29:14 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-2828f7a1-f985-41c9-a7b0-d868b2f8cdb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192672355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.2192672355 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.2804330902 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 189410838 ps |
| CPU time | 9.58 seconds |
| Started | Jul 12 07:28:42 PM PDT 24 |
| Finished | Jul 12 07:28:58 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-2073961d-5634-4d97-8b93-fdd0b84645fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804330902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2804330902 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.4250952861 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 8759610088 ps |
| CPU time | 97.78 seconds |
| Started | Jul 12 07:28:41 PM PDT 24 |
| Finished | Jul 12 07:30:25 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-c7ced333-3e3e-4293-a9af-4ab4660e21ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250952861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.4250952861 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.3090289882 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 4269293825 ps |
| CPU time | 74.69 seconds |
| Started | Jul 12 07:28:42 PM PDT 24 |
| Finished | Jul 12 07:30:02 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-b8357de7-e0b8-4340-a127-9137008c68b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090289882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3090289882 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.2399072402 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 58208541 ps |
| CPU time | 6.78 seconds |
| Started | Jul 12 07:28:42 PM PDT 24 |
| Finished | Jul 12 07:28:55 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-63e0612b-11f2-43ca-a3d1-d47adbf28ba1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399072402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay s.2399072402 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.3857842362 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 1826744812 ps |
| CPU time | 133.54 seconds |
| Started | Jul 12 07:28:44 PM PDT 24 |
| Finished | Jul 12 07:31:02 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-24d1acff-c7ec-4b14-8317-e49884a23264 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857842362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3857842362 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.712431865 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 673211176 ps |
| CPU time | 57.48 seconds |
| Started | Jul 12 07:28:51 PM PDT 24 |
| Finished | Jul 12 07:29:51 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-6517ce02-9333-47b8-bd31-565c741361d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712431865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.712431865 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.849208308 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 118630725 ps |
| CPU time | 30.98 seconds |
| Started | Jul 12 07:28:50 PM PDT 24 |
| Finished | Jul 12 07:29:23 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-4df94524-c4d4-47e6-bcd6-06036f11230e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849208308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_ with_rand_reset.849208308 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.1946006494 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 556367042 ps |
| CPU time | 151.69 seconds |
| Started | Jul 12 07:28:57 PM PDT 24 |
| Finished | Jul 12 07:31:34 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-dc228d27-f993-428b-b9e6-3f48f8a59de9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946006494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.1946006494 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.2175276109 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 1204942526 ps |
| CPU time | 54.21 seconds |
| Started | Jul 12 07:28:43 PM PDT 24 |
| Finished | Jul 12 07:29:43 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-c68987d0-6f86-4acb-8969-4321cf5ffe0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175276109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.2175276109 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.3382338753 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 509309273 ps |
| CPU time | 33.09 seconds |
| Started | Jul 12 07:28:56 PM PDT 24 |
| Finished | Jul 12 07:29:34 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-afa4fd5e-5a0e-43ea-b9da-60c78c3a5119 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382338753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .3382338753 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.3376023235 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 79642466734 ps |
| CPU time | 1476.31 seconds |
| Started | Jul 12 07:28:52 PM PDT 24 |
| Finished | Jul 12 07:53:32 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-6e7f388c-930f-4ed6-a61c-abc88a786c51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376023235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_ device_slow_rsp.3376023235 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.4225545431 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 489599922 ps |
| CPU time | 21.81 seconds |
| Started | Jul 12 07:28:57 PM PDT 24 |
| Finished | Jul 12 07:29:25 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-b480cd95-59a6-4d82-bfdb-b7fe148cb891 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225545431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.4225545431 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.2612426941 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 1289670513 ps |
| CPU time | 40.41 seconds |
| Started | Jul 12 07:28:52 PM PDT 24 |
| Finished | Jul 12 07:29:36 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-f436f403-cb75-4fc8-a7a0-def04b1ad57c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612426941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2612426941 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.1244253539 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 2555863253 ps |
| CPU time | 82.25 seconds |
| Started | Jul 12 07:29:03 PM PDT 24 |
| Finished | Jul 12 07:30:30 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-dfeeaf9e-1f87-44b6-9561-a6074a6db3e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244253539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.1244253539 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.3268440642 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 112085992970 ps |
| CPU time | 1192.15 seconds |
| Started | Jul 12 07:28:52 PM PDT 24 |
| Finished | Jul 12 07:48:48 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-1b416d88-e985-463f-bc0b-8fb7027c1e27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268440642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3268440642 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.243307180 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 13144259322 ps |
| CPU time | 209.76 seconds |
| Started | Jul 12 07:28:57 PM PDT 24 |
| Finished | Jul 12 07:32:33 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-4e6fe005-5233-43da-9453-510b2cfd12c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243307180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.243307180 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.664068944 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 188187928 ps |
| CPU time | 18.54 seconds |
| Started | Jul 12 07:29:02 PM PDT 24 |
| Finished | Jul 12 07:29:25 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-d3382487-b0ba-4c3f-a002-da9855baae50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664068944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_dela ys.664068944 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.3579389808 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 261847603 ps |
| CPU time | 21.81 seconds |
| Started | Jul 12 07:28:52 PM PDT 24 |
| Finished | Jul 12 07:29:17 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-326285e2-007c-4c90-b3cf-2bab7ec0ccba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579389808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3579389808 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.2108584999 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 168855012 ps |
| CPU time | 7.74 seconds |
| Started | Jul 12 07:28:51 PM PDT 24 |
| Finished | Jul 12 07:29:01 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-b85b8904-ae16-4ef6-8bbe-fcd99d791813 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108584999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2108584999 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.3651736032 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 7608757075 ps |
| CPU time | 87.37 seconds |
| Started | Jul 12 07:28:52 PM PDT 24 |
| Finished | Jul 12 07:30:23 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-d9620f5b-ccc9-4eed-a15c-5e47570ea3b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651736032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3651736032 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.2817202955 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 4559749214 ps |
| CPU time | 78.27 seconds |
| Started | Jul 12 07:28:52 PM PDT 24 |
| Finished | Jul 12 07:30:13 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-fadfad08-a951-4328-a93d-4698b6a1f327 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817202955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2817202955 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.3886008858 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 51832967 ps |
| CPU time | 6.6 seconds |
| Started | Jul 12 07:28:57 PM PDT 24 |
| Finished | Jul 12 07:29:09 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-c37e485e-2cea-467d-8f6e-0fad0a62b5ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886008858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.3886008858 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.2783229987 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 3232178196 ps |
| CPU time | 142.8 seconds |
| Started | Jul 12 07:28:50 PM PDT 24 |
| Finished | Jul 12 07:31:16 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-cc842ce9-f1fb-4887-a0a4-822e2de39225 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783229987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2783229987 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.999867404 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 8628687130 ps |
| CPU time | 283.34 seconds |
| Started | Jul 12 07:29:02 PM PDT 24 |
| Finished | Jul 12 07:33:50 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-d5e5abb1-a6e2-48a5-a57a-9bde867b9ed0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999867404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.999867404 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.2148765841 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 219724247 ps |
| CPU time | 109.71 seconds |
| Started | Jul 12 07:29:01 PM PDT 24 |
| Finished | Jul 12 07:30:56 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-b5ae3bc3-66a2-4e1c-a5e2-b7e87779e9e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148765841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_rand_reset.2148765841 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.2274003806 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 263062293 ps |
| CPU time | 111.06 seconds |
| Started | Jul 12 07:29:01 PM PDT 24 |
| Finished | Jul 12 07:30:57 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-5b9b8b70-fe95-4bdf-baa3-75d1b88ba4a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274003806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.2274003806 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.394388011 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 35684165 ps |
| CPU time | 7.18 seconds |
| Started | Jul 12 07:28:51 PM PDT 24 |
| Finished | Jul 12 07:29:02 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-ebc365ad-f63e-4df4-b90b-35b1d8ccc037 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394388011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.394388011 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.3063203746 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 3141563452 ps |
| CPU time | 130.58 seconds |
| Started | Jul 12 07:29:06 PM PDT 24 |
| Finished | Jul 12 07:31:21 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-c6e3bc37-2d2e-4e07-9edb-8f2885eeb48c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063203746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .3063203746 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1843096836 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 115524337400 ps |
| CPU time | 2211.51 seconds |
| Started | Jul 12 07:29:05 PM PDT 24 |
| Finished | Jul 12 08:06:02 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-6609632f-d669-40dd-ae05-4d781dbf6560 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843096836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.1843096836 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.3687955835 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 75862398 ps |
| CPU time | 8.78 seconds |
| Started | Jul 12 07:29:12 PM PDT 24 |
| Finished | Jul 12 07:29:29 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-9abebdf3-312a-437b-b9f9-29341220f001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687955835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.3687955835 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.55613457 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 232200403 ps |
| CPU time | 21.52 seconds |
| Started | Jul 12 07:29:04 PM PDT 24 |
| Finished | Jul 12 07:29:30 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-c5a17096-84a5-4968-a289-27f0387c9e45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55613457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.55613457 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.1952289343 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 946640127 ps |
| CPU time | 35.54 seconds |
| Started | Jul 12 07:29:11 PM PDT 24 |
| Finished | Jul 12 07:29:54 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-5112dc92-4316-4551-bcf2-3c9def51312d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952289343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.1952289343 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.2131016957 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 108962080014 ps |
| CPU time | 1281.14 seconds |
| Started | Jul 12 07:29:03 PM PDT 24 |
| Finished | Jul 12 07:50:29 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-5cf23267-f77d-468e-8e52-407995187c03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131016957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2131016957 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.3170082102 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 54482474369 ps |
| CPU time | 933.6 seconds |
| Started | Jul 12 07:29:04 PM PDT 24 |
| Finished | Jul 12 07:44:42 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-ca24d29d-fe03-417b-b418-9acb944dcf5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170082102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3170082102 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.2857744400 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 489554690 ps |
| CPU time | 40.15 seconds |
| Started | Jul 12 07:29:02 PM PDT 24 |
| Finished | Jul 12 07:29:47 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-7c4b58cc-e59e-42d7-a4ad-d215e41d6f4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857744400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.2857744400 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.3922781421 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 311172313 ps |
| CPU time | 24.64 seconds |
| Started | Jul 12 07:29:04 PM PDT 24 |
| Finished | Jul 12 07:29:33 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-9e92faf5-5deb-4746-972a-80b3a18996a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922781421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3922781421 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.1700125034 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 47334147 ps |
| CPU time | 6.11 seconds |
| Started | Jul 12 07:29:05 PM PDT 24 |
| Finished | Jul 12 07:29:15 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-8c558964-bdee-4cc3-a9ea-c9b95501ac69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700125034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1700125034 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.1703750575 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 6429971925 ps |
| CPU time | 72.43 seconds |
| Started | Jul 12 07:29:05 PM PDT 24 |
| Finished | Jul 12 07:30:22 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-1c9ed9ad-3691-4f9e-8147-432971cbece1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703750575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1703750575 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.239697952 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 6777074178 ps |
| CPU time | 113.97 seconds |
| Started | Jul 12 07:29:12 PM PDT 24 |
| Finished | Jul 12 07:31:13 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-b5ffd073-2d85-4bb7-bc7d-13825008bde0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239697952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.239697952 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.1820949043 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 36693347 ps |
| CPU time | 5.82 seconds |
| Started | Jul 12 07:29:11 PM PDT 24 |
| Finished | Jul 12 07:29:24 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-4f46013a-97d6-4026-a608-68fe580735c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820949043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.1820949043 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.3771094328 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 1458365616 ps |
| CPU time | 113.19 seconds |
| Started | Jul 12 07:29:04 PM PDT 24 |
| Finished | Jul 12 07:31:02 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-c1fe998e-bd16-43e5-8119-f2554e2f5af7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771094328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3771094328 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.1936936214 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 1729289716 ps |
| CPU time | 67.48 seconds |
| Started | Jul 12 07:29:13 PM PDT 24 |
| Finished | Jul 12 07:30:31 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-b95d4f56-7bc3-400f-ad90-939aee136305 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936936214 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1936936214 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3493033041 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 1565980753 ps |
| CPU time | 300.86 seconds |
| Started | Jul 12 07:29:13 PM PDT 24 |
| Finished | Jul 12 07:34:24 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-613182cd-8bf2-47da-af5a-9f96e2bd51ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493033041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.3493033041 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2753932480 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 318013531 ps |
| CPU time | 101.78 seconds |
| Started | Jul 12 07:29:11 PM PDT 24 |
| Finished | Jul 12 07:31:00 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-59b69b2b-999f-4ab2-93ca-db199f2216ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753932480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.2753932480 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.2073859743 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 86179921 ps |
| CPU time | 11.95 seconds |
| Started | Jul 12 07:29:04 PM PDT 24 |
| Finished | Jul 12 07:29:21 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-910eab69-28f6-4b26-af73-dc4668c60696 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073859743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2073859743 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.2587169670 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 994173005 ps |
| CPU time | 45.57 seconds |
| Started | Jul 12 07:29:12 PM PDT 24 |
| Finished | Jul 12 07:30:06 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-518cd260-80e0-445d-a6a0-11aff1e7ecdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587169670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .2587169670 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.526996648 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 30414172561 ps |
| CPU time | 554.99 seconds |
| Started | Jul 12 07:29:14 PM PDT 24 |
| Finished | Jul 12 07:38:40 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-aaa02fac-b3ab-4c4e-b73a-f24295488fbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526996648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_d evice_slow_rsp.526996648 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.2522097301 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 215551781 ps |
| CPU time | 11.58 seconds |
| Started | Jul 12 07:29:12 PM PDT 24 |
| Finished | Jul 12 07:29:32 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-170faa86-18e4-49b8-8044-e96c2fb039b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522097301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.2522097301 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.2769177856 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 589292150 ps |
| CPU time | 25.6 seconds |
| Started | Jul 12 07:29:13 PM PDT 24 |
| Finished | Jul 12 07:29:49 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-3a6fc6de-117a-495c-bdc6-e553a4c0cea6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769177856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2769177856 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.2192757210 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 66226139 ps |
| CPU time | 8.84 seconds |
| Started | Jul 12 07:29:13 PM PDT 24 |
| Finished | Jul 12 07:29:33 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-cfb9e3f0-caa9-42a9-9738-f290462ecd9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192757210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.2192757210 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.3438733004 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 81856232346 ps |
| CPU time | 1008.33 seconds |
| Started | Jul 12 07:29:13 PM PDT 24 |
| Finished | Jul 12 07:46:12 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-313b9958-bb06-4c9a-af6f-35103436deb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438733004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3438733004 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.2594128076 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 47225466370 ps |
| CPU time | 827.87 seconds |
| Started | Jul 12 07:29:17 PM PDT 24 |
| Finished | Jul 12 07:43:18 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-f57d97fb-732c-47c3-b01b-af0b06355708 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594128076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2594128076 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.3609330120 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 571341324 ps |
| CPU time | 47.92 seconds |
| Started | Jul 12 07:29:13 PM PDT 24 |
| Finished | Jul 12 07:30:10 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-feb91e74-42ed-407c-9f97-35fb26a5f88a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609330120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del ays.3609330120 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.2656746785 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 396744145 ps |
| CPU time | 28.46 seconds |
| Started | Jul 12 07:29:11 PM PDT 24 |
| Finished | Jul 12 07:29:48 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-9d1e3fb2-ea60-49a6-9845-e3d22bf58839 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656746785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2656746785 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.3810699961 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 44881572 ps |
| CPU time | 6.01 seconds |
| Started | Jul 12 07:29:17 PM PDT 24 |
| Finished | Jul 12 07:29:36 PM PDT 24 |
| Peak memory | 574036 kb |
| Host | smart-2ae19d60-70c3-4833-8e40-58d87422f31b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810699961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3810699961 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.4267612058 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 7449588936 ps |
| CPU time | 80.24 seconds |
| Started | Jul 12 07:29:13 PM PDT 24 |
| Finished | Jul 12 07:30:42 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-2e3d4c28-f9ec-4e76-918b-4e34120d1c22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267612058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.4267612058 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.3740076325 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 5003065525 ps |
| CPU time | 77.71 seconds |
| Started | Jul 12 07:29:11 PM PDT 24 |
| Finished | Jul 12 07:30:36 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-c9200a5a-0f4f-4ca3-9b40-adfd7aec5b97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740076325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3740076325 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.1972412431 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 49431612 ps |
| CPU time | 6.39 seconds |
| Started | Jul 12 07:29:18 PM PDT 24 |
| Finished | Jul 12 07:29:37 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-3d420396-2c76-47b6-9603-9478b2e3ef24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972412431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay s.1972412431 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.721863489 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 11108164150 ps |
| CPU time | 452.86 seconds |
| Started | Jul 12 07:29:13 PM PDT 24 |
| Finished | Jul 12 07:36:57 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-4feadcf6-e4d7-47b0-9cd9-1acf79908e5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721863489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.721863489 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.3266222193 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 1416117906 ps |
| CPU time | 51.75 seconds |
| Started | Jul 12 07:29:12 PM PDT 24 |
| Finished | Jul 12 07:30:12 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-162d6e59-0b87-410e-862f-03c8cb02d92a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266222193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3266222193 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.2256851347 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 6803552239 ps |
| CPU time | 310.71 seconds |
| Started | Jul 12 07:29:13 PM PDT 24 |
| Finished | Jul 12 07:34:33 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-3a2bb31e-f228-4746-a965-cfcbb5f0e232 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256851347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.2256851347 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.1767959538 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 3083822360 ps |
| CPU time | 436.43 seconds |
| Started | Jul 12 07:29:23 PM PDT 24 |
| Finished | Jul 12 07:36:55 PM PDT 24 |
| Peak memory | 578980 kb |
| Host | smart-f277e739-22dc-42ce-9925-a67771f56e1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767959538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.1767959538 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.3551794854 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1230678875 ps |
| CPU time | 55.88 seconds |
| Started | Jul 12 07:29:13 PM PDT 24 |
| Finished | Jul 12 07:30:19 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-f88526f1-6efb-4b60-8062-a55391ca9e18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551794854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3551794854 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.3344182804 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 15906742 ps |
| CPU time | 6.02 seconds |
| Started | Jul 12 07:29:24 PM PDT 24 |
| Finished | Jul 12 07:29:45 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-527f64b9-c393-4f36-92d4-4ff398a693c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344182804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .3344182804 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.2440994909 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 55094798182 ps |
| CPU time | 987.34 seconds |
| Started | Jul 12 07:29:23 PM PDT 24 |
| Finished | Jul 12 07:46:05 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-cc30ef62-8dd5-4cdb-a8d2-f3b65aff6aa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440994909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_ device_slow_rsp.2440994909 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.2103070081 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 309750720 ps |
| CPU time | 32.09 seconds |
| Started | Jul 12 07:29:23 PM PDT 24 |
| Finished | Jul 12 07:30:10 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-dc662986-6bbc-46a1-b7df-6e1e5446068a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103070081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.2103070081 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.4054376899 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 1491641790 ps |
| CPU time | 49.26 seconds |
| Started | Jul 12 07:29:24 PM PDT 24 |
| Finished | Jul 12 07:30:28 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-5f01313b-6876-4b05-97c2-ab52b1f295b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054376899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.4054376899 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.679395071 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 500295708 ps |
| CPU time | 19.12 seconds |
| Started | Jul 12 07:29:22 PM PDT 24 |
| Finished | Jul 12 07:29:56 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-bfd5b041-e4ba-4c60-9beb-c6e756c265cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679395071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.679395071 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.3127842741 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 39746775945 ps |
| CPU time | 424.8 seconds |
| Started | Jul 12 07:29:24 PM PDT 24 |
| Finished | Jul 12 07:36:43 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-5d43e6ea-4435-4128-bcad-68b36af4a5cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127842741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3127842741 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.2102130866 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 15719665600 ps |
| CPU time | 269.84 seconds |
| Started | Jul 12 07:29:22 PM PDT 24 |
| Finished | Jul 12 07:34:07 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-8e6c058d-6547-44ba-807a-390d28cbd628 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102130866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2102130866 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.61315090 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 95829979 ps |
| CPU time | 10.86 seconds |
| Started | Jul 12 07:29:21 PM PDT 24 |
| Finished | Jul 12 07:29:46 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-f7906be6-25b9-483f-916f-4b2e2f0bc792 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61315090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delay s.61315090 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.3804342974 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 2242216528 ps |
| CPU time | 72.89 seconds |
| Started | Jul 12 07:29:21 PM PDT 24 |
| Finished | Jul 12 07:30:48 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-7b90fa9e-63e7-4892-ab7b-99e8bdd2f8b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804342974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3804342974 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.466868916 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 163641454 ps |
| CPU time | 8.31 seconds |
| Started | Jul 12 07:29:23 PM PDT 24 |
| Finished | Jul 12 07:29:45 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-9189cea9-ebb0-4bfe-90fe-5eaf110d942a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466868916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.466868916 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.2181007956 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 8755101181 ps |
| CPU time | 95.39 seconds |
| Started | Jul 12 07:29:21 PM PDT 24 |
| Finished | Jul 12 07:31:10 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-2705f241-5892-495c-a6f6-43f4700f9708 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181007956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2181007956 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.569475842 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 6031747695 ps |
| CPU time | 106.43 seconds |
| Started | Jul 12 07:29:21 PM PDT 24 |
| Finished | Jul 12 07:31:22 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-2741c986-9938-41e4-90eb-5403689de01a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569475842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.569475842 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.2985551737 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 52252856 ps |
| CPU time | 6.68 seconds |
| Started | Jul 12 07:29:21 PM PDT 24 |
| Finished | Jul 12 07:29:43 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-29c466aa-c115-42b9-ae72-a6fe2e1dfad6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985551737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.2985551737 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.2434534278 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 2591437498 ps |
| CPU time | 182.09 seconds |
| Started | Jul 12 07:29:20 PM PDT 24 |
| Finished | Jul 12 07:32:37 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-6d84bfba-29b2-483b-a942-689ce41f8006 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434534278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2434534278 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.3301726900 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 16505967045 ps |
| CPU time | 618.63 seconds |
| Started | Jul 12 07:29:24 PM PDT 24 |
| Finished | Jul 12 07:39:57 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-c6567d60-2cd1-46e4-8da5-ba2f67ca702e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301726900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3301726900 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1916547701 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 3022630958 ps |
| CPU time | 356.02 seconds |
| Started | Jul 12 07:29:22 PM PDT 24 |
| Finished | Jul 12 07:35:32 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-1a8a1e05-1a35-4b6e-a879-dc0950c642f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916547701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_rand_reset.1916547701 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.1249452950 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 410433419 ps |
| CPU time | 89.68 seconds |
| Started | Jul 12 07:29:21 PM PDT 24 |
| Finished | Jul 12 07:31:06 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-e4fa09a5-f5ca-4926-a597-aa39835ed3d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249452950 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.1249452950 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.3623652094 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 1267584498 ps |
| CPU time | 49.85 seconds |
| Started | Jul 12 07:29:26 PM PDT 24 |
| Finished | Jul 12 07:30:30 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-5149682a-e75f-47ba-a88f-aacab9a3492b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623652094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3623652094 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.3723361863 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 69959024 ps |
| CPU time | 7.44 seconds |
| Started | Jul 12 07:29:31 PM PDT 24 |
| Finished | Jul 12 07:29:50 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-62dfec58-e140-4ce9-b456-b56cedc93797 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723361863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .3723361863 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.3432760762 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 38397697891 ps |
| CPU time | 699.91 seconds |
| Started | Jul 12 07:29:31 PM PDT 24 |
| Finished | Jul 12 07:41:23 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-c099c431-5b84-4fa8-9a3a-26d75ea4f2d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432760762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.3432760762 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.4293164535 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 1165911973 ps |
| CPU time | 44.77 seconds |
| Started | Jul 12 07:29:45 PM PDT 24 |
| Finished | Jul 12 07:30:38 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-65fea001-6c3f-4303-9f20-897c0683191f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293164535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.4293164535 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.815227456 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 146774116 ps |
| CPU time | 13.43 seconds |
| Started | Jul 12 07:29:43 PM PDT 24 |
| Finished | Jul 12 07:30:04 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-50214be6-4d04-42b4-9543-bbf1505f7c06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815227456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.815227456 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.201398545 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 900423091 ps |
| CPU time | 34.55 seconds |
| Started | Jul 12 07:29:33 PM PDT 24 |
| Finished | Jul 12 07:30:19 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-92348ba7-15a6-42e9-9f4f-877bd0be646f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201398545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.201398545 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.1011607871 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 111770257816 ps |
| CPU time | 1290.62 seconds |
| Started | Jul 12 07:29:32 PM PDT 24 |
| Finished | Jul 12 07:51:14 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-0340b5e8-fa1e-4b33-a9f7-6fd04ef06e48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011607871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1011607871 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.2074005399 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 67515525225 ps |
| CPU time | 1269.38 seconds |
| Started | Jul 12 07:29:30 PM PDT 24 |
| Finished | Jul 12 07:50:52 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-9009146e-61f3-4bb8-91f4-a0e094efbf71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074005399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2074005399 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.3357750481 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 422532973 ps |
| CPU time | 36.79 seconds |
| Started | Jul 12 07:29:31 PM PDT 24 |
| Finished | Jul 12 07:30:20 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-1e56ef31-a5d8-43ff-8ff2-d28ce28b59a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357750481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.3357750481 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.2606008013 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 295592323 ps |
| CPU time | 11.66 seconds |
| Started | Jul 12 07:29:51 PM PDT 24 |
| Finished | Jul 12 07:30:09 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-876755ea-83f7-4196-9dc4-bc4e8cf76792 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606008013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2606008013 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.3286050287 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 249882943 ps |
| CPU time | 10.12 seconds |
| Started | Jul 12 07:29:27 PM PDT 24 |
| Finished | Jul 12 07:29:50 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-e6799923-c57b-4cf0-bec9-1a0248945da2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286050287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3286050287 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.1516796840 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 7237493896 ps |
| CPU time | 82.73 seconds |
| Started | Jul 12 07:29:32 PM PDT 24 |
| Finished | Jul 12 07:31:06 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-3ebe6153-f592-486d-a980-3c3f5d15ab5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516796840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1516796840 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.2829988380 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 4904525049 ps |
| CPU time | 86.97 seconds |
| Started | Jul 12 07:29:31 PM PDT 24 |
| Finished | Jul 12 07:31:10 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-86f68f48-f9d7-4e86-8143-8bf22ba6666b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829988380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2829988380 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.272728731 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 48743220 ps |
| CPU time | 6.17 seconds |
| Started | Jul 12 07:29:31 PM PDT 24 |
| Finished | Jul 12 07:29:49 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-9287caf5-9f05-4589-bf7d-e746941229c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272728731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays .272728731 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.3743482263 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 722451039 ps |
| CPU time | 64.56 seconds |
| Started | Jul 12 07:29:42 PM PDT 24 |
| Finished | Jul 12 07:30:55 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-f881c324-12f6-4494-b050-4d3432fa17fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743482263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3743482263 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.843933606 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 3799496483 ps |
| CPU time | 289.86 seconds |
| Started | Jul 12 07:29:46 PM PDT 24 |
| Finished | Jul 12 07:34:44 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-2833fef9-c552-4ac4-86a7-b95609381939 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843933606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.843933606 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.244752433 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 344126943 ps |
| CPU time | 86.01 seconds |
| Started | Jul 12 07:29:45 PM PDT 24 |
| Finished | Jul 12 07:31:20 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-14d0e59e-5d6c-41a0-9e37-e683c67f0c45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244752433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_reset_error.244752433 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.2545863060 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 1319741984 ps |
| CPU time | 56.28 seconds |
| Started | Jul 12 07:29:50 PM PDT 24 |
| Finished | Jul 12 07:30:53 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-77d620b1-dbd4-4354-9501-9bfc53930e87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545863060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2545863060 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.649280534 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 945248415 ps |
| CPU time | 39.83 seconds |
| Started | Jul 12 07:29:53 PM PDT 24 |
| Finished | Jul 12 07:30:39 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-0dbe7fb6-c64a-486e-99da-a2f6bfe22c7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649280534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device. 649280534 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.4273899298 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 105723667722 ps |
| CPU time | 1979.7 seconds |
| Started | Jul 12 07:29:46 PM PDT 24 |
| Finished | Jul 12 08:02:54 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-0143e53d-56d8-4c98-8dd4-b82c7ed60d3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273899298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_ device_slow_rsp.4273899298 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.2356816665 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 826028144 ps |
| CPU time | 33.65 seconds |
| Started | Jul 12 07:29:46 PM PDT 24 |
| Finished | Jul 12 07:30:27 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-4ee2b4f6-13ab-443a-95e5-41d773539936 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356816665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.2356816665 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.2111169840 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 2092525517 ps |
| CPU time | 66.03 seconds |
| Started | Jul 12 07:29:45 PM PDT 24 |
| Finished | Jul 12 07:30:59 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-2b0d95ab-7f31-48d6-92d7-17f5404625df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111169840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2111169840 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.899633681 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 367725118 ps |
| CPU time | 29.9 seconds |
| Started | Jul 12 07:29:44 PM PDT 24 |
| Finished | Jul 12 07:30:22 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-5edaea68-9c8b-4000-826e-59e46cbad67d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899633681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.899633681 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.2172522323 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 100047065564 ps |
| CPU time | 1128.06 seconds |
| Started | Jul 12 07:29:45 PM PDT 24 |
| Finished | Jul 12 07:48:41 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-4bff637f-afd6-4086-8101-c8307e61a406 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172522323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2172522323 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.1918873920 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 35213966380 ps |
| CPU time | 649.15 seconds |
| Started | Jul 12 07:29:44 PM PDT 24 |
| Finished | Jul 12 07:40:41 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-f6ebd382-9e19-4bcc-87ef-0eb5060f0624 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918873920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1918873920 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.358696727 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 271308225 ps |
| CPU time | 26.87 seconds |
| Started | Jul 12 07:29:45 PM PDT 24 |
| Finished | Jul 12 07:30:20 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-cf5900fa-25a2-4e58-b12b-09d05834e824 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358696727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_dela ys.358696727 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.1103928872 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 2087633170 ps |
| CPU time | 64.29 seconds |
| Started | Jul 12 07:29:49 PM PDT 24 |
| Finished | Jul 12 07:31:01 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-4e0864cb-bf8f-4021-908e-4db006b05ea8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103928872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.1103928872 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.2500727442 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 203261101 ps |
| CPU time | 8.99 seconds |
| Started | Jul 12 07:29:45 PM PDT 24 |
| Finished | Jul 12 07:30:02 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-817ab02e-5003-41dd-8007-a409bc30fe0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500727442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2500727442 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.4018446939 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 6109467404 ps |
| CPU time | 72.76 seconds |
| Started | Jul 12 07:29:44 PM PDT 24 |
| Finished | Jul 12 07:31:05 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-d7873f2f-3e1c-45c7-9f00-ba0de644c6ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018446939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.4018446939 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.4153921821 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 4674085432 ps |
| CPU time | 85.22 seconds |
| Started | Jul 12 07:29:45 PM PDT 24 |
| Finished | Jul 12 07:31:18 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-1141eb29-f377-4f1c-84e4-359f756bff7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153921821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.4153921821 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.2264704297 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 48193736 ps |
| CPU time | 6.71 seconds |
| Started | Jul 12 07:29:45 PM PDT 24 |
| Finished | Jul 12 07:29:59 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-20d09a38-6c25-4491-9bcb-5938881175bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264704297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay s.2264704297 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.961662656 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 2442131224 ps |
| CPU time | 189.13 seconds |
| Started | Jul 12 07:29:44 PM PDT 24 |
| Finished | Jul 12 07:33:01 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-4677b4c6-29a5-4a23-b673-ed6066057831 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961662656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.961662656 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.3752187631 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 9635786531 ps |
| CPU time | 327.76 seconds |
| Started | Jul 12 07:30:07 PM PDT 24 |
| Finished | Jul 12 07:35:46 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-6c1bc240-51a2-4f53-8822-31371c28962b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752187631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3752187631 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.1052227516 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 667428703 ps |
| CPU time | 239.64 seconds |
| Started | Jul 12 07:29:52 PM PDT 24 |
| Finished | Jul 12 07:33:58 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-16580fb9-5c35-4f74-8588-8b6860f664cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052227516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.1052227516 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.3403144180 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 3720435503 ps |
| CPU time | 196.33 seconds |
| Started | Jul 12 07:30:06 PM PDT 24 |
| Finished | Jul 12 07:33:31 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-4f951780-fb81-4b52-8267-d9ebcfb20532 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403144180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.3403144180 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.2719937232 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 107121689 ps |
| CPU time | 14.43 seconds |
| Started | Jul 12 07:29:44 PM PDT 24 |
| Finished | Jul 12 07:30:06 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-ca2173a8-c5f3-46ab-9316-b8700d369195 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719937232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2719937232 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.2986264766 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 343034803 ps |
| CPU time | 27.47 seconds |
| Started | Jul 12 07:30:09 PM PDT 24 |
| Finished | Jul 12 07:30:46 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-b2a513b3-6038-4a39-a7c6-421a278ceeb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986264766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .2986264766 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.979551991 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 121967830002 ps |
| CPU time | 2232.84 seconds |
| Started | Jul 12 07:30:09 PM PDT 24 |
| Finished | Jul 12 08:07:32 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-a2282a57-89b6-4ff7-84cf-52c10a936bd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979551991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_d evice_slow_rsp.979551991 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.1528534 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 129172259 ps |
| CPU time | 7.87 seconds |
| Started | Jul 12 07:30:09 PM PDT 24 |
| Finished | Jul 12 07:30:28 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-44d54793-87dc-49aa-a5ef-2e23d89b4d0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.1528534 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.1344287722 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 2221160421 ps |
| CPU time | 77.83 seconds |
| Started | Jul 12 07:30:07 PM PDT 24 |
| Finished | Jul 12 07:31:36 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-8f70e0a4-3c97-4bbb-b2c6-8deb91780d32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344287722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1344287722 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.1022758019 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 268633182 ps |
| CPU time | 27.99 seconds |
| Started | Jul 12 07:30:07 PM PDT 24 |
| Finished | Jul 12 07:30:46 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-849142b2-ecf3-40ca-992c-15f67ddda441 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022758019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.1022758019 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.4209205646 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 41093566282 ps |
| CPU time | 446.18 seconds |
| Started | Jul 12 07:30:07 PM PDT 24 |
| Finished | Jul 12 07:37:43 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-3f5acd25-7871-4525-9dd0-34fda5cdafa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209205646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.4209205646 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.4231206194 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 15642072800 ps |
| CPU time | 260.78 seconds |
| Started | Jul 12 07:30:06 PM PDT 24 |
| Finished | Jul 12 07:34:36 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-79bf2221-1fa1-42c0-95b4-0968c14a2f9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231206194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.4231206194 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.3278048869 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 174880647 ps |
| CPU time | 16.23 seconds |
| Started | Jul 12 07:30:06 PM PDT 24 |
| Finished | Jul 12 07:30:31 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-c451e8e2-52a3-42f3-9ab4-59f5c368f47d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278048869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del ays.3278048869 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.1052168218 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 252234855 ps |
| CPU time | 19.38 seconds |
| Started | Jul 12 07:30:06 PM PDT 24 |
| Finished | Jul 12 07:30:33 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-3d1ac1e3-dbf1-4472-aabc-5521c035afe4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052168218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1052168218 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.2271376840 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 198132144 ps |
| CPU time | 8.56 seconds |
| Started | Jul 12 07:30:09 PM PDT 24 |
| Finished | Jul 12 07:30:27 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-774c4aaa-5b49-4fa7-8e09-77d80ac018d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271376840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2271376840 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.764936610 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 4916889440 ps |
| CPU time | 58.26 seconds |
| Started | Jul 12 07:30:06 PM PDT 24 |
| Finished | Jul 12 07:31:13 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-dafecb77-a6b9-45ca-86ed-917b09507b0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764936610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.764936610 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.3792237628 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 5213355746 ps |
| CPU time | 91.41 seconds |
| Started | Jul 12 07:30:09 PM PDT 24 |
| Finished | Jul 12 07:31:50 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-3cac4f5b-e926-4202-806e-d9db004747bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792237628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3792237628 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.763660537 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 45235556 ps |
| CPU time | 6.52 seconds |
| Started | Jul 12 07:30:06 PM PDT 24 |
| Finished | Jul 12 07:30:22 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-0af51d22-8f76-4604-aa47-ae11c12b79fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763660537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays .763660537 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.408901191 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 671249026 ps |
| CPU time | 64.45 seconds |
| Started | Jul 12 07:30:07 PM PDT 24 |
| Finished | Jul 12 07:31:22 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-a7d5b602-e2f5-4ded-924f-98cda00e57dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408901191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.408901191 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.745742220 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 4426041324 ps |
| CPU time | 162.99 seconds |
| Started | Jul 12 07:30:24 PM PDT 24 |
| Finished | Jul 12 07:33:16 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-59ce8e40-1230-4ab5-8658-c07915d4005e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745742220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.745742220 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.3508076833 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 18780052648 ps |
| CPU time | 907.99 seconds |
| Started | Jul 12 07:30:29 PM PDT 24 |
| Finished | Jul 12 07:45:45 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-e9c722ae-2f4c-4756-80b6-8f85b721317e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508076833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_rand_reset.3508076833 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.1518430056 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 40722581 ps |
| CPU time | 49.08 seconds |
| Started | Jul 12 07:30:24 PM PDT 24 |
| Finished | Jul 12 07:31:22 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-1e2633df-b878-4971-b1df-43d3f1085fd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518430056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.1518430056 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.669361197 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 67887583 ps |
| CPU time | 10.96 seconds |
| Started | Jul 12 07:30:07 PM PDT 24 |
| Finished | Jul 12 07:30:29 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-78e61b86-4bde-4d6f-b328-6218bfa10b9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669361197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.669361197 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.3073956563 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 525606230 ps |
| CPU time | 49.74 seconds |
| Started | Jul 12 07:30:29 PM PDT 24 |
| Finished | Jul 12 07:31:27 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-0b51292c-c759-4e76-a450-042a95ee33d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073956563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device .3073956563 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.1722269167 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 30098499176 ps |
| CPU time | 528.09 seconds |
| Started | Jul 12 07:30:29 PM PDT 24 |
| Finished | Jul 12 07:39:25 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-6d171a8b-7548-4c70-bfc3-b880c88edb0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722269167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_ device_slow_rsp.1722269167 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.3183882140 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 230389131 ps |
| CPU time | 23.52 seconds |
| Started | Jul 12 07:30:28 PM PDT 24 |
| Finished | Jul 12 07:31:01 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-c5bd2927-a1a5-4f4e-8352-3e57952c7d62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183882140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add r.3183882140 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.2303750242 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 536014610 ps |
| CPU time | 17.2 seconds |
| Started | Jul 12 07:30:29 PM PDT 24 |
| Finished | Jul 12 07:30:54 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-d1ad4f67-a64b-4235-8981-5e102450c41d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303750242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2303750242 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.3636352640 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 215108535 ps |
| CPU time | 21.08 seconds |
| Started | Jul 12 07:30:23 PM PDT 24 |
| Finished | Jul 12 07:30:54 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-1fe642a3-71b0-4696-b656-b6199aea3095 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636352640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.3636352640 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.494996313 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 88703793719 ps |
| CPU time | 967.58 seconds |
| Started | Jul 12 07:30:28 PM PDT 24 |
| Finished | Jul 12 07:46:45 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-9a5eef97-f22d-4418-adff-b76d9bfa4fa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494996313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.494996313 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.2117263815 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 39152937805 ps |
| CPU time | 668.36 seconds |
| Started | Jul 12 07:30:22 PM PDT 24 |
| Finished | Jul 12 07:41:40 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-c1544497-d628-4d12-8d60-1e7b38da2f25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117263815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2117263815 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.4123125453 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 466647781 ps |
| CPU time | 45.16 seconds |
| Started | Jul 12 07:30:27 PM PDT 24 |
| Finished | Jul 12 07:31:20 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-ceb34416-b1de-4409-9152-833edc021929 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123125453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_del ays.4123125453 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.2959000804 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 1080744497 ps |
| CPU time | 33.15 seconds |
| Started | Jul 12 07:30:28 PM PDT 24 |
| Finished | Jul 12 07:31:09 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-bbe55842-8700-464a-8eb3-c16be09f3f0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959000804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.2959000804 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.581589159 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 180994411 ps |
| CPU time | 8.89 seconds |
| Started | Jul 12 07:30:29 PM PDT 24 |
| Finished | Jul 12 07:30:46 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-a586c30e-ab7a-4448-acbc-c8477cd8a335 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581589159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.581589159 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.2225505589 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 7977820242 ps |
| CPU time | 84.82 seconds |
| Started | Jul 12 07:30:23 PM PDT 24 |
| Finished | Jul 12 07:31:57 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-289c07f1-fe13-4a35-85a7-3bca1f88128e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225505589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2225505589 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.697988618 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 4837411699 ps |
| CPU time | 82.29 seconds |
| Started | Jul 12 07:30:28 PM PDT 24 |
| Finished | Jul 12 07:31:59 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-1cd721a6-e0b5-4b73-a292-539a0747183a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697988618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.697988618 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.2909875929 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 39662044 ps |
| CPU time | 6.31 seconds |
| Started | Jul 12 07:30:25 PM PDT 24 |
| Finished | Jul 12 07:30:39 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-dee976e1-40e2-4c56-bfea-8b23df4cc341 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909875929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.2909875929 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.1589577078 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 298532154 ps |
| CPU time | 34.52 seconds |
| Started | Jul 12 07:30:27 PM PDT 24 |
| Finished | Jul 12 07:31:10 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-98d35b36-bd62-4b4f-9644-fbef8f7eee3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589577078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1589577078 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.2597137253 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 2684523705 ps |
| CPU time | 106.16 seconds |
| Started | Jul 12 07:30:25 PM PDT 24 |
| Finished | Jul 12 07:32:20 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-a4855c9f-849c-4e79-a055-1f02c573bf41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597137253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2597137253 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.1498563305 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 522616480 ps |
| CPU time | 142.6 seconds |
| Started | Jul 12 07:38:30 PM PDT 24 |
| Finished | Jul 12 07:40:55 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-ab97e30c-6f70-4df9-851f-31bb8dd642ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498563305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.1498563305 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.1774100699 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 97709516 ps |
| CPU time | 34.9 seconds |
| Started | Jul 12 07:30:24 PM PDT 24 |
| Finished | Jul 12 07:31:08 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-037dd3b1-fff1-41f7-9264-9315966f3d44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774100699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.1774100699 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.427632401 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 105565536 ps |
| CPU time | 7.8 seconds |
| Started | Jul 12 07:30:30 PM PDT 24 |
| Finished | Jul 12 07:30:45 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-67c507ab-322b-4d23-9f4b-365e4744825d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427632401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.427632401 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.4022438428 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 3633240200 ps |
| CPU time | 257.49 seconds |
| Started | Jul 12 07:23:49 PM PDT 24 |
| Finished | Jul 12 07:28:10 PM PDT 24 |
| Peak memory | 590572 kb |
| Host | smart-35cf6713-dc36-44fb-a280-a384925175b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022438428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.4022438428 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.1829528958 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 4765933920 ps |
| CPU time | 244.91 seconds |
| Started | Jul 12 07:23:57 PM PDT 24 |
| Finished | Jul 12 07:28:04 PM PDT 24 |
| Peak memory | 661004 kb |
| Host | smart-489630ed-7a90-4acf-99d1-53b4d0c2f322 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829528958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r eset.1829528958 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.1582547654 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 6440518759 ps |
| CPU time | 737.78 seconds |
| Started | Jul 12 07:23:56 PM PDT 24 |
| Finished | Jul 12 07:36:16 PM PDT 24 |
| Peak memory | 598848 kb |
| Host | smart-02afc5a7-fd9e-48f1-bd81-9c909c5895a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582547654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.1582547654 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.3916490192 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 15524537649 ps |
| CPU time | 1799.75 seconds |
| Started | Jul 12 07:23:47 PM PDT 24 |
| Finished | Jul 12 07:53:51 PM PDT 24 |
| Peak memory | 593140 kb |
| Host | smart-bf18b3e0-abb3-4be9-b620-1b8e0c53f1d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916490192 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.3916490192 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.3545739146 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 4706991251 ps |
| CPU time | 387.12 seconds |
| Started | Jul 12 07:23:49 PM PDT 24 |
| Finished | Jul 12 07:30:19 PM PDT 24 |
| Peak memory | 603648 kb |
| Host | smart-39e40e4c-bff5-4a55-aafa-69013a2639c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545739146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.3545739146 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.2752684728 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 4003857753 ps |
| CPU time | 171.06 seconds |
| Started | Jul 12 07:23:53 PM PDT 24 |
| Finished | Jul 12 07:26:45 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-3ed5f18f-9ce5-4fc0-af37-124915566886 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752684728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device. 2752684728 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.3225920325 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 162071459805 ps |
| CPU time | 3048.05 seconds |
| Started | Jul 12 07:23:54 PM PDT 24 |
| Finished | Jul 12 08:14:45 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-847976bc-10e9-48f1-b439-783bdaa1c3f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225920325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d evice_slow_rsp.3225920325 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.86379066 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 286312920 ps |
| CPU time | 13.92 seconds |
| Started | Jul 12 07:23:57 PM PDT 24 |
| Finished | Jul 12 07:24:13 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-d5dc4398-3c42-42ce-8904-ca2fddae6444 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86379066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.86379066 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.1489406136 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 608172732 ps |
| CPU time | 52.09 seconds |
| Started | Jul 12 07:23:57 PM PDT 24 |
| Finished | Jul 12 07:24:52 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-116897dd-6a51-4aa9-9a4e-435b0f709ede |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489406136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1489406136 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.432402155 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 955160262 ps |
| CPU time | 35.6 seconds |
| Started | Jul 12 07:23:54 PM PDT 24 |
| Finished | Jul 12 07:24:32 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-badf5760-7b98-457e-b0a1-d45783c7c2fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432402155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.432402155 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.2341159745 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 15378007315 ps |
| CPU time | 167.52 seconds |
| Started | Jul 12 07:23:58 PM PDT 24 |
| Finished | Jul 12 07:26:48 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-26ef4bbe-53b5-4285-a57c-e28acbc4ff62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341159745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2341159745 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.878138290 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 4248748359 ps |
| CPU time | 79.32 seconds |
| Started | Jul 12 07:23:54 PM PDT 24 |
| Finished | Jul 12 07:25:15 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-56a759e5-b25f-4eca-ab2a-2aa0cbb71175 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878138290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.878138290 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.3688017512 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 189530755 ps |
| CPU time | 17.86 seconds |
| Started | Jul 12 07:23:55 PM PDT 24 |
| Finished | Jul 12 07:24:15 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-58e6ae2f-f490-4bf7-bcca-21dfcd015140 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688017512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela ys.3688017512 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.4146860303 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 2611192544 ps |
| CPU time | 81.7 seconds |
| Started | Jul 12 07:23:53 PM PDT 24 |
| Finished | Jul 12 07:25:16 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-9824e7db-9a89-46eb-b9e7-45d200ea4532 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146860303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.4146860303 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.4284008792 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 215691868 ps |
| CPU time | 9.36 seconds |
| Started | Jul 12 07:23:47 PM PDT 24 |
| Finished | Jul 12 07:24:00 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-1b6b5321-cf8a-4f7f-9676-d460443ac942 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284008792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.4284008792 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.808346235 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 8897290041 ps |
| CPU time | 98.95 seconds |
| Started | Jul 12 07:23:47 PM PDT 24 |
| Finished | Jul 12 07:25:28 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-e0ed09a8-6565-4b13-83f9-edc15b01fb64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808346235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.808346235 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.386650680 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 6076607959 ps |
| CPU time | 108.83 seconds |
| Started | Jul 12 07:23:55 PM PDT 24 |
| Finished | Jul 12 07:25:46 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-75a960b8-d8bd-46ae-91e5-4245db1c81e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386650680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.386650680 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.58287650 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 38173894 ps |
| CPU time | 5.79 seconds |
| Started | Jul 12 07:23:45 PM PDT 24 |
| Finished | Jul 12 07:23:53 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-07faf42b-0a53-4d69-ab20-4478e0e6400f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58287650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.58287650 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.1241583102 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 45156037 ps |
| CPU time | 5.78 seconds |
| Started | Jul 12 07:23:58 PM PDT 24 |
| Finished | Jul 12 07:24:07 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-8933cda8-ea26-4b73-9b9e-6ece6fd85947 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241583102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1241583102 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.1093619374 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 8390633888 ps |
| CPU time | 315.06 seconds |
| Started | Jul 12 07:23:55 PM PDT 24 |
| Finished | Jul 12 07:29:13 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-9cd6d404-a91d-4b5f-8298-fec09bbb243b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093619374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1093619374 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.1786237847 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 4146916221 ps |
| CPU time | 587.36 seconds |
| Started | Jul 12 07:23:56 PM PDT 24 |
| Finished | Jul 12 07:33:46 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-ff801b6c-97b3-4561-bc24-a73b1fcf949c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786237847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.1786237847 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.327567211 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 7564022016 ps |
| CPU time | 445.26 seconds |
| Started | Jul 12 07:23:54 PM PDT 24 |
| Finished | Jul 12 07:31:21 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-915c0113-3788-4df0-ade8-0fa884495782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327567211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_reset_error.327567211 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.3579067561 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 1352769895 ps |
| CPU time | 61.55 seconds |
| Started | Jul 12 07:23:55 PM PDT 24 |
| Finished | Jul 12 07:24:59 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-97a3d65d-0c6e-498e-aedd-0908c61b22a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579067561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3579067561 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.4098712435 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 87580359 ps |
| CPU time | 8.42 seconds |
| Started | Jul 12 07:30:23 PM PDT 24 |
| Finished | Jul 12 07:30:41 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-2c347c99-9d00-4a5f-b3f7-f15dc4dfbe9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098712435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device .4098712435 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.4197957731 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 50493557120 ps |
| CPU time | 917.31 seconds |
| Started | Jul 12 07:30:26 PM PDT 24 |
| Finished | Jul 12 07:45:53 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-72c54ccc-cede-4222-abe2-133bff81c2e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197957731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_ device_slow_rsp.4197957731 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.199805838 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 154045455 ps |
| CPU time | 18.84 seconds |
| Started | Jul 12 07:30:24 PM PDT 24 |
| Finished | Jul 12 07:30:52 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-08ad96be-d1a3-4b45-bb46-896d9a4875e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199805838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr .199805838 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.3861784559 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 398665978 ps |
| CPU time | 16.2 seconds |
| Started | Jul 12 07:30:29 PM PDT 24 |
| Finished | Jul 12 07:30:54 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-c9d5c6a3-ac77-4201-947a-b5f4de69b097 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861784559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3861784559 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.121970007 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 166320053 ps |
| CPU time | 17.5 seconds |
| Started | Jul 12 07:30:22 PM PDT 24 |
| Finished | Jul 12 07:30:49 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-4a1e3781-caf1-44b1-bbc7-c04bbf011b01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121970007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.121970007 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.3137588647 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 67411423824 ps |
| CPU time | 740.88 seconds |
| Started | Jul 12 07:30:29 PM PDT 24 |
| Finished | Jul 12 07:42:59 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-2330bc53-3694-4cfd-a5db-ec9d945c190e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137588647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3137588647 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.1038009001 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 2600691667 ps |
| CPU time | 43.42 seconds |
| Started | Jul 12 07:30:25 PM PDT 24 |
| Finished | Jul 12 07:31:17 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-db69b6d2-3a1c-411b-9d9f-20773eed58b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038009001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1038009001 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.3062495530 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 531683725 ps |
| CPU time | 49.17 seconds |
| Started | Jul 12 07:30:24 PM PDT 24 |
| Finished | Jul 12 07:31:22 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-61ff5018-bc34-4b06-9a84-c17552736757 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062495530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.3062495530 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.2662483216 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 346395720 ps |
| CPU time | 28.86 seconds |
| Started | Jul 12 07:30:24 PM PDT 24 |
| Finished | Jul 12 07:31:02 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-fede7966-d1a9-4792-b353-daaee1fc1b3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662483216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2662483216 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.3541061154 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 41201480 ps |
| CPU time | 6.21 seconds |
| Started | Jul 12 07:30:27 PM PDT 24 |
| Finished | Jul 12 07:30:41 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-898cdffc-fa80-47c9-9561-d27bdf3a331d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541061154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3541061154 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.546287322 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 6844762542 ps |
| CPU time | 77.38 seconds |
| Started | Jul 12 07:30:30 PM PDT 24 |
| Finished | Jul 12 07:31:55 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-7f2cd0cd-6d28-4985-8066-b51f5fd4f083 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546287322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.546287322 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.2919328669 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 3374835542 ps |
| CPU time | 59.59 seconds |
| Started | Jul 12 07:30:26 PM PDT 24 |
| Finished | Jul 12 07:31:35 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-64669fbc-cc7f-4830-acb6-66398a82c022 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919328669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2919328669 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.2092208549 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 40963289 ps |
| CPU time | 6.08 seconds |
| Started | Jul 12 07:30:24 PM PDT 24 |
| Finished | Jul 12 07:30:39 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-ca074e02-862b-40eb-9981-e71800230782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092208549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.2092208549 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.1202119686 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 3174210186 ps |
| CPU time | 279.47 seconds |
| Started | Jul 12 07:30:25 PM PDT 24 |
| Finished | Jul 12 07:35:13 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-8e9cbda1-5749-46a2-a4ac-2c72e4e3605d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202119686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1202119686 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.3707660219 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 5574116569 ps |
| CPU time | 209.86 seconds |
| Started | Jul 12 07:30:28 PM PDT 24 |
| Finished | Jul 12 07:34:05 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-d145dd61-adda-4020-acce-a40cd886876f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707660219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3707660219 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.2394112186 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 336353325 ps |
| CPU time | 197.01 seconds |
| Started | Jul 12 07:30:23 PM PDT 24 |
| Finished | Jul 12 07:33:50 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-92bf9d9c-8df4-419f-980e-c869394d6c90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394112186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_rand_reset.2394112186 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.2415065419 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 1599913508 ps |
| CPU time | 155.42 seconds |
| Started | Jul 12 07:30:27 PM PDT 24 |
| Finished | Jul 12 07:33:10 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-09712237-6364-43ad-9f79-2b97900e3110 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415065419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.2415065419 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.3519161674 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 1150907159 ps |
| CPU time | 44.09 seconds |
| Started | Jul 12 07:30:30 PM PDT 24 |
| Finished | Jul 12 07:31:22 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-97e4bbfb-20b3-4d4a-a4d0-f29862e98de3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519161674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3519161674 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.2773787385 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 125012551 ps |
| CPU time | 14.35 seconds |
| Started | Jul 12 07:30:35 PM PDT 24 |
| Finished | Jul 12 07:30:56 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-70b19639-5229-456f-b2fb-cf9da7d283e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773787385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device .2773787385 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.1438010922 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 105293634910 ps |
| CPU time | 1930.54 seconds |
| Started | Jul 12 07:30:41 PM PDT 24 |
| Finished | Jul 12 08:02:59 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-7ce787c1-75a1-4a63-a505-526e8db2fafd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438010922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.1438010922 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.2500971669 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 191434634 ps |
| CPU time | 19.65 seconds |
| Started | Jul 12 07:30:33 PM PDT 24 |
| Finished | Jul 12 07:30:59 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-9869f22a-ee94-4ef7-bd88-081f824dfafb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500971669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2500971669 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.2583270139 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 101729899 ps |
| CPU time | 6.66 seconds |
| Started | Jul 12 07:30:24 PM PDT 24 |
| Finished | Jul 12 07:30:39 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-ec99560e-99e9-4144-90b6-0bb39ba84d61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583270139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.2583270139 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.1819553668 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 70169106403 ps |
| CPU time | 758.07 seconds |
| Started | Jul 12 07:30:38 PM PDT 24 |
| Finished | Jul 12 07:43:23 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-9f573e76-933b-4c11-adbf-b70e9bb42938 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819553668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1819553668 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.1249233414 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 44316290267 ps |
| CPU time | 776.56 seconds |
| Started | Jul 12 07:30:39 PM PDT 24 |
| Finished | Jul 12 07:43:42 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-5a1e7a7a-a12d-488c-aa2d-d3ae0b98eaa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249233414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1249233414 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.810745203 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 587205882 ps |
| CPU time | 48.57 seconds |
| Started | Jul 12 07:30:41 PM PDT 24 |
| Finished | Jul 12 07:31:36 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-64c30221-3283-4c67-885a-d45ca67cd95a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810745203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_dela ys.810745203 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.4136007695 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 448294058 ps |
| CPU time | 31.07 seconds |
| Started | Jul 12 07:30:35 PM PDT 24 |
| Finished | Jul 12 07:31:13 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-ae35cfc4-e86b-4394-8b86-1c02f4dc8c8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136007695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.4136007695 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.2640041171 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 165112669 ps |
| CPU time | 8.03 seconds |
| Started | Jul 12 07:30:24 PM PDT 24 |
| Finished | Jul 12 07:30:41 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-0d62a508-48ae-49b4-ab55-fea589c8d816 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640041171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2640041171 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.2560209635 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 9039105946 ps |
| CPU time | 101.32 seconds |
| Started | Jul 12 07:30:25 PM PDT 24 |
| Finished | Jul 12 07:32:15 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-605821bd-7862-43f3-84f2-60e40e37198a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560209635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2560209635 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.2201799705 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 5164066430 ps |
| CPU time | 95.77 seconds |
| Started | Jul 12 07:30:25 PM PDT 24 |
| Finished | Jul 12 07:32:10 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-23c88500-8349-473d-9013-cd7819ba237c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201799705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2201799705 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.4165006646 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 39313670 ps |
| CPU time | 5.57 seconds |
| Started | Jul 12 07:30:28 PM PDT 24 |
| Finished | Jul 12 07:30:42 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-5f5267a9-258b-45b8-8752-bd6731602088 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165006646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.4165006646 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.4053237841 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 11193716881 ps |
| CPU time | 419.74 seconds |
| Started | Jul 12 07:30:40 PM PDT 24 |
| Finished | Jul 12 07:37:47 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-c67277ec-7025-477d-81f3-555121ba4673 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053237841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.4053237841 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.3947588988 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 4142652656 ps |
| CPU time | 273.7 seconds |
| Started | Jul 12 07:30:39 PM PDT 24 |
| Finished | Jul 12 07:35:20 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-1f187bd4-2522-4edb-8b9e-203eebb353b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947588988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3947588988 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.3713645277 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 1220215318 ps |
| CPU time | 149.11 seconds |
| Started | Jul 12 07:30:39 PM PDT 24 |
| Finished | Jul 12 07:33:15 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-fbe56dcc-0c98-4972-a67b-7144ec0426f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713645277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.3713645277 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.1759272722 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 89175737 ps |
| CPU time | 12.59 seconds |
| Started | Jul 12 07:30:38 PM PDT 24 |
| Finished | Jul 12 07:30:57 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-5a4fb7f6-5b5c-43a3-b69f-8999ce3118e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759272722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1759272722 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.3588392737 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 1396181541 ps |
| CPU time | 70.83 seconds |
| Started | Jul 12 07:30:41 PM PDT 24 |
| Finished | Jul 12 07:31:59 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-ed046b2c-f7ca-4c93-815e-d2f9e69236fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588392737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device .3588392737 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.3142603808 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 60372143149 ps |
| CPU time | 1043.85 seconds |
| Started | Jul 12 07:30:41 PM PDT 24 |
| Finished | Jul 12 07:48:13 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-9682bd0a-2b6c-4029-ba6f-23b635ceb7a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142603808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_ device_slow_rsp.3142603808 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.2689730271 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 203949805 ps |
| CPU time | 20.79 seconds |
| Started | Jul 12 07:30:38 PM PDT 24 |
| Finished | Jul 12 07:31:06 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-89bd550c-db26-45ab-813e-94047dc80f68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689730271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add r.2689730271 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.3360422184 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 575659918 ps |
| CPU time | 20.94 seconds |
| Started | Jul 12 07:30:39 PM PDT 24 |
| Finished | Jul 12 07:31:06 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-a1240677-0f64-4bad-b02a-41d17fa355ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360422184 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3360422184 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.2049668078 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 347363725 ps |
| CPU time | 29.21 seconds |
| Started | Jul 12 07:30:40 PM PDT 24 |
| Finished | Jul 12 07:31:16 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-ec71f43d-6136-4cfc-9ef3-278b6be5bdc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049668078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.2049668078 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.2129012026 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 56090545169 ps |
| CPU time | 608.64 seconds |
| Started | Jul 12 07:30:40 PM PDT 24 |
| Finished | Jul 12 07:40:56 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-4e6d41bc-c371-4baa-b6b9-c7e288ff6baf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129012026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2129012026 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.3739766463 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 63541668140 ps |
| CPU time | 1107.22 seconds |
| Started | Jul 12 07:30:35 PM PDT 24 |
| Finished | Jul 12 07:49:09 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-583e13ca-240b-496b-9c98-959be564ffa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739766463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.3739766463 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.18394478 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 72553729 ps |
| CPU time | 9.39 seconds |
| Started | Jul 12 07:30:38 PM PDT 24 |
| Finished | Jul 12 07:30:54 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-f5a81678-9728-4c6f-8d88-292c93eea8d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18394478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delay s.18394478 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.421593164 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 128594797 ps |
| CPU time | 12.22 seconds |
| Started | Jul 12 07:30:40 PM PDT 24 |
| Finished | Jul 12 07:31:00 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-a805b70c-141b-4f5d-b61f-d67924c8af3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421593164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.421593164 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.1413532388 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 183192662 ps |
| CPU time | 8.07 seconds |
| Started | Jul 12 07:30:39 PM PDT 24 |
| Finished | Jul 12 07:30:55 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-8c417e04-233b-4f75-99df-0d7690242290 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413532388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1413532388 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.3396163697 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 6465317829 ps |
| CPU time | 71.11 seconds |
| Started | Jul 12 07:30:34 PM PDT 24 |
| Finished | Jul 12 07:31:52 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-41ac6d31-aa09-4fa7-a55b-51327cd97811 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396163697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.3396163697 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.889887686 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 5968494496 ps |
| CPU time | 108.87 seconds |
| Started | Jul 12 07:30:31 PM PDT 24 |
| Finished | Jul 12 07:32:28 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-547594cc-82e5-4998-96d4-0cb582719e5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889887686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.889887686 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.3933277758 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 53688713 ps |
| CPU time | 6.2 seconds |
| Started | Jul 12 07:30:34 PM PDT 24 |
| Finished | Jul 12 07:30:47 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-2f939797-ce86-412a-85be-c2845b771040 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933277758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay s.3933277758 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.1859935312 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 1660287201 ps |
| CPU time | 131.56 seconds |
| Started | Jul 12 07:30:42 PM PDT 24 |
| Finished | Jul 12 07:33:01 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-099870c5-f956-4c54-9d43-f61b0f98ce20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859935312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1859935312 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2077021785 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 581581542 ps |
| CPU time | 153.39 seconds |
| Started | Jul 12 07:30:45 PM PDT 24 |
| Finished | Jul 12 07:33:28 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-2c610222-f394-4920-9977-4ea78300668c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077021785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.2077021785 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.4272123167 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 3724227291 ps |
| CPU time | 219.78 seconds |
| Started | Jul 12 07:30:45 PM PDT 24 |
| Finished | Jul 12 07:34:33 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-1fcd8d54-633a-4ef9-985c-a005a2cc477e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272123167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al l_with_reset_error.4272123167 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.3861531526 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 365364436 ps |
| CPU time | 18.65 seconds |
| Started | Jul 12 07:30:40 PM PDT 24 |
| Finished | Jul 12 07:31:06 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-b60ce317-45f6-4a4f-8a14-fa7cd7614033 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861531526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3861531526 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.2029529387 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 806975851 ps |
| CPU time | 56.35 seconds |
| Started | Jul 12 07:30:46 PM PDT 24 |
| Finished | Jul 12 07:31:51 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-c4b21108-7616-4be6-b880-f6a3b7bcf9c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029529387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device .2029529387 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1730884275 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 129305636762 ps |
| CPU time | 2724.03 seconds |
| Started | Jul 12 07:30:49 PM PDT 24 |
| Finished | Jul 12 08:16:23 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-c6e46e26-7621-4a4d-95cc-59c3582064c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730884275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_ device_slow_rsp.1730884275 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.1499591777 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 1178943394 ps |
| CPU time | 46.22 seconds |
| Started | Jul 12 07:30:47 PM PDT 24 |
| Finished | Jul 12 07:31:42 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-0c67438c-9e58-4c4b-b5b8-9beab9a08180 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499591777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.1499591777 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.3534095894 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 768149735 ps |
| CPU time | 28.67 seconds |
| Started | Jul 12 07:30:47 PM PDT 24 |
| Finished | Jul 12 07:31:24 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-e214465e-676b-4191-a685-b70dad7b7f88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534095894 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3534095894 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.2813608522 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 403707026 ps |
| CPU time | 15.34 seconds |
| Started | Jul 12 07:30:46 PM PDT 24 |
| Finished | Jul 12 07:31:10 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-83002027-88f4-4c2c-b640-a8cf1844d47c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813608522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.2813608522 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.2793419231 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 92888775653 ps |
| CPU time | 1061.43 seconds |
| Started | Jul 12 07:30:48 PM PDT 24 |
| Finished | Jul 12 07:48:38 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-15d5b510-b531-494f-96dc-a5288ea15eaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793419231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2793419231 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.2336059345 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 51883553337 ps |
| CPU time | 972.91 seconds |
| Started | Jul 12 07:30:44 PM PDT 24 |
| Finished | Jul 12 07:47:05 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-8635a294-4d92-4bb4-8a35-f4b08462129d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336059345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2336059345 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.826084083 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 61994366 ps |
| CPU time | 8.47 seconds |
| Started | Jul 12 07:30:44 PM PDT 24 |
| Finished | Jul 12 07:31:02 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-748e8b6a-074c-457f-a466-b15674921fd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826084083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_dela ys.826084083 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.2885537061 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 403890094 ps |
| CPU time | 28.25 seconds |
| Started | Jul 12 07:30:44 PM PDT 24 |
| Finished | Jul 12 07:31:21 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-947bc1e4-e985-40bf-8ab2-8eff3b95023c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885537061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2885537061 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.1016738315 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 50253590 ps |
| CPU time | 5.87 seconds |
| Started | Jul 12 07:30:46 PM PDT 24 |
| Finished | Jul 12 07:31:00 PM PDT 24 |
| Peak memory | 574012 kb |
| Host | smart-eb7dea52-089f-4ccd-b4e7-9bd0d14cd26c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016738315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1016738315 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.3712021847 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 7268821555 ps |
| CPU time | 81.41 seconds |
| Started | Jul 12 07:30:49 PM PDT 24 |
| Finished | Jul 12 07:32:20 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-fa181bce-8f3d-41ae-9957-0e0c096c12ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712021847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3712021847 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.1414415053 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 4580081466 ps |
| CPU time | 80.27 seconds |
| Started | Jul 12 07:30:43 PM PDT 24 |
| Finished | Jul 12 07:32:11 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-17729d52-48e7-4519-8a76-a0596019cec0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414415053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1414415053 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.870888298 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 43088166 ps |
| CPU time | 5.65 seconds |
| Started | Jul 12 07:30:46 PM PDT 24 |
| Finished | Jul 12 07:31:00 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-8dca98e7-35cc-4b08-a3a3-f42f770f2305 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870888298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays .870888298 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.2284937825 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 1681236314 ps |
| CPU time | 68.47 seconds |
| Started | Jul 12 07:30:44 PM PDT 24 |
| Finished | Jul 12 07:32:02 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-6950dccb-a727-419a-90e0-daccad7f001f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284937825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2284937825 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.2144636850 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 8821440288 ps |
| CPU time | 310.84 seconds |
| Started | Jul 12 07:30:44 PM PDT 24 |
| Finished | Jul 12 07:36:03 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-a6254b6e-5414-470e-b355-01ea83354ff0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144636850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2144636850 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.2996017683 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 143255291 ps |
| CPU time | 46.48 seconds |
| Started | Jul 12 07:30:48 PM PDT 24 |
| Finished | Jul 12 07:31:43 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-ea85c601-2107-43a6-b9c7-d4ead72d2790 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996017683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.2996017683 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.771309828 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 2663131543 ps |
| CPU time | 136.11 seconds |
| Started | Jul 12 07:30:45 PM PDT 24 |
| Finished | Jul 12 07:33:10 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-4f7876be-deb2-4b12-b928-e42de6ac9035 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771309828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_reset_error.771309828 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.2848878436 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 17662597 ps |
| CPU time | 5.43 seconds |
| Started | Jul 12 07:30:47 PM PDT 24 |
| Finished | Jul 12 07:31:01 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-c6592342-bf5b-4b43-aa04-bfa7caed98a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848878436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2848878436 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.3902654553 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 305779196 ps |
| CPU time | 13.03 seconds |
| Started | Jul 12 07:30:58 PM PDT 24 |
| Finished | Jul 12 07:31:20 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-2b1fbb8e-644f-40ce-a0b1-5af44b993a97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902654553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .3902654553 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.1195160602 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 1178467774 ps |
| CPU time | 44.23 seconds |
| Started | Jul 12 07:30:58 PM PDT 24 |
| Finished | Jul 12 07:31:51 PM PDT 24 |
| Peak memory | 575192 kb |
| Host | smart-9b2005e8-1ead-44b3-9ab4-d323c4db2db3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195160602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add r.1195160602 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.1068571253 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 1703621807 ps |
| CPU time | 62.05 seconds |
| Started | Jul 12 07:30:58 PM PDT 24 |
| Finished | Jul 12 07:32:09 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-45ac483b-1f0d-4704-81e8-cb43559c15a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068571253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1068571253 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.1303475016 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 1490435683 ps |
| CPU time | 53.82 seconds |
| Started | Jul 12 07:31:01 PM PDT 24 |
| Finished | Jul 12 07:32:04 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-24e3240e-54c3-41c4-b6f9-e133259094f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303475016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.1303475016 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.399630177 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 101444018134 ps |
| CPU time | 1147.21 seconds |
| Started | Jul 12 07:30:58 PM PDT 24 |
| Finished | Jul 12 07:50:14 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-597713c5-1a7e-4e18-948b-115cb9f0bca2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399630177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.399630177 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.2022818643 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 58457872907 ps |
| CPU time | 1070.25 seconds |
| Started | Jul 12 07:41:48 PM PDT 24 |
| Finished | Jul 12 07:59:40 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-eefd6379-8e38-4d06-a94e-f76926bd1fe8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022818643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2022818643 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.2298393867 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 617534292 ps |
| CPU time | 52.58 seconds |
| Started | Jul 12 07:30:58 PM PDT 24 |
| Finished | Jul 12 07:31:59 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-ae2dd240-17e7-4db2-be56-eadd00b43026 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298393867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.2298393867 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.1973487325 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 395510115 ps |
| CPU time | 30.17 seconds |
| Started | Jul 12 07:31:03 PM PDT 24 |
| Finished | Jul 12 07:31:42 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-3b67c898-348d-4134-8204-2df8e760acec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973487325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1973487325 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.527017151 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 46208130 ps |
| CPU time | 6.26 seconds |
| Started | Jul 12 07:30:44 PM PDT 24 |
| Finished | Jul 12 07:30:58 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-8892aac8-2c4e-45e7-920d-e3c0044d8d60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527017151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.527017151 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.97449703 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 9346052861 ps |
| CPU time | 97.72 seconds |
| Started | Jul 12 07:30:47 PM PDT 24 |
| Finished | Jul 12 07:32:33 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-1c4ef56b-8227-40cb-abe7-26a354fde17e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97449703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.97449703 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.1915669839 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 5534405375 ps |
| CPU time | 92.62 seconds |
| Started | Jul 12 07:30:59 PM PDT 24 |
| Finished | Jul 12 07:32:40 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-a4a7f64a-e37b-4e70-9e26-fccdb722a393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915669839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1915669839 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.2960344993 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 43194857 ps |
| CPU time | 6.08 seconds |
| Started | Jul 12 07:30:45 PM PDT 24 |
| Finished | Jul 12 07:30:59 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-91dc2e06-0947-41b8-9d46-21b8d00f2d2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960344993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay s.2960344993 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.4134749983 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 6517656037 ps |
| CPU time | 243.06 seconds |
| Started | Jul 12 07:31:00 PM PDT 24 |
| Finished | Jul 12 07:35:13 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-36fb8970-cbbf-4572-a6d8-dd9c60c2a423 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134749983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.4134749983 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.1664096409 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 12634605528 ps |
| CPU time | 750.4 seconds |
| Started | Jul 12 07:30:59 PM PDT 24 |
| Finished | Jul 12 07:43:39 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-001d946f-9da3-4af9-9f24-496378a4ff17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664096409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.1664096409 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.1785258570 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 249222308 ps |
| CPU time | 84.72 seconds |
| Started | Jul 12 07:31:00 PM PDT 24 |
| Finished | Jul 12 07:32:33 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-5ac668bb-4ad7-44e6-8a8d-59605807bae2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785258570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.1785258570 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.563510929 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 281397841 ps |
| CPU time | 32.02 seconds |
| Started | Jul 12 07:31:00 PM PDT 24 |
| Finished | Jul 12 07:31:41 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-8da3293f-d7ae-482f-ba88-4579cbb98b38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563510929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.563510929 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.3145605443 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 1510188706 ps |
| CPU time | 88.01 seconds |
| Started | Jul 12 07:31:15 PM PDT 24 |
| Finished | Jul 12 07:32:48 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-383bb058-17b0-45c0-9657-511f7c483a7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145605443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .3145605443 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.1656154306 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 135759822304 ps |
| CPU time | 2344.8 seconds |
| Started | Jul 12 07:31:14 PM PDT 24 |
| Finished | Jul 12 08:10:24 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-4d2d507d-84b7-4b41-a8a9-5e746b1e9651 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656154306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.1656154306 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.1619032149 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 1167333689 ps |
| CPU time | 44.54 seconds |
| Started | Jul 12 07:31:14 PM PDT 24 |
| Finished | Jul 12 07:32:04 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-1426d904-b238-4a07-bbdf-574f3e16c9f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619032149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add r.1619032149 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.3644572376 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 383011350 ps |
| CPU time | 14.19 seconds |
| Started | Jul 12 07:31:15 PM PDT 24 |
| Finished | Jul 12 07:31:35 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-62cc3f89-3eff-4b1b-9cc7-62700c31d48b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644572376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3644572376 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.2435945121 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 397226116 ps |
| CPU time | 15.03 seconds |
| Started | Jul 12 07:31:02 PM PDT 24 |
| Finished | Jul 12 07:31:26 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-edc48453-b979-45c0-aa4d-d377c7b15bbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435945121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.2435945121 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.661808578 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 68249209008 ps |
| CPU time | 761.89 seconds |
| Started | Jul 12 07:30:59 PM PDT 24 |
| Finished | Jul 12 07:43:51 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-352dbaac-af0a-47bd-bd74-85e097571543 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661808578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.661808578 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.3927862401 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 65067580496 ps |
| CPU time | 1150.34 seconds |
| Started | Jul 12 07:31:15 PM PDT 24 |
| Finished | Jul 12 07:50:31 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-3865fe1d-f976-48ff-9b9d-2db4769d5659 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927862401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3927862401 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.2915730190 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 257364111 ps |
| CPU time | 22.78 seconds |
| Started | Jul 12 07:30:58 PM PDT 24 |
| Finished | Jul 12 07:31:29 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-12e33b4e-5556-4144-b117-5fec846fecfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915730190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del ays.2915730190 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.2235617045 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 109102548 ps |
| CPU time | 10.14 seconds |
| Started | Jul 12 07:31:14 PM PDT 24 |
| Finished | Jul 12 07:31:29 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-a42a627e-e8d6-41c3-9376-46402c37f430 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235617045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2235617045 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.4030225125 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 49465352 ps |
| CPU time | 6.18 seconds |
| Started | Jul 12 07:30:58 PM PDT 24 |
| Finished | Jul 12 07:31:14 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-d75a96c0-9b20-497d-8983-183bcada2f9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030225125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.4030225125 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.2404596323 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 9720180787 ps |
| CPU time | 109.83 seconds |
| Started | Jul 12 07:31:00 PM PDT 24 |
| Finished | Jul 12 07:33:00 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-f4fe22d9-a702-40f6-b1d3-2c92e056d618 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404596323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2404596323 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.246219143 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 4492192827 ps |
| CPU time | 77.14 seconds |
| Started | Jul 12 07:30:59 PM PDT 24 |
| Finished | Jul 12 07:32:26 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-1329c812-348a-4d2e-beae-94bb6d1caf38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246219143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.246219143 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.2379540685 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 48010941 ps |
| CPU time | 6.56 seconds |
| Started | Jul 12 07:30:58 PM PDT 24 |
| Finished | Jul 12 07:31:14 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-142000f2-2c8a-4efc-9824-bbdc2051b1ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379540685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay s.2379540685 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.3618828993 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 177465277 ps |
| CPU time | 8.78 seconds |
| Started | Jul 12 07:31:14 PM PDT 24 |
| Finished | Jul 12 07:31:28 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-b8816d18-5d5e-4611-a62b-b360ce1f7782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618828993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3618828993 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.387769532 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 2162547479 ps |
| CPU time | 173.05 seconds |
| Started | Jul 12 07:31:17 PM PDT 24 |
| Finished | Jul 12 07:34:15 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-2957c2cc-ac1f-48fd-8a0f-29df0feedd2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387769532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_ with_rand_reset.387769532 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.2406717491 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 267153527 ps |
| CPU time | 64.24 seconds |
| Started | Jul 12 07:31:12 PM PDT 24 |
| Finished | Jul 12 07:32:23 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-77364194-24d8-4213-adb4-ec2ff4570d93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406717491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.2406717491 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.3930266228 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 1152712793 ps |
| CPU time | 47.04 seconds |
| Started | Jul 12 07:31:11 PM PDT 24 |
| Finished | Jul 12 07:32:04 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-4d834dc6-4c0a-4ec3-91bf-94a14ec9ce5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930266228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3930266228 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.2239667015 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 224927026 ps |
| CPU time | 19.28 seconds |
| Started | Jul 12 07:31:30 PM PDT 24 |
| Finished | Jul 12 07:31:51 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-35aff616-1f3e-48e7-9816-710519f7988f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239667015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device .2239667015 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.924523369 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 60942099415 ps |
| CPU time | 1157.88 seconds |
| Started | Jul 12 07:31:26 PM PDT 24 |
| Finished | Jul 12 07:50:47 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-e76bf6ad-2328-4ab1-ac76-e2c48a95c7c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924523369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_d evice_slow_rsp.924523369 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.2906647445 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 1286204428 ps |
| CPU time | 51.15 seconds |
| Started | Jul 12 07:31:26 PM PDT 24 |
| Finished | Jul 12 07:32:19 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-0238db33-38f1-4f7b-a408-9b4e13da46f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906647445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add r.2906647445 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.2014073656 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 433597823 ps |
| CPU time | 35.49 seconds |
| Started | Jul 12 07:31:44 PM PDT 24 |
| Finished | Jul 12 07:32:26 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-dc714dc8-2bfa-4ab7-a949-c4dd190b5768 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014073656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2014073656 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.3053467859 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 2282857705 ps |
| CPU time | 80.16 seconds |
| Started | Jul 12 07:31:14 PM PDT 24 |
| Finished | Jul 12 07:32:39 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-343a7cf8-e9ee-459e-9526-8d6a49e97b01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053467859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.3053467859 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.3179923358 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 76078862996 ps |
| CPU time | 883.32 seconds |
| Started | Jul 12 07:31:26 PM PDT 24 |
| Finished | Jul 12 07:46:12 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-16790996-b888-4a15-b41e-bc4a9cab7557 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179923358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3179923358 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.2400698600 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 3876766391 ps |
| CPU time | 69.99 seconds |
| Started | Jul 12 07:31:25 PM PDT 24 |
| Finished | Jul 12 07:32:37 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-11b2c970-aa2c-43f8-8cfe-4333f8aea966 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400698600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2400698600 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.3393352094 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 45925884 ps |
| CPU time | 7.45 seconds |
| Started | Jul 12 07:31:26 PM PDT 24 |
| Finished | Jul 12 07:31:36 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-ae7b0a4f-f402-487b-a1dd-b8a490c3b6a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393352094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del ays.3393352094 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.2650958201 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 1601015177 ps |
| CPU time | 52.48 seconds |
| Started | Jul 12 07:31:27 PM PDT 24 |
| Finished | Jul 12 07:32:22 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-d308c720-8ed0-4d65-a607-c703a21916ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650958201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2650958201 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.4004951013 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 168400076 ps |
| CPU time | 8.28 seconds |
| Started | Jul 12 07:31:15 PM PDT 24 |
| Finished | Jul 12 07:31:29 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-57214b01-6a08-42ca-a2fd-887fc83eacc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004951013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.4004951013 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.767356418 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 7629698688 ps |
| CPU time | 82.82 seconds |
| Started | Jul 12 07:31:14 PM PDT 24 |
| Finished | Jul 12 07:32:42 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-151f9d01-e085-4733-85b9-9fa45af36800 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767356418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.767356418 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.1301969347 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 3474133279 ps |
| CPU time | 62.52 seconds |
| Started | Jul 12 07:31:13 PM PDT 24 |
| Finished | Jul 12 07:32:21 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-90a313ee-19c8-4fd3-954d-b1fd5d080af3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301969347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1301969347 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.1968705936 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 54744120 ps |
| CPU time | 6.72 seconds |
| Started | Jul 12 07:31:15 PM PDT 24 |
| Finished | Jul 12 07:31:27 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-4ea0e8da-7a19-446e-944c-3fc89e7b1afa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968705936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.1968705936 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.1800576639 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 1082991657 ps |
| CPU time | 93.14 seconds |
| Started | Jul 12 07:31:27 PM PDT 24 |
| Finished | Jul 12 07:33:03 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-a2aadff5-2f39-481b-a8ea-6223db8683f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800576639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1800576639 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.885411401 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 6427838259 ps |
| CPU time | 210.17 seconds |
| Started | Jul 12 07:31:25 PM PDT 24 |
| Finished | Jul 12 07:34:57 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-94552520-0f1e-4441-851c-02d019094b81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885411401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.885411401 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.1242151152 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 11339555625 ps |
| CPU time | 488.83 seconds |
| Started | Jul 12 07:31:28 PM PDT 24 |
| Finished | Jul 12 07:39:39 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-73665bdb-1da8-4437-8d44-b5fa0fdf571c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242151152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.1242151152 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.1244054022 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 3337784318 ps |
| CPU time | 259.51 seconds |
| Started | Jul 12 07:31:27 PM PDT 24 |
| Finished | Jul 12 07:35:49 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-e897a7db-060d-462c-a199-c2523e9e5769 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244054022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.1244054022 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.247762838 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 333839249 ps |
| CPU time | 36.99 seconds |
| Started | Jul 12 07:31:27 PM PDT 24 |
| Finished | Jul 12 07:32:06 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-84f9f398-89bd-4576-9af1-e6baf1b896ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247762838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.247762838 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.4010104703 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 14983734 ps |
| CPU time | 6.07 seconds |
| Started | Jul 12 07:31:27 PM PDT 24 |
| Finished | Jul 12 07:31:36 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-8c9d6776-1fe8-4302-ac3a-b620bbb9f613 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010104703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device .4010104703 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.2238009547 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 108301639260 ps |
| CPU time | 2082.46 seconds |
| Started | Jul 12 07:31:23 PM PDT 24 |
| Finished | Jul 12 08:06:08 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-293ac7ad-e69d-4a95-8a3a-eee7eb47495d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238009547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.2238009547 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.17688949 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 619018853 ps |
| CPU time | 25.25 seconds |
| Started | Jul 12 07:31:36 PM PDT 24 |
| Finished | Jul 12 07:32:07 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-9e1776c3-454d-491b-b91e-df78e2801ff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17688949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.17688949 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.1618376846 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 1586240676 ps |
| CPU time | 61.43 seconds |
| Started | Jul 12 07:31:35 PM PDT 24 |
| Finished | Jul 12 07:32:42 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-1e22bf9b-132b-4b94-b273-94eff49b5606 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618376846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1618376846 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.2167958354 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 174250164 ps |
| CPU time | 18.2 seconds |
| Started | Jul 12 07:31:27 PM PDT 24 |
| Finished | Jul 12 07:31:48 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-088a2b3f-1e80-4bc3-b7cf-872922ae4e43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167958354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.2167958354 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.3644576139 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 71189810783 ps |
| CPU time | 835.12 seconds |
| Started | Jul 12 07:31:23 PM PDT 24 |
| Finished | Jul 12 07:45:21 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-f96e781d-4b33-4ddd-b5c4-be1f150f1e4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644576139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3644576139 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.2748769983 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 6451772443 ps |
| CPU time | 112.04 seconds |
| Started | Jul 12 07:31:24 PM PDT 24 |
| Finished | Jul 12 07:33:18 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-5367255c-0342-46a8-a613-9d0345accfe7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748769983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2748769983 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.1091480530 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 462719272 ps |
| CPU time | 36.78 seconds |
| Started | Jul 12 07:31:26 PM PDT 24 |
| Finished | Jul 12 07:32:06 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-d0001075-6bb1-4438-9777-ec662b70e8b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091480530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del ays.1091480530 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.1142229964 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 2519664054 ps |
| CPU time | 74.35 seconds |
| Started | Jul 12 07:31:38 PM PDT 24 |
| Finished | Jul 12 07:32:59 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-ac8fb126-4a2b-4117-8963-c10a42966f1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142229964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1142229964 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.1672471472 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 250182809 ps |
| CPU time | 10.62 seconds |
| Started | Jul 12 07:31:26 PM PDT 24 |
| Finished | Jul 12 07:31:39 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-87e59b65-e47a-4709-ae5c-5fad82a8bd3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672471472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1672471472 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.2714497114 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 7098220822 ps |
| CPU time | 78.57 seconds |
| Started | Jul 12 07:31:24 PM PDT 24 |
| Finished | Jul 12 07:32:45 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-3de75097-59ac-4e6e-a1e2-4f9ef0124edc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714497114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2714497114 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.3284547002 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 4889934157 ps |
| CPU time | 87.18 seconds |
| Started | Jul 12 07:31:28 PM PDT 24 |
| Finished | Jul 12 07:32:58 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-5005b6c1-0735-4684-869f-c3a7f886676e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284547002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3284547002 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.154813871 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 41619723 ps |
| CPU time | 6.12 seconds |
| Started | Jul 12 07:31:31 PM PDT 24 |
| Finished | Jul 12 07:31:39 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-8a4f70ac-ad36-400e-a64e-045b4036d077 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154813871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays .154813871 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.1378799535 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 3772515510 ps |
| CPU time | 284.7 seconds |
| Started | Jul 12 07:31:37 PM PDT 24 |
| Finished | Jul 12 07:36:27 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-bdf51e9b-3888-4c7c-a798-6389924255a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378799535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1378799535 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.16114067 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 2984414874 ps |
| CPU time | 346.63 seconds |
| Started | Jul 12 07:31:37 PM PDT 24 |
| Finished | Jul 12 07:37:31 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-01872cd9-2f61-4db8-816b-953dffb89061 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16114067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_w ith_rand_reset.16114067 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.1481022010 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 787371765 ps |
| CPU time | 38.29 seconds |
| Started | Jul 12 07:31:36 PM PDT 24 |
| Finished | Jul 12 07:32:20 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-823b49e4-814f-4002-9785-df199f148864 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481022010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1481022010 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.1851201363 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 696747353 ps |
| CPU time | 59.56 seconds |
| Started | Jul 12 07:31:36 PM PDT 24 |
| Finished | Jul 12 07:32:42 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-fb7819b7-ff74-4c17-b209-848aaee08ada |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851201363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .1851201363 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.4278691763 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 98841296957 ps |
| CPU time | 1937.25 seconds |
| Started | Jul 12 07:31:48 PM PDT 24 |
| Finished | Jul 12 08:04:12 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-d60567c4-0e84-4740-b6c0-467f09afbeed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278691763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.4278691763 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.1191616052 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 301098476 ps |
| CPU time | 33.05 seconds |
| Started | Jul 12 07:31:36 PM PDT 24 |
| Finished | Jul 12 07:32:14 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-92ab8907-ce41-4136-a038-62cb3e5839a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191616052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.1191616052 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.2650909222 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 34631145 ps |
| CPU time | 5.92 seconds |
| Started | Jul 12 07:31:41 PM PDT 24 |
| Finished | Jul 12 07:31:54 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-d4a95f45-5599-407a-8909-0645e5e5317e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650909222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2650909222 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.4202571358 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 674136480 ps |
| CPU time | 29.9 seconds |
| Started | Jul 12 07:31:37 PM PDT 24 |
| Finished | Jul 12 07:32:12 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-9efa575f-5658-4520-b946-ecb3633d134c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202571358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.4202571358 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.1152015219 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 89685294646 ps |
| CPU time | 979.99 seconds |
| Started | Jul 12 07:31:42 PM PDT 24 |
| Finished | Jul 12 07:48:09 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-82b7d9cf-3974-4531-afd2-4db7a65d418d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152015219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1152015219 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.2634771764 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 63776835710 ps |
| CPU time | 1188.54 seconds |
| Started | Jul 12 07:31:40 PM PDT 24 |
| Finished | Jul 12 07:51:36 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-d6936e69-2ca7-4d39-ae9f-3f47a5b418dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634771764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2634771764 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.1589338814 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 551296744 ps |
| CPU time | 44.86 seconds |
| Started | Jul 12 07:31:47 PM PDT 24 |
| Finished | Jul 12 07:32:39 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-926e1a7a-e91f-4adc-be30-a60106720d55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589338814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.1589338814 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.3461335130 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 320986951 ps |
| CPU time | 24.01 seconds |
| Started | Jul 12 07:31:41 PM PDT 24 |
| Finished | Jul 12 07:32:12 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-b012a921-05a7-474e-a27b-24b1ee070d6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461335130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3461335130 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.113586372 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 181061082 ps |
| CPU time | 9.39 seconds |
| Started | Jul 12 07:31:37 PM PDT 24 |
| Finished | Jul 12 07:31:52 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-68c8d13a-ca63-4968-8bc1-f9685adb47eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113586372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.113586372 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.1370156760 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 6653593305 ps |
| CPU time | 76.77 seconds |
| Started | Jul 12 07:31:39 PM PDT 24 |
| Finished | Jul 12 07:33:02 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-0b7677d2-2268-4bf3-9205-cddb79489337 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370156760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1370156760 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.3126943194 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 4376989708 ps |
| CPU time | 76.44 seconds |
| Started | Jul 12 07:31:39 PM PDT 24 |
| Finished | Jul 12 07:33:02 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-db540d73-f1d4-4802-9b98-b7735496fe25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126943194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3126943194 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.4265139356 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 51225782 ps |
| CPU time | 6.63 seconds |
| Started | Jul 12 07:31:34 PM PDT 24 |
| Finished | Jul 12 07:31:46 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-e8d9eb96-fea7-4d8c-bec2-8196e7a0fbdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265139356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delay s.4265139356 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.1577183457 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 196468899 ps |
| CPU time | 15.15 seconds |
| Started | Jul 12 07:31:37 PM PDT 24 |
| Finished | Jul 12 07:31:59 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-334f10ff-2fb1-4031-a15f-e6f26f556989 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577183457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1577183457 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.2237713321 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 6868305078 ps |
| CPU time | 487.29 seconds |
| Started | Jul 12 07:31:47 PM PDT 24 |
| Finished | Jul 12 07:40:02 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-695bb6dc-8034-4b9c-9410-ba1734887be2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237713321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.2237713321 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.2473511989 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 5762046327 ps |
| CPU time | 467.86 seconds |
| Started | Jul 12 07:31:37 PM PDT 24 |
| Finished | Jul 12 07:39:31 PM PDT 24 |
| Peak memory | 577892 kb |
| Host | smart-ee859aac-573a-4fc9-8ea4-718908d4505b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473511989 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al l_with_reset_error.2473511989 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.2160299603 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 202059866 ps |
| CPU time | 25.28 seconds |
| Started | Jul 12 07:31:39 PM PDT 24 |
| Finished | Jul 12 07:32:11 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-018f3811-8d24-4938-a5cf-ef507c649349 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160299603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2160299603 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.4123200764 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 728137801 ps |
| CPU time | 49.17 seconds |
| Started | Jul 12 07:31:59 PM PDT 24 |
| Finished | Jul 12 07:32:51 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-83e563ca-7bb1-4b73-9c74-e4e7543700ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123200764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device .4123200764 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.1362346259 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 1323554747 ps |
| CPU time | 52.02 seconds |
| Started | Jul 12 07:31:48 PM PDT 24 |
| Finished | Jul 12 07:32:47 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-79ef4f35-4490-4339-b8a9-3b0177019a18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362346259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.1362346259 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.3037087663 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 1483301275 ps |
| CPU time | 51.43 seconds |
| Started | Jul 12 07:31:49 PM PDT 24 |
| Finished | Jul 12 07:32:47 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-4b364e75-e387-4fad-8b4c-75dcd0b788bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037087663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3037087663 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.539666989 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1782346266 ps |
| CPU time | 65.06 seconds |
| Started | Jul 12 07:31:58 PM PDT 24 |
| Finished | Jul 12 07:33:06 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-fa043945-3d0d-49ae-9d2b-33a47d52a245 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539666989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.539666989 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.555182760 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 86155510637 ps |
| CPU time | 1032.99 seconds |
| Started | Jul 12 07:31:49 PM PDT 24 |
| Finished | Jul 12 07:49:09 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-d7e81d3b-ef6e-455c-bca7-fe4e895f7a94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555182760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.555182760 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.80309905 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 47125073440 ps |
| CPU time | 852.68 seconds |
| Started | Jul 12 07:31:48 PM PDT 24 |
| Finished | Jul 12 07:46:07 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-f121f2a1-be1e-4180-a9a0-bd4dee4c8c78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80309905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.80309905 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.30249714 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 258010750 ps |
| CPU time | 22.24 seconds |
| Started | Jul 12 07:31:57 PM PDT 24 |
| Finished | Jul 12 07:32:23 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-d5b64c96-bbc6-4f02-a762-691542ed4a76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30249714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delay s.30249714 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.3632753448 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 89569827 ps |
| CPU time | 9.73 seconds |
| Started | Jul 12 07:31:47 PM PDT 24 |
| Finished | Jul 12 07:32:03 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-5790f316-04da-459f-b0d6-17e2bfcf67b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632753448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3632753448 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.1064014530 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 41609226 ps |
| CPU time | 6.32 seconds |
| Started | Jul 12 07:31:40 PM PDT 24 |
| Finished | Jul 12 07:31:53 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-1c9aee06-f868-49ff-9940-2cab1423f7b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064014530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1064014530 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.572554474 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 7606622478 ps |
| CPU time | 84.04 seconds |
| Started | Jul 12 07:31:57 PM PDT 24 |
| Finished | Jul 12 07:33:25 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-5933265a-ac35-43ce-9dfb-28637fe042e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572554474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.572554474 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.3595813490 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 5340798286 ps |
| CPU time | 89.26 seconds |
| Started | Jul 12 07:31:47 PM PDT 24 |
| Finished | Jul 12 07:33:23 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-ebeb3f40-b08a-4611-99f9-b3ad7b53de64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595813490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3595813490 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.1794962605 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 46927711 ps |
| CPU time | 6.17 seconds |
| Started | Jul 12 07:31:51 PM PDT 24 |
| Finished | Jul 12 07:32:03 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-24f9dee4-ba83-4d4d-980e-735478594520 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794962605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.1794962605 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.606163720 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 454986090 ps |
| CPU time | 33.33 seconds |
| Started | Jul 12 07:31:50 PM PDT 24 |
| Finished | Jul 12 07:32:29 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-409de106-98a8-4674-87f3-048d60327cb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606163720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.606163720 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.1080585140 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 1049736009 ps |
| CPU time | 70.36 seconds |
| Started | Jul 12 07:32:00 PM PDT 24 |
| Finished | Jul 12 07:33:13 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-e70e5562-c22c-48be-a3b8-acd82f731561 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080585140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1080585140 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.3693983465 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 1657312622 ps |
| CPU time | 169.98 seconds |
| Started | Jul 12 07:31:51 PM PDT 24 |
| Finished | Jul 12 07:34:48 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-17e7cb25-c78f-42ad-8f98-f6af80218e61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693983465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_rand_reset.3693983465 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.1966264683 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 1911114789 ps |
| CPU time | 180.39 seconds |
| Started | Jul 12 07:31:48 PM PDT 24 |
| Finished | Jul 12 07:34:56 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-a6f690e0-72fe-491f-83cd-d1bf42100dfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966264683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.1966264683 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.1262995622 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 187173899 ps |
| CPU time | 22.01 seconds |
| Started | Jul 12 07:31:57 PM PDT 24 |
| Finished | Jul 12 07:32:23 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-81b4294e-4218-4c64-9714-83eb810cbc12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262995622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1262995622 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.1817230007 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 3775791804 ps |
| CPU time | 336.99 seconds |
| Started | Jul 12 07:24:11 PM PDT 24 |
| Finished | Jul 12 07:29:49 PM PDT 24 |
| Peak memory | 598456 kb |
| Host | smart-985add9e-2ad5-4fce-93e2-a325a47be1e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817230007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.1817230007 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.3627435626 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 27202599287 ps |
| CPU time | 4103.26 seconds |
| Started | Jul 12 07:23:54 PM PDT 24 |
| Finished | Jul 12 08:32:19 PM PDT 24 |
| Peak memory | 593568 kb |
| Host | smart-a16993ed-74f1-4068-a76c-986af4f2160d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627435626 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.3627435626 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.2804060319 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 4002367577 ps |
| CPU time | 165.3 seconds |
| Started | Jul 12 07:24:05 PM PDT 24 |
| Finished | Jul 12 07:26:51 PM PDT 24 |
| Peak memory | 603752 kb |
| Host | smart-f0858a37-ba47-41a4-ac93-f3914eb3f27e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804060319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.2804060319 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.1384549798 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 532871810 ps |
| CPU time | 46.87 seconds |
| Started | Jul 12 07:24:05 PM PDT 24 |
| Finished | Jul 12 07:24:53 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-eec5d916-43d0-44a2-85bb-4a4a0169dfd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384549798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 1384549798 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.3997001430 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 95071453871 ps |
| CPU time | 1609.09 seconds |
| Started | Jul 12 07:24:08 PM PDT 24 |
| Finished | Jul 12 07:50:59 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-22467da8-f69a-4407-8853-d226220cc489 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997001430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d evice_slow_rsp.3997001430 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.3718381117 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 253522958 ps |
| CPU time | 28.43 seconds |
| Started | Jul 12 07:24:09 PM PDT 24 |
| Finished | Jul 12 07:24:39 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-828da30b-0904-427a-8734-016ae59ad3c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718381117 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .3718381117 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.246250789 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 140165767 ps |
| CPU time | 8.38 seconds |
| Started | Jul 12 07:24:03 PM PDT 24 |
| Finished | Jul 12 07:24:13 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-a9ce36e1-fa26-4ba9-8e35-f12e5886d214 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246250789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.246250789 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.838631261 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1967616053 ps |
| CPU time | 78.81 seconds |
| Started | Jul 12 07:24:02 PM PDT 24 |
| Finished | Jul 12 07:25:23 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-52790194-5b93-46b5-8308-4bfef523752a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838631261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.838631261 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.3916262775 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 21974312802 ps |
| CPU time | 228.41 seconds |
| Started | Jul 12 07:24:02 PM PDT 24 |
| Finished | Jul 12 07:27:52 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-372cc720-90b2-48b4-9318-a740aab4f2b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916262775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3916262775 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.1555966705 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 57632234375 ps |
| CPU time | 1064.74 seconds |
| Started | Jul 12 07:24:03 PM PDT 24 |
| Finished | Jul 12 07:41:50 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-5e55ec1d-3c20-489a-9e6f-b93ed285dabe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555966705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1555966705 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.776662473 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 376224085 ps |
| CPU time | 28.89 seconds |
| Started | Jul 12 07:24:01 PM PDT 24 |
| Finished | Jul 12 07:24:31 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-53826b04-c19f-4646-a31d-94f8cb18a24f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776662473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delay s.776662473 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.1950556131 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 1090289213 ps |
| CPU time | 33.33 seconds |
| Started | Jul 12 07:24:04 PM PDT 24 |
| Finished | Jul 12 07:24:38 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-25aafdf2-ec95-499a-8549-a7e142033913 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950556131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1950556131 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.248357655 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 46568260 ps |
| CPU time | 6.64 seconds |
| Started | Jul 12 07:24:04 PM PDT 24 |
| Finished | Jul 12 07:24:11 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-12ea158e-3dcf-4002-9e79-737d245ff521 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248357655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.248357655 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.462453401 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 6455683606 ps |
| CPU time | 69.73 seconds |
| Started | Jul 12 07:24:08 PM PDT 24 |
| Finished | Jul 12 07:25:20 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-aac5a210-0af8-42e3-ab10-8fc69dee4bc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462453401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.462453401 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.1381421314 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 6485911060 ps |
| CPU time | 104.85 seconds |
| Started | Jul 12 07:24:07 PM PDT 24 |
| Finished | Jul 12 07:25:53 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-23ec3ad8-559a-4f89-8221-aaa8482a02c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381421314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1381421314 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.8142026 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 47037325 ps |
| CPU time | 5.79 seconds |
| Started | Jul 12 07:24:05 PM PDT 24 |
| Finished | Jul 12 07:24:12 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-9b2f4d0d-5356-44c2-b423-18a50165d78b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8142026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.8142026 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.3891129741 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 7247953355 ps |
| CPU time | 255.41 seconds |
| Started | Jul 12 07:24:01 PM PDT 24 |
| Finished | Jul 12 07:28:18 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-91973060-9e35-4829-bd90-b64954826d51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891129741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3891129741 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.466147237 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 1853568525 ps |
| CPU time | 146.15 seconds |
| Started | Jul 12 07:24:03 PM PDT 24 |
| Finished | Jul 12 07:26:30 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-12451090-af89-45b6-b199-ba531afaf88f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466147237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.466147237 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.1857171544 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 171735243 ps |
| CPU time | 35.91 seconds |
| Started | Jul 12 07:24:08 PM PDT 24 |
| Finished | Jul 12 07:24:45 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-55ebb6a4-566f-4e28-af8c-9fc58fe1c1eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857171544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.1857171544 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.2510030532 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 55372757 ps |
| CPU time | 5.68 seconds |
| Started | Jul 12 07:24:05 PM PDT 24 |
| Finished | Jul 12 07:24:11 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-98d0687e-025d-47dd-9a1d-b77c61eaf866 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510030532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2510030532 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.3632108455 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 395922364 ps |
| CPU time | 16.73 seconds |
| Started | Jul 12 07:31:49 PM PDT 24 |
| Finished | Jul 12 07:32:12 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-e6cf2b60-6e1b-4f3c-9dd7-34b473cff46b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632108455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .3632108455 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.1442777928 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 46019781164 ps |
| CPU time | 820.34 seconds |
| Started | Jul 12 07:31:59 PM PDT 24 |
| Finished | Jul 12 07:45:42 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-9bc02409-18f2-4642-b0e7-e1c8c5551918 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442777928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.1442777928 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.2032087807 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 1130085349 ps |
| CPU time | 41.43 seconds |
| Started | Jul 12 07:32:06 PM PDT 24 |
| Finished | Jul 12 07:32:50 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-6723922e-5439-41d9-81f2-a52443fba059 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032087807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add r.2032087807 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.2763101108 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 547796488 ps |
| CPU time | 20.54 seconds |
| Started | Jul 12 07:31:58 PM PDT 24 |
| Finished | Jul 12 07:32:21 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-67d4bb89-90d0-4209-9de6-28d8b4a37540 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763101108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.2763101108 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.522490523 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 264261057 ps |
| CPU time | 23.51 seconds |
| Started | Jul 12 07:32:00 PM PDT 24 |
| Finished | Jul 12 07:32:27 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-275c28d0-dbc5-41c3-b54d-228a947d3d3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522490523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.522490523 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.1428668905 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 10806349548 ps |
| CPU time | 113.51 seconds |
| Started | Jul 12 07:32:02 PM PDT 24 |
| Finished | Jul 12 07:33:58 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-3d2a0939-ffb2-4aa8-9c87-f0ad5a839532 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428668905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.1428668905 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.1009312885 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 36743810085 ps |
| CPU time | 619.91 seconds |
| Started | Jul 12 07:31:57 PM PDT 24 |
| Finished | Jul 12 07:42:20 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-a3d1eab6-ea40-44ee-9412-a0fb8977a3b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009312885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.1009312885 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.4279153053 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 397046258 ps |
| CPU time | 39.51 seconds |
| Started | Jul 12 07:31:48 PM PDT 24 |
| Finished | Jul 12 07:32:34 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-0b46a21d-61df-4ae9-91a7-564b59f9c90c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279153053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.4279153053 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.4091048941 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 430632698 ps |
| CPU time | 34.75 seconds |
| Started | Jul 12 07:32:02 PM PDT 24 |
| Finished | Jul 12 07:32:40 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-e464a865-bc26-426e-9a76-72dd16fae50d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091048941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.4091048941 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.3153743063 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 175556603 ps |
| CPU time | 8.69 seconds |
| Started | Jul 12 07:31:49 PM PDT 24 |
| Finished | Jul 12 07:32:04 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-747261cc-1ce5-4e24-80c5-c97fed08f4cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153743063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.3153743063 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.2835271659 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 8476394814 ps |
| CPU time | 98.41 seconds |
| Started | Jul 12 07:31:48 PM PDT 24 |
| Finished | Jul 12 07:33:33 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-af40c9bc-03b4-4c89-8b1c-6bde0316a78b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835271659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.2835271659 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.3893873219 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 5644652958 ps |
| CPU time | 110.1 seconds |
| Started | Jul 12 07:31:47 PM PDT 24 |
| Finished | Jul 12 07:33:44 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-4dab3679-5dc9-405b-b4ea-7e368076562a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893873219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.3893873219 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.454385643 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 45050132 ps |
| CPU time | 6.45 seconds |
| Started | Jul 12 07:31:57 PM PDT 24 |
| Finished | Jul 12 07:32:07 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-182c096e-5c16-4e71-ba7f-2acd4ed29a7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454385643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delays .454385643 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.1066106415 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 3160227257 ps |
| CPU time | 246.46 seconds |
| Started | Jul 12 07:32:05 PM PDT 24 |
| Finished | Jul 12 07:36:15 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-19614813-90de-4e48-82c6-33740e5dc220 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066106415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.1066106415 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.976395759 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 2308053648 ps |
| CPU time | 157.53 seconds |
| Started | Jul 12 07:32:02 PM PDT 24 |
| Finished | Jul 12 07:34:42 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-444051e1-e335-4680-9712-b7c21eb333e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976395759 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.976395759 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.418875948 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 1400913347 ps |
| CPU time | 235.22 seconds |
| Started | Jul 12 07:32:06 PM PDT 24 |
| Finished | Jul 12 07:36:05 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-f42d0484-aeac-4c14-8bf9-be9fc5338643 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418875948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_ with_rand_reset.418875948 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.746763953 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 3921358825 ps |
| CPU time | 189.91 seconds |
| Started | Jul 12 07:32:00 PM PDT 24 |
| Finished | Jul 12 07:35:13 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-8dbaef11-69f3-4bc1-a8ef-48b36c584917 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746763953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_reset_error.746763953 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.2170870109 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 137480459 ps |
| CPU time | 16.55 seconds |
| Started | Jul 12 07:32:03 PM PDT 24 |
| Finished | Jul 12 07:32:22 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-0786db4c-cbaf-48f3-a702-54f1423cb0c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170870109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.2170870109 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.3207158955 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 1456768724 ps |
| CPU time | 54.52 seconds |
| Started | Jul 12 07:32:06 PM PDT 24 |
| Finished | Jul 12 07:33:04 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-4bd9c521-2d8e-4834-aeff-7ae12586d938 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207158955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .3207158955 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.981424351 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 115681621259 ps |
| CPU time | 2307.22 seconds |
| Started | Jul 12 07:32:02 PM PDT 24 |
| Finished | Jul 12 08:10:32 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-bca67240-385c-447e-bda6-a950f8667465 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981424351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_d evice_slow_rsp.981424351 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.1931222121 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 945917430 ps |
| CPU time | 36.42 seconds |
| Started | Jul 12 07:32:02 PM PDT 24 |
| Finished | Jul 12 07:32:41 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-64e7553a-ff42-4cbd-a44a-1713460d664d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931222121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.1931222121 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.503879096 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 456357372 ps |
| CPU time | 32.53 seconds |
| Started | Jul 12 07:32:06 PM PDT 24 |
| Finished | Jul 12 07:32:42 PM PDT 24 |
| Peak memory | 575180 kb |
| Host | smart-caa3ad03-148b-4756-ae96-45605206fa33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503879096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.503879096 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.3746379769 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 1216417822 ps |
| CPU time | 47.52 seconds |
| Started | Jul 12 07:32:00 PM PDT 24 |
| Finished | Jul 12 07:32:51 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-d7de4570-6b51-49bc-8546-442b68641125 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746379769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.3746379769 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.2481404678 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 5305555646 ps |
| CPU time | 56.2 seconds |
| Started | Jul 12 07:32:06 PM PDT 24 |
| Finished | Jul 12 07:33:05 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-48a32d2c-3662-4159-a7ee-7d6d145000c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481404678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.2481404678 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.2422419146 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 5067777519 ps |
| CPU time | 83.52 seconds |
| Started | Jul 12 07:32:06 PM PDT 24 |
| Finished | Jul 12 07:33:33 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-fb1a2678-f386-4ec0-bbcc-ef558f5c2a0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422419146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.2422419146 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.2364887509 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 141700833 ps |
| CPU time | 15.14 seconds |
| Started | Jul 12 07:32:03 PM PDT 24 |
| Finished | Jul 12 07:32:21 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-2cc6e689-1070-462a-808d-49947c479583 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364887509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del ays.2364887509 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.2191554770 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 465950799 ps |
| CPU time | 37.61 seconds |
| Started | Jul 12 07:32:01 PM PDT 24 |
| Finished | Jul 12 07:32:41 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-4b1b9605-3014-4702-90d6-deb27a49fefc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191554770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.2191554770 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.3670741490 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 203951326 ps |
| CPU time | 8.9 seconds |
| Started | Jul 12 07:32:03 PM PDT 24 |
| Finished | Jul 12 07:32:15 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-3eae6c41-b734-4f98-adc8-353d84fcc630 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670741490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.3670741490 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.911709009 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 9879670511 ps |
| CPU time | 107.98 seconds |
| Started | Jul 12 07:32:01 PM PDT 24 |
| Finished | Jul 12 07:33:52 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-0d0be03f-b3b2-4e3b-b290-feb1a4a6a86d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911709009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.911709009 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.924197785 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 4065881441 ps |
| CPU time | 68.86 seconds |
| Started | Jul 12 07:32:06 PM PDT 24 |
| Finished | Jul 12 07:33:18 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-98e2761f-87b0-4441-9c35-224433059b58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924197785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.924197785 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.2189507769 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 56126200 ps |
| CPU time | 6.58 seconds |
| Started | Jul 12 07:32:00 PM PDT 24 |
| Finished | Jul 12 07:32:10 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-41fd71f7-b05b-4f8b-8013-68a848258318 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189507769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay s.2189507769 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.2386473562 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 1351672783 ps |
| CPU time | 97.67 seconds |
| Started | Jul 12 07:32:17 PM PDT 24 |
| Finished | Jul 12 07:33:58 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-1fbd12be-6d97-454d-8207-6996a3ee0783 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386473562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.2386473562 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.3333812279 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 1001643827 ps |
| CPU time | 73.45 seconds |
| Started | Jul 12 07:32:16 PM PDT 24 |
| Finished | Jul 12 07:33:32 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-da08cf18-faec-4878-8197-3daccb37dd23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333812279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.3333812279 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.932859200 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 7101556525 ps |
| CPU time | 841.21 seconds |
| Started | Jul 12 07:32:15 PM PDT 24 |
| Finished | Jul 12 07:46:17 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-f1eebd2d-5e4e-45a1-9d09-1c1f0ed67377 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932859200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_ with_rand_reset.932859200 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.2752063185 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 2932669279 ps |
| CPU time | 253.33 seconds |
| Started | Jul 12 07:32:16 PM PDT 24 |
| Finished | Jul 12 07:36:31 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-79cc76d1-1b69-41a2-9709-e501f17f362b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752063185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al l_with_reset_error.2752063185 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.2795183332 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 206166365 ps |
| CPU time | 11.84 seconds |
| Started | Jul 12 07:32:03 PM PDT 24 |
| Finished | Jul 12 07:32:18 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-ccdd6c85-288c-4ec4-a378-bc229658e90f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795183332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.2795183332 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.1365771258 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 1009141658 ps |
| CPU time | 81.8 seconds |
| Started | Jul 12 07:32:18 PM PDT 24 |
| Finished | Jul 12 07:33:44 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-35b8a43c-7fe0-4235-a823-bdaa7f8bcc18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365771258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device .1365771258 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.3703300990 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 34457667044 ps |
| CPU time | 613.36 seconds |
| Started | Jul 12 07:32:19 PM PDT 24 |
| Finished | Jul 12 07:42:39 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-380bb029-df89-4608-b301-6274310882b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703300990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.3703300990 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.3461781156 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 1119157461 ps |
| CPU time | 43.09 seconds |
| Started | Jul 12 07:32:19 PM PDT 24 |
| Finished | Jul 12 07:33:08 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-2b9793da-b2e8-4ace-bc9c-ba86029d0777 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461781156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.3461781156 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.3778518937 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 429977575 ps |
| CPU time | 15.6 seconds |
| Started | Jul 12 07:32:21 PM PDT 24 |
| Finished | Jul 12 07:32:43 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-7c8497e5-c06b-4c19-957f-ba0c19cd6b28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778518937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.3778518937 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.1572320617 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 461525500 ps |
| CPU time | 36.96 seconds |
| Started | Jul 12 07:32:21 PM PDT 24 |
| Finished | Jul 12 07:33:04 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-9d35be67-6c13-495e-ae0b-441202fd7f1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572320617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.1572320617 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.1801716567 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 86048276794 ps |
| CPU time | 982.41 seconds |
| Started | Jul 12 07:32:16 PM PDT 24 |
| Finished | Jul 12 07:48:40 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-669abb6a-c143-4707-9ff0-9fc437d58976 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801716567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.1801716567 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.629768009 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 40112838446 ps |
| CPU time | 725.01 seconds |
| Started | Jul 12 07:32:22 PM PDT 24 |
| Finished | Jul 12 07:44:34 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-68022044-9ce9-45a0-96d2-4861e702265b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629768009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.629768009 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.2270406846 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 538885284 ps |
| CPU time | 44.41 seconds |
| Started | Jul 12 07:32:24 PM PDT 24 |
| Finished | Jul 12 07:33:14 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-3403f237-d9e0-4a3d-a147-4a6ed414750d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270406846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del ays.2270406846 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.4266506031 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 2505720706 ps |
| CPU time | 72.37 seconds |
| Started | Jul 12 07:32:18 PM PDT 24 |
| Finished | Jul 12 07:33:36 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-f4ca4d86-6ff7-4830-bd15-a120aaf702fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266506031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.4266506031 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.2781553376 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 196069921 ps |
| CPU time | 8.6 seconds |
| Started | Jul 12 07:32:16 PM PDT 24 |
| Finished | Jul 12 07:32:27 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-9ddb3dfc-245a-45b9-8571-567279e167da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781553376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.2781553376 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.236524531 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 8859636831 ps |
| CPU time | 93.04 seconds |
| Started | Jul 12 07:32:21 PM PDT 24 |
| Finished | Jul 12 07:34:00 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-2a94dd6f-33d5-4e59-bcb4-11c664285a2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236524531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.236524531 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.3414733572 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 3131939522 ps |
| CPU time | 56.47 seconds |
| Started | Jul 12 07:32:19 PM PDT 24 |
| Finished | Jul 12 07:33:22 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-73768904-1e22-4a5f-a507-280b3692e370 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414733572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.3414733572 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.3882763027 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 43393092 ps |
| CPU time | 5.96 seconds |
| Started | Jul 12 07:32:22 PM PDT 24 |
| Finished | Jul 12 07:32:34 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-f79b5f0a-152b-41c8-ae01-743587a03540 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882763027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay s.3882763027 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.2819042988 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 15485254011 ps |
| CPU time | 592.65 seconds |
| Started | Jul 12 07:32:18 PM PDT 24 |
| Finished | Jul 12 07:42:16 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-d76d7022-ff44-451a-99b1-8456634f859b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819042988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.2819042988 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.1768436555 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 3168632220 ps |
| CPU time | 238.34 seconds |
| Started | Jul 12 07:32:22 PM PDT 24 |
| Finished | Jul 12 07:36:27 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-8573ed41-1335-432d-9e56-08cd96fce813 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768436555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.1768436555 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.795036626 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 683478420 ps |
| CPU time | 268.38 seconds |
| Started | Jul 12 07:32:15 PM PDT 24 |
| Finished | Jul 12 07:36:45 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-4b299661-ea63-479c-9b94-9cc15ff5b869 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795036626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_ with_rand_reset.795036626 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.1955680155 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 9350190016 ps |
| CPU time | 446.39 seconds |
| Started | Jul 12 07:32:16 PM PDT 24 |
| Finished | Jul 12 07:39:44 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-374fef1b-1fd9-4a76-afb1-5af8198bfd0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955680155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.1955680155 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.903700027 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 88022218 ps |
| CPU time | 11.84 seconds |
| Started | Jul 12 07:32:18 PM PDT 24 |
| Finished | Jul 12 07:32:35 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-b2073a73-231c-48cd-9bbf-bffd19b33bc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903700027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.903700027 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.330611147 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 223869451 ps |
| CPU time | 19.07 seconds |
| Started | Jul 12 07:32:17 PM PDT 24 |
| Finished | Jul 12 07:32:40 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-1d897afa-fe39-4c9f-9b6f-e0c50d288b29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330611147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device. 330611147 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.1541290572 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 123510254718 ps |
| CPU time | 2202.9 seconds |
| Started | Jul 12 07:32:22 PM PDT 24 |
| Finished | Jul 12 08:09:11 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-aa31bb37-6a58-49c3-b807-569b64265d4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541290572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.1541290572 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.2995033351 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 85512594 ps |
| CPU time | 11.1 seconds |
| Started | Jul 12 07:32:18 PM PDT 24 |
| Finished | Jul 12 07:32:35 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-337930d0-6d2e-450b-a050-466fb8928bff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995033351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.2995033351 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.3886306339 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 451984844 ps |
| CPU time | 16.28 seconds |
| Started | Jul 12 07:32:14 PM PDT 24 |
| Finished | Jul 12 07:32:31 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-8ecc423d-80da-4375-95f6-0b5fdcabb576 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886306339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.3886306339 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.2330328353 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 205602900 ps |
| CPU time | 20.99 seconds |
| Started | Jul 12 07:32:23 PM PDT 24 |
| Finished | Jul 12 07:32:49 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-e68fe0c3-2b93-4478-9425-6140fcf96883 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330328353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.2330328353 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.2382775490 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 6689344350 ps |
| CPU time | 74.19 seconds |
| Started | Jul 12 07:32:17 PM PDT 24 |
| Finished | Jul 12 07:33:35 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-06049ca6-db55-4a4b-bd74-04885fabc590 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382775490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.2382775490 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.3354480156 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 48673678368 ps |
| CPU time | 873.12 seconds |
| Started | Jul 12 07:32:18 PM PDT 24 |
| Finished | Jul 12 07:46:56 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-6312d4f9-a3b1-4f6f-b373-85ee4e95a6c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354480156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.3354480156 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.3440127542 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 275086368 ps |
| CPU time | 23.34 seconds |
| Started | Jul 12 07:32:17 PM PDT 24 |
| Finished | Jul 12 07:32:44 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-1daa84a7-666d-40d8-9af1-4ce480312453 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440127542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del ays.3440127542 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.1367959234 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 341117473 ps |
| CPU time | 12.63 seconds |
| Started | Jul 12 07:32:16 PM PDT 24 |
| Finished | Jul 12 07:32:32 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-4c015b1f-3507-4573-bf13-0fbc7a9a3b1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367959234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.1367959234 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.1243101495 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 220318110 ps |
| CPU time | 9.23 seconds |
| Started | Jul 12 07:32:20 PM PDT 24 |
| Finished | Jul 12 07:32:35 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-f914574a-9dbc-423e-9bae-59383a196415 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243101495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.1243101495 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.51968497 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 7729895420 ps |
| CPU time | 86.77 seconds |
| Started | Jul 12 07:32:20 PM PDT 24 |
| Finished | Jul 12 07:33:52 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-51b0eee2-3ba1-44ae-a355-b04ed1220137 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51968497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.51968497 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.451004291 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 3149705385 ps |
| CPU time | 56.06 seconds |
| Started | Jul 12 07:32:18 PM PDT 24 |
| Finished | Jul 12 07:33:20 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-a2d8f210-f53d-4033-bff0-f80452d22c5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451004291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.451004291 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.3053815172 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 37787727 ps |
| CPU time | 5.88 seconds |
| Started | Jul 12 07:32:17 PM PDT 24 |
| Finished | Jul 12 07:32:26 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-87434331-84a3-4c9c-975a-5c06d8322974 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053815172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delay s.3053815172 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.894735451 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 11906466558 ps |
| CPU time | 474.74 seconds |
| Started | Jul 12 07:32:35 PM PDT 24 |
| Finished | Jul 12 07:40:36 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-1793add5-3b65-4a39-9262-a7fd2078eca4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894735451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.894735451 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.2880947506 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 3019265603 ps |
| CPU time | 220.4 seconds |
| Started | Jul 12 07:32:29 PM PDT 24 |
| Finished | Jul 12 07:36:16 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-678ede53-690e-4f34-9089-467f9ce0b542 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880947506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.2880947506 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.2826436925 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 6275359386 ps |
| CPU time | 335.64 seconds |
| Started | Jul 12 07:32:31 PM PDT 24 |
| Finished | Jul 12 07:38:14 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-1fa1ad7c-8597-468a-aa3c-065760d2f668 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826436925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.2826436925 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2485222166 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 35165761 ps |
| CPU time | 18.77 seconds |
| Started | Jul 12 07:32:30 PM PDT 24 |
| Finished | Jul 12 07:32:57 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-d0a6da4e-5cc5-469e-8367-13ea9e8177a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485222166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.2485222166 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.3999806772 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 53441464 ps |
| CPU time | 8.65 seconds |
| Started | Jul 12 07:32:17 PM PDT 24 |
| Finished | Jul 12 07:32:31 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-cd7ade9b-8f5c-4125-949b-cdd4ff6dc7df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999806772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.3999806772 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.2771087202 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 602332998 ps |
| CPU time | 52.73 seconds |
| Started | Jul 12 07:32:32 PM PDT 24 |
| Finished | Jul 12 07:33:31 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-6614326c-39ec-4995-82c4-1e2bfa9ab94a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771087202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .2771087202 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.4215648737 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 563629786 ps |
| CPU time | 23.47 seconds |
| Started | Jul 12 07:32:34 PM PDT 24 |
| Finished | Jul 12 07:33:04 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-1b5ca120-1f0d-4f3f-853f-ab439671c045 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215648737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add r.4215648737 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.255421323 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 2359944779 ps |
| CPU time | 80.83 seconds |
| Started | Jul 12 07:32:31 PM PDT 24 |
| Finished | Jul 12 07:33:59 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-8351a678-4da6-458e-a7c0-def2bbe22595 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255421323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.255421323 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.4107352546 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 560555782 ps |
| CPU time | 48.24 seconds |
| Started | Jul 12 07:32:29 PM PDT 24 |
| Finished | Jul 12 07:33:25 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-f9d24ba6-69ab-4003-8a88-5bc7a1b7ef56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107352546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.4107352546 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.1838857343 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 23654904349 ps |
| CPU time | 268.17 seconds |
| Started | Jul 12 07:32:31 PM PDT 24 |
| Finished | Jul 12 07:37:06 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-b48c3cc6-f328-4887-ac3c-6d61eea574a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838857343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.1838857343 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.851357132 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 45642787001 ps |
| CPU time | 823.43 seconds |
| Started | Jul 12 07:32:29 PM PDT 24 |
| Finished | Jul 12 07:46:20 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-eb43a1a8-1054-4c18-96e3-aefd4b75d732 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851357132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.851357132 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.1644283075 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 236678430 ps |
| CPU time | 24.05 seconds |
| Started | Jul 12 07:32:29 PM PDT 24 |
| Finished | Jul 12 07:33:00 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-c75c3b79-dd16-4698-9762-57165ebe1897 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644283075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del ays.1644283075 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.3559116481 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 231700690 ps |
| CPU time | 9.69 seconds |
| Started | Jul 12 07:32:29 PM PDT 24 |
| Finished | Jul 12 07:32:46 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-b963eb70-9846-46d6-8178-e4e290325fa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559116481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.3559116481 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.1876709511 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 47533985 ps |
| CPU time | 6.78 seconds |
| Started | Jul 12 07:32:30 PM PDT 24 |
| Finished | Jul 12 07:32:44 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-964d0872-6f06-40f1-bc32-cf8c2a97ad26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876709511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.1876709511 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.1974600311 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 7363459948 ps |
| CPU time | 82.95 seconds |
| Started | Jul 12 07:32:30 PM PDT 24 |
| Finished | Jul 12 07:34:00 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-01b411c2-be64-4bd1-a885-bed6247ef787 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974600311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.1974600311 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.436925531 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 5195264297 ps |
| CPU time | 88.3 seconds |
| Started | Jul 12 07:32:30 PM PDT 24 |
| Finished | Jul 12 07:34:06 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-80660ba3-62f4-4e5c-b252-6779b8164f8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436925531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.436925531 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1927284435 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 35309494 ps |
| CPU time | 5.82 seconds |
| Started | Jul 12 07:32:30 PM PDT 24 |
| Finished | Jul 12 07:32:44 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-a590b61c-b99d-48e3-b9ff-7f298ff270ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927284435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.1927284435 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.3153064226 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 387126013 ps |
| CPU time | 32.47 seconds |
| Started | Jul 12 07:32:33 PM PDT 24 |
| Finished | Jul 12 07:33:12 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-3b198389-434b-430d-8f89-096be6d489ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153064226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.3153064226 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.3803788412 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 1093682704 ps |
| CPU time | 91.73 seconds |
| Started | Jul 12 07:32:29 PM PDT 24 |
| Finished | Jul 12 07:34:08 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-18bd088d-f4ff-4b36-ab60-a05b358fd06e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803788412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.3803788412 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.2037957633 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 16388584219 ps |
| CPU time | 819.05 seconds |
| Started | Jul 12 07:32:30 PM PDT 24 |
| Finished | Jul 12 07:46:17 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-f47d8997-d636-46f7-b5b2-4a64bd295f98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037957633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_rand_reset.2037957633 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.4170793564 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 3419870005 ps |
| CPU time | 270.67 seconds |
| Started | Jul 12 07:32:31 PM PDT 24 |
| Finished | Jul 12 07:37:09 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-b4a49f93-d89b-40cf-9ab0-ca7f85b423a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170793564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.4170793564 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.851737572 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 1302984188 ps |
| CPU time | 54.17 seconds |
| Started | Jul 12 07:32:29 PM PDT 24 |
| Finished | Jul 12 07:33:31 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-4ec429d8-90eb-4a4f-bc26-9b746010bc0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851737572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.851737572 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.2546238791 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 3965092599 ps |
| CPU time | 153.97 seconds |
| Started | Jul 12 07:32:33 PM PDT 24 |
| Finished | Jul 12 07:35:14 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-05f77249-9e3e-41ea-b9e3-bfe5c52cd49b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546238791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .2546238791 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.1536920356 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 11697435642 ps |
| CPU time | 205.84 seconds |
| Started | Jul 12 07:32:39 PM PDT 24 |
| Finished | Jul 12 07:36:10 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-4eed3a5d-1b12-4415-923f-3dcca89cff77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536920356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.1536920356 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.3992658604 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 58565879 ps |
| CPU time | 5.34 seconds |
| Started | Jul 12 07:32:33 PM PDT 24 |
| Finished | Jul 12 07:32:46 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-b80d39dc-034d-4d59-a77e-74ea31baeb4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992658604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_add r.3992658604 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.440941885 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 2306956051 ps |
| CPU time | 86.78 seconds |
| Started | Jul 12 07:32:32 PM PDT 24 |
| Finished | Jul 12 07:34:05 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-b66bfba1-9f7a-43b8-a8a4-e19d17c05d8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440941885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.440941885 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.2741977967 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 1970127595 ps |
| CPU time | 70.14 seconds |
| Started | Jul 12 07:32:34 PM PDT 24 |
| Finished | Jul 12 07:33:51 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-0d110abe-b34a-4c3d-88fb-f98a94736a80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741977967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.2741977967 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.1683659654 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 66071472672 ps |
| CPU time | 758.55 seconds |
| Started | Jul 12 07:32:40 PM PDT 24 |
| Finished | Jul 12 07:45:24 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-1afee3fc-15aa-4594-8df8-3732de4c2262 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683659654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.1683659654 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.1488292659 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 28949025813 ps |
| CPU time | 464.16 seconds |
| Started | Jul 12 07:32:40 PM PDT 24 |
| Finished | Jul 12 07:40:30 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-fbdec922-dcb6-48e7-ad70-59b4b58c66a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488292659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.1488292659 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.17613243 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 266948477 ps |
| CPU time | 24.34 seconds |
| Started | Jul 12 07:32:31 PM PDT 24 |
| Finished | Jul 12 07:33:03 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-e9dbd43f-f1e9-4af3-9a07-e68797e5856c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17613243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_delay s.17613243 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.4073912773 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 545184238 ps |
| CPU time | 37.64 seconds |
| Started | Jul 12 07:32:40 PM PDT 24 |
| Finished | Jul 12 07:33:23 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-782d1271-f2ed-46e6-8c71-215c3b6a4308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073912773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.4073912773 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.2694236422 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 223313633 ps |
| CPU time | 9.95 seconds |
| Started | Jul 12 07:32:36 PM PDT 24 |
| Finished | Jul 12 07:32:52 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-ccb73705-ac7d-4692-96df-eee84eb44ee4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694236422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.2694236422 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.2764219627 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 8769753593 ps |
| CPU time | 107.51 seconds |
| Started | Jul 12 07:32:35 PM PDT 24 |
| Finished | Jul 12 07:34:29 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-56598100-824a-4c40-ac56-30e7b75ff95d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764219627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.2764219627 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.1632899510 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 6228295202 ps |
| CPU time | 109.99 seconds |
| Started | Jul 12 07:38:48 PM PDT 24 |
| Finished | Jul 12 07:40:39 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-d16384b3-0241-4f76-8033-2db527ae4bce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632899510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.1632899510 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.3545535988 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 51169921 ps |
| CPU time | 6.48 seconds |
| Started | Jul 12 07:32:30 PM PDT 24 |
| Finished | Jul 12 07:32:44 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-2f128b34-fc53-40c7-8d6b-742140c5a7af |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545535988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay s.3545535988 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.3285586133 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 8018150805 ps |
| CPU time | 287.35 seconds |
| Started | Jul 12 07:32:32 PM PDT 24 |
| Finished | Jul 12 07:37:26 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-c7b6c2b7-df9c-4f22-82fc-afe47b0e99c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285586133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.3285586133 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.2395097774 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 5935452 ps |
| CPU time | 3.81 seconds |
| Started | Jul 12 07:32:32 PM PDT 24 |
| Finished | Jul 12 07:32:42 PM PDT 24 |
| Peak memory | 565748 kb |
| Host | smart-2a07bf8d-b927-4cbb-bad1-dbc2dc6460c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395097774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.2395097774 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.2305171095 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 1995112856 ps |
| CPU time | 305.01 seconds |
| Started | Jul 12 07:35:18 PM PDT 24 |
| Finished | Jul 12 07:40:28 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-429f9035-f71c-4327-8e44-56177725d899 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305171095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.2305171095 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.2907927303 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 168598113 ps |
| CPU time | 61.28 seconds |
| Started | Jul 12 07:32:44 PM PDT 24 |
| Finished | Jul 12 07:33:49 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-896cde64-038c-4f54-a174-1fe3117292c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907927303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al l_with_reset_error.2907927303 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.1365677166 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 158195632 ps |
| CPU time | 17.87 seconds |
| Started | Jul 12 07:32:33 PM PDT 24 |
| Finished | Jul 12 07:32:58 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-805b2c4a-0d8c-40c1-b358-a5e13f874a79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365677166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.1365677166 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.4227678637 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 1410911650 ps |
| CPU time | 58.76 seconds |
| Started | Jul 12 07:32:44 PM PDT 24 |
| Finished | Jul 12 07:33:46 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-0c7fc006-49b3-4c6d-a16e-0a23dc9a594c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227678637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .4227678637 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.1109461000 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 13457474869 ps |
| CPU time | 219.26 seconds |
| Started | Jul 12 07:32:45 PM PDT 24 |
| Finished | Jul 12 07:36:27 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-062b0f5f-60e2-4506-bdb9-4e48b4ed9a6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109461000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.1109461000 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.2161046808 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 622203328 ps |
| CPU time | 28.13 seconds |
| Started | Jul 12 07:32:44 PM PDT 24 |
| Finished | Jul 12 07:33:16 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-4f7c1c7e-1fde-49bd-87a1-4c397f837eb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161046808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.2161046808 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.1865264351 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 2189666150 ps |
| CPU time | 79.77 seconds |
| Started | Jul 12 07:32:41 PM PDT 24 |
| Finished | Jul 12 07:34:06 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-3da4c163-7564-408a-bbac-e754a221e4dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865264351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.1865264351 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.1091888408 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 1577255251 ps |
| CPU time | 56.19 seconds |
| Started | Jul 12 07:32:41 PM PDT 24 |
| Finished | Jul 12 07:33:42 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-8b818147-9cf9-4b9b-a54a-129678301f3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091888408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.1091888408 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.1579152584 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 107420978328 ps |
| CPU time | 1217.26 seconds |
| Started | Jul 12 07:32:40 PM PDT 24 |
| Finished | Jul 12 07:53:03 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-993acc34-d662-4a2f-897e-f1a936258070 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579152584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.1579152584 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.2483689054 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 31204517555 ps |
| CPU time | 537.46 seconds |
| Started | Jul 12 07:32:46 PM PDT 24 |
| Finished | Jul 12 07:41:46 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-3ff9dee1-4442-430f-a23a-ac0a57d8a5e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483689054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.2483689054 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.1240959250 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 349453513 ps |
| CPU time | 27.82 seconds |
| Started | Jul 12 07:32:44 PM PDT 24 |
| Finished | Jul 12 07:33:16 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-ff0d068f-0297-4f37-a1fa-88e4a6f54b43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240959250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.1240959250 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.3203518651 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 38908940 ps |
| CPU time | 6.01 seconds |
| Started | Jul 12 07:32:44 PM PDT 24 |
| Finished | Jul 12 07:32:54 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-2d8c1f31-7cae-4314-8fec-ca289ce947b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203518651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.3203518651 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.3950721395 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 48614627 ps |
| CPU time | 6.57 seconds |
| Started | Jul 12 07:32:42 PM PDT 24 |
| Finished | Jul 12 07:32:53 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-5a29518c-0753-47ee-bbb6-aafabb1d5324 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950721395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.3950721395 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.3847905703 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 9800602019 ps |
| CPU time | 111.56 seconds |
| Started | Jul 12 07:32:47 PM PDT 24 |
| Finished | Jul 12 07:34:41 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-0ff1c8a5-950d-4c29-873b-16f89510289a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847905703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.3847905703 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.2379210185 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 6621520982 ps |
| CPU time | 114.08 seconds |
| Started | Jul 12 07:32:45 PM PDT 24 |
| Finished | Jul 12 07:34:43 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-25b10c13-c867-44d0-a7ce-a38150a73466 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379210185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.2379210185 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.2616771925 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 37951775 ps |
| CPU time | 5.84 seconds |
| Started | Jul 12 07:32:44 PM PDT 24 |
| Finished | Jul 12 07:32:53 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-15d8a78a-b310-46de-a61f-995acb395e78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616771925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.2616771925 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.4161601459 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 8819834614 ps |
| CPU time | 293.83 seconds |
| Started | Jul 12 07:32:42 PM PDT 24 |
| Finished | Jul 12 07:37:41 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-c9459840-bc68-4ecc-9840-c84b18ca1888 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161601459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.4161601459 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.4044687354 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 2863088301 ps |
| CPU time | 91.92 seconds |
| Started | Jul 12 07:32:45 PM PDT 24 |
| Finished | Jul 12 07:34:20 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-113cf312-4e57-4814-9d54-997769efeea3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044687354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.4044687354 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.2680102125 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 105140231 ps |
| CPU time | 88.51 seconds |
| Started | Jul 12 07:32:45 PM PDT 24 |
| Finished | Jul 12 07:34:17 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-fad483a3-1cf0-4472-9577-8b37fbe19c35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680102125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al l_with_reset_error.2680102125 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.2985298471 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 118194336 ps |
| CPU time | 15.4 seconds |
| Started | Jul 12 07:32:45 PM PDT 24 |
| Finished | Jul 12 07:33:04 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-7888b8f6-3bda-471e-b8f1-d7d8e98a1465 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985298471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.2985298471 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.353101166 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 202046042 ps |
| CPU time | 19.46 seconds |
| Started | Jul 12 07:32:52 PM PDT 24 |
| Finished | Jul 12 07:33:14 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-229761db-07ff-44cc-ab24-d72472e5281c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353101166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device. 353101166 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.3021770815 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 134435273904 ps |
| CPU time | 2620.38 seconds |
| Started | Jul 12 07:33:01 PM PDT 24 |
| Finished | Jul 12 08:16:46 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-d66fd5e7-6b54-427e-b4b2-8dcb00c82c43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021770815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_ device_slow_rsp.3021770815 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.2412478527 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 211648904 ps |
| CPU time | 23.33 seconds |
| Started | Jul 12 07:32:53 PM PDT 24 |
| Finished | Jul 12 07:33:19 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-30ce11ac-54f1-4b59-b7b3-dab302ec6500 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412478527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.2412478527 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.2950870026 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 152018936 ps |
| CPU time | 8.68 seconds |
| Started | Jul 12 07:33:01 PM PDT 24 |
| Finished | Jul 12 07:33:14 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-31f7f4a0-8392-4fa8-a8f2-529140a7f6af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950870026 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.2950870026 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.4017581104 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 2386400507 ps |
| CPU time | 85.91 seconds |
| Started | Jul 12 07:33:01 PM PDT 24 |
| Finished | Jul 12 07:34:31 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-a6ee0340-7da5-4dc0-9164-ea996be1438d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017581104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.4017581104 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.1918173341 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 61328313019 ps |
| CPU time | 711.93 seconds |
| Started | Jul 12 07:32:54 PM PDT 24 |
| Finished | Jul 12 07:44:50 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-ba86cf6f-4571-4661-86c7-94756324f412 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918173341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.1918173341 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.2231735210 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 16637723874 ps |
| CPU time | 284.34 seconds |
| Started | Jul 12 07:33:00 PM PDT 24 |
| Finished | Jul 12 07:37:49 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-519c3ba2-8f93-462b-8643-fadc2a172ff8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231735210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.2231735210 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.1731152918 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 540068158 ps |
| CPU time | 46.49 seconds |
| Started | Jul 12 07:32:54 PM PDT 24 |
| Finished | Jul 12 07:33:44 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-f37b16da-4264-4fc7-a7cb-b41c61e923ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731152918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del ays.1731152918 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.3098937235 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 553497808 ps |
| CPU time | 20.64 seconds |
| Started | Jul 12 07:32:52 PM PDT 24 |
| Finished | Jul 12 07:33:15 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-3d6191b1-c11c-43af-941b-a933b3dba331 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098937235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.3098937235 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.169878736 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 178787350 ps |
| CPU time | 8.58 seconds |
| Started | Jul 12 07:32:54 PM PDT 24 |
| Finished | Jul 12 07:33:06 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-58c83a6f-2af0-451e-bd35-5818ac4a7c1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169878736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.169878736 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.1359129051 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 7676680663 ps |
| CPU time | 80.68 seconds |
| Started | Jul 12 07:32:54 PM PDT 24 |
| Finished | Jul 12 07:34:18 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-343d3a2e-3c10-47c8-9cca-765362be90c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359129051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.1359129051 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.1392950774 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 4085533904 ps |
| CPU time | 65.28 seconds |
| Started | Jul 12 07:33:01 PM PDT 24 |
| Finished | Jul 12 07:34:10 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-049796f9-dc66-4c7d-b9bc-c5e3a5547b09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392950774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.1392950774 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.3924411960 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 58483596 ps |
| CPU time | 6.93 seconds |
| Started | Jul 12 07:32:53 PM PDT 24 |
| Finished | Jul 12 07:33:02 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-f374cea7-0762-4305-bd07-3a512f9662a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924411960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay s.3924411960 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.2517937319 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 9005463467 ps |
| CPU time | 375.48 seconds |
| Started | Jul 12 07:32:53 PM PDT 24 |
| Finished | Jul 12 07:39:11 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-2633c8b9-ed1f-4ded-9700-7fffc64383e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517937319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.2517937319 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.3422733206 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 16311323140 ps |
| CPU time | 532.17 seconds |
| Started | Jul 12 07:32:51 PM PDT 24 |
| Finished | Jul 12 07:41:45 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-91bbadac-e909-4eda-a018-734844b06ae7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422733206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.3422733206 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.3824227581 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 220087642 ps |
| CPU time | 94.4 seconds |
| Started | Jul 12 07:32:53 PM PDT 24 |
| Finished | Jul 12 07:34:30 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-9bf5e8cf-2e1f-4e4c-9c54-002912bfbd8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824227581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.3824227581 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.2932858493 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 198723775 ps |
| CPU time | 40.35 seconds |
| Started | Jul 12 07:32:55 PM PDT 24 |
| Finished | Jul 12 07:33:39 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-0c900ad1-c2d5-488f-91f2-319fde780d3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932858493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al l_with_reset_error.2932858493 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.3148804547 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 1134040368 ps |
| CPU time | 48.1 seconds |
| Started | Jul 12 07:32:54 PM PDT 24 |
| Finished | Jul 12 07:33:45 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-b097934f-e667-47ef-b295-db1b063fe3c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148804547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.3148804547 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.336476327 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 776805962 ps |
| CPU time | 62.85 seconds |
| Started | Jul 12 07:33:05 PM PDT 24 |
| Finished | Jul 12 07:34:11 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-86196c9b-c14c-47ac-8702-8068c7072dd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336476327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device. 336476327 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.2674776390 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 2841887328 ps |
| CPU time | 52.4 seconds |
| Started | Jul 12 07:33:05 PM PDT 24 |
| Finished | Jul 12 07:34:01 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-70ccf130-487b-4171-b917-d8f3ddeef1f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674776390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.2674776390 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3523546425 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 599709210 ps |
| CPU time | 25.36 seconds |
| Started | Jul 12 07:33:07 PM PDT 24 |
| Finished | Jul 12 07:33:36 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-98633f1f-fc21-4615-8128-f09f462642f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523546425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.3523546425 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.654128938 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 250356556 ps |
| CPU time | 11.64 seconds |
| Started | Jul 12 07:33:06 PM PDT 24 |
| Finished | Jul 12 07:33:21 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-c03a7662-4193-40ce-8f59-2f420846bf9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654128938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.654128938 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.1562842490 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 341007269 ps |
| CPU time | 33.3 seconds |
| Started | Jul 12 07:33:03 PM PDT 24 |
| Finished | Jul 12 07:33:40 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-15aaa568-09f2-43d6-8d9a-8f6f1c3d3915 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562842490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.1562842490 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.710170643 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 39408792746 ps |
| CPU time | 428.86 seconds |
| Started | Jul 12 07:33:05 PM PDT 24 |
| Finished | Jul 12 07:40:18 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-c25e3303-be64-464e-885a-06b7a40e587f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710170643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.710170643 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.1304376214 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 28799348637 ps |
| CPU time | 487.89 seconds |
| Started | Jul 12 07:33:07 PM PDT 24 |
| Finished | Jul 12 07:41:18 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-be7c48f0-a188-4577-b30f-51521f212445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304376214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.1304376214 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.2338753217 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 267168298 ps |
| CPU time | 28.37 seconds |
| Started | Jul 12 07:33:05 PM PDT 24 |
| Finished | Jul 12 07:33:37 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-75499a37-7760-45c3-aad7-977d50f18b19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338753217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del ays.2338753217 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.2949832099 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 475561521 ps |
| CPU time | 34.66 seconds |
| Started | Jul 12 07:33:03 PM PDT 24 |
| Finished | Jul 12 07:33:42 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-229a0194-738a-4b3d-aa44-698dd735e3f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949832099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.2949832099 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.2514131416 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 184177212 ps |
| CPU time | 8.08 seconds |
| Started | Jul 12 07:33:06 PM PDT 24 |
| Finished | Jul 12 07:33:17 PM PDT 24 |
| Peak memory | 575196 kb |
| Host | smart-2e27d13f-0669-46fa-9f27-d1f203d316ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514131416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.2514131416 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.740817670 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 9885439172 ps |
| CPU time | 103.15 seconds |
| Started | Jul 12 07:33:11 PM PDT 24 |
| Finished | Jul 12 07:34:55 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-3be33b0d-a882-4f3d-8022-8bdea4754b10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740817670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.740817670 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.2960401884 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 5443454580 ps |
| CPU time | 93.12 seconds |
| Started | Jul 12 07:33:06 PM PDT 24 |
| Finished | Jul 12 07:34:42 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-e610a19d-575f-46a4-842e-ecdede72cf87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960401884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.2960401884 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.3841094164 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 46435795 ps |
| CPU time | 6.46 seconds |
| Started | Jul 12 07:33:07 PM PDT 24 |
| Finished | Jul 12 07:33:17 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-161fae60-632d-447e-8cad-dfc91a286da7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841094164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.3841094164 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.668569128 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 3310114463 ps |
| CPU time | 286.43 seconds |
| Started | Jul 12 07:33:06 PM PDT 24 |
| Finished | Jul 12 07:37:56 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-28c82852-2011-4b28-b63a-1a97b924fcc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668569128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.668569128 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.1255579224 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 2985422861 ps |
| CPU time | 228.65 seconds |
| Started | Jul 12 07:33:05 PM PDT 24 |
| Finished | Jul 12 07:36:57 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-5536a5b3-03ef-48fe-be4f-a8ae56b73e81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255579224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.1255579224 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.3176468586 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 291309740 ps |
| CPU time | 104.23 seconds |
| Started | Jul 12 07:33:05 PM PDT 24 |
| Finished | Jul 12 07:34:53 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-1d1486d7-0ca1-4b77-9c83-3427b281384c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176468586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_rand_reset.3176468586 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.1032228010 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 3055823911 ps |
| CPU time | 357.61 seconds |
| Started | Jul 12 07:33:04 PM PDT 24 |
| Finished | Jul 12 07:39:05 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-5916fea3-ff74-4e37-9bc0-71c8294d0979 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032228010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.1032228010 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.2474400191 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 91114393 ps |
| CPU time | 6.95 seconds |
| Started | Jul 12 07:33:05 PM PDT 24 |
| Finished | Jul 12 07:33:15 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-db6c2c1e-f231-4951-8dd2-c5b8922475f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474400191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.2474400191 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.937901416 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 90912235 ps |
| CPU time | 8.58 seconds |
| Started | Jul 12 07:33:18 PM PDT 24 |
| Finished | Jul 12 07:33:29 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-263869d6-0703-4000-aa5a-b13fa022731e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937901416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device. 937901416 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.2699986199 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 108850520712 ps |
| CPU time | 2044.13 seconds |
| Started | Jul 12 07:33:18 PM PDT 24 |
| Finished | Jul 12 08:07:26 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-2abb37c5-4e01-4260-9002-f19d80c5d7ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699986199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_ device_slow_rsp.2699986199 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.4262058001 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 1511315476 ps |
| CPU time | 63.89 seconds |
| Started | Jul 12 07:33:21 PM PDT 24 |
| Finished | Jul 12 07:34:27 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-0b873dda-fffb-4731-86b0-23ca38fb3299 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262058001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.4262058001 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.3366402441 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 513573822 ps |
| CPU time | 42.9 seconds |
| Started | Jul 12 07:33:19 PM PDT 24 |
| Finished | Jul 12 07:34:05 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-b50ecca8-2b24-4ed0-9d85-3fe231fb4a6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366402441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.3366402441 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.3444735762 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 935778721 ps |
| CPU time | 38.55 seconds |
| Started | Jul 12 07:33:17 PM PDT 24 |
| Finished | Jul 12 07:33:58 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-0c783f4a-114a-4e94-90fc-5da064bc6808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444735762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.3444735762 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.751110051 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 32855088906 ps |
| CPU time | 357.74 seconds |
| Started | Jul 12 07:33:18 PM PDT 24 |
| Finished | Jul 12 07:39:19 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-8738419e-30af-467a-a213-03ab7c13a4e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751110051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.751110051 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.978550792 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 55458009667 ps |
| CPU time | 954.28 seconds |
| Started | Jul 12 07:33:22 PM PDT 24 |
| Finished | Jul 12 07:49:19 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-f1bad1b7-5916-443a-928b-00f0ee87db6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978550792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.978550792 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.3186731655 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 487900614 ps |
| CPU time | 49.17 seconds |
| Started | Jul 12 07:33:20 PM PDT 24 |
| Finished | Jul 12 07:34:13 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-1c290783-6005-4e42-bfcb-ae89ddb31578 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186731655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del ays.3186731655 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.1496094650 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 1270726043 ps |
| CPU time | 40.81 seconds |
| Started | Jul 12 07:33:17 PM PDT 24 |
| Finished | Jul 12 07:34:00 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-b363b025-548f-4a23-ab3b-8ee736a417dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496094650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.1496094650 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.219019069 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 258776355 ps |
| CPU time | 11.02 seconds |
| Started | Jul 12 07:33:05 PM PDT 24 |
| Finished | Jul 12 07:33:20 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-23f54687-890e-447c-be2e-31eb1d92f69a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219019069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.219019069 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.420551528 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 6264084323 ps |
| CPU time | 70.14 seconds |
| Started | Jul 12 07:33:04 PM PDT 24 |
| Finished | Jul 12 07:34:18 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-3daad7f7-ff48-4f83-9061-9627249a35f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420551528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.420551528 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.3310316761 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 4489569640 ps |
| CPU time | 79.96 seconds |
| Started | Jul 12 07:33:03 PM PDT 24 |
| Finished | Jul 12 07:34:27 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-fbc4fa55-e8db-4287-a75c-663077aeaa79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310316761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.3310316761 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.3972270217 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 52673110 ps |
| CPU time | 6.67 seconds |
| Started | Jul 12 07:33:07 PM PDT 24 |
| Finished | Jul 12 07:33:17 PM PDT 24 |
| Peak memory | 573952 kb |
| Host | smart-f84fa1d1-d7d8-44a8-b949-fd61f57f4ce3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972270217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.3972270217 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.3853903869 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 8870648274 ps |
| CPU time | 340.94 seconds |
| Started | Jul 12 07:33:18 PM PDT 24 |
| Finished | Jul 12 07:39:01 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-5ce5b1c9-aa83-4256-ab72-80448f39fa94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853903869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.3853903869 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.1412860126 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 1387920717 ps |
| CPU time | 112.68 seconds |
| Started | Jul 12 07:33:20 PM PDT 24 |
| Finished | Jul 12 07:35:16 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-4556c765-d085-41cc-a312-e7a22188fc24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412860126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.1412860126 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.1250209441 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 25105284 ps |
| CPU time | 16.71 seconds |
| Started | Jul 12 07:33:18 PM PDT 24 |
| Finished | Jul 12 07:33:38 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-2b459e96-8dca-4169-a56b-a688155e176b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250209441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_rand_reset.1250209441 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.2875101846 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 542056957 ps |
| CPU time | 164.24 seconds |
| Started | Jul 12 07:33:17 PM PDT 24 |
| Finished | Jul 12 07:36:03 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-bbda7b59-0ce3-4bae-9067-4b65716d27be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875101846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.2875101846 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.3870685586 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 1411856405 ps |
| CPU time | 66.67 seconds |
| Started | Jul 12 07:33:21 PM PDT 24 |
| Finished | Jul 12 07:34:30 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-9eb0debc-99f8-4c20-9522-fa668474c434 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870685586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.3870685586 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.1068347104 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 3891783810 ps |
| CPU time | 325.31 seconds |
| Started | Jul 12 07:24:21 PM PDT 24 |
| Finished | Jul 12 07:29:47 PM PDT 24 |
| Peak memory | 597320 kb |
| Host | smart-e30d3645-35df-4a7f-8143-7da869e3d332 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068347104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.1068347104 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.3397780881 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 13992777385 ps |
| CPU time | 1437.83 seconds |
| Started | Jul 12 07:24:11 PM PDT 24 |
| Finished | Jul 12 07:48:10 PM PDT 24 |
| Peak memory | 592776 kb |
| Host | smart-6d9d19a8-d329-4f4c-a991-ea896fb19314 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397780881 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.3397780881 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.2912065833 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 4429139999 ps |
| CPU time | 378.26 seconds |
| Started | Jul 12 07:24:13 PM PDT 24 |
| Finished | Jul 12 07:30:34 PM PDT 24 |
| Peak memory | 598604 kb |
| Host | smart-eb6d70d8-b06a-4e8d-9f71-3251c7a3260e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912065833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.2912065833 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.99893481 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 553918463 ps |
| CPU time | 39.81 seconds |
| Started | Jul 12 07:24:19 PM PDT 24 |
| Finished | Jul 12 07:25:00 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-0f60b8b1-6ddf-4d02-96bb-d2a52ad945ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99893481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.99893481 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.1969267112 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 20301872246 ps |
| CPU time | 352.1 seconds |
| Started | Jul 12 07:24:21 PM PDT 24 |
| Finished | Jul 12 07:30:14 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-bd43953f-fdb4-4dd5-96ab-2becad67ba3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969267112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d evice_slow_rsp.1969267112 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3680434457 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 302156944 ps |
| CPU time | 13.62 seconds |
| Started | Jul 12 07:24:29 PM PDT 24 |
| Finished | Jul 12 07:24:44 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-85cc5215-4066-4c9f-829d-2608e5b42ef9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680434457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .3680434457 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.277003383 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 492042675 ps |
| CPU time | 36.31 seconds |
| Started | Jul 12 07:24:18 PM PDT 24 |
| Finished | Jul 12 07:24:55 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-1a4efe04-f201-4100-a9c3-9c9555eace74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277003383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.277003383 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.2081934399 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 2359135004 ps |
| CPU time | 82.33 seconds |
| Started | Jul 12 07:24:09 PM PDT 24 |
| Finished | Jul 12 07:25:33 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-62846e07-a797-488c-8ed2-d882ed97b23e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081934399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.2081934399 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.1474559342 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 2832720547 ps |
| CPU time | 33.25 seconds |
| Started | Jul 12 07:24:10 PM PDT 24 |
| Finished | Jul 12 07:24:45 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-f3ee8a6b-daa6-4647-9ce7-1f7b68465c09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474559342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1474559342 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.2833397194 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 24783688707 ps |
| CPU time | 425.35 seconds |
| Started | Jul 12 07:24:23 PM PDT 24 |
| Finished | Jul 12 07:31:29 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-8cdd7f64-2dc1-436e-8a1a-3d1023eb009a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833397194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2833397194 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.573508597 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 258446752 ps |
| CPU time | 25.81 seconds |
| Started | Jul 12 07:24:15 PM PDT 24 |
| Finished | Jul 12 07:24:42 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-7734625b-5d14-4d4a-b032-4aba602a9986 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573508597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delay s.573508597 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.2091979534 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 1320668449 ps |
| CPU time | 41.98 seconds |
| Started | Jul 12 07:24:23 PM PDT 24 |
| Finished | Jul 12 07:25:07 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-4e1f8459-8a74-4eca-bf18-21be1f2408bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091979534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2091979534 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.2909449193 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 247570915 ps |
| CPU time | 10.58 seconds |
| Started | Jul 12 07:24:14 PM PDT 24 |
| Finished | Jul 12 07:24:26 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-10322643-b43d-42d7-b0ec-89e97dc04f1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909449193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2909449193 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.2047393771 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 8668302779 ps |
| CPU time | 97.13 seconds |
| Started | Jul 12 07:24:14 PM PDT 24 |
| Finished | Jul 12 07:25:52 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-70839b02-b189-49d6-863b-ad25528f9854 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047393771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2047393771 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.3946268857 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 3430739386 ps |
| CPU time | 59.09 seconds |
| Started | Jul 12 07:24:14 PM PDT 24 |
| Finished | Jul 12 07:25:15 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-c06df953-2d93-4e77-bab6-44b34b90fbb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946268857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3946268857 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.414875270 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 45383318 ps |
| CPU time | 6.08 seconds |
| Started | Jul 12 07:24:09 PM PDT 24 |
| Finished | Jul 12 07:24:17 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-56cc923c-7d77-44c6-8d57-bb6af978d883 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414875270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays. 414875270 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.1185709408 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 824384835 ps |
| CPU time | 62.08 seconds |
| Started | Jul 12 07:24:29 PM PDT 24 |
| Finished | Jul 12 07:25:33 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-1a34405b-efa1-4aca-a42a-9bd206291d0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185709408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1185709408 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.328074025 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 2684968322 ps |
| CPU time | 116.5 seconds |
| Started | Jul 12 07:24:30 PM PDT 24 |
| Finished | Jul 12 07:26:28 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-7a3f4d6a-9f9f-41c5-96df-c8f220613d4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328074025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.328074025 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.2919417626 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 83814201 ps |
| CPU time | 21.75 seconds |
| Started | Jul 12 07:24:21 PM PDT 24 |
| Finished | Jul 12 07:24:44 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-f572d48c-c2b5-4469-9c05-3aaadde7fc41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919417626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_rand_reset.2919417626 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.4199867384 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 2357016118 ps |
| CPU time | 259.22 seconds |
| Started | Jul 12 07:24:19 PM PDT 24 |
| Finished | Jul 12 07:28:39 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-178e0577-23fb-4de6-8388-fd3bed3c68c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199867384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.4199867384 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.137302206 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 310096229 ps |
| CPU time | 15.38 seconds |
| Started | Jul 12 07:24:19 PM PDT 24 |
| Finished | Jul 12 07:24:36 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-68cd508f-6311-4e4f-bdd4-5b2d9702779e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137302206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.137302206 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.2383018422 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 31243658 ps |
| CPU time | 8.82 seconds |
| Started | Jul 12 07:33:31 PM PDT 24 |
| Finished | Jul 12 07:33:42 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-405062f7-0a40-4cc5-9067-e83575273f0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383018422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .2383018422 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.795949439 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 1513278345 ps |
| CPU time | 55.3 seconds |
| Started | Jul 12 07:33:29 PM PDT 24 |
| Finished | Jul 12 07:34:27 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-3a6ad5b2-8ab0-40fa-86e3-914b46d6ed54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795949439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_addr .795949439 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.2441237671 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 484934594 ps |
| CPU time | 37.8 seconds |
| Started | Jul 12 07:33:31 PM PDT 24 |
| Finished | Jul 12 07:34:12 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-00c5e080-25ba-4aeb-9aca-ae059cea8b2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441237671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.2441237671 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.1522125352 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 508002993 ps |
| CPU time | 41.07 seconds |
| Started | Jul 12 07:33:19 PM PDT 24 |
| Finished | Jul 12 07:34:03 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-bf1581a2-28e7-43a0-b5f5-c5b4005bf370 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522125352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.1522125352 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.1874075045 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 11995068600 ps |
| CPU time | 137.63 seconds |
| Started | Jul 12 07:33:18 PM PDT 24 |
| Finished | Jul 12 07:35:38 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-e048d058-4ca3-4608-8e64-163ad227752d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874075045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.1874075045 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.502763936 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 10463921293 ps |
| CPU time | 192.64 seconds |
| Started | Jul 12 07:33:17 PM PDT 24 |
| Finished | Jul 12 07:36:32 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-9b3d6d89-476c-4191-8a93-2622e538f178 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502763936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.502763936 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.3558666227 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 498927510 ps |
| CPU time | 37.32 seconds |
| Started | Jul 12 07:33:23 PM PDT 24 |
| Finished | Jul 12 07:34:02 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-700ae15d-69f6-4bb4-a4d8-3b30f806b1ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558666227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.3558666227 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.2115965682 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 1441089602 ps |
| CPU time | 44.94 seconds |
| Started | Jul 12 07:33:30 PM PDT 24 |
| Finished | Jul 12 07:34:18 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-6296db3e-73e0-4460-82e6-6a7dcf348de7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115965682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.2115965682 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.2422536627 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 158323876 ps |
| CPU time | 7.24 seconds |
| Started | Jul 12 07:33:19 PM PDT 24 |
| Finished | Jul 12 07:33:29 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-db6e156b-1d77-4714-870c-806ed642c60a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422536627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.2422536627 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.2373409264 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 10362410503 ps |
| CPU time | 114.72 seconds |
| Started | Jul 12 07:33:19 PM PDT 24 |
| Finished | Jul 12 07:35:17 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-d107654e-2580-4327-8a79-9f05b04b6a79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373409264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.2373409264 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.4240691461 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 4593787029 ps |
| CPU time | 85.71 seconds |
| Started | Jul 12 07:33:18 PM PDT 24 |
| Finished | Jul 12 07:34:48 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-b739b724-b09a-42af-963d-9b3c1e498fac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240691461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.4240691461 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.2197759235 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 48051054 ps |
| CPU time | 6.62 seconds |
| Started | Jul 12 07:33:18 PM PDT 24 |
| Finished | Jul 12 07:33:28 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-4ded39eb-9148-482e-ae85-077dceda036b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197759235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.2197759235 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.2887130360 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 10326589297 ps |
| CPU time | 399.19 seconds |
| Started | Jul 12 07:33:31 PM PDT 24 |
| Finished | Jul 12 07:40:13 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-b4931534-7c0e-4214-bc88-62da0ca10036 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887130360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.2887130360 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.343767289 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 4844633302 ps |
| CPU time | 163.86 seconds |
| Started | Jul 12 07:33:30 PM PDT 24 |
| Finished | Jul 12 07:36:17 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-3100d9ff-d4a5-4dcd-b10a-9b2b7a6b790f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343767289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.343767289 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.1545602020 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 7117789285 ps |
| CPU time | 374.56 seconds |
| Started | Jul 12 07:33:31 PM PDT 24 |
| Finished | Jul 12 07:39:48 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-e36335c5-cac7-471f-b553-108ef2543400 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545602020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_rand_reset.1545602020 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.3800373682 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 711424194 ps |
| CPU time | 174.94 seconds |
| Started | Jul 12 07:33:30 PM PDT 24 |
| Finished | Jul 12 07:36:27 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-6d030e4f-cba9-4d69-b895-b86967ba1213 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800373682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.3800373682 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.2782607412 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1258490158 ps |
| CPU time | 56.13 seconds |
| Started | Jul 12 07:33:29 PM PDT 24 |
| Finished | Jul 12 07:34:29 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-c1f0e636-5deb-4439-ab2d-5472a84121de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782607412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.2782607412 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.4293788360 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 911325040 ps |
| CPU time | 41.31 seconds |
| Started | Jul 12 07:33:29 PM PDT 24 |
| Finished | Jul 12 07:34:13 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-81af93fe-d6c8-43ee-bd43-efc333a76121 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293788360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device .4293788360 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.1340533780 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 132639708903 ps |
| CPU time | 2583.33 seconds |
| Started | Jul 12 07:33:29 PM PDT 24 |
| Finished | Jul 12 08:16:35 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-f8a775d2-387a-4216-bcd6-85b20605bbdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340533780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_ device_slow_rsp.1340533780 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.3710305480 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 221056400 ps |
| CPU time | 23.49 seconds |
| Started | Jul 12 07:33:43 PM PDT 24 |
| Finished | Jul 12 07:34:08 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-f3106b16-f82d-445e-8c4c-238468b483a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710305480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add r.3710305480 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.1883843 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 1272244548 ps |
| CPU time | 41.71 seconds |
| Started | Jul 12 07:33:36 PM PDT 24 |
| Finished | Jul 12 07:34:20 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-404419c0-58a4-4cff-89a6-9f77b9175266 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.1883843 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.1700354778 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2459138202 ps |
| CPU time | 81.48 seconds |
| Started | Jul 12 07:33:36 PM PDT 24 |
| Finished | Jul 12 07:35:00 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-5993d742-509f-4b19-b1fa-e3552a2eeee9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700354778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.1700354778 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.380502293 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 82410606738 ps |
| CPU time | 924.64 seconds |
| Started | Jul 12 07:33:36 PM PDT 24 |
| Finished | Jul 12 07:49:03 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-e4d6d411-4742-4b9a-8fc3-4f6a4dacd73c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380502293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.380502293 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.1790307994 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 42571688784 ps |
| CPU time | 707.69 seconds |
| Started | Jul 12 07:33:31 PM PDT 24 |
| Finished | Jul 12 07:45:21 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-fdf199c3-3c37-4ec4-92a9-4f5843da3eb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790307994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.1790307994 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.2902004044 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 101809856 ps |
| CPU time | 12.4 seconds |
| Started | Jul 12 07:33:34 PM PDT 24 |
| Finished | Jul 12 07:33:50 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-6ee246c2-3b86-4a19-91ae-7b1b8de6d85d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902004044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del ays.2902004044 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.1351817226 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 473188137 ps |
| CPU time | 29.89 seconds |
| Started | Jul 12 07:33:34 PM PDT 24 |
| Finished | Jul 12 07:34:07 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-6ea77052-5c62-4bf9-92ff-57c29483ade5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351817226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.1351817226 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.1060794132 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 190866741 ps |
| CPU time | 8.73 seconds |
| Started | Jul 12 07:33:29 PM PDT 24 |
| Finished | Jul 12 07:33:40 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-3ed02c3f-1881-4ed1-a8ab-29658a9e6f0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060794132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.1060794132 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.1098609858 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 8154936545 ps |
| CPU time | 87.36 seconds |
| Started | Jul 12 07:33:33 PM PDT 24 |
| Finished | Jul 12 07:35:03 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-6a523029-f3ac-4a43-9807-c9c53ee57784 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098609858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.1098609858 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.2027272918 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 5426898591 ps |
| CPU time | 97.36 seconds |
| Started | Jul 12 07:33:31 PM PDT 24 |
| Finished | Jul 12 07:35:11 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-53b47d61-32cf-43df-9808-0248fe6bf3b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027272918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.2027272918 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.3007132504 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 52742572 ps |
| CPU time | 6.55 seconds |
| Started | Jul 12 07:33:28 PM PDT 24 |
| Finished | Jul 12 07:33:37 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-d852b89d-09c1-472f-b974-07642f387238 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007132504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.3007132504 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.2490570963 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 7201390820 ps |
| CPU time | 275.91 seconds |
| Started | Jul 12 07:33:41 PM PDT 24 |
| Finished | Jul 12 07:38:18 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-f78cee4d-574e-4e61-856f-a43ae44a74c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490570963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.2490570963 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.3823068082 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 974085651 ps |
| CPU time | 76.77 seconds |
| Started | Jul 12 07:33:42 PM PDT 24 |
| Finished | Jul 12 07:35:00 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-79367e73-dda3-441b-bd8c-71d77db7a590 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823068082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.3823068082 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.2292073348 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 1028141978 ps |
| CPU time | 163.75 seconds |
| Started | Jul 12 07:33:41 PM PDT 24 |
| Finished | Jul 12 07:36:27 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-88b1c8da-66f9-4a64-9872-377ad1591dda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292073348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.2292073348 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.3248615737 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 469439840 ps |
| CPU time | 80.05 seconds |
| Started | Jul 12 07:33:41 PM PDT 24 |
| Finished | Jul 12 07:35:02 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-38f45346-df04-485e-ba47-ee8c22b39619 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248615737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.3248615737 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.1238330184 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 149926620 ps |
| CPU time | 20.7 seconds |
| Started | Jul 12 07:33:34 PM PDT 24 |
| Finished | Jul 12 07:33:58 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-d91ebced-d8c3-4a72-8844-9cd011b58ba6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238330184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.1238330184 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.3157805284 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 1485726570 ps |
| CPU time | 60.62 seconds |
| Started | Jul 12 07:33:42 PM PDT 24 |
| Finished | Jul 12 07:34:44 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-70f4ec90-98fd-47f7-8db3-5a348b60aa98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157805284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device .3157805284 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.3130088345 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 39340356228 ps |
| CPU time | 765.66 seconds |
| Started | Jul 12 07:33:45 PM PDT 24 |
| Finished | Jul 12 07:46:32 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-af81aeec-1680-4008-aa8d-545f12c388fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130088345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_ device_slow_rsp.3130088345 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.286847165 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 318644498 ps |
| CPU time | 14.37 seconds |
| Started | Jul 12 07:33:45 PM PDT 24 |
| Finished | Jul 12 07:34:01 PM PDT 24 |
| Peak memory | 575104 kb |
| Host | smart-0e4c4ef1-f630-4be6-b9a0-e445172859d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286847165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_addr .286847165 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.3274506431 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 2058868415 ps |
| CPU time | 74.21 seconds |
| Started | Jul 12 07:33:45 PM PDT 24 |
| Finished | Jul 12 07:35:01 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-b4ee3138-c242-4a65-9b25-9f1da8177c2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274506431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.3274506431 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.3880854215 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 1547497955 ps |
| CPU time | 50.37 seconds |
| Started | Jul 12 07:33:45 PM PDT 24 |
| Finished | Jul 12 07:34:37 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-84715a53-4828-46e0-8cd8-ce7f3df85920 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880854215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.3880854215 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.162682291 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 105651208915 ps |
| CPU time | 1254.24 seconds |
| Started | Jul 12 07:33:42 PM PDT 24 |
| Finished | Jul 12 07:54:38 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-be65f4c4-aacc-408a-98e0-8ac6e400e262 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162682291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.162682291 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.2256850814 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 36308927312 ps |
| CPU time | 625.64 seconds |
| Started | Jul 12 07:33:42 PM PDT 24 |
| Finished | Jul 12 07:44:10 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-e662d156-1371-4c64-b301-5aad43b485ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256850814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.2256850814 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.2129351600 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 199988981 ps |
| CPU time | 18.16 seconds |
| Started | Jul 12 07:33:40 PM PDT 24 |
| Finished | Jul 12 07:34:00 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-efda1ef0-9740-4eff-903b-529f3f12f02d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129351600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.2129351600 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.3839202288 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 711661788 ps |
| CPU time | 23.55 seconds |
| Started | Jul 12 07:33:44 PM PDT 24 |
| Finished | Jul 12 07:34:09 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-0e136c06-af95-48bd-bf10-84f51d542662 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839202288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.3839202288 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.1571086638 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 187619285 ps |
| CPU time | 9.44 seconds |
| Started | Jul 12 07:33:43 PM PDT 24 |
| Finished | Jul 12 07:33:54 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-69046349-c863-4816-82ec-d575099d9a05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571086638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.1571086638 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.3727702598 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 9613385600 ps |
| CPU time | 105.97 seconds |
| Started | Jul 12 07:33:41 PM PDT 24 |
| Finished | Jul 12 07:35:28 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-f12b9e3e-0ba8-48c7-8e9c-c73c7af2792c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727702598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.3727702598 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.1454472600 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 4220984387 ps |
| CPU time | 66.97 seconds |
| Started | Jul 12 07:33:42 PM PDT 24 |
| Finished | Jul 12 07:34:50 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-0d83cd97-4687-4b80-b95f-6938c90768d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454472600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.1454472600 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.2174134622 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 39161369 ps |
| CPU time | 5.83 seconds |
| Started | Jul 12 07:33:44 PM PDT 24 |
| Finished | Jul 12 07:33:51 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-5b6f2b31-5a70-4790-ba25-75b7e0d9c4c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174134622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.2174134622 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.2864640846 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 20848576445 ps |
| CPU time | 826.85 seconds |
| Started | Jul 12 07:33:52 PM PDT 24 |
| Finished | Jul 12 07:47:42 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-916321cb-ed66-43ac-8b7d-7e66b236ad42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864640846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.2864640846 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.3026194255 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 942847940 ps |
| CPU time | 71.69 seconds |
| Started | Jul 12 07:33:42 PM PDT 24 |
| Finished | Jul 12 07:34:55 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-baf0bebd-485a-4930-bcb3-c5637bfbe03c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026194255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.3026194255 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.1963624101 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 1084307458 ps |
| CPU time | 253.63 seconds |
| Started | Jul 12 07:33:43 PM PDT 24 |
| Finished | Jul 12 07:37:58 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-bef4f716-e9cc-40cb-a759-8c325c3d7191 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963624101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_rand_reset.1963624101 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.3420988135 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 3487499275 ps |
| CPU time | 326.18 seconds |
| Started | Jul 12 07:33:52 PM PDT 24 |
| Finished | Jul 12 07:39:21 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-6ea4a402-f4e8-45c5-9a8c-33e52d3aaae5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420988135 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.3420988135 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.3172730873 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 180143703 ps |
| CPU time | 9.63 seconds |
| Started | Jul 12 07:33:44 PM PDT 24 |
| Finished | Jul 12 07:33:55 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-58cb3402-709a-4699-9d06-fd1de06f3d1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172730873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.3172730873 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.3429185117 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 789261105 ps |
| CPU time | 28.33 seconds |
| Started | Jul 12 07:33:56 PM PDT 24 |
| Finished | Jul 12 07:34:28 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-866f48a9-0d6e-478b-9e90-fb540900b510 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429185117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .3429185117 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.360382213 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 44365458924 ps |
| CPU time | 805.42 seconds |
| Started | Jul 12 07:33:53 PM PDT 24 |
| Finished | Jul 12 07:47:22 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-d8552cb3-4f4f-4b89-8578-0597b61d1d5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360382213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_d evice_slow_rsp.360382213 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.3578643318 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 908683126 ps |
| CPU time | 35.74 seconds |
| Started | Jul 12 07:33:56 PM PDT 24 |
| Finished | Jul 12 07:34:35 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-8ec1056d-13d2-48c1-8ae1-7e5f3eae883f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578643318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add r.3578643318 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.1016966051 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 569053607 ps |
| CPU time | 42.2 seconds |
| Started | Jul 12 07:33:54 PM PDT 24 |
| Finished | Jul 12 07:34:39 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-3ce49dd4-92e3-44b4-bf75-c7c54b2f1e32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016966051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.1016966051 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.4039251150 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 383061549 ps |
| CPU time | 17.55 seconds |
| Started | Jul 12 07:33:54 PM PDT 24 |
| Finished | Jul 12 07:34:14 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-a8c94cd6-0ee6-4cb7-aa21-0050c9c7484f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039251150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.4039251150 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.2976628205 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 66903713089 ps |
| CPU time | 745.36 seconds |
| Started | Jul 12 07:33:56 PM PDT 24 |
| Finished | Jul 12 07:46:24 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-8b8713c0-5608-4794-951e-ede3a73e13a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976628205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.2976628205 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.325375442 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 61092703103 ps |
| CPU time | 1118.98 seconds |
| Started | Jul 12 07:33:55 PM PDT 24 |
| Finished | Jul 12 07:52:37 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-f2e34705-a4f5-4e16-8423-c4cbad19997d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325375442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.325375442 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.1982587147 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 454975343 ps |
| CPU time | 36.4 seconds |
| Started | Jul 12 07:33:59 PM PDT 24 |
| Finished | Jul 12 07:34:38 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-99c3ccda-0356-4b7b-a8a4-fbf6d499eac0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982587147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_del ays.1982587147 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.3333627899 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 57263562 ps |
| CPU time | 7.54 seconds |
| Started | Jul 12 07:33:57 PM PDT 24 |
| Finished | Jul 12 07:34:08 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-f9e548ff-d4a5-44e2-84bb-a8e52f0fff18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333627899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.3333627899 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.3821954012 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 49376135 ps |
| CPU time | 5.9 seconds |
| Started | Jul 12 07:33:52 PM PDT 24 |
| Finished | Jul 12 07:34:01 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-18de6969-5d93-4c4a-88ae-bb32dfb374f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821954012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.3821954012 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.1268830292 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 8071915302 ps |
| CPU time | 88.99 seconds |
| Started | Jul 12 07:33:57 PM PDT 24 |
| Finished | Jul 12 07:35:29 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-4570c4ce-45a6-452a-ac6b-c0e7b626321c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268830292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.1268830292 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.2221492771 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 5841400659 ps |
| CPU time | 107.84 seconds |
| Started | Jul 12 07:34:03 PM PDT 24 |
| Finished | Jul 12 07:35:52 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-7590e232-f08b-4789-bb18-2e0870e7d90c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221492771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.2221492771 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.68197773 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 52746867 ps |
| CPU time | 7.14 seconds |
| Started | Jul 12 07:33:54 PM PDT 24 |
| Finished | Jul 12 07:34:04 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-1542c617-a2a4-40f1-8175-25d25bf8ad4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68197773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delays.68197773 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.1108538835 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 1646379259 ps |
| CPU time | 120.59 seconds |
| Started | Jul 12 07:33:55 PM PDT 24 |
| Finished | Jul 12 07:35:59 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-5f056624-c444-48dc-ae93-f6a8db114e1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108538835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.1108538835 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.3247600905 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 660249850 ps |
| CPU time | 45.03 seconds |
| Started | Jul 12 07:33:54 PM PDT 24 |
| Finished | Jul 12 07:34:42 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-778fdb40-6e57-4468-83d0-8d1109de1707 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247600905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.3247600905 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3960133288 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 167463158 ps |
| CPU time | 66.16 seconds |
| Started | Jul 12 07:33:56 PM PDT 24 |
| Finished | Jul 12 07:35:05 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-7cc0e7dd-f2ef-4100-b9ee-51e82f001040 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960133288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.3960133288 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.2766959926 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 99119734 ps |
| CPU time | 26.9 seconds |
| Started | Jul 12 07:33:55 PM PDT 24 |
| Finished | Jul 12 07:34:25 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-52257b0a-69d5-468a-b5fc-4f285891fa5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766959926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.2766959926 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.1793651561 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 374414243 ps |
| CPU time | 18 seconds |
| Started | Jul 12 07:33:58 PM PDT 24 |
| Finished | Jul 12 07:34:19 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-a010a7a6-3fb2-42e7-bc07-2cb52b96914e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793651561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.1793651561 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.786547169 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 420227594 ps |
| CPU time | 38.44 seconds |
| Started | Jul 12 07:33:59 PM PDT 24 |
| Finished | Jul 12 07:34:40 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-d8a1b386-71ad-43c5-a39f-8a57c4046454 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786547169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device. 786547169 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.2116246730 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 110394715856 ps |
| CPU time | 2065.4 seconds |
| Started | Jul 12 07:34:01 PM PDT 24 |
| Finished | Jul 12 08:08:28 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-1577cbd8-c0ed-4a6b-8b42-16baa3bbe959 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116246730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_ device_slow_rsp.2116246730 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.1005319878 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 238331138 ps |
| CPU time | 12.45 seconds |
| Started | Jul 12 07:34:02 PM PDT 24 |
| Finished | Jul 12 07:34:15 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-efc6dc6b-b742-49e5-adba-153e954360be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005319878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.1005319878 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.964038631 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 482494190 ps |
| CPU time | 45.62 seconds |
| Started | Jul 12 07:33:55 PM PDT 24 |
| Finished | Jul 12 07:34:44 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-17153846-a9a0-4fa0-9734-3f58d8ae42a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964038631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.964038631 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.2232974813 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 321233963 ps |
| CPU time | 13.49 seconds |
| Started | Jul 12 07:33:55 PM PDT 24 |
| Finished | Jul 12 07:34:12 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-f7eef318-63aa-40b7-a454-b87aab9e56d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232974813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.2232974813 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.2039422216 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 15747519516 ps |
| CPU time | 173.54 seconds |
| Started | Jul 12 07:36:06 PM PDT 24 |
| Finished | Jul 12 07:39:01 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-8ebe2269-6213-40cf-b7c7-764f39475962 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039422216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.2039422216 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.284556083 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 13994500246 ps |
| CPU time | 248.59 seconds |
| Started | Jul 12 07:33:58 PM PDT 24 |
| Finished | Jul 12 07:38:10 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-98799f1e-24af-499b-b6dc-7f2e8090e240 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284556083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.284556083 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.426670983 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 485025445 ps |
| CPU time | 45.1 seconds |
| Started | Jul 12 07:33:54 PM PDT 24 |
| Finished | Jul 12 07:34:42 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-b6f47536-d041-4ded-92d1-82a2937eb492 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426670983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_dela ys.426670983 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.1200545964 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 828410680 ps |
| CPU time | 26.92 seconds |
| Started | Jul 12 07:33:54 PM PDT 24 |
| Finished | Jul 12 07:34:24 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-719247d2-9646-42a2-a508-0fbab148f739 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200545964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.1200545964 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.2382273641 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 182906745 ps |
| CPU time | 9.08 seconds |
| Started | Jul 12 07:33:57 PM PDT 24 |
| Finished | Jul 12 07:34:09 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-bdd06979-381b-427d-b86f-83337d456472 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382273641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.2382273641 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.2453654325 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 7173809896 ps |
| CPU time | 77.61 seconds |
| Started | Jul 12 07:33:57 PM PDT 24 |
| Finished | Jul 12 07:35:18 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-ae9faa22-884b-443c-9219-fe82db566c4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453654325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.2453654325 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.1049711991 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 4411848379 ps |
| CPU time | 76.19 seconds |
| Started | Jul 12 07:33:54 PM PDT 24 |
| Finished | Jul 12 07:35:13 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-a13df83f-d5f2-44d8-a604-85730f16446f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049711991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.1049711991 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.2042936135 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 50264031 ps |
| CPU time | 6.3 seconds |
| Started | Jul 12 07:33:57 PM PDT 24 |
| Finished | Jul 12 07:34:06 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-8babde92-ff82-487b-ace7-958942f0f77c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042936135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay s.2042936135 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.3636621555 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 573059510 ps |
| CPU time | 49.87 seconds |
| Started | Jul 12 07:33:54 PM PDT 24 |
| Finished | Jul 12 07:34:47 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-8da8d88b-f751-4866-b308-9e9716798b53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636621555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.3636621555 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.4068011356 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 3931134170 ps |
| CPU time | 120.33 seconds |
| Started | Jul 12 07:34:15 PM PDT 24 |
| Finished | Jul 12 07:36:19 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-467cb4d5-149a-466d-beea-f1fd3f9e41ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068011356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.4068011356 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.1897496620 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 6296483829 ps |
| CPU time | 771.52 seconds |
| Started | Jul 12 07:34:06 PM PDT 24 |
| Finished | Jul 12 07:47:00 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-1a6597c6-f44e-45b8-92fb-7f8607fe2bcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897496620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_rand_reset.1897496620 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3906799559 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 5027633615 ps |
| CPU time | 417.73 seconds |
| Started | Jul 12 07:34:06 PM PDT 24 |
| Finished | Jul 12 07:41:06 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-970635bf-b2fc-4173-9e47-e1ecd602e5fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906799559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al l_with_reset_error.3906799559 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.1315144792 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 1012382233 ps |
| CPU time | 44.39 seconds |
| Started | Jul 12 07:33:53 PM PDT 24 |
| Finished | Jul 12 07:34:41 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-d9c7f79e-faa2-47ee-b23f-058978d58a30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315144792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.1315144792 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.120620368 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 1074720006 ps |
| CPU time | 42.28 seconds |
| Started | Jul 12 07:34:08 PM PDT 24 |
| Finished | Jul 12 07:34:53 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-30eb5328-0e37-4f82-96af-334b8f0817a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120620368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device. 120620368 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.1351210316 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 144621775160 ps |
| CPU time | 2833.59 seconds |
| Started | Jul 12 07:34:09 PM PDT 24 |
| Finished | Jul 12 08:21:27 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-19b581d0-4d77-4ba5-8817-824756d65a81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351210316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.1351210316 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.3677337537 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 1086420909 ps |
| CPU time | 42.69 seconds |
| Started | Jul 12 07:34:08 PM PDT 24 |
| Finished | Jul 12 07:34:54 PM PDT 24 |
| Peak memory | 575184 kb |
| Host | smart-c55bb098-6bd9-44a7-ba58-3b655b2f3d7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677337537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add r.3677337537 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.689219475 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 240759692 ps |
| CPU time | 20.43 seconds |
| Started | Jul 12 07:34:10 PM PDT 24 |
| Finished | Jul 12 07:34:35 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-47bf2127-dc43-46bf-8158-50723a92b60b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689219475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.689219475 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.2800243280 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 224430092 ps |
| CPU time | 19.98 seconds |
| Started | Jul 12 07:34:09 PM PDT 24 |
| Finished | Jul 12 07:34:33 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-c9b42e87-568a-4d1b-8611-7ad8dda88106 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800243280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.2800243280 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.2380887194 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 75018627611 ps |
| CPU time | 930.05 seconds |
| Started | Jul 12 07:34:15 PM PDT 24 |
| Finished | Jul 12 07:49:49 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-e0b21c10-53de-43ab-a20b-9e81d888317b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380887194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.2380887194 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.2608757415 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 66164251655 ps |
| CPU time | 1082.82 seconds |
| Started | Jul 12 07:34:07 PM PDT 24 |
| Finished | Jul 12 07:52:12 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-8d08a234-fe3c-487e-9af7-c0ebc30c9c28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608757415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.2608757415 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.63866986 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 155396509 ps |
| CPU time | 16 seconds |
| Started | Jul 12 07:34:07 PM PDT 24 |
| Finished | Jul 12 07:34:26 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-b889f9fa-1725-45d2-8064-1ef4356a8e55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63866986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_delay s.63866986 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.1394012874 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 1956055752 ps |
| CPU time | 63.85 seconds |
| Started | Jul 12 07:34:04 PM PDT 24 |
| Finished | Jul 12 07:35:08 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-6dfbf85f-f8fa-4f1e-8519-f257088c61cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394012874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.1394012874 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.3030325586 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 42265577 ps |
| CPU time | 6.28 seconds |
| Started | Jul 12 07:34:08 PM PDT 24 |
| Finished | Jul 12 07:34:17 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-115e79dc-1e04-4294-a898-5c2f86d0f780 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030325586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.3030325586 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.2124018504 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 6845648531 ps |
| CPU time | 76.04 seconds |
| Started | Jul 12 07:34:08 PM PDT 24 |
| Finished | Jul 12 07:35:27 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-a212cf11-095a-4dde-9c53-6bb228f7be76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124018504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.2124018504 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.3281820609 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 5476149700 ps |
| CPU time | 94.06 seconds |
| Started | Jul 12 07:34:07 PM PDT 24 |
| Finished | Jul 12 07:35:43 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-ef214ff0-eca3-417f-b7e4-d9da7f1be206 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281820609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.3281820609 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.2186769097 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 50933876 ps |
| CPU time | 6.3 seconds |
| Started | Jul 12 07:34:06 PM PDT 24 |
| Finished | Jul 12 07:34:15 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-6bc84ee1-3bcf-48e6-96df-7e3a45a149a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186769097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay s.2186769097 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.2580498026 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 6625061 ps |
| CPU time | 3.99 seconds |
| Started | Jul 12 07:34:05 PM PDT 24 |
| Finished | Jul 12 07:34:10 PM PDT 24 |
| Peak memory | 565644 kb |
| Host | smart-68c6f8b2-6aa1-4cde-b5ad-ab01e42cef80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580498026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.2580498026 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.3462112458 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 1201085965 ps |
| CPU time | 96.09 seconds |
| Started | Jul 12 07:34:09 PM PDT 24 |
| Finished | Jul 12 07:35:50 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-b39c3076-9cf2-47cb-b3c6-c8f8ce86d142 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462112458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.3462112458 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.598755 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 3861519489 ps |
| CPU time | 402.89 seconds |
| Started | Jul 12 07:34:06 PM PDT 24 |
| Finished | Jul 12 07:40:50 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-b4f1faf5-a38a-4114-b676-f0511fe1788f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_wit h_rand_reset.598755 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.1384615565 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 2107426333 ps |
| CPU time | 262.22 seconds |
| Started | Jul 12 07:34:07 PM PDT 24 |
| Finished | Jul 12 07:38:32 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-1ed64115-c2e9-4370-a7fe-8196c27b9293 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384615565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.1384615565 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.3536200228 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 178583666 ps |
| CPU time | 11.15 seconds |
| Started | Jul 12 07:34:10 PM PDT 24 |
| Finished | Jul 12 07:34:26 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-843eadf5-6952-4a73-b7e7-adc0eb546bf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536200228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.3536200228 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.2473412596 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 709211676 ps |
| CPU time | 53.46 seconds |
| Started | Jul 12 07:34:22 PM PDT 24 |
| Finished | Jul 12 07:35:19 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-73acf85c-c154-430e-ad89-f08a3a132602 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473412596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .2473412596 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.437638601 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 43604194934 ps |
| CPU time | 852.91 seconds |
| Started | Jul 12 07:34:17 PM PDT 24 |
| Finished | Jul 12 07:48:34 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-dfe5de08-90f5-4660-a6c7-c1f1e12aa8f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437638601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_d evice_slow_rsp.437638601 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.1338981868 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 132857453 ps |
| CPU time | 8.31 seconds |
| Started | Jul 12 07:34:23 PM PDT 24 |
| Finished | Jul 12 07:34:34 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-fff15ecf-8df9-4623-9454-0309888b5577 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338981868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add r.1338981868 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.1634445364 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 2372041344 ps |
| CPU time | 86.77 seconds |
| Started | Jul 12 07:34:24 PM PDT 24 |
| Finished | Jul 12 07:35:54 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-2d9c8a54-c4a8-4f5a-89c4-c05042b5ab6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634445364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.1634445364 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.1083237592 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 363570307 ps |
| CPU time | 29.8 seconds |
| Started | Jul 12 07:34:19 PM PDT 24 |
| Finished | Jul 12 07:34:52 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-2e5fba54-fd96-4b98-9af6-5f528c5c66aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083237592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.1083237592 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.338670113 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 37407977531 ps |
| CPU time | 391.5 seconds |
| Started | Jul 12 07:34:25 PM PDT 24 |
| Finished | Jul 12 07:41:00 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-9b2d4e5b-53f8-4cb1-8caf-3edbfa09e9e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338670113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.338670113 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.1823828705 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 16540500520 ps |
| CPU time | 279.55 seconds |
| Started | Jul 12 07:34:19 PM PDT 24 |
| Finished | Jul 12 07:39:02 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-88ce74b2-3d31-4e3d-90e7-f06027c1ad9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823828705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.1823828705 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.3292808845 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 57007839 ps |
| CPU time | 7.21 seconds |
| Started | Jul 12 07:34:19 PM PDT 24 |
| Finished | Jul 12 07:34:29 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-7f8952fc-7381-4d16-aaca-05f03042bbd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292808845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del ays.3292808845 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.553928913 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 1657394043 ps |
| CPU time | 52.8 seconds |
| Started | Jul 12 07:34:17 PM PDT 24 |
| Finished | Jul 12 07:35:14 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-d4241850-3555-4307-9c69-3076be9c3216 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553928913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.553928913 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.1357857096 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 193632523 ps |
| CPU time | 8.19 seconds |
| Started | Jul 12 07:34:14 PM PDT 24 |
| Finished | Jul 12 07:34:26 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-d03798a5-80d7-4024-8619-2c4ad85fe5f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357857096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.1357857096 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.3285523684 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 8209416848 ps |
| CPU time | 88.48 seconds |
| Started | Jul 12 07:34:23 PM PDT 24 |
| Finished | Jul 12 07:35:55 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-7e4ab31f-c99d-4b3f-854b-dcfd7aa912c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285523684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.3285523684 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.526188146 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 3600837214 ps |
| CPU time | 61.7 seconds |
| Started | Jul 12 07:34:22 PM PDT 24 |
| Finished | Jul 12 07:35:26 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-623c9f91-f41e-4f39-9570-db0541c0af5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526188146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.526188146 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.1338855869 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 53045667 ps |
| CPU time | 6.61 seconds |
| Started | Jul 12 07:34:19 PM PDT 24 |
| Finished | Jul 12 07:34:29 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-6c31ed77-cff7-4163-b82f-95d1763cf5a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338855869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delay s.1338855869 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.2415893785 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 136857495 ps |
| CPU time | 12.03 seconds |
| Started | Jul 12 07:34:22 PM PDT 24 |
| Finished | Jul 12 07:34:37 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-ea3d21fb-6298-410f-97b6-e6e4e8458acb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415893785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.2415893785 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.1907159474 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 13056760734 ps |
| CPU time | 408.53 seconds |
| Started | Jul 12 07:34:19 PM PDT 24 |
| Finished | Jul 12 07:41:11 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-5a07d5b9-67f6-465e-a63a-87a0e0cb9922 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907159474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.1907159474 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.984613072 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 102743374 ps |
| CPU time | 11.03 seconds |
| Started | Jul 12 07:34:26 PM PDT 24 |
| Finished | Jul 12 07:34:39 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-b8975d1c-ba69-4875-b0f5-5b855ed054e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984613072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_ with_rand_reset.984613072 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.1007308482 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 187263711 ps |
| CPU time | 50.21 seconds |
| Started | Jul 12 07:34:17 PM PDT 24 |
| Finished | Jul 12 07:35:11 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-c7791ace-a44a-4d53-81b3-1653d69a8160 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007308482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al l_with_reset_error.1007308482 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.1011033966 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 71966282 ps |
| CPU time | 12.05 seconds |
| Started | Jul 12 07:34:19 PM PDT 24 |
| Finished | Jul 12 07:34:34 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-5192eaad-22f4-421f-a7ab-c97abd335356 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011033966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.1011033966 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.3516793476 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 390464312 ps |
| CPU time | 28.17 seconds |
| Started | Jul 12 07:34:41 PM PDT 24 |
| Finished | Jul 12 07:35:12 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-ad26246a-cc69-4617-b8e6-a74366c56ca9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516793476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .3516793476 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.3218733180 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 98507126640 ps |
| CPU time | 1707.89 seconds |
| Started | Jul 12 07:34:41 PM PDT 24 |
| Finished | Jul 12 08:03:13 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-8c2c8e78-177f-4b57-abe1-7f50a9c63d1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218733180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.3218733180 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.2684784191 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 165092402 ps |
| CPU time | 19.84 seconds |
| Started | Jul 12 07:34:29 PM PDT 24 |
| Finished | Jul 12 07:34:50 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-4a0094d3-4af6-462a-8ffe-94819eac9190 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684784191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.2684784191 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.2011413785 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 1800040206 ps |
| CPU time | 62.47 seconds |
| Started | Jul 12 07:34:32 PM PDT 24 |
| Finished | Jul 12 07:35:37 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-c0bd72b7-82ee-4553-8a0d-c7a7371263fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011413785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.2011413785 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.1815875912 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 1498067796 ps |
| CPU time | 50.67 seconds |
| Started | Jul 12 07:34:24 PM PDT 24 |
| Finished | Jul 12 07:35:18 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-e3133a57-75f7-45ff-8e2c-3ea9d41a8327 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815875912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.1815875912 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.1089338924 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 22566162086 ps |
| CPU time | 234.9 seconds |
| Started | Jul 12 07:34:29 PM PDT 24 |
| Finished | Jul 12 07:38:26 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-3637edf3-6905-4ac3-b51a-58dba4f5fc69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089338924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.1089338924 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.3122475920 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 28959585740 ps |
| CPU time | 519.73 seconds |
| Started | Jul 12 07:34:31 PM PDT 24 |
| Finished | Jul 12 07:43:14 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-0571643c-9cc5-4606-aca9-a2daf10bb3ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122475920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.3122475920 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.3772011256 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 172312853 ps |
| CPU time | 17.29 seconds |
| Started | Jul 12 07:34:32 PM PDT 24 |
| Finished | Jul 12 07:34:53 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-dada09bc-1cbe-4e98-aa9b-500c8cf661b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772011256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.3772011256 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.798629301 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 256366660 ps |
| CPU time | 10.36 seconds |
| Started | Jul 12 07:34:32 PM PDT 24 |
| Finished | Jul 12 07:34:46 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-e31c9014-2374-477d-853a-b7618b46e6e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798629301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.798629301 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.2461964120 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 43822567 ps |
| CPU time | 6.04 seconds |
| Started | Jul 12 07:34:17 PM PDT 24 |
| Finished | Jul 12 07:34:27 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-87386f1a-bca1-4c34-abc1-474b58f0147e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461964120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.2461964120 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.1618284335 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 8176804015 ps |
| CPU time | 88.44 seconds |
| Started | Jul 12 07:34:18 PM PDT 24 |
| Finished | Jul 12 07:35:50 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-3bee6866-b66c-4419-811b-716882245f86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618284335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.1618284335 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.2929325143 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 6324561721 ps |
| CPU time | 107.13 seconds |
| Started | Jul 12 07:34:25 PM PDT 24 |
| Finished | Jul 12 07:36:15 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-00a5b718-64eb-4a3f-b86a-2c2c81511551 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929325143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.2929325143 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.367443651 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 47385039 ps |
| CPU time | 6.27 seconds |
| Started | Jul 12 07:34:25 PM PDT 24 |
| Finished | Jul 12 07:34:34 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-9998dc0d-2514-4cba-a254-f2ac62acdcd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367443651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delays .367443651 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.1306638422 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 5225482655 ps |
| CPU time | 161.88 seconds |
| Started | Jul 12 07:34:31 PM PDT 24 |
| Finished | Jul 12 07:37:16 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-5d34ae5f-64fb-4153-bca5-73db80b1ff4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306638422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.1306638422 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.3270042796 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 355906795 ps |
| CPU time | 18.06 seconds |
| Started | Jul 12 07:34:30 PM PDT 24 |
| Finished | Jul 12 07:34:50 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-7513cab2-8ab6-400d-a2e9-a814e0d1230b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270042796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.3270042796 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.2917646018 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 9228014111 ps |
| CPU time | 445.89 seconds |
| Started | Jul 12 07:34:28 PM PDT 24 |
| Finished | Jul 12 07:41:55 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-02482863-199f-4eba-bcda-b75a840c121d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917646018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.2917646018 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.3299320402 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 163412918 ps |
| CPU time | 74.46 seconds |
| Started | Jul 12 07:34:29 PM PDT 24 |
| Finished | Jul 12 07:35:46 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-707de990-3252-448c-8876-d19a92016ac3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299320402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.3299320402 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.1122925103 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 256347700 ps |
| CPU time | 29.91 seconds |
| Started | Jul 12 07:34:41 PM PDT 24 |
| Finished | Jul 12 07:35:15 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-c252c0ec-3462-4a00-948a-1a6b03a6b3d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122925103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.1122925103 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.634637527 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 324176665 ps |
| CPU time | 16.72 seconds |
| Started | Jul 12 07:34:29 PM PDT 24 |
| Finished | Jul 12 07:34:48 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-b0f40f5c-2559-4b1a-b970-3bf0dc59e0e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634637527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device. 634637527 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.4007152630 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 39770790189 ps |
| CPU time | 711.31 seconds |
| Started | Jul 12 07:34:32 PM PDT 24 |
| Finished | Jul 12 07:46:27 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-0acce9ef-9c03-4c97-ace0-f8b64243f338 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007152630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.4007152630 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.844414663 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 140783259 ps |
| CPU time | 9.13 seconds |
| Started | Jul 12 07:34:39 PM PDT 24 |
| Finished | Jul 12 07:34:50 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-9a12e45f-a257-4ed5-9cbf-147e4a7d2ebe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844414663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_addr .844414663 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.1033389132 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 977757798 ps |
| CPU time | 32.04 seconds |
| Started | Jul 12 07:34:31 PM PDT 24 |
| Finished | Jul 12 07:35:06 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-06a1dbaf-d7f7-4f37-8140-970c9eb3fd19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033389132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.1033389132 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.2094709890 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 495224268 ps |
| CPU time | 19.11 seconds |
| Started | Jul 12 07:34:32 PM PDT 24 |
| Finished | Jul 12 07:34:54 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-3b165ca1-5586-4be1-929e-cf2546feccde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094709890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.2094709890 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.247844778 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 120884814576 ps |
| CPU time | 1371.59 seconds |
| Started | Jul 12 07:34:32 PM PDT 24 |
| Finished | Jul 12 07:57:27 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-ff2b0d5e-cce9-4009-86cb-3d2f07fc08ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247844778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.247844778 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.2807361692 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 21544357332 ps |
| CPU time | 377.54 seconds |
| Started | Jul 12 07:34:31 PM PDT 24 |
| Finished | Jul 12 07:40:51 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-40159bae-6841-4a5a-98dd-b002b6b48476 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807361692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.2807361692 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.2376117145 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 249596732 ps |
| CPU time | 23.41 seconds |
| Started | Jul 12 07:34:32 PM PDT 24 |
| Finished | Jul 12 07:34:59 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-ebc323e0-c2bb-4925-ba2f-1c884f217b5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376117145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del ays.2376117145 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.2549963747 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 269574871 ps |
| CPU time | 19.66 seconds |
| Started | Jul 12 07:34:29 PM PDT 24 |
| Finished | Jul 12 07:34:51 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-bf3ece9a-e73d-488e-b6c5-632062c59a24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549963747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.2549963747 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.2435360865 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 193233900 ps |
| CPU time | 9.13 seconds |
| Started | Jul 12 07:34:29 PM PDT 24 |
| Finished | Jul 12 07:34:41 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-119dd7c7-9828-466b-9d00-82ebd70f4ab6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435360865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.2435360865 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.2663183736 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 8869255845 ps |
| CPU time | 101.61 seconds |
| Started | Jul 12 07:34:33 PM PDT 24 |
| Finished | Jul 12 07:36:18 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-088edc7a-4235-448f-a6b2-831212690159 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663183736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.2663183736 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.2852206480 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 4740828659 ps |
| CPU time | 83.79 seconds |
| Started | Jul 12 07:34:32 PM PDT 24 |
| Finished | Jul 12 07:35:58 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-067c2d2e-0262-4fce-9fa0-c93f697fd688 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852206480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.2852206480 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.523845144 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 48232177 ps |
| CPU time | 6.41 seconds |
| Started | Jul 12 07:34:31 PM PDT 24 |
| Finished | Jul 12 07:34:40 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-635f4588-73f0-4c12-90c1-2bb2065b95d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523845144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delays .523845144 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.125051660 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 7699623675 ps |
| CPU time | 296.49 seconds |
| Started | Jul 12 07:34:41 PM PDT 24 |
| Finished | Jul 12 07:39:41 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-8a0331a8-53cf-4bdc-a62d-eeecddb689b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125051660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.125051660 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.1929353746 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 8177278488 ps |
| CPU time | 273.57 seconds |
| Started | Jul 12 07:34:41 PM PDT 24 |
| Finished | Jul 12 07:39:18 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-9fa66e2c-efcf-440c-9d49-e5bef78e9c12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929353746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.1929353746 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.735083243 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 2197479073 ps |
| CPU time | 184.13 seconds |
| Started | Jul 12 07:34:43 PM PDT 24 |
| Finished | Jul 12 07:37:51 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-979bd97a-a12f-4e83-bc67-ec5b8e96502c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735083243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_ with_rand_reset.735083243 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.2671116344 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 2054684860 ps |
| CPU time | 113.77 seconds |
| Started | Jul 12 07:34:41 PM PDT 24 |
| Finished | Jul 12 07:36:38 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-5892ed40-831b-4194-b65f-80135c4abf1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671116344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.2671116344 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.764141673 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 194675952 ps |
| CPU time | 23.23 seconds |
| Started | Jul 12 07:34:40 PM PDT 24 |
| Finished | Jul 12 07:35:06 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-970a9faa-5b60-4a62-9a8f-2aa8447c45c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764141673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.764141673 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.2647890230 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 987305231 ps |
| CPU time | 42.65 seconds |
| Started | Jul 12 07:34:44 PM PDT 24 |
| Finished | Jul 12 07:35:30 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-58c32352-62b3-4a4a-889c-aa2e07ec792e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647890230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device .2647890230 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.3174571018 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 765994750 ps |
| CPU time | 32.49 seconds |
| Started | Jul 12 07:34:39 PM PDT 24 |
| Finished | Jul 12 07:35:13 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-0e2d5008-184a-46b4-a33a-7d218c15a359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174571018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add r.3174571018 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.1171637338 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 151151946 ps |
| CPU time | 8.66 seconds |
| Started | Jul 12 07:34:41 PM PDT 24 |
| Finished | Jul 12 07:34:54 PM PDT 24 |
| Peak memory | 573996 kb |
| Host | smart-76c18b9e-e614-4b64-924e-a91dcfd6b7cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171637338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.1171637338 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.2017803850 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 1049276155 ps |
| CPU time | 40.46 seconds |
| Started | Jul 12 07:34:46 PM PDT 24 |
| Finished | Jul 12 07:35:31 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-812968a3-97cf-4336-a154-68ac1692658c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017803850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.2017803850 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.2420073363 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 17813711450 ps |
| CPU time | 177.62 seconds |
| Started | Jul 12 07:34:43 PM PDT 24 |
| Finished | Jul 12 07:37:44 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-bf59e718-09f3-4dfd-bf66-14d15f593e0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420073363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.2420073363 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.3354606236 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 38144526777 ps |
| CPU time | 716.46 seconds |
| Started | Jul 12 07:34:41 PM PDT 24 |
| Finished | Jul 12 07:46:42 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-1003ed46-71ac-4fc3-8449-7a729693c6a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354606236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.3354606236 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.3188345745 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 306411784 ps |
| CPU time | 26.91 seconds |
| Started | Jul 12 07:34:39 PM PDT 24 |
| Finished | Jul 12 07:35:09 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-12ecd53b-7297-4056-8a4f-df72aa5fc711 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188345745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del ays.3188345745 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.3003415704 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 1733262432 ps |
| CPU time | 53.65 seconds |
| Started | Jul 12 07:34:39 PM PDT 24 |
| Finished | Jul 12 07:35:35 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-09862a51-e2f9-4488-ae3c-f1407fa41084 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003415704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.3003415704 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.3745450676 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 39228720 ps |
| CPU time | 6.29 seconds |
| Started | Jul 12 07:34:48 PM PDT 24 |
| Finished | Jul 12 07:34:57 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-ffa97442-de7a-4d23-96fb-b9672b9be31a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745450676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.3745450676 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.3458616171 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 8179413110 ps |
| CPU time | 90.12 seconds |
| Started | Jul 12 07:34:39 PM PDT 24 |
| Finished | Jul 12 07:36:12 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-6c0aa1f0-0aa5-4124-9d35-386b2c7302de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458616171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.3458616171 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.4229857805 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 5438417514 ps |
| CPU time | 99.35 seconds |
| Started | Jul 12 07:34:40 PM PDT 24 |
| Finished | Jul 12 07:36:22 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-2f1a48e9-04d8-4e4d-9738-f13851893425 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229857805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.4229857805 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.3489314769 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 41720063 ps |
| CPU time | 5.79 seconds |
| Started | Jul 12 07:34:39 PM PDT 24 |
| Finished | Jul 12 07:34:47 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-a7f699d5-dd16-4486-bb11-6a94d2b1c2ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489314769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay s.3489314769 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.3915568902 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 65455412 ps |
| CPU time | 9.78 seconds |
| Started | Jul 12 07:34:53 PM PDT 24 |
| Finished | Jul 12 07:35:05 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-f4d6a488-832c-4330-94f9-029fdac65814 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915568902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.3915568902 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.759854374 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 5994939805 ps |
| CPU time | 206.8 seconds |
| Started | Jul 12 07:35:00 PM PDT 24 |
| Finished | Jul 12 07:38:32 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-0989e2f7-c9a7-4f59-9c8a-1c5ed0387055 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759854374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.759854374 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.401270443 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 4954327089 ps |
| CPU time | 253.15 seconds |
| Started | Jul 12 07:34:54 PM PDT 24 |
| Finished | Jul 12 07:39:10 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-0c3b59f9-2afc-4e72-856f-9207ad8fd54b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401270443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_ with_rand_reset.401270443 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.364569072 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 727288368 ps |
| CPU time | 170.23 seconds |
| Started | Jul 12 07:34:57 PM PDT 24 |
| Finished | Jul 12 07:37:49 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-92f6d986-d450-441f-b499-c7677ff0d206 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364569072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_reset_error.364569072 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.1294605607 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 142068618 ps |
| CPU time | 8.98 seconds |
| Started | Jul 12 07:34:42 PM PDT 24 |
| Finished | Jul 12 07:34:55 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-b2f732a2-56ae-49a4-8b50-fe4031ea6f0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294605607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.1294605607 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.4267438826 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 3836816150 ps |
| CPU time | 241.71 seconds |
| Started | Jul 12 07:24:55 PM PDT 24 |
| Finished | Jul 12 07:29:00 PM PDT 24 |
| Peak memory | 599348 kb |
| Host | smart-3685b540-98f6-486f-a6dc-22a6751e7e6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267438826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.4267438826 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.3498564979 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 30926633086 ps |
| CPU time | 5328.05 seconds |
| Started | Jul 12 07:24:20 PM PDT 24 |
| Finished | Jul 12 08:53:10 PM PDT 24 |
| Peak memory | 593500 kb |
| Host | smart-54889836-a79b-4c44-8d10-2ad92a7371eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498564979 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.3498564979 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.3014756053 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 551115511 ps |
| CPU time | 36.41 seconds |
| Started | Jul 12 07:24:33 PM PDT 24 |
| Finished | Jul 12 07:25:12 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-2b175acf-ec1b-407e-b8be-c72736bc850e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014756053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device. 3014756053 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.1228860069 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 58435115158 ps |
| CPU time | 1007.13 seconds |
| Started | Jul 12 07:24:36 PM PDT 24 |
| Finished | Jul 12 07:41:26 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-14ee5ab1-b932-49ac-8e3e-1904cda6b8c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228860069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d evice_slow_rsp.1228860069 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.1563933459 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 844930352 ps |
| CPU time | 34.63 seconds |
| Started | Jul 12 07:24:33 PM PDT 24 |
| Finished | Jul 12 07:25:10 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-be2e008a-227d-48de-9010-0f7df4c45d98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563933459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .1563933459 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.1733618339 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 423822773 ps |
| CPU time | 17.79 seconds |
| Started | Jul 12 07:24:34 PM PDT 24 |
| Finished | Jul 12 07:24:54 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-57314e01-56a5-468b-88ba-60f3b0114540 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733618339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1733618339 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.1364384724 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 133554888 ps |
| CPU time | 13.71 seconds |
| Started | Jul 12 07:24:33 PM PDT 24 |
| Finished | Jul 12 07:24:49 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-0f4172a5-a6f5-4c00-8456-b2d16c4c384d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364384724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.1364384724 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.1261969890 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 18300255390 ps |
| CPU time | 210.31 seconds |
| Started | Jul 12 07:24:35 PM PDT 24 |
| Finished | Jul 12 07:28:09 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-94fa5a14-8c27-49ac-8046-cfc9ad7f11d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261969890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1261969890 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.2954763215 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 49015459890 ps |
| CPU time | 821.47 seconds |
| Started | Jul 12 07:24:32 PM PDT 24 |
| Finished | Jul 12 07:38:15 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-dc3f63b9-4368-470f-bffd-a93b1a3a9e69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954763215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2954763215 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.1636921116 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 545162092 ps |
| CPU time | 49.86 seconds |
| Started | Jul 12 07:24:36 PM PDT 24 |
| Finished | Jul 12 07:25:29 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-3f500e53-c627-4d34-a2b4-fa46d8e2f7f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636921116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela ys.1636921116 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.3791374436 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 523956644 ps |
| CPU time | 17.54 seconds |
| Started | Jul 12 07:24:37 PM PDT 24 |
| Finished | Jul 12 07:24:57 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-0b9738e1-180c-4e11-8606-af69bb73b466 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791374436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3791374436 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.403445568 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 41973404 ps |
| CPU time | 6.12 seconds |
| Started | Jul 12 07:24:18 PM PDT 24 |
| Finished | Jul 12 07:24:25 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-4732c25f-a33f-4597-a517-4e4cf0e19be2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403445568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.403445568 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.2956396886 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 9163956494 ps |
| CPU time | 95.31 seconds |
| Started | Jul 12 07:24:35 PM PDT 24 |
| Finished | Jul 12 07:26:13 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-fe604582-03c7-4808-bc46-dc1a8c8c45f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956396886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2956396886 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.1770528516 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 6367190674 ps |
| CPU time | 114.21 seconds |
| Started | Jul 12 07:24:34 PM PDT 24 |
| Finished | Jul 12 07:26:30 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-a8deb187-6bb9-4229-8f6a-b12cf3951eb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770528516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1770528516 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.923524437 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 43107364 ps |
| CPU time | 5.96 seconds |
| Started | Jul 12 07:24:18 PM PDT 24 |
| Finished | Jul 12 07:24:25 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-a464a905-be43-41f3-b899-66eea0d60090 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923524437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays. 923524437 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.1958066007 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 12134723078 ps |
| CPU time | 439.62 seconds |
| Started | Jul 12 07:24:32 PM PDT 24 |
| Finished | Jul 12 07:31:54 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-b60841df-cfca-4524-b865-f04ba678a927 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958066007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1958066007 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.2681941669 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 2704150702 ps |
| CPU time | 112.27 seconds |
| Started | Jul 12 07:24:33 PM PDT 24 |
| Finished | Jul 12 07:26:27 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-0a39039f-0cbd-4423-b9eb-e8b858e3b58d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681941669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2681941669 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.3570827619 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 8116070 ps |
| CPU time | 30.42 seconds |
| Started | Jul 12 07:24:31 PM PDT 24 |
| Finished | Jul 12 07:25:03 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-63e7388c-b7a5-4f2f-bcf2-ccce99f5dba6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570827619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_rand_reset.3570827619 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.451996697 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 374733524 ps |
| CPU time | 109.26 seconds |
| Started | Jul 12 07:24:56 PM PDT 24 |
| Finished | Jul 12 07:26:49 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-721849ac-ed81-4819-8dee-e4791f52348b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451996697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_reset_error.451996697 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.1883036671 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 1006500061 ps |
| CPU time | 47.65 seconds |
| Started | Jul 12 07:24:33 PM PDT 24 |
| Finished | Jul 12 07:25:23 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-a79f835f-2397-46dd-a33d-ce37016f8880 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883036671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1883036671 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.4245333420 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 987839208 ps |
| CPU time | 76.65 seconds |
| Started | Jul 12 07:34:58 PM PDT 24 |
| Finished | Jul 12 07:36:17 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-97fc85a2-3366-4211-b6c3-684f375f8a28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245333420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .4245333420 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.2188998309 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 13576487255 ps |
| CPU time | 241.2 seconds |
| Started | Jul 12 07:34:59 PM PDT 24 |
| Finished | Jul 12 07:39:05 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-70765b34-035b-4cf2-9216-07468a1e0ed2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188998309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.2188998309 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.1497909191 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 402430929 ps |
| CPU time | 17.02 seconds |
| Started | Jul 12 07:34:53 PM PDT 24 |
| Finished | Jul 12 07:35:12 PM PDT 24 |
| Peak memory | 575192 kb |
| Host | smart-49b7189e-a5c8-4170-8a6c-d33edc9532af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497909191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add r.1497909191 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.2554943776 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 317422285 ps |
| CPU time | 26.61 seconds |
| Started | Jul 12 07:34:56 PM PDT 24 |
| Finished | Jul 12 07:35:25 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-c70f7cf6-a223-4e49-981d-cc44a5c32b9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554943776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.2554943776 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.2319441965 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 155379259 ps |
| CPU time | 15.38 seconds |
| Started | Jul 12 07:34:53 PM PDT 24 |
| Finished | Jul 12 07:35:11 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-76fe3795-a4b9-4e9a-8e22-37e2bc23fb56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319441965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.2319441965 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.3101611537 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 14169706165 ps |
| CPU time | 249.49 seconds |
| Started | Jul 12 07:34:58 PM PDT 24 |
| Finished | Jul 12 07:39:10 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-d322d9b6-9999-48c3-b709-3fe6828c0f1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101611537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.3101611537 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.4062924804 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 158263030 ps |
| CPU time | 14.85 seconds |
| Started | Jul 12 07:34:53 PM PDT 24 |
| Finished | Jul 12 07:35:10 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-2a9ec3cf-af2f-4e88-9a3a-d9c9d0389f83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062924804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del ays.4062924804 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.2018988532 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 216197298 ps |
| CPU time | 9.74 seconds |
| Started | Jul 12 07:34:55 PM PDT 24 |
| Finished | Jul 12 07:35:07 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-69c58586-0a1b-4766-8d4b-977a00e65bc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018988532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.2018988532 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.143608182 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 244451055 ps |
| CPU time | 8.99 seconds |
| Started | Jul 12 07:34:57 PM PDT 24 |
| Finished | Jul 12 07:35:09 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-0114596f-c65d-416c-b412-02fa27ad95a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143608182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.143608182 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.1026048257 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 8044208525 ps |
| CPU time | 88.7 seconds |
| Started | Jul 12 07:36:38 PM PDT 24 |
| Finished | Jul 12 07:38:08 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-0608c877-cbcb-466b-8700-6252b7b220aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026048257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.1026048257 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.3700314925 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 3291433948 ps |
| CPU time | 56.38 seconds |
| Started | Jul 12 07:34:54 PM PDT 24 |
| Finished | Jul 12 07:35:53 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-9ce39f12-b10e-4757-ae4c-6e5530bc0398 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700314925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.3700314925 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.3038520541 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 42305526 ps |
| CPU time | 6.21 seconds |
| Started | Jul 12 07:35:00 PM PDT 24 |
| Finished | Jul 12 07:35:11 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-7d573dd7-24cd-4e34-9b4e-c96ec189ae47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038520541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay s.3038520541 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.1184929563 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 2126248887 ps |
| CPU time | 154.59 seconds |
| Started | Jul 12 07:34:57 PM PDT 24 |
| Finished | Jul 12 07:37:34 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-6419e690-c865-4d76-82af-05b3ccb79b91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184929563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.1184929563 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.603532163 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 4237964818 ps |
| CPU time | 144.09 seconds |
| Started | Jul 12 07:34:55 PM PDT 24 |
| Finished | Jul 12 07:37:21 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-ff78f7d2-d01e-4471-88e8-d96937d7ee25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603532163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.603532163 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.2462814229 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 15745189055 ps |
| CPU time | 843.02 seconds |
| Started | Jul 12 07:34:57 PM PDT 24 |
| Finished | Jul 12 07:49:03 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-6026d0f8-a94f-47aa-b742-327a80aecd99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462814229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.2462814229 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.183488496 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 10286562016 ps |
| CPU time | 562.69 seconds |
| Started | Jul 12 07:35:15 PM PDT 24 |
| Finished | Jul 12 07:44:44 PM PDT 24 |
| Peak memory | 577004 kb |
| Host | smart-ab6ddbbe-1ad1-4ddf-b33d-9066ccf2a52b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183488496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_reset_error.183488496 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.4243209050 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 293081291 ps |
| CPU time | 34.69 seconds |
| Started | Jul 12 07:34:57 PM PDT 24 |
| Finished | Jul 12 07:35:34 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-f42f6321-d078-41fa-a848-6ec5e7ca9426 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243209050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.4243209050 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.1526295653 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 440182696 ps |
| CPU time | 19.84 seconds |
| Started | Jul 12 07:35:15 PM PDT 24 |
| Finished | Jul 12 07:35:41 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-e2de9a08-caf5-444b-807a-3d09f751412d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526295653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .1526295653 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.3553611434 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 58084732094 ps |
| CPU time | 1052.58 seconds |
| Started | Jul 12 07:35:15 PM PDT 24 |
| Finished | Jul 12 07:52:54 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-219d8064-f10d-4faa-8abb-6fb2d48c8eff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553611434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.3553611434 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.815691425 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 277515601 ps |
| CPU time | 29.47 seconds |
| Started | Jul 12 07:35:13 PM PDT 24 |
| Finished | Jul 12 07:35:50 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-b821c65a-1f06-4c3c-b389-54d6aff4cef4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815691425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_addr .815691425 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.3170643556 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 317702350 ps |
| CPU time | 25.05 seconds |
| Started | Jul 12 07:35:12 PM PDT 24 |
| Finished | Jul 12 07:35:43 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-321cd716-63c2-4b49-8d5a-15409ea60497 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170643556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.3170643556 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.1229444 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 172032407 ps |
| CPU time | 9.18 seconds |
| Started | Jul 12 07:35:13 PM PDT 24 |
| Finished | Jul 12 07:35:28 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-6b723b29-10d4-487d-a9a7-433a0c6da38f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.1229444 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.4220206476 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 57895878070 ps |
| CPU time | 661.28 seconds |
| Started | Jul 12 07:35:13 PM PDT 24 |
| Finished | Jul 12 07:46:21 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-28a91881-9f60-4132-af28-238bfeaccfa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220206476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.4220206476 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.2937760572 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 26079468105 ps |
| CPU time | 497.99 seconds |
| Started | Jul 12 07:35:12 PM PDT 24 |
| Finished | Jul 12 07:43:37 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-3ed65c5d-6c3b-4d26-bba0-03894d3e0d9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937760572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.2937760572 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.1392761197 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 252955466 ps |
| CPU time | 22.32 seconds |
| Started | Jul 12 07:35:12 PM PDT 24 |
| Finished | Jul 12 07:35:41 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-ed0a6e3d-d49c-4c01-b72a-5c845d23b261 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392761197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.1392761197 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.2956811850 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 151899201 ps |
| CPU time | 13.53 seconds |
| Started | Jul 12 07:35:13 PM PDT 24 |
| Finished | Jul 12 07:35:33 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-5d9aea8f-d1e0-4402-aeb4-591cbe06222d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956811850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.2956811850 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.733720295 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 32924455 ps |
| CPU time | 5.91 seconds |
| Started | Jul 12 07:35:11 PM PDT 24 |
| Finished | Jul 12 07:35:21 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-1c197863-7b85-4d2d-b87a-691161770223 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733720295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.733720295 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.1651977768 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 8147425542 ps |
| CPU time | 88.56 seconds |
| Started | Jul 12 07:35:14 PM PDT 24 |
| Finished | Jul 12 07:36:49 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-fdb7c09e-a4e2-4d95-8300-025ba7e10a42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651977768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.1651977768 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.2423205872 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 6992303146 ps |
| CPU time | 118.32 seconds |
| Started | Jul 12 07:35:11 PM PDT 24 |
| Finished | Jul 12 07:37:13 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-0aa83c83-aaab-46af-a436-b222a4e268b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423205872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.2423205872 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.3474437796 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 41826931 ps |
| CPU time | 6.26 seconds |
| Started | Jul 12 07:35:13 PM PDT 24 |
| Finished | Jul 12 07:35:25 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-9c4a2934-7cd1-4465-98a2-085fbba4e95c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474437796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.3474437796 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.562776569 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 1937904895 ps |
| CPU time | 146.31 seconds |
| Started | Jul 12 07:35:12 PM PDT 24 |
| Finished | Jul 12 07:37:45 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-1b59bc2c-8ac2-4b74-86f8-5c2b3de2c5a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562776569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.562776569 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.74806566 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 1759358742 ps |
| CPU time | 91.08 seconds |
| Started | Jul 12 07:35:12 PM PDT 24 |
| Finished | Jul 12 07:36:48 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-68659524-6b12-478b-8c2a-67d7955d46b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74806566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.74806566 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.1868253258 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2882315964 ps |
| CPU time | 395.82 seconds |
| Started | Jul 12 07:35:13 PM PDT 24 |
| Finished | Jul 12 07:41:55 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-fd46ff49-011d-458d-b7e5-b3bfb53008a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868253258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.1868253258 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.132526957 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 38308094 ps |
| CPU time | 23.04 seconds |
| Started | Jul 12 07:35:12 PM PDT 24 |
| Finished | Jul 12 07:35:41 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-b9796ae2-7f34-4588-8497-b8de673e1f3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132526957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_reset_error.132526957 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.2481047115 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 46258559 ps |
| CPU time | 9.03 seconds |
| Started | Jul 12 07:35:12 PM PDT 24 |
| Finished | Jul 12 07:35:27 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-4b16d8ea-6685-4037-baa9-01c4d873e053 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481047115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.2481047115 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.2826024188 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 614759908 ps |
| CPU time | 42.3 seconds |
| Started | Jul 12 07:35:37 PM PDT 24 |
| Finished | Jul 12 07:36:23 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-895693fb-b6c6-4a7e-9fd7-02b0910c4673 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826024188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device .2826024188 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.3583026645 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 65908957400 ps |
| CPU time | 1177.15 seconds |
| Started | Jul 12 07:35:31 PM PDT 24 |
| Finished | Jul 12 07:55:12 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-0ead65ad-475a-488e-ac24-d62008c60e82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583026645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.3583026645 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.1740149034 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 251679468 ps |
| CPU time | 27.9 seconds |
| Started | Jul 12 07:35:25 PM PDT 24 |
| Finished | Jul 12 07:35:58 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-8779124d-62c5-48bc-bf89-a3f17fc9a581 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740149034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.1740149034 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.657779250 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 2165592684 ps |
| CPU time | 77.01 seconds |
| Started | Jul 12 07:35:33 PM PDT 24 |
| Finished | Jul 12 07:36:54 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-baf776f4-9f38-421d-afc6-258bd32f504a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657779250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.657779250 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.1781696366 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 254197855 ps |
| CPU time | 23.04 seconds |
| Started | Jul 12 07:35:14 PM PDT 24 |
| Finished | Jul 12 07:35:43 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-fcfb804a-25ba-4613-b64d-737c5c71d06b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781696366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.1781696366 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.364915027 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 15914711296 ps |
| CPU time | 172.7 seconds |
| Started | Jul 12 07:35:15 PM PDT 24 |
| Finished | Jul 12 07:38:14 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-f9d09727-e1cd-45d2-887e-09d951467200 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364915027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.364915027 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.2222325290 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 17741067876 ps |
| CPU time | 320.76 seconds |
| Started | Jul 12 07:35:28 PM PDT 24 |
| Finished | Jul 12 07:40:53 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-adff40fc-dbac-48df-a65f-096c47e21796 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222325290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.2222325290 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.675005814 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 37405218 ps |
| CPU time | 6.18 seconds |
| Started | Jul 12 07:35:12 PM PDT 24 |
| Finished | Jul 12 07:35:24 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-26f06c34-d3bf-4d1c-b8a3-7ca830849702 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675005814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_dela ys.675005814 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.1126452815 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 2411446032 ps |
| CPU time | 67.28 seconds |
| Started | Jul 12 07:35:33 PM PDT 24 |
| Finished | Jul 12 07:36:45 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-79040687-6090-4b97-9fa5-1927673f70f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126452815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.1126452815 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.1647284873 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 42521480 ps |
| CPU time | 5.6 seconds |
| Started | Jul 12 07:35:12 PM PDT 24 |
| Finished | Jul 12 07:35:22 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-ef2ae43a-4567-460e-a685-aa1e4e31a9ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647284873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.1647284873 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.699304094 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 6848488757 ps |
| CPU time | 80.33 seconds |
| Started | Jul 12 07:35:13 PM PDT 24 |
| Finished | Jul 12 07:36:40 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-18266880-18c3-4c19-b833-71a170b8ab93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699304094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.699304094 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.2177094203 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 5995771213 ps |
| CPU time | 106.7 seconds |
| Started | Jul 12 07:35:13 PM PDT 24 |
| Finished | Jul 12 07:37:07 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-205abe0e-0404-4e2e-92b6-420263a01f85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177094203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.2177094203 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.1056736081 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 45735658 ps |
| CPU time | 6.35 seconds |
| Started | Jul 12 07:35:16 PM PDT 24 |
| Finished | Jul 12 07:35:28 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-be8977d8-acfb-415e-809d-b539d5154fb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056736081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay s.1056736081 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.3346300181 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 10375896443 ps |
| CPU time | 402.89 seconds |
| Started | Jul 12 07:35:33 PM PDT 24 |
| Finished | Jul 12 07:42:20 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-57fa3339-36c3-4620-bc58-17bef164fcde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346300181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.3346300181 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.792402487 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 8330009088 ps |
| CPU time | 259.04 seconds |
| Started | Jul 12 07:35:34 PM PDT 24 |
| Finished | Jul 12 07:39:57 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-29966b38-4c56-4f12-a266-eed14bc24a04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792402487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.792402487 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.1643262752 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 524099099 ps |
| CPU time | 113.49 seconds |
| Started | Jul 12 07:35:32 PM PDT 24 |
| Finished | Jul 12 07:37:30 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-135e2797-cfdc-42eb-89cd-989f05e76978 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643262752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.1643262752 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.1543198785 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 6349002957 ps |
| CPU time | 350.75 seconds |
| Started | Jul 12 07:35:25 PM PDT 24 |
| Finished | Jul 12 07:41:20 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-f3a381ba-f444-4c85-9d7a-39dad3007222 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543198785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.1543198785 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.3806642901 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 1126465781 ps |
| CPU time | 46.73 seconds |
| Started | Jul 12 07:35:37 PM PDT 24 |
| Finished | Jul 12 07:36:28 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-f1b5f163-9c3c-44d4-a8c9-e568f565c831 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806642901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.3806642901 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.2735646070 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 424061799 ps |
| CPU time | 20.56 seconds |
| Started | Jul 12 07:35:31 PM PDT 24 |
| Finished | Jul 12 07:35:56 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-cba5f36f-8628-4604-b293-4710440cebaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735646070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device .2735646070 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.3400417432 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 57512830768 ps |
| CPU time | 961.84 seconds |
| Started | Jul 12 07:35:24 PM PDT 24 |
| Finished | Jul 12 07:51:31 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-2163a083-b3e5-45ae-a303-97ce2b46c0d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400417432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.3400417432 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.415051973 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 98268821 ps |
| CPU time | 14.18 seconds |
| Started | Jul 12 07:35:24 PM PDT 24 |
| Finished | Jul 12 07:35:42 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-5fe9b5c7-466b-480c-975a-ddd152cfd73e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415051973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_addr .415051973 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.631752100 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 2111001075 ps |
| CPU time | 73.77 seconds |
| Started | Jul 12 07:35:37 PM PDT 24 |
| Finished | Jul 12 07:36:55 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-6b8ae7a8-0357-43dd-bd4f-44a359970df5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631752100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.631752100 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.1220659702 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 227390988 ps |
| CPU time | 22.17 seconds |
| Started | Jul 12 07:35:33 PM PDT 24 |
| Finished | Jul 12 07:36:00 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-5c76a321-12fa-4a70-a8bb-f8909872e16a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220659702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.1220659702 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.1583249353 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 11957676846 ps |
| CPU time | 131.73 seconds |
| Started | Jul 12 07:35:28 PM PDT 24 |
| Finished | Jul 12 07:37:44 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-9bd449aa-a80c-4d7c-9201-669d4d999543 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583249353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.1583249353 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.2032579279 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 61351006553 ps |
| CPU time | 1166.88 seconds |
| Started | Jul 12 07:35:31 PM PDT 24 |
| Finished | Jul 12 07:55:02 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-6c1db95d-eb16-42a5-9fdf-350e128170d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032579279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.2032579279 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.2692508559 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 28979810 ps |
| CPU time | 5.82 seconds |
| Started | Jul 12 07:35:30 PM PDT 24 |
| Finished | Jul 12 07:35:40 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-be7c095e-6a9c-4992-bdbf-5889ef38ee8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692508559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.2692508559 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.3178370855 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 246162729 ps |
| CPU time | 20.32 seconds |
| Started | Jul 12 07:35:32 PM PDT 24 |
| Finished | Jul 12 07:35:56 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-d6ed41d6-1f30-48d7-b3c0-44db74b098c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178370855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.3178370855 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.4116839503 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 44874568 ps |
| CPU time | 6.41 seconds |
| Started | Jul 12 07:35:32 PM PDT 24 |
| Finished | Jul 12 07:35:43 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-2d0c642c-6955-46c1-a60a-79626714d4d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116839503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.4116839503 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.870272027 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 7726121953 ps |
| CPU time | 84.31 seconds |
| Started | Jul 12 07:35:32 PM PDT 24 |
| Finished | Jul 12 07:37:00 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-29ff9def-d627-4350-b077-8a7caa8349ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870272027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.870272027 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.3144823633 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 5106844266 ps |
| CPU time | 89.18 seconds |
| Started | Jul 12 07:35:29 PM PDT 24 |
| Finished | Jul 12 07:37:02 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-0e9ccb51-69d3-4ebf-ba3f-d51a9ea04184 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144823633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.3144823633 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.3224252130 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 42163067 ps |
| CPU time | 5.74 seconds |
| Started | Jul 12 07:35:28 PM PDT 24 |
| Finished | Jul 12 07:35:38 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-525ead94-0462-4c6c-ac3a-ff4de0ab8bdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224252130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay s.3224252130 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.1515330833 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 6603753143 ps |
| CPU time | 279.67 seconds |
| Started | Jul 12 07:35:30 PM PDT 24 |
| Finished | Jul 12 07:40:14 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-3ff61f03-3c31-48a7-9615-c8a43cc5b623 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515330833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.1515330833 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.2186388776 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 4115138318 ps |
| CPU time | 285.73 seconds |
| Started | Jul 12 07:35:31 PM PDT 24 |
| Finished | Jul 12 07:40:20 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-1973c7cf-5123-4ba1-8127-d52936cd0139 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186388776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.2186388776 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.2300810024 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 174265009 ps |
| CPU time | 93.82 seconds |
| Started | Jul 12 07:35:33 PM PDT 24 |
| Finished | Jul 12 07:37:11 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-adaca366-f7c5-4af0-bd45-5bbbb2a04c08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300810024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_rand_reset.2300810024 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.4132268729 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1349692517 ps |
| CPU time | 58.03 seconds |
| Started | Jul 12 07:35:30 PM PDT 24 |
| Finished | Jul 12 07:36:32 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-1192acc3-1616-4c75-8737-c779054e4766 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132268729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.4132268729 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.3809675971 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 738722841 ps |
| CPU time | 56.07 seconds |
| Started | Jul 12 07:35:24 PM PDT 24 |
| Finished | Jul 12 07:36:24 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-bea7b02c-c316-4c2c-bcf9-5b5a930e137d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809675971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .3809675971 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.2108183920 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 27655756043 ps |
| CPU time | 503.02 seconds |
| Started | Jul 12 07:35:31 PM PDT 24 |
| Finished | Jul 12 07:43:58 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-56d87d52-3387-47bf-8cc9-8b134d69d199 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108183920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.2108183920 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.575439188 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 915218011 ps |
| CPU time | 37.39 seconds |
| Started | Jul 12 07:35:40 PM PDT 24 |
| Finished | Jul 12 07:36:21 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-762f2222-223c-4308-bc97-a75a3194c47b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575439188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_addr .575439188 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.3768306794 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 319000726 ps |
| CPU time | 30.04 seconds |
| Started | Jul 12 07:35:49 PM PDT 24 |
| Finished | Jul 12 07:36:23 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-07b130da-0b69-44c5-9189-2fda223262bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768306794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.3768306794 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.2363684644 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 534446580 ps |
| CPU time | 23.26 seconds |
| Started | Jul 12 07:35:26 PM PDT 24 |
| Finished | Jul 12 07:35:54 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-899a547c-df04-40d8-9dec-9c9bee8b5308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363684644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.2363684644 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.921765491 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 16597129643 ps |
| CPU time | 182.49 seconds |
| Started | Jul 12 07:35:29 PM PDT 24 |
| Finished | Jul 12 07:38:35 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-3685ae8e-e324-4c96-a86f-add5dd5a3814 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921765491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.921765491 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.1023074776 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 15420350548 ps |
| CPU time | 253.45 seconds |
| Started | Jul 12 07:35:26 PM PDT 24 |
| Finished | Jul 12 07:39:44 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-6cf01eff-c4f3-4854-b759-d65f9178cb6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023074776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.1023074776 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.3336621495 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 205406586 ps |
| CPU time | 21.25 seconds |
| Started | Jul 12 07:35:37 PM PDT 24 |
| Finished | Jul 12 07:36:02 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-7b670f07-5d85-4116-8f24-6efd9be69df6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336621495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.3336621495 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.3257440450 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 1962304808 ps |
| CPU time | 51.3 seconds |
| Started | Jul 12 07:35:35 PM PDT 24 |
| Finished | Jul 12 07:36:31 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-b8fb93fd-a540-4e87-8626-b5cc439c55bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257440450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.3257440450 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.1960006657 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 220790607 ps |
| CPU time | 9.07 seconds |
| Started | Jul 12 07:35:29 PM PDT 24 |
| Finished | Jul 12 07:35:43 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-c4b51c7a-deb4-4e17-b6c9-760e3e66ba43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960006657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.1960006657 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.986329775 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 9405865278 ps |
| CPU time | 105.09 seconds |
| Started | Jul 12 07:35:32 PM PDT 24 |
| Finished | Jul 12 07:37:21 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-c3c438a6-b9d8-4c4f-aa3a-1dec1899b1eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986329775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.986329775 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.42953697 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 5172308259 ps |
| CPU time | 91.89 seconds |
| Started | Jul 12 07:35:27 PM PDT 24 |
| Finished | Jul 12 07:37:04 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-c2595b5e-b7da-4225-9c33-b58dcdcda761 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42953697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.42953697 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.2800700 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 46616012 ps |
| CPU time | 6.26 seconds |
| Started | Jul 12 07:35:33 PM PDT 24 |
| Finished | Jul 12 07:35:44 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-54503851-ce48-440a-aecf-cb50e3d2ecd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delays.2800700 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.3792292185 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 4195141632 ps |
| CPU time | 155.34 seconds |
| Started | Jul 12 07:35:38 PM PDT 24 |
| Finished | Jul 12 07:38:18 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-da7dd09d-c533-4831-a574-36dd29a86b87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792292185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.3792292185 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.1749798178 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 4650677778 ps |
| CPU time | 165.33 seconds |
| Started | Jul 12 07:35:45 PM PDT 24 |
| Finished | Jul 12 07:38:34 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-37203ffe-d39a-4233-855b-8a63b4cb1593 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749798178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.1749798178 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.203431593 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 197829016 ps |
| CPU time | 94.69 seconds |
| Started | Jul 12 07:35:40 PM PDT 24 |
| Finished | Jul 12 07:37:19 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-13fc2f33-5bad-4914-8746-0a019566c465 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203431593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_ with_rand_reset.203431593 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.1428371584 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 535880568 ps |
| CPU time | 159.95 seconds |
| Started | Jul 12 07:35:41 PM PDT 24 |
| Finished | Jul 12 07:38:25 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-c02541f2-50ce-444f-8138-9c6fb0d406be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428371584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al l_with_reset_error.1428371584 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.2213314814 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 111490652 ps |
| CPU time | 13.14 seconds |
| Started | Jul 12 07:35:43 PM PDT 24 |
| Finished | Jul 12 07:36:00 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-536be51f-56f1-4e7c-8047-49e875321426 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213314814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.2213314814 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.2714320464 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 495344981 ps |
| CPU time | 20.57 seconds |
| Started | Jul 12 07:35:39 PM PDT 24 |
| Finished | Jul 12 07:36:03 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-8d2d96e7-2765-4a7c-83a8-fed978622cda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714320464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device .2714320464 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.654007718 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 28874341317 ps |
| CPU time | 524.01 seconds |
| Started | Jul 12 07:35:38 PM PDT 24 |
| Finished | Jul 12 07:44:26 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-163dc32f-2400-4a99-9535-388ff4ef7242 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654007718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_d evice_slow_rsp.654007718 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.3911430216 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 306270719 ps |
| CPU time | 33.97 seconds |
| Started | Jul 12 07:35:38 PM PDT 24 |
| Finished | Jul 12 07:36:16 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-2c233ea3-74f9-499a-9272-88c075df7df0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911430216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add r.3911430216 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.74582501 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 1872304774 ps |
| CPU time | 61.18 seconds |
| Started | Jul 12 07:35:38 PM PDT 24 |
| Finished | Jul 12 07:36:43 PM PDT 24 |
| Peak memory | 575172 kb |
| Host | smart-0f998800-b100-4761-a8e2-a7375d8e2fb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74582501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.74582501 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.4314955 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 2306186899 ps |
| CPU time | 88.69 seconds |
| Started | Jul 12 07:35:39 PM PDT 24 |
| Finished | Jul 12 07:37:11 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-9579fa6f-37f9-47a9-985b-951429f58719 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4314955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.4314955 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.139637878 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 39977826439 ps |
| CPU time | 430.35 seconds |
| Started | Jul 12 07:35:38 PM PDT 24 |
| Finished | Jul 12 07:42:53 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-19c95156-f76d-44eb-a66a-38fe4361e542 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139637878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.139637878 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.2168174299 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 44853236142 ps |
| CPU time | 824.2 seconds |
| Started | Jul 12 07:35:43 PM PDT 24 |
| Finished | Jul 12 07:49:31 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-4c5bac61-fe94-4f19-8e73-eccbefed89c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168174299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.2168174299 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.1925135584 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 580683344 ps |
| CPU time | 46.05 seconds |
| Started | Jul 12 07:35:45 PM PDT 24 |
| Finished | Jul 12 07:36:34 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-c6913e19-07f4-4d15-8cca-96023ef62d84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925135584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.1925135584 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.3265040670 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 381149349 ps |
| CPU time | 28.65 seconds |
| Started | Jul 12 07:35:50 PM PDT 24 |
| Finished | Jul 12 07:36:25 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-020f328d-1923-4c2c-82d3-a43644e03f8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265040670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.3265040670 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.3471163440 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 214087532 ps |
| CPU time | 9.57 seconds |
| Started | Jul 12 07:35:41 PM PDT 24 |
| Finished | Jul 12 07:35:56 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-36eb247b-8f3d-4fec-8565-4d74f8653f00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471163440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.3471163440 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.848779585 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 9295080188 ps |
| CPU time | 104.47 seconds |
| Started | Jul 12 07:35:40 PM PDT 24 |
| Finished | Jul 12 07:37:29 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-5b7a629b-4fe6-4e15-b47f-828513a248a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848779585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.848779585 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.2324617806 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 5301840723 ps |
| CPU time | 89.07 seconds |
| Started | Jul 12 07:35:38 PM PDT 24 |
| Finished | Jul 12 07:37:11 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-fdb4263c-950c-40d8-8f12-9a88a3411c9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324617806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.2324617806 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2617421959 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 56494046 ps |
| CPU time | 6.95 seconds |
| Started | Jul 12 07:35:46 PM PDT 24 |
| Finished | Jul 12 07:35:56 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-590f9dd2-582d-4c4d-8f72-f232310c7651 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617421959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.2617421959 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.3124639466 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 3006720989 ps |
| CPU time | 215.36 seconds |
| Started | Jul 12 07:35:40 PM PDT 24 |
| Finished | Jul 12 07:39:19 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-575384ec-caf1-4b71-a5c6-bcda38a02936 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124639466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.3124639466 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.1512842519 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 679328829 ps |
| CPU time | 229.93 seconds |
| Started | Jul 12 07:35:37 PM PDT 24 |
| Finished | Jul 12 07:39:31 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-a79ce451-9f72-440d-ae52-f7d440e19521 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512842519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_rand_reset.1512842519 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1074550259 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 427646765 ps |
| CPU time | 119.16 seconds |
| Started | Jul 12 07:35:39 PM PDT 24 |
| Finished | Jul 12 07:37:42 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-b89b3582-75ea-4da4-9287-b581e0770df3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074550259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.1074550259 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.1715633877 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 497630290 ps |
| CPU time | 21.41 seconds |
| Started | Jul 12 07:35:41 PM PDT 24 |
| Finished | Jul 12 07:36:06 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-51d97e34-ee77-4f19-bef6-9b7940225139 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715633877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.1715633877 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.1290618410 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 3334868562 ps |
| CPU time | 136.19 seconds |
| Started | Jul 12 07:35:59 PM PDT 24 |
| Finished | Jul 12 07:38:17 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-b2e623ea-d224-41da-ab25-1439db7f17bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290618410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .1290618410 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.999827268 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 2834675563 ps |
| CPU time | 51.18 seconds |
| Started | Jul 12 07:35:53 PM PDT 24 |
| Finished | Jul 12 07:36:50 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-34159f05-ef9e-4999-a9df-632b5f2b926d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999827268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_d evice_slow_rsp.999827268 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.3635265073 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 664729420 ps |
| CPU time | 28.22 seconds |
| Started | Jul 12 07:35:51 PM PDT 24 |
| Finished | Jul 12 07:36:24 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-1192050e-81d3-4d0c-acf7-d2d12a982ddf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635265073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.3635265073 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.3555348610 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 1412077540 ps |
| CPU time | 51.93 seconds |
| Started | Jul 12 07:35:51 PM PDT 24 |
| Finished | Jul 12 07:36:49 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-184da578-8437-4f14-a76d-aaec753550e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555348610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.3555348610 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.2101977226 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 731083568 ps |
| CPU time | 29.1 seconds |
| Started | Jul 12 07:35:52 PM PDT 24 |
| Finished | Jul 12 07:36:26 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-d2639f4f-6e9f-4e84-92a3-820ce8fdbd49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101977226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.2101977226 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.3119587098 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 12281379141 ps |
| CPU time | 143.6 seconds |
| Started | Jul 12 07:35:51 PM PDT 24 |
| Finished | Jul 12 07:38:20 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-dbe7e6b0-d461-4293-b2cb-6ca1921aa191 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119587098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.3119587098 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.2980953954 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 54765265873 ps |
| CPU time | 972.9 seconds |
| Started | Jul 12 07:36:03 PM PDT 24 |
| Finished | Jul 12 07:52:18 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-f04af70e-cb45-4ed1-86f8-ed1076266326 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980953954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.2980953954 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.793240185 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 319563601 ps |
| CPU time | 27.08 seconds |
| Started | Jul 12 07:35:49 PM PDT 24 |
| Finished | Jul 12 07:36:21 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-5ce8f9e6-f3db-4f7f-9c8d-e918cc4310aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793240185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_dela ys.793240185 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.3015081663 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 2067090620 ps |
| CPU time | 58.66 seconds |
| Started | Jul 12 07:35:50 PM PDT 24 |
| Finished | Jul 12 07:36:55 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-f59b16a5-26d1-4cb5-93ed-4508a4b366e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015081663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.3015081663 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.3084469530 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 192778095 ps |
| CPU time | 8.52 seconds |
| Started | Jul 12 07:35:38 PM PDT 24 |
| Finished | Jul 12 07:35:51 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-d0ae2d63-203a-44a0-8de8-d0227ad74975 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084469530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.3084469530 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.1117095132 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 7476425604 ps |
| CPU time | 79.33 seconds |
| Started | Jul 12 07:35:38 PM PDT 24 |
| Finished | Jul 12 07:37:02 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-2266ffac-5277-43f6-9ca1-bf19af21d5ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117095132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.1117095132 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.1946484892 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 4910447990 ps |
| CPU time | 85.09 seconds |
| Started | Jul 12 07:35:50 PM PDT 24 |
| Finished | Jul 12 07:37:20 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-291fefb7-d64d-4758-b3ca-c91a39185d53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946484892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.1946484892 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.2428189506 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 50479853 ps |
| CPU time | 6.82 seconds |
| Started | Jul 12 07:35:42 PM PDT 24 |
| Finished | Jul 12 07:35:53 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-0b53da88-fd09-4ad5-9a7d-5d56a3bcf074 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428189506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delay s.2428189506 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.1876645397 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 3607419619 ps |
| CPU time | 260.3 seconds |
| Started | Jul 12 07:36:02 PM PDT 24 |
| Finished | Jul 12 07:40:25 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-0f5284cc-006c-4ad4-9dd5-623c075b495c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876645397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.1876645397 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.4069722980 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 7337293226 ps |
| CPU time | 246.28 seconds |
| Started | Jul 12 07:35:53 PM PDT 24 |
| Finished | Jul 12 07:40:04 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-271fc71b-c92a-468c-8886-847628b37c57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069722980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.4069722980 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.1151566503 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 273714239 ps |
| CPU time | 74.13 seconds |
| Started | Jul 12 07:36:02 PM PDT 24 |
| Finished | Jul 12 07:37:19 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-5f6e3fb0-8351-441f-a56c-9ef215fa9b85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151566503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.1151566503 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.2633186514 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 8358974359 ps |
| CPU time | 406.9 seconds |
| Started | Jul 12 07:35:52 PM PDT 24 |
| Finished | Jul 12 07:42:44 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-5eae61f1-0c1b-4693-b1fc-f86f182771d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633186514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.2633186514 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.3313440247 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 64758716 ps |
| CPU time | 9.87 seconds |
| Started | Jul 12 07:35:52 PM PDT 24 |
| Finished | Jul 12 07:36:07 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-71663e72-2e45-48f9-a7d9-885d17c6a4fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313440247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.3313440247 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.1383736018 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 690854497 ps |
| CPU time | 31.03 seconds |
| Started | Jul 12 07:35:52 PM PDT 24 |
| Finished | Jul 12 07:36:29 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-37f61421-ee71-40fd-b592-14827f485626 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383736018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .1383736018 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.56553577 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 131071119175 ps |
| CPU time | 2562.28 seconds |
| Started | Jul 12 07:36:02 PM PDT 24 |
| Finished | Jul 12 08:18:47 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-3bde773f-d756-4bb5-bd20-5fbcbed7510f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56553577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_de vice_slow_rsp.56553577 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.2536984715 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 692120914 ps |
| CPU time | 24.29 seconds |
| Started | Jul 12 07:35:53 PM PDT 24 |
| Finished | Jul 12 07:36:23 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-3bf50902-f24f-4fcb-b2f6-7e16589a9092 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536984715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add r.2536984715 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.2548993334 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 399924696 ps |
| CPU time | 32.93 seconds |
| Started | Jul 12 07:35:50 PM PDT 24 |
| Finished | Jul 12 07:36:29 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-5fee20f9-d476-4570-9aa3-5bc106c478fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548993334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.2548993334 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.1807306904 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 83019488 ps |
| CPU time | 6.5 seconds |
| Started | Jul 12 07:35:51 PM PDT 24 |
| Finished | Jul 12 07:36:03 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-4d91c9cc-729a-4720-9d49-b08264889145 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807306904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.1807306904 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.1250667638 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 84681030513 ps |
| CPU time | 961.7 seconds |
| Started | Jul 12 07:37:29 PM PDT 24 |
| Finished | Jul 12 07:53:36 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-31c47d18-49c8-4881-9e7b-a0621e989bd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250667638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.1250667638 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.4018265228 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 28220137219 ps |
| CPU time | 501.33 seconds |
| Started | Jul 12 07:35:50 PM PDT 24 |
| Finished | Jul 12 07:44:18 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-720338d5-ac95-4a72-8672-3234e23e6ad5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018265228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.4018265228 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.3325294047 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 264269596 ps |
| CPU time | 23.89 seconds |
| Started | Jul 12 07:35:48 PM PDT 24 |
| Finished | Jul 12 07:36:17 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-9e2c5d3a-78d5-43dd-a2c7-ff41d4d1d08a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325294047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.3325294047 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.3686683153 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 75234232 ps |
| CPU time | 8.04 seconds |
| Started | Jul 12 07:35:52 PM PDT 24 |
| Finished | Jul 12 07:36:06 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-8be02947-e72b-4b85-a362-f9bb8b6a05d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686683153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.3686683153 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.2491652029 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 39248422 ps |
| CPU time | 6.23 seconds |
| Started | Jul 12 07:35:53 PM PDT 24 |
| Finished | Jul 12 07:36:04 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-f4e797e3-b409-4803-b39f-2427b905a603 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491652029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.2491652029 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.1104599436 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 8392342495 ps |
| CPU time | 93.61 seconds |
| Started | Jul 12 07:35:53 PM PDT 24 |
| Finished | Jul 12 07:37:32 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-8476751b-ae6d-4ec3-baca-78a9bf128a9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104599436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.1104599436 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.966388513 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 4744130612 ps |
| CPU time | 84.11 seconds |
| Started | Jul 12 07:37:24 PM PDT 24 |
| Finished | Jul 12 07:38:52 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-6bf2db5f-0eff-4f46-b83d-5588a2cc47f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966388513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.966388513 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.3789963235 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 36209369 ps |
| CPU time | 5.65 seconds |
| Started | Jul 12 07:35:51 PM PDT 24 |
| Finished | Jul 12 07:36:03 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-3c912d59-3ce9-4b4a-8898-70e5a0a7372b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789963235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay s.3789963235 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.3470256891 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 9148741751 ps |
| CPU time | 325.29 seconds |
| Started | Jul 12 07:36:02 PM PDT 24 |
| Finished | Jul 12 07:41:30 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-e4a3ebe3-aae3-4c4e-beb3-ffff3f1364e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470256891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.3470256891 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.3235742323 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 5743339599 ps |
| CPU time | 178.36 seconds |
| Started | Jul 12 07:35:53 PM PDT 24 |
| Finished | Jul 12 07:38:56 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-36455f09-8ba8-4b84-a798-3c2e1807da4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235742323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.3235742323 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.3485062157 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 347985086 ps |
| CPU time | 127.58 seconds |
| Started | Jul 12 07:35:56 PM PDT 24 |
| Finished | Jul 12 07:38:08 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-04e511f2-ca23-428e-b2fc-32f28f32fee6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485062157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_rand_reset.3485062157 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.1484619320 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 248231205 ps |
| CPU time | 60.2 seconds |
| Started | Jul 12 07:36:00 PM PDT 24 |
| Finished | Jul 12 07:37:02 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-394b851b-8b6b-4afc-bfdb-bc81fa54a20c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484619320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.1484619320 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.733804283 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 683655231 ps |
| CPU time | 31.69 seconds |
| Started | Jul 12 07:35:50 PM PDT 24 |
| Finished | Jul 12 07:36:27 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-723223f6-e99f-439f-9058-a91e51d4f8ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733804283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.733804283 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.782172554 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 1041457367 ps |
| CPU time | 85.46 seconds |
| Started | Jul 12 07:36:01 PM PDT 24 |
| Finished | Jul 12 07:37:29 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-619a9df5-1ee9-49ee-bbec-8c8468f03bbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782172554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device. 782172554 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.3649690719 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 104875157996 ps |
| CPU time | 2042.75 seconds |
| Started | Jul 12 07:36:01 PM PDT 24 |
| Finished | Jul 12 08:10:07 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-0991513a-88bc-4a97-8542-0be744b7b15d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649690719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_ device_slow_rsp.3649690719 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.4015651219 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 39593397 ps |
| CPU time | 6.77 seconds |
| Started | Jul 12 07:36:16 PM PDT 24 |
| Finished | Jul 12 07:36:27 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-24c586aa-c3ec-400e-8e11-42daa2bfdd9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015651219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.4015651219 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.1522257527 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 40718532 ps |
| CPU time | 6.27 seconds |
| Started | Jul 12 07:36:04 PM PDT 24 |
| Finished | Jul 12 07:36:12 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-a7e6a00f-eb6f-4837-a61c-ab3c6340a9ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522257527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.1522257527 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.3197648338 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 312748148 ps |
| CPU time | 29.37 seconds |
| Started | Jul 12 07:36:01 PM PDT 24 |
| Finished | Jul 12 07:36:33 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-e188af80-2f2b-4d30-a47c-b170ff545afd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197648338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.3197648338 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.3387847245 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 92927503938 ps |
| CPU time | 1107.94 seconds |
| Started | Jul 12 07:36:01 PM PDT 24 |
| Finished | Jul 12 07:54:32 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-cdb2b7f2-5570-4e63-94a0-727fec8397ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387847245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.3387847245 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.3580894149 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 43639691486 ps |
| CPU time | 775.34 seconds |
| Started | Jul 12 07:36:00 PM PDT 24 |
| Finished | Jul 12 07:48:58 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-1566b7e6-db84-4b88-93c8-5f99a2c37448 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580894149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.3580894149 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.2816194526 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 477788350 ps |
| CPU time | 39.28 seconds |
| Started | Jul 12 07:36:16 PM PDT 24 |
| Finished | Jul 12 07:36:59 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-1317ebe6-f2f8-4216-bbe4-168db6873936 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816194526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.2816194526 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.4093352167 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 2049955717 ps |
| CPU time | 60.46 seconds |
| Started | Jul 12 07:36:00 PM PDT 24 |
| Finished | Jul 12 07:37:03 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-0d02dddb-feba-47ad-a058-b3f0cef20df7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093352167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.4093352167 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.3648887427 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 232290846 ps |
| CPU time | 9.84 seconds |
| Started | Jul 12 07:36:02 PM PDT 24 |
| Finished | Jul 12 07:36:14 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-2f670366-8ba9-47be-a8e0-c94462dfb1fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648887427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.3648887427 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.152166740 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 7468430748 ps |
| CPU time | 80.04 seconds |
| Started | Jul 12 07:36:16 PM PDT 24 |
| Finished | Jul 12 07:37:40 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-1595f07a-3d4e-4a71-8b2f-40287baa6eaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152166740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.152166740 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.1538839197 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 4956987357 ps |
| CPU time | 86.67 seconds |
| Started | Jul 12 07:36:04 PM PDT 24 |
| Finished | Jul 12 07:37:33 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-0cc84eb0-b809-46bc-b683-7cc2cf2c57ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538839197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.1538839197 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.2381988419 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 53924752 ps |
| CPU time | 6.5 seconds |
| Started | Jul 12 07:36:04 PM PDT 24 |
| Finished | Jul 12 07:36:12 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-b8ac8758-55f4-48f6-9ed1-d6a511c99e12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381988419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.2381988419 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.3302807740 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 8805163904 ps |
| CPU time | 405.53 seconds |
| Started | Jul 12 07:36:01 PM PDT 24 |
| Finished | Jul 12 07:42:50 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-fed6e87c-050a-4234-ac66-e58bad1b7a93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302807740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.3302807740 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.1656762317 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 618319912 ps |
| CPU time | 44.82 seconds |
| Started | Jul 12 07:36:06 PM PDT 24 |
| Finished | Jul 12 07:36:52 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-781df7b6-daa3-4ef3-94a4-23dfdc2bff9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656762317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.1656762317 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.2153801806 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 1224559714 ps |
| CPU time | 324.15 seconds |
| Started | Jul 12 07:36:06 PM PDT 24 |
| Finished | Jul 12 07:41:31 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-cd065703-e758-4962-abad-30dc4ac6cd29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153801806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.2153801806 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.174936070 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 1039117669 ps |
| CPU time | 222.7 seconds |
| Started | Jul 12 07:36:00 PM PDT 24 |
| Finished | Jul 12 07:39:45 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-cce8fb77-182b-4c9d-8b74-0454f77da7e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174936070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_reset_error.174936070 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.3072677954 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 119963200 ps |
| CPU time | 14.93 seconds |
| Started | Jul 12 07:36:02 PM PDT 24 |
| Finished | Jul 12 07:36:19 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-8831bed2-0eeb-4c3f-b1c1-ba2d84f7211e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072677954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.3072677954 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.3447889265 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 1473143666 ps |
| CPU time | 61.2 seconds |
| Started | Jul 12 07:36:16 PM PDT 24 |
| Finished | Jul 12 07:37:20 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-0872b26b-80d6-40d4-b836-da55779cfa6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447889265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device .3447889265 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.1969129849 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 22021137036 ps |
| CPU time | 420.24 seconds |
| Started | Jul 12 07:36:14 PM PDT 24 |
| Finished | Jul 12 07:43:19 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-49298bbe-dff7-4428-9fd2-0ad078658aa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969129849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_ device_slow_rsp.1969129849 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.2335474756 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 560900661 ps |
| CPU time | 24.91 seconds |
| Started | Jul 12 07:36:15 PM PDT 24 |
| Finished | Jul 12 07:36:43 PM PDT 24 |
| Peak memory | 575200 kb |
| Host | smart-63032780-e21e-40a5-bb23-b5697b620e79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335474756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.2335474756 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.1417122857 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 2165121032 ps |
| CPU time | 76.43 seconds |
| Started | Jul 12 07:36:13 PM PDT 24 |
| Finished | Jul 12 07:37:33 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-1016a927-f40b-4b0c-8fb5-2e045a9d5cd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417122857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.1417122857 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.830064340 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 1133660705 ps |
| CPU time | 38.34 seconds |
| Started | Jul 12 07:36:01 PM PDT 24 |
| Finished | Jul 12 07:36:42 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-7faf1fbd-d00d-4a4e-991e-bee9dc0aa4ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830064340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.830064340 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.2608650481 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 56006468674 ps |
| CPU time | 672.24 seconds |
| Started | Jul 12 07:36:02 PM PDT 24 |
| Finished | Jul 12 07:47:18 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-a7e9fa8c-6a94-422d-9f78-1bc0e791554d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608650481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.2608650481 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.3247030584 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 21440868320 ps |
| CPU time | 362.85 seconds |
| Started | Jul 12 07:36:14 PM PDT 24 |
| Finished | Jul 12 07:42:21 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-841c03df-0c37-42e3-bb09-c85a36b9769e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247030584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.3247030584 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.3707566794 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 34364971 ps |
| CPU time | 6.27 seconds |
| Started | Jul 12 07:36:02 PM PDT 24 |
| Finished | Jul 12 07:36:11 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-9e51ee41-a2f8-4e9c-9f91-f7409a7db93c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707566794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del ays.3707566794 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.2363018734 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 2157865655 ps |
| CPU time | 63.62 seconds |
| Started | Jul 12 07:36:14 PM PDT 24 |
| Finished | Jul 12 07:37:21 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-1a1e834c-9282-4714-8a81-9bbf60f10af8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363018734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.2363018734 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.2012120848 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 49923546 ps |
| CPU time | 6.49 seconds |
| Started | Jul 12 07:36:05 PM PDT 24 |
| Finished | Jul 12 07:36:13 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-74351590-5f18-41df-909c-002dc8df4b59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012120848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.2012120848 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.3612833421 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 10273871537 ps |
| CPU time | 120.66 seconds |
| Started | Jul 12 07:36:15 PM PDT 24 |
| Finished | Jul 12 07:38:20 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-8591b6c0-20bb-4a04-8d14-6d9557b1be63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612833421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.3612833421 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.3958654113 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 3211023024 ps |
| CPU time | 50.35 seconds |
| Started | Jul 12 07:36:02 PM PDT 24 |
| Finished | Jul 12 07:36:55 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-730568d4-cacd-475d-8391-c3e352594f8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958654113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.3958654113 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.4107171576 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 52104777 ps |
| CPU time | 6.25 seconds |
| Started | Jul 12 07:36:01 PM PDT 24 |
| Finished | Jul 12 07:36:10 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-f0dcb198-fcd1-426c-8694-e2382931bdde |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107171576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.4107171576 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.83886845 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 4119196042 ps |
| CPU time | 147.95 seconds |
| Started | Jul 12 07:36:16 PM PDT 24 |
| Finished | Jul 12 07:38:48 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-c03d92f3-592d-478b-94be-e8815b617dfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83886845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.83886845 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.3064828610 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 204908623 ps |
| CPU time | 94.05 seconds |
| Started | Jul 12 07:36:18 PM PDT 24 |
| Finished | Jul 12 07:37:55 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-a931ca28-4cc8-439a-aa8b-c336f20460bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064828610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.3064828610 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.1531759139 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 5116568364 ps |
| CPU time | 227.88 seconds |
| Started | Jul 12 07:36:14 PM PDT 24 |
| Finished | Jul 12 07:40:06 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-67a7c626-bc14-4149-870a-3b357a3908ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531759139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.1531759139 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.3422484777 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 1452278223 ps |
| CPU time | 61.17 seconds |
| Started | Jul 12 07:36:13 PM PDT 24 |
| Finished | Jul 12 07:37:18 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-1b7466ec-dd7f-47ad-a29d-db4eb672792b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422484777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.3422484777 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.3172944534 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 4027821557 ps |
| CPU time | 291.52 seconds |
| Started | Jul 12 07:24:54 PM PDT 24 |
| Finished | Jul 12 07:29:49 PM PDT 24 |
| Peak memory | 598408 kb |
| Host | smart-8a4e5d94-5234-4e8d-9662-cb1d75539bcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172944534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.3172944534 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.697312188 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 3375161307 ps |
| CPU time | 182.13 seconds |
| Started | Jul 12 07:24:53 PM PDT 24 |
| Finished | Jul 12 07:27:56 PM PDT 24 |
| Peak memory | 603744 kb |
| Host | smart-99673eb2-4a76-40be-99f7-fb6d01e58e34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697312188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.697312188 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.1481271102 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 16348156 ps |
| CPU time | 6.79 seconds |
| Started | Jul 12 07:24:53 PM PDT 24 |
| Finished | Jul 12 07:25:01 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-0a8c6269-93d1-4a83-81cb-cffb9f470a67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481271102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 1481271102 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.4133467076 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 117135204118 ps |
| CPU time | 2213.75 seconds |
| Started | Jul 12 07:24:55 PM PDT 24 |
| Finished | Jul 12 08:01:53 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-a5943074-7cad-40c7-869d-68df5e2a9da9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133467076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_d evice_slow_rsp.4133467076 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.491579890 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 857801469 ps |
| CPU time | 38.59 seconds |
| Started | Jul 12 07:24:55 PM PDT 24 |
| Finished | Jul 12 07:25:37 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-fc276499-9848-424d-8d8a-38e458020dbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491579890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr. 491579890 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.1907150462 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 1165088317 ps |
| CPU time | 38.22 seconds |
| Started | Jul 12 07:24:55 PM PDT 24 |
| Finished | Jul 12 07:25:37 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-d2f8cb34-733e-4e07-97d0-eb84f1bde9d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907150462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1907150462 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.454749820 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 1915512408 ps |
| CPU time | 67 seconds |
| Started | Jul 12 07:24:53 PM PDT 24 |
| Finished | Jul 12 07:26:02 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-070af36b-fe2f-4fd4-a8c3-b3045de2df8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454749820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.454749820 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.3104773344 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 91660123220 ps |
| CPU time | 1085.49 seconds |
| Started | Jul 12 07:24:53 PM PDT 24 |
| Finished | Jul 12 07:43:01 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-c4698888-337d-4d8a-b3cb-3e1bb6344ae7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104773344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3104773344 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.1883646244 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 32300225443 ps |
| CPU time | 552.2 seconds |
| Started | Jul 12 07:24:56 PM PDT 24 |
| Finished | Jul 12 07:34:12 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-c8a9246e-f82b-440e-b313-105880afc418 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883646244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1883646244 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.190866588 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 534061398 ps |
| CPU time | 45.45 seconds |
| Started | Jul 12 07:24:53 PM PDT 24 |
| Finished | Jul 12 07:25:40 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-267b55a7-41a9-45cf-a847-258abcbcb47d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190866588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delay s.190866588 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.1266815638 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 1396095910 ps |
| CPU time | 39.44 seconds |
| Started | Jul 12 07:24:54 PM PDT 24 |
| Finished | Jul 12 07:25:37 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-74d54a33-d72d-47a9-b570-d12b2f640e72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266815638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1266815638 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.3726278536 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 131231463 ps |
| CPU time | 7.61 seconds |
| Started | Jul 12 07:24:54 PM PDT 24 |
| Finished | Jul 12 07:25:05 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-9dd3c87c-92bf-41a4-8d6e-f8a28874eeda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726278536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3726278536 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.1109996301 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 8780251615 ps |
| CPU time | 100.27 seconds |
| Started | Jul 12 07:24:56 PM PDT 24 |
| Finished | Jul 12 07:26:40 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-4219b91b-06b6-4b86-9c5d-2d1ec7f30dd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109996301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1109996301 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3200608934 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 5206367469 ps |
| CPU time | 92.44 seconds |
| Started | Jul 12 07:24:55 PM PDT 24 |
| Finished | Jul 12 07:26:31 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-440e75a8-6e2d-41c1-ae00-b4a325c6c82d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200608934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3200608934 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.4210384814 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 35630702 ps |
| CPU time | 5.74 seconds |
| Started | Jul 12 07:24:57 PM PDT 24 |
| Finished | Jul 12 07:25:06 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-46b9808b-501d-467d-93f3-ab1921f08309 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210384814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .4210384814 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.896011483 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 12108365463 ps |
| CPU time | 503.64 seconds |
| Started | Jul 12 07:24:54 PM PDT 24 |
| Finished | Jul 12 07:33:21 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-6b2b56d3-8b88-4705-8aec-29cb0b671d90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896011483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.896011483 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.2397799160 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 6825047510 ps |
| CPU time | 207.18 seconds |
| Started | Jul 12 07:24:54 PM PDT 24 |
| Finished | Jul 12 07:28:24 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-f119b59a-ed16-4c4a-a32d-7f3c45271894 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397799160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2397799160 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1136831206 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 564427532 ps |
| CPU time | 177.16 seconds |
| Started | Jul 12 07:24:54 PM PDT 24 |
| Finished | Jul 12 07:27:54 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-b85cbd2f-0bc5-46e6-9fed-b6efa428f09a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136831206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_rand_reset.1136831206 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.2186079469 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 3431091410 ps |
| CPU time | 268 seconds |
| Started | Jul 12 07:24:54 PM PDT 24 |
| Finished | Jul 12 07:29:24 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-e8ec1ed8-4316-4c25-b3f6-dac812b4ebfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186079469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.2186079469 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.1103480719 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 103289064 ps |
| CPU time | 14.7 seconds |
| Started | Jul 12 07:24:56 PM PDT 24 |
| Finished | Jul 12 07:25:14 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-fcda4cf8-e7c7-4a8a-aa78-f1e251eacf95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103480719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1103480719 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.3458790260 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 112854945 ps |
| CPU time | 8.56 seconds |
| Started | Jul 12 07:36:27 PM PDT 24 |
| Finished | Jul 12 07:36:39 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-be75077d-4961-4a0a-8abd-928f68bd7e6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458790260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .3458790260 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.3100561637 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 103470777425 ps |
| CPU time | 1991.79 seconds |
| Started | Jul 12 07:36:26 PM PDT 24 |
| Finished | Jul 12 08:09:39 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-e9b3282d-0e01-4a97-bbed-38a64c25e94d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100561637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.3100561637 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.1990233544 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 142560534 ps |
| CPU time | 15.01 seconds |
| Started | Jul 12 07:36:31 PM PDT 24 |
| Finished | Jul 12 07:36:48 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-cdce31c2-4f1e-44d0-a923-1d6c8313f009 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990233544 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add r.1990233544 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.420226182 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 604548473 ps |
| CPU time | 53.56 seconds |
| Started | Jul 12 07:36:29 PM PDT 24 |
| Finished | Jul 12 07:37:26 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-03c595a2-76ff-4162-b490-0f79e9fb51e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420226182 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.420226182 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.1096533532 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 106248364 ps |
| CPU time | 12.39 seconds |
| Started | Jul 12 07:36:14 PM PDT 24 |
| Finished | Jul 12 07:36:30 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-0f8740a3-448b-40ed-9267-4861e488e005 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096533532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.1096533532 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.1435999854 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 71688186332 ps |
| CPU time | 803.66 seconds |
| Started | Jul 12 07:36:13 PM PDT 24 |
| Finished | Jul 12 07:49:41 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-5e098e96-7dc0-4d69-9657-ee93ebf7bf1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435999854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.1435999854 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.3124426613 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 52180880634 ps |
| CPU time | 841.65 seconds |
| Started | Jul 12 07:36:28 PM PDT 24 |
| Finished | Jul 12 07:50:34 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-ab66022b-6eaf-4435-a31a-a8625d65c01e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124426613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.3124426613 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.4203788143 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 379310037 ps |
| CPU time | 32.01 seconds |
| Started | Jul 12 07:36:18 PM PDT 24 |
| Finished | Jul 12 07:36:53 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-32655e2d-8475-48cd-985e-783e744222af |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203788143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.4203788143 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.4076291256 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 409065545 ps |
| CPU time | 29.57 seconds |
| Started | Jul 12 07:36:27 PM PDT 24 |
| Finished | Jul 12 07:37:00 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-a08f2bfb-580d-41d2-9e23-09f1d33870ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076291256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.4076291256 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.2452494013 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 235589253 ps |
| CPU time | 9.9 seconds |
| Started | Jul 12 07:36:16 PM PDT 24 |
| Finished | Jul 12 07:36:30 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-219824d2-e66f-48b5-b359-cfffcc94e079 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452494013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.2452494013 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.687870372 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 7722874509 ps |
| CPU time | 89.58 seconds |
| Started | Jul 12 07:36:15 PM PDT 24 |
| Finished | Jul 12 07:37:48 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-240e67c3-c131-4be9-a403-fd7d469b7f3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687870372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.687870372 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.2922702188 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 5711087961 ps |
| CPU time | 96.12 seconds |
| Started | Jul 12 07:36:15 PM PDT 24 |
| Finished | Jul 12 07:37:55 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-333c68ec-ad28-4112-929e-033bff14d496 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922702188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.2922702188 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.1889992682 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 42956044 ps |
| CPU time | 5.91 seconds |
| Started | Jul 12 07:36:18 PM PDT 24 |
| Finished | Jul 12 07:36:27 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-e752d01e-acea-41af-b4c3-ae197bb7e59f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889992682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.1889992682 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.2791544402 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 757311938 ps |
| CPU time | 31.11 seconds |
| Started | Jul 12 07:36:27 PM PDT 24 |
| Finished | Jul 12 07:37:01 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-ca95eff6-3cfa-4878-8d9e-2364390c19ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791544402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.2791544402 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.174639058 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 3079186350 ps |
| CPU time | 254.88 seconds |
| Started | Jul 12 07:36:26 PM PDT 24 |
| Finished | Jul 12 07:40:44 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-49a66ede-4449-483d-9bc2-9e1ba24379c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174639058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.174639058 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.1147453213 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 84039334 ps |
| CPU time | 34.4 seconds |
| Started | Jul 12 07:36:27 PM PDT 24 |
| Finished | Jul 12 07:37:04 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-e9da8f0f-1e7f-4139-94cf-2cd7676f3bd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147453213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.1147453213 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.1038487391 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 113856932 ps |
| CPU time | 15.21 seconds |
| Started | Jul 12 07:36:28 PM PDT 24 |
| Finished | Jul 12 07:36:47 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-2dd22b30-a9b4-4dc4-b05b-03e686f21092 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038487391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.1038487391 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.1923862169 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 160749963 ps |
| CPU time | 11.61 seconds |
| Started | Jul 12 07:36:35 PM PDT 24 |
| Finished | Jul 12 07:36:48 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-acd73840-3160-4998-a6ed-152e438a999e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923862169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .1923862169 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.1006944082 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 115022094248 ps |
| CPU time | 2213.22 seconds |
| Started | Jul 12 07:36:25 PM PDT 24 |
| Finished | Jul 12 08:13:20 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-eafaf7c6-5b98-4b04-b720-df663fc5ee3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006944082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.1006944082 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.2675895604 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 71536680 ps |
| CPU time | 9.17 seconds |
| Started | Jul 12 07:36:29 PM PDT 24 |
| Finished | Jul 12 07:36:42 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-109daf70-b095-4354-a018-003403ae36a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675895604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.2675895604 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.4268028566 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 1561450124 ps |
| CPU time | 55.18 seconds |
| Started | Jul 12 07:36:29 PM PDT 24 |
| Finished | Jul 12 07:37:28 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-3c731192-a25a-4fd9-bd1e-02b1ed719adc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268028566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.4268028566 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.2149543548 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 416366931 ps |
| CPU time | 39.8 seconds |
| Started | Jul 12 07:36:29 PM PDT 24 |
| Finished | Jul 12 07:37:12 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-5a81eec2-a807-4067-9045-9870ee2fefb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149543548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.2149543548 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.2394844667 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 75284844736 ps |
| CPU time | 860.22 seconds |
| Started | Jul 12 07:36:26 PM PDT 24 |
| Finished | Jul 12 07:50:49 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-c3319cbd-4f61-4fa5-ba93-625f1f39541c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394844667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.2394844667 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.3815708193 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 25881885534 ps |
| CPU time | 445.48 seconds |
| Started | Jul 12 07:36:29 PM PDT 24 |
| Finished | Jul 12 07:43:58 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-1796a569-c179-4adb-8457-a4da3c660728 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815708193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.3815708193 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.2626418095 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 226960926 ps |
| CPU time | 19.65 seconds |
| Started | Jul 12 07:36:26 PM PDT 24 |
| Finished | Jul 12 07:36:48 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-040cc590-38bf-4694-8265-610279150730 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626418095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.2626418095 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.839279633 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 1731911439 ps |
| CPU time | 51.56 seconds |
| Started | Jul 12 07:36:30 PM PDT 24 |
| Finished | Jul 12 07:37:25 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-532872f9-1f6f-4949-a3e4-6699e9b4dc0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839279633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.839279633 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.4070546224 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 45547705 ps |
| CPU time | 6.78 seconds |
| Started | Jul 12 07:36:34 PM PDT 24 |
| Finished | Jul 12 07:36:42 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-fdb3eba1-0d9b-4a62-b856-7c2b6b817a2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070546224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.4070546224 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.2417428733 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 9259691804 ps |
| CPU time | 103.27 seconds |
| Started | Jul 12 07:36:27 PM PDT 24 |
| Finished | Jul 12 07:38:14 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-239a7472-1eb8-4a68-8ae8-e51b6885af64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417428733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.2417428733 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.1030435120 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 6186114774 ps |
| CPU time | 107.15 seconds |
| Started | Jul 12 07:36:28 PM PDT 24 |
| Finished | Jul 12 07:38:19 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-961debf0-37de-4b9a-8f87-0e78567e4c12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030435120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.1030435120 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.83544143 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 45080798 ps |
| CPU time | 5.96 seconds |
| Started | Jul 12 07:36:29 PM PDT 24 |
| Finished | Jul 12 07:36:38 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-e1352271-352b-4cc7-8933-e18b9b92bbd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83544143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delays.83544143 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.176463769 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 13920610924 ps |
| CPU time | 528.23 seconds |
| Started | Jul 12 07:36:28 PM PDT 24 |
| Finished | Jul 12 07:45:20 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-4e1d4741-b24c-492c-91d7-9997d811f78f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176463769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.176463769 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.2149483032 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 1402433465 ps |
| CPU time | 98.52 seconds |
| Started | Jul 12 07:36:44 PM PDT 24 |
| Finished | Jul 12 07:38:26 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-bddb73de-36ca-4b07-b54d-f6341a9cd832 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149483032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.2149483032 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.2666603376 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 174791520 ps |
| CPU time | 82.73 seconds |
| Started | Jul 12 07:36:45 PM PDT 24 |
| Finished | Jul 12 07:38:11 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-79610d2a-2d25-490b-ad91-9a53aec5e236 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666603376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.2666603376 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.3766414952 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 5324201356 ps |
| CPU time | 375.25 seconds |
| Started | Jul 12 07:36:43 PM PDT 24 |
| Finished | Jul 12 07:43:02 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-42f58907-3915-4cb4-b1b7-a47ccbac87ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766414952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.3766414952 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.1821704507 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 743870534 ps |
| CPU time | 35.41 seconds |
| Started | Jul 12 07:36:34 PM PDT 24 |
| Finished | Jul 12 07:37:11 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-d7aa625e-ba8a-4f9d-a8ca-40c3f76f9c1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821704507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.1821704507 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.2687506008 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 1187664434 ps |
| CPU time | 87.85 seconds |
| Started | Jul 12 07:36:43 PM PDT 24 |
| Finished | Jul 12 07:38:14 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-a652415d-7a95-43d0-9475-4e8bc455b08f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687506008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .2687506008 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.804887837 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 18602257983 ps |
| CPU time | 359.61 seconds |
| Started | Jul 12 07:36:41 PM PDT 24 |
| Finished | Jul 12 07:42:44 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-3c042972-e662-4f5a-b09d-df8161db0828 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804887837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_d evice_slow_rsp.804887837 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.1912123332 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 302674090 ps |
| CPU time | 31.35 seconds |
| Started | Jul 12 07:36:42 PM PDT 24 |
| Finished | Jul 12 07:37:18 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-f30d9f86-1b1c-4bf3-a568-07a634e0cf18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912123332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.1912123332 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.3489836908 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 1241652353 ps |
| CPU time | 38.87 seconds |
| Started | Jul 12 07:36:43 PM PDT 24 |
| Finished | Jul 12 07:37:26 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-928c4a19-929f-4fc5-91dd-af8be54c20e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489836908 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.3489836908 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.1392960464 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 2571529435 ps |
| CPU time | 91.57 seconds |
| Started | Jul 12 07:36:42 PM PDT 24 |
| Finished | Jul 12 07:38:17 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-3b6a945e-f748-4395-b291-8d1ebd24cf68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392960464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.1392960464 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.2665306016 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 105061579019 ps |
| CPU time | 1323.31 seconds |
| Started | Jul 12 07:36:41 PM PDT 24 |
| Finished | Jul 12 07:58:47 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-bffcf6ec-91af-429d-b7b9-d4e3d73e1e66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665306016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.2665306016 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.695076991 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 31221653258 ps |
| CPU time | 601.99 seconds |
| Started | Jul 12 07:36:44 PM PDT 24 |
| Finished | Jul 12 07:46:50 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-a48505dc-ccbc-4a67-b0de-5e5625ce8a71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695076991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.695076991 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.4294029406 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 463842289 ps |
| CPU time | 38.3 seconds |
| Started | Jul 12 07:36:44 PM PDT 24 |
| Finished | Jul 12 07:37:26 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-9b49c49c-74cf-4e2e-a228-df85f428fede |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294029406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del ays.4294029406 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.2351600 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 111365069 ps |
| CPU time | 10.4 seconds |
| Started | Jul 12 07:36:45 PM PDT 24 |
| Finished | Jul 12 07:36:59 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-d2a5cdba-50fc-454b-99aa-36538a97fbe4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.2351600 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.3827553840 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 47443186 ps |
| CPU time | 7.02 seconds |
| Started | Jul 12 07:36:43 PM PDT 24 |
| Finished | Jul 12 07:36:54 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-1690bcac-7480-4dd1-a353-dd255f139b0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827553840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.3827553840 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.4212211965 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 8822648473 ps |
| CPU time | 95.13 seconds |
| Started | Jul 12 07:36:42 PM PDT 24 |
| Finished | Jul 12 07:38:21 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-ae5dbf7e-8079-4363-a443-8bbcfe34bbb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212211965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.4212211965 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.151949578 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 5613857125 ps |
| CPU time | 97.47 seconds |
| Started | Jul 12 07:36:43 PM PDT 24 |
| Finished | Jul 12 07:38:24 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-58794828-749f-4cb8-8a1f-59795b6df05f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151949578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.151949578 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.3374046937 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 43156275 ps |
| CPU time | 6.05 seconds |
| Started | Jul 12 07:36:43 PM PDT 24 |
| Finished | Jul 12 07:36:53 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-55938e49-c335-4f94-ba49-a6e37382563f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374046937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delay s.3374046937 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.3949782285 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 437592714 ps |
| CPU time | 37.06 seconds |
| Started | Jul 12 07:36:42 PM PDT 24 |
| Finished | Jul 12 07:37:23 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-0f4a7044-ddf8-43f5-88a9-8f7224864020 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949782285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.3949782285 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.2603498892 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 1011011288 ps |
| CPU time | 35.13 seconds |
| Started | Jul 12 07:36:44 PM PDT 24 |
| Finished | Jul 12 07:37:22 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-75da2fcb-00fc-49f0-a369-ef6e1c5e0a50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603498892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.2603498892 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.1128483586 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 7805430637 ps |
| CPU time | 542.48 seconds |
| Started | Jul 12 07:36:44 PM PDT 24 |
| Finished | Jul 12 07:45:50 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-23ce2560-5992-4f78-8e5a-51b25bbdbf4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128483586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_rand_reset.1128483586 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.2790253649 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 104814394 ps |
| CPU time | 34.5 seconds |
| Started | Jul 12 07:36:51 PM PDT 24 |
| Finished | Jul 12 07:37:27 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-29079856-726f-4d37-bb74-bb1965551bf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790253649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al l_with_reset_error.2790253649 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.59641400 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 1235238464 ps |
| CPU time | 49.49 seconds |
| Started | Jul 12 07:36:43 PM PDT 24 |
| Finished | Jul 12 07:37:37 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-71253fc1-40d6-4fe6-a5ab-c3feb0517f4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59641400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.59641400 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.1704314832 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 80616964 ps |
| CPU time | 7.56 seconds |
| Started | Jul 12 07:36:58 PM PDT 24 |
| Finished | Jul 12 07:37:07 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-b05df334-0633-42cb-8300-bbc260cf7313 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704314832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device .1704314832 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.2690399920 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 154173703310 ps |
| CPU time | 2809.17 seconds |
| Started | Jul 12 07:36:58 PM PDT 24 |
| Finished | Jul 12 08:23:50 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-201d75f7-7646-4bbd-ae0c-b548c960dc3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690399920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.2690399920 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.2002524396 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 1237531286 ps |
| CPU time | 51.89 seconds |
| Started | Jul 12 07:36:53 PM PDT 24 |
| Finished | Jul 12 07:37:47 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-1305b1b3-7d53-478e-a747-f06841fecb5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002524396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.2002524396 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.2142695303 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 2591085925 ps |
| CPU time | 87.67 seconds |
| Started | Jul 12 07:36:53 PM PDT 24 |
| Finished | Jul 12 07:38:22 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-c017c5dd-a735-4033-9da9-f4a7e8f72001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142695303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.2142695303 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.3485164550 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 258187885 ps |
| CPU time | 25.59 seconds |
| Started | Jul 12 07:36:53 PM PDT 24 |
| Finished | Jul 12 07:37:21 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-80ef5090-6c7a-4dd5-94a9-b6b681c106f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485164550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.3485164550 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.1943362920 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 6506930421 ps |
| CPU time | 65.54 seconds |
| Started | Jul 12 07:36:52 PM PDT 24 |
| Finished | Jul 12 07:37:59 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-d7aa2903-6331-4f46-96f0-88402c6b3e04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943362920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.1943362920 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.1191183610 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 13825066187 ps |
| CPU time | 231.21 seconds |
| Started | Jul 12 07:36:55 PM PDT 24 |
| Finished | Jul 12 07:40:47 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-8bdcd8b6-e116-4761-9ae8-c82f891cd823 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191183610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.1191183610 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.1825867080 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 255345024 ps |
| CPU time | 23.59 seconds |
| Started | Jul 12 07:36:53 PM PDT 24 |
| Finished | Jul 12 07:37:19 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-82b6d3d3-c13c-4aa9-8af9-a73d4af67e17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825867080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.1825867080 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.3168884752 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 648902536 ps |
| CPU time | 23.01 seconds |
| Started | Jul 12 07:36:57 PM PDT 24 |
| Finished | Jul 12 07:37:21 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-0ea15c7e-00ab-4a13-8298-c12cf90b7a53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168884752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.3168884752 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.1770712488 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 225509544 ps |
| CPU time | 9.6 seconds |
| Started | Jul 12 07:36:54 PM PDT 24 |
| Finished | Jul 12 07:37:05 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-800f654b-8ea9-4daa-85f9-ae961b6c7fc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770712488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.1770712488 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.606465625 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 8800282453 ps |
| CPU time | 95.32 seconds |
| Started | Jul 12 07:36:58 PM PDT 24 |
| Finished | Jul 12 07:38:34 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-d7fdc091-b13c-4921-bd35-87d0c8735bc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606465625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.606465625 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.1037623636 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 3996904714 ps |
| CPU time | 64.98 seconds |
| Started | Jul 12 07:36:52 PM PDT 24 |
| Finished | Jul 12 07:37:58 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-8eec4c1a-21fb-480d-baf5-11a7f2835368 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037623636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.1037623636 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.3861908502 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 54749006 ps |
| CPU time | 7.28 seconds |
| Started | Jul 12 07:36:57 PM PDT 24 |
| Finished | Jul 12 07:37:05 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-77feb56a-494e-4ee4-befc-044d501ce58a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861908502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.3861908502 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.1212459355 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 4410324732 ps |
| CPU time | 344.75 seconds |
| Started | Jul 12 07:36:56 PM PDT 24 |
| Finished | Jul 12 07:42:41 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-d6c09743-dfa5-4cd7-b355-0da5a772ad78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212459355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.1212459355 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.3929644464 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 2552197840 ps |
| CPU time | 87.19 seconds |
| Started | Jul 12 07:36:52 PM PDT 24 |
| Finished | Jul 12 07:38:21 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-96c72b41-9746-4ac9-98fc-fe8112ca8641 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929644464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.3929644464 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.1986651089 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 2628960706 ps |
| CPU time | 306.82 seconds |
| Started | Jul 12 07:36:52 PM PDT 24 |
| Finished | Jul 12 07:42:00 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-05d94841-f81d-4231-9552-54350a9408e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986651089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_rand_reset.1986651089 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.1207404428 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 4529747499 ps |
| CPU time | 382.1 seconds |
| Started | Jul 12 07:36:53 PM PDT 24 |
| Finished | Jul 12 07:43:17 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-3cf0db95-7cd6-4f03-b950-09c441976d99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207404428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.1207404428 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.2630894870 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 539682149 ps |
| CPU time | 27.25 seconds |
| Started | Jul 12 07:36:52 PM PDT 24 |
| Finished | Jul 12 07:37:21 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-b7551d3f-bc1c-4276-9e14-5bb2dda5be87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630894870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.2630894870 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.425687051 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 2638717625 ps |
| CPU time | 107.1 seconds |
| Started | Jul 12 07:37:04 PM PDT 24 |
| Finished | Jul 12 07:38:53 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-7a6200f3-5020-4ac4-9992-3e156f2556b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425687051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device. 425687051 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.3575428783 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 12991773163 ps |
| CPU time | 248.73 seconds |
| Started | Jul 12 07:37:05 PM PDT 24 |
| Finished | Jul 12 07:41:16 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-14d257f3-ac70-4fe9-9aeb-67bf4aa37a57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575428783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_ device_slow_rsp.3575428783 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.2828425973 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 205689960 ps |
| CPU time | 24.09 seconds |
| Started | Jul 12 07:37:04 PM PDT 24 |
| Finished | Jul 12 07:37:29 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-a0b227ec-e648-481a-98d9-8ff2b438ae52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828425973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.2828425973 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.2768348100 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 546785116 ps |
| CPU time | 39.61 seconds |
| Started | Jul 12 07:37:03 PM PDT 24 |
| Finished | Jul 12 07:37:43 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-1eea1531-ed87-4c67-a7ed-e5323dfd84a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768348100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.2768348100 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.3099597339 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 1163781002 ps |
| CPU time | 45.17 seconds |
| Started | Jul 12 07:38:39 PM PDT 24 |
| Finished | Jul 12 07:39:25 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-027422f6-1bf4-4b81-a63f-4cb74e8ce88e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099597339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.3099597339 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.1707476833 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 64987866435 ps |
| CPU time | 791.71 seconds |
| Started | Jul 12 07:37:05 PM PDT 24 |
| Finished | Jul 12 07:50:20 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-95b379a2-788c-4ce4-8fc9-f60e677f84b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707476833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.1707476833 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.958802171 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 49781781049 ps |
| CPU time | 896.39 seconds |
| Started | Jul 12 07:37:05 PM PDT 24 |
| Finished | Jul 12 07:52:04 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-2e842cbf-c7ec-4337-a70b-360950129a1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958802171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.958802171 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.2812704110 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 511181861 ps |
| CPU time | 49.08 seconds |
| Started | Jul 12 07:37:07 PM PDT 24 |
| Finished | Jul 12 07:37:59 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-34a60ac6-0c0c-4103-8503-317797353d2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812704110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_del ays.2812704110 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.3583049157 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 1254428885 ps |
| CPU time | 40.67 seconds |
| Started | Jul 12 07:37:04 PM PDT 24 |
| Finished | Jul 12 07:37:47 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-855f4213-6073-487d-b5d2-5717fdeb21df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583049157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.3583049157 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.3816470182 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 185080270 ps |
| CPU time | 8.07 seconds |
| Started | Jul 12 07:36:56 PM PDT 24 |
| Finished | Jul 12 07:37:05 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-c3517757-a536-42f2-838f-671e3b6f7d97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816470182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.3816470182 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.1856207481 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 7258995947 ps |
| CPU time | 77.25 seconds |
| Started | Jul 12 07:36:52 PM PDT 24 |
| Finished | Jul 12 07:38:11 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-081c8e2b-d995-4b13-934b-9701f74391c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856207481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.1856207481 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.3827754620 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 5712374667 ps |
| CPU time | 97.28 seconds |
| Started | Jul 12 07:37:09 PM PDT 24 |
| Finished | Jul 12 07:38:49 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-322bc5aa-4b64-4574-8e84-82abf5b1c49e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827754620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.3827754620 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.2114484334 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 39631729 ps |
| CPU time | 5.6 seconds |
| Started | Jul 12 07:36:54 PM PDT 24 |
| Finished | Jul 12 07:37:01 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-ab60a94b-ea01-4ad3-8160-af2c9858ae42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114484334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay s.2114484334 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.526099506 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 7816462539 ps |
| CPU time | 301.96 seconds |
| Started | Jul 12 07:37:04 PM PDT 24 |
| Finished | Jul 12 07:42:08 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-932dbc0e-871f-4db5-bee8-7b9b51ecacac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526099506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.526099506 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.1669991155 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 17227742376 ps |
| CPU time | 625.4 seconds |
| Started | Jul 12 07:37:08 PM PDT 24 |
| Finished | Jul 12 07:47:35 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-5cbb7067-e0f1-4351-b11b-d7029f0b4008 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669991155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.1669991155 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.2677290929 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 451249651 ps |
| CPU time | 220.24 seconds |
| Started | Jul 12 07:37:06 PM PDT 24 |
| Finished | Jul 12 07:40:49 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-4ed49eea-14ad-4eda-a87e-a8c312611820 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677290929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_rand_reset.2677290929 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.1797065694 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 542305836 ps |
| CPU time | 222.41 seconds |
| Started | Jul 12 07:37:11 PM PDT 24 |
| Finished | Jul 12 07:40:55 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-62cdb08d-edd7-4462-aa50-a696a4fb1373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797065694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.1797065694 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.3310590936 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 53154971 ps |
| CPU time | 9.08 seconds |
| Started | Jul 12 07:37:08 PM PDT 24 |
| Finished | Jul 12 07:37:19 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-0e73fec5-4dcf-4c82-a95d-110a16ff6c49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310590936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.3310590936 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.3646850385 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 522476998 ps |
| CPU time | 22.53 seconds |
| Started | Jul 12 07:37:25 PM PDT 24 |
| Finished | Jul 12 07:37:51 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-ae2b9789-7328-4305-81f5-f107734d20ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646850385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .3646850385 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.2127298229 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 93667891695 ps |
| CPU time | 1737.3 seconds |
| Started | Jul 12 07:37:17 PM PDT 24 |
| Finished | Jul 12 08:06:16 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-3e19fd8d-d401-44ff-95d6-e3b06389a909 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127298229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_ device_slow_rsp.2127298229 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1929678481 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 177461996 ps |
| CPU time | 9.29 seconds |
| Started | Jul 12 07:37:16 PM PDT 24 |
| Finished | Jul 12 07:37:27 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-1fecd455-006e-4d93-acc1-ea17951a3d9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929678481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add r.1929678481 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.2972281542 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 262439029 ps |
| CPU time | 11.96 seconds |
| Started | Jul 12 07:37:24 PM PDT 24 |
| Finished | Jul 12 07:37:41 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-ec61e3c1-8532-46ba-9c23-beac34aba29d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972281542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.2972281542 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.3372734751 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 500364115 ps |
| CPU time | 49.13 seconds |
| Started | Jul 12 07:37:05 PM PDT 24 |
| Finished | Jul 12 07:37:56 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-37712609-f17a-4ea3-88e4-2566daff8815 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372734751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.3372734751 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.1354302364 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 10322884263 ps |
| CPU time | 117.68 seconds |
| Started | Jul 12 07:37:07 PM PDT 24 |
| Finished | Jul 12 07:39:07 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-d4ac9ca1-7484-4ead-b17d-9384051f0cc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354302364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.1354302364 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.2452776137 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 44705321901 ps |
| CPU time | 889.8 seconds |
| Started | Jul 12 07:37:17 PM PDT 24 |
| Finished | Jul 12 07:52:08 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-68879165-ea23-4fcc-8426-15ac5ebe30a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452776137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.2452776137 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.578081432 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 461849472 ps |
| CPU time | 40.95 seconds |
| Started | Jul 12 07:37:08 PM PDT 24 |
| Finished | Jul 12 07:37:51 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-5b80f8dc-3154-4851-a1bd-f8451c292d30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578081432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_dela ys.578081432 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.3153169521 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 1853978606 ps |
| CPU time | 47.89 seconds |
| Started | Jul 12 07:37:18 PM PDT 24 |
| Finished | Jul 12 07:38:07 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-263f9cb4-2c9d-43d2-bd76-0dd22374ce08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153169521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.3153169521 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.3338891071 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 213104989 ps |
| CPU time | 9.77 seconds |
| Started | Jul 12 07:37:04 PM PDT 24 |
| Finished | Jul 12 07:37:16 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-93941039-5bb5-4b91-8f61-a44f37d48680 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338891071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.3338891071 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.3476207497 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 7380282876 ps |
| CPU time | 79.7 seconds |
| Started | Jul 12 07:37:05 PM PDT 24 |
| Finished | Jul 12 07:38:27 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-54ff2795-9eba-46e8-8d46-37e7cc62919e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476207497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.3476207497 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.1065784554 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 3511023690 ps |
| CPU time | 65.19 seconds |
| Started | Jul 12 07:37:05 PM PDT 24 |
| Finished | Jul 12 07:38:12 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-d38be8ac-897f-4bd8-8fa9-2fb19ee8e8ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065784554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.1065784554 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.3653005806 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 45427862 ps |
| CPU time | 6.27 seconds |
| Started | Jul 12 07:37:04 PM PDT 24 |
| Finished | Jul 12 07:37:13 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-e8a261da-8776-457c-a1de-73c91cea0205 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653005806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.3653005806 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.711672377 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 336538080 ps |
| CPU time | 29.15 seconds |
| Started | Jul 12 07:37:15 PM PDT 24 |
| Finished | Jul 12 07:37:46 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-05fc5e13-8b3a-4af8-be87-2f128eb12530 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711672377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.711672377 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.4271889235 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 1563615267 ps |
| CPU time | 134.52 seconds |
| Started | Jul 12 07:37:15 PM PDT 24 |
| Finished | Jul 12 07:39:31 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-e7b99c5e-9510-444f-9425-db2d565c42fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271889235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.4271889235 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.3634833880 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 47365863 ps |
| CPU time | 20.4 seconds |
| Started | Jul 12 07:37:18 PM PDT 24 |
| Finished | Jul 12 07:37:39 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-6130e64d-2fa0-421a-8e98-0bda2554b74f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634833880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_rand_reset.3634833880 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.236093006 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 183132771 ps |
| CPU time | 52.86 seconds |
| Started | Jul 12 07:37:14 PM PDT 24 |
| Finished | Jul 12 07:38:08 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-3dcf4d89-f75c-4bcb-a63b-96f6a922fbe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236093006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_reset_error.236093006 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.2055891240 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 1123710589 ps |
| CPU time | 46.72 seconds |
| Started | Jul 12 07:37:15 PM PDT 24 |
| Finished | Jul 12 07:38:03 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-18c58e70-0bdd-4b68-b62e-4bd190ac7d60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055891240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.2055891240 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.1185941416 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 71168736 ps |
| CPU time | 8.39 seconds |
| Started | Jul 12 07:37:28 PM PDT 24 |
| Finished | Jul 12 07:37:41 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-ad708689-2856-4fbe-a0aa-91b9620fe5b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185941416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .1185941416 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.3734481861 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 73526490739 ps |
| CPU time | 1320.93 seconds |
| Started | Jul 12 07:37:29 PM PDT 24 |
| Finished | Jul 12 07:59:35 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-b60293c1-0ae2-468a-8d2c-6bd87846af62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734481861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.3734481861 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3831713961 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 806176522 ps |
| CPU time | 28.57 seconds |
| Started | Jul 12 07:37:33 PM PDT 24 |
| Finished | Jul 12 07:38:04 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-8ee1aaec-13be-408c-8a44-9bf6f1e8de85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831713961 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.3831713961 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.156320291 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 29605254 ps |
| CPU time | 5.86 seconds |
| Started | Jul 12 07:37:32 PM PDT 24 |
| Finished | Jul 12 07:37:41 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-be49027d-6201-43e4-b2b5-cd907e51a4c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156320291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.156320291 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.1416390406 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 2565896719 ps |
| CPU time | 92.9 seconds |
| Started | Jul 12 07:37:15 PM PDT 24 |
| Finished | Jul 12 07:38:49 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-bba5ef1f-89b9-41ed-8c67-29fc245421ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416390406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.1416390406 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.3787864488 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 52682360340 ps |
| CPU time | 643.15 seconds |
| Started | Jul 12 07:37:31 PM PDT 24 |
| Finished | Jul 12 07:48:18 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-41895ea8-5a05-474e-953b-c5bfa945d1cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787864488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.3787864488 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.536079391 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 15833531420 ps |
| CPU time | 269.62 seconds |
| Started | Jul 12 07:37:27 PM PDT 24 |
| Finished | Jul 12 07:42:02 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-0137530e-c59e-41fc-a776-67a9ca0fb3eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536079391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.536079391 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.3831029673 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 367091295 ps |
| CPU time | 32.93 seconds |
| Started | Jul 12 07:37:14 PM PDT 24 |
| Finished | Jul 12 07:37:49 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-8ff81099-7cc6-48d0-a7b9-91c167ac936c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831029673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.3831029673 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.2580875754 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 557708195 ps |
| CPU time | 37.98 seconds |
| Started | Jul 12 07:37:26 PM PDT 24 |
| Finished | Jul 12 07:38:09 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-55dec5f9-5f5e-41d6-ad9e-3c2ce45ff3c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580875754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.2580875754 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.1401420260 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 218646294 ps |
| CPU time | 8.96 seconds |
| Started | Jul 12 07:37:17 PM PDT 24 |
| Finished | Jul 12 07:37:27 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-0c84146f-d489-411f-b6c7-f4b0e5447329 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401420260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.1401420260 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.2700446377 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 7819529020 ps |
| CPU time | 90.02 seconds |
| Started | Jul 12 07:37:22 PM PDT 24 |
| Finished | Jul 12 07:38:54 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-92f4806a-4fe0-4878-bb27-759d6fc1f28c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700446377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.2700446377 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.2101270610 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 6272147885 ps |
| CPU time | 107.02 seconds |
| Started | Jul 12 07:37:17 PM PDT 24 |
| Finished | Jul 12 07:39:05 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-e9728ad2-0fa9-4784-8bd1-c96c5ecd2c04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101270610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.2101270610 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.2246075613 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 48646124 ps |
| CPU time | 5.99 seconds |
| Started | Jul 12 07:37:16 PM PDT 24 |
| Finished | Jul 12 07:37:24 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-b91199f2-060a-4f92-9ac2-5298909a4aa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246075613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.2246075613 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.976332862 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 9603684459 ps |
| CPU time | 348.47 seconds |
| Started | Jul 12 07:37:26 PM PDT 24 |
| Finished | Jul 12 07:43:20 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-936e0c8a-0b10-403b-ae95-f7247317b94d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976332862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.976332862 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.2831270200 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 7092397867 ps |
| CPU time | 406.65 seconds |
| Started | Jul 12 07:37:27 PM PDT 24 |
| Finished | Jul 12 07:44:19 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-a4641415-2242-4577-8f9c-4b720fa393a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831270200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_rand_reset.2831270200 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.181404409 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 830977609 ps |
| CPU time | 282.34 seconds |
| Started | Jul 12 07:37:26 PM PDT 24 |
| Finished | Jul 12 07:42:14 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-e1c9cf63-df0f-4ee4-a57e-90421b48429a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181404409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_reset_error.181404409 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.3930581751 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 1229779708 ps |
| CPU time | 52.59 seconds |
| Started | Jul 12 07:37:27 PM PDT 24 |
| Finished | Jul 12 07:38:25 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-deacb398-e492-451e-bc22-a3a4946e867b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930581751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.3930581751 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.264920847 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 2094970667 ps |
| CPU time | 79.32 seconds |
| Started | Jul 12 07:37:28 PM PDT 24 |
| Finished | Jul 12 07:38:52 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-da024ee3-4512-4ba3-8b5c-ca5b1bf5ae30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264920847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device. 264920847 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.4245052720 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 77817014087 ps |
| CPU time | 1498.69 seconds |
| Started | Jul 12 07:37:39 PM PDT 24 |
| Finished | Jul 12 08:02:40 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-1351885c-599b-41ae-9d2d-0d79d5a4e3aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245052720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.4245052720 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.438532302 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 76577632 ps |
| CPU time | 6.14 seconds |
| Started | Jul 12 07:37:38 PM PDT 24 |
| Finished | Jul 12 07:37:46 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-8f23b4fe-d737-4a1e-8cfc-27c8bb0ae39e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438532302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_addr .438532302 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.4010976252 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 2068900731 ps |
| CPU time | 71.36 seconds |
| Started | Jul 12 07:37:37 PM PDT 24 |
| Finished | Jul 12 07:38:50 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-aa1d3122-7186-4666-8cc1-c382cf2e45bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010976252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.4010976252 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.1247149588 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 1901903131 ps |
| CPU time | 60.35 seconds |
| Started | Jul 12 07:37:25 PM PDT 24 |
| Finished | Jul 12 07:38:31 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-35f65e1b-c252-4234-8b54-399204d92141 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247149588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.1247149588 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.2976267900 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 63749197234 ps |
| CPU time | 745.13 seconds |
| Started | Jul 12 07:37:26 PM PDT 24 |
| Finished | Jul 12 07:49:57 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-5e258d20-2caf-42e9-89a4-c92e3798c6d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976267900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.2976267900 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.4123832670 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 7414786847 ps |
| CPU time | 125.76 seconds |
| Started | Jul 12 07:37:29 PM PDT 24 |
| Finished | Jul 12 07:39:40 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-96838e52-6157-452b-a7b1-7cd64b9e0a05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123832670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.4123832670 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.3533248539 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 103723366 ps |
| CPU time | 10.79 seconds |
| Started | Jul 12 07:37:30 PM PDT 24 |
| Finished | Jul 12 07:37:45 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-f011a63a-4eb4-4808-af38-2c7ae62a82ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533248539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.3533248539 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.3582971543 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 2556803135 ps |
| CPU time | 79.56 seconds |
| Started | Jul 12 07:37:46 PM PDT 24 |
| Finished | Jul 12 07:39:08 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-ee1b5080-763a-4565-a4f5-36f818d5f3dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582971543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.3582971543 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.2562703422 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 35547415 ps |
| CPU time | 5.83 seconds |
| Started | Jul 12 07:37:32 PM PDT 24 |
| Finished | Jul 12 07:37:41 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-0928bf2d-a8f9-40c1-9533-6488346a86a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562703422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.2562703422 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.3332993282 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 9347294410 ps |
| CPU time | 102.7 seconds |
| Started | Jul 12 07:37:31 PM PDT 24 |
| Finished | Jul 12 07:39:17 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-220d414f-2d98-45a4-a185-a384f463bda2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332993282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.3332993282 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.3996380241 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 4587073418 ps |
| CPU time | 82.97 seconds |
| Started | Jul 12 07:37:30 PM PDT 24 |
| Finished | Jul 12 07:38:57 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-47b538f7-5dfd-4d5a-b376-0bfdb78a396f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996380241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.3996380241 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.2808360311 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 50629647 ps |
| CPU time | 6.86 seconds |
| Started | Jul 12 07:37:30 PM PDT 24 |
| Finished | Jul 12 07:37:41 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-a5f4c1d6-95f5-48ab-baef-a8139557de91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808360311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.2808360311 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.308350991 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 2005908522 ps |
| CPU time | 83.18 seconds |
| Started | Jul 12 07:37:45 PM PDT 24 |
| Finished | Jul 12 07:39:11 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-41741eca-d4c2-48f4-81d0-ecdbc2406fa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308350991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.308350991 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.459482683 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 736970132 ps |
| CPU time | 49.29 seconds |
| Started | Jul 12 07:37:40 PM PDT 24 |
| Finished | Jul 12 07:38:31 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-63fdeb58-b7d6-45fa-a46b-433d28be541e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459482683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.459482683 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.1288516252 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 9167828271 ps |
| CPU time | 495.47 seconds |
| Started | Jul 12 07:37:41 PM PDT 24 |
| Finished | Jul 12 07:45:58 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-36109077-2850-45b9-892d-5454545ff79f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288516252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al l_with_reset_error.1288516252 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.3577574249 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 1278841996 ps |
| CPU time | 50.63 seconds |
| Started | Jul 12 07:37:38 PM PDT 24 |
| Finished | Jul 12 07:38:31 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-b4569e71-207c-4fd7-a6e2-b81f96ea8709 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577574249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.3577574249 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.2202031308 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 2939158531 ps |
| CPU time | 106.17 seconds |
| Started | Jul 12 07:37:38 PM PDT 24 |
| Finished | Jul 12 07:39:26 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-2575125d-f240-4998-945f-95e8f2bcd6a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202031308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .2202031308 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.1496925786 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 117855513495 ps |
| CPU time | 2281.36 seconds |
| Started | Jul 12 07:37:42 PM PDT 24 |
| Finished | Jul 12 08:15:46 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-74c28608-3976-4b6d-b3ff-cf6df363b2d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496925786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.1496925786 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.343035126 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 1287744146 ps |
| CPU time | 48.62 seconds |
| Started | Jul 12 07:37:38 PM PDT 24 |
| Finished | Jul 12 07:38:29 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-6c81e92c-e27d-4e38-ad25-fd109e550cf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343035126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_addr .343035126 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.297540330 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 279035178 ps |
| CPU time | 25.36 seconds |
| Started | Jul 12 07:37:37 PM PDT 24 |
| Finished | Jul 12 07:38:04 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-5a06a7c7-d996-40e4-8071-3c16eaa3e7b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297540330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.297540330 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.3563968814 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 1536174939 ps |
| CPU time | 49.77 seconds |
| Started | Jul 12 07:37:38 PM PDT 24 |
| Finished | Jul 12 07:38:30 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-d0b64051-4928-496a-9589-fe4207c67765 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563968814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.3563968814 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.597208739 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 90081200492 ps |
| CPU time | 1061.75 seconds |
| Started | Jul 12 07:37:40 PM PDT 24 |
| Finished | Jul 12 07:55:23 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-92b03f54-893a-4f8e-a3e4-bc3bba3170a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597208739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.597208739 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.2326410102 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 15236245379 ps |
| CPU time | 269.57 seconds |
| Started | Jul 12 07:37:38 PM PDT 24 |
| Finished | Jul 12 07:42:10 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-7d3513c7-7f8f-410c-a3e3-d3186331ec2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326410102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.2326410102 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.953415348 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 206472035 ps |
| CPU time | 19.97 seconds |
| Started | Jul 12 07:37:38 PM PDT 24 |
| Finished | Jul 12 07:37:59 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-1a851d17-c9da-4081-9c6e-65f06b89a9a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953415348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_dela ys.953415348 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.495411711 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 1041319394 ps |
| CPU time | 30.75 seconds |
| Started | Jul 12 07:37:43 PM PDT 24 |
| Finished | Jul 12 07:38:16 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-2439ed64-9ca3-432c-808e-46dd230d760e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495411711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.495411711 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.68032404 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 50180886 ps |
| CPU time | 6.33 seconds |
| Started | Jul 12 07:37:38 PM PDT 24 |
| Finished | Jul 12 07:37:46 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-afbe8a42-ca51-4bce-a828-d3fb79a487c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68032404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.68032404 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.1425798703 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 8655525425 ps |
| CPU time | 97.59 seconds |
| Started | Jul 12 07:37:37 PM PDT 24 |
| Finished | Jul 12 07:39:17 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-174d825e-43ee-4023-860d-997885d17abc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425798703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.1425798703 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.2554116406 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 4941613761 ps |
| CPU time | 84.35 seconds |
| Started | Jul 12 07:37:43 PM PDT 24 |
| Finished | Jul 12 07:39:10 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-c5d92c67-dab4-4287-9a95-c72daad2bcdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554116406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.2554116406 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.865829578 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 49114567 ps |
| CPU time | 6.11 seconds |
| Started | Jul 12 07:37:40 PM PDT 24 |
| Finished | Jul 12 07:37:48 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-16958dd4-20ad-4a00-b0e0-ab68f53094b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865829578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delays .865829578 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.3862847892 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 9916664391 ps |
| CPU time | 502.91 seconds |
| Started | Jul 12 07:37:40 PM PDT 24 |
| Finished | Jul 12 07:46:04 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-784a9a36-113a-45de-a538-4a4e6ba43e6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862847892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.3862847892 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.2351781553 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 2666927115 ps |
| CPU time | 107.85 seconds |
| Started | Jul 12 07:37:46 PM PDT 24 |
| Finished | Jul 12 07:39:36 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-057738fe-f224-420a-a77a-9990a81188d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351781553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.2351781553 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.3736056758 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 4362251891 ps |
| CPU time | 341 seconds |
| Started | Jul 12 07:37:40 PM PDT 24 |
| Finished | Jul 12 07:43:23 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-14e61677-3373-4500-9168-e2e072ee5fa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736056758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.3736056758 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.1605652295 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 24520727748 ps |
| CPU time | 904.58 seconds |
| Started | Jul 12 07:37:39 PM PDT 24 |
| Finished | Jul 12 07:52:45 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-ac75fd2f-272d-4e59-8aa4-bf928f8f6377 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605652295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.1605652295 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.54492867 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 1230293218 ps |
| CPU time | 51.63 seconds |
| Started | Jul 12 07:37:37 PM PDT 24 |
| Finished | Jul 12 07:38:30 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-43cc41c6-2c75-4a75-8c52-ec5a3c7dae1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54492867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.54492867 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.2983271686 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 1195308304 ps |
| CPU time | 81.21 seconds |
| Started | Jul 12 07:37:50 PM PDT 24 |
| Finished | Jul 12 07:39:14 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-2c6bbda9-6784-4c8f-be64-70c488ff3634 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983271686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device .2983271686 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.563175732 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 15495019496 ps |
| CPU time | 247.49 seconds |
| Started | Jul 12 07:37:50 PM PDT 24 |
| Finished | Jul 12 07:42:00 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-56f9762b-d5ab-4ae2-9560-ba9f5039e0e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563175732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_d evice_slow_rsp.563175732 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.85466326 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 404356347 ps |
| CPU time | 17.98 seconds |
| Started | Jul 12 07:37:51 PM PDT 24 |
| Finished | Jul 12 07:38:11 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-ce2ec357-d394-4114-bd86-891ef85bd793 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85466326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_addr.85466326 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.2949224334 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 575690122 ps |
| CPU time | 20.63 seconds |
| Started | Jul 12 07:37:55 PM PDT 24 |
| Finished | Jul 12 07:38:17 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-c6200398-1dab-426d-be5e-c20ba9430ff8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949224334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.2949224334 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.2883030735 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 426428868 ps |
| CPU time | 39.23 seconds |
| Started | Jul 12 07:37:50 PM PDT 24 |
| Finished | Jul 12 07:38:32 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-942b8902-a8a2-481f-ae60-bae4062bdfa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883030735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.2883030735 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.1553667416 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 105545143343 ps |
| CPU time | 1265.95 seconds |
| Started | Jul 12 07:37:50 PM PDT 24 |
| Finished | Jul 12 07:58:58 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-912cef42-cf8e-499f-9a5b-f2982917dc89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553667416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.1553667416 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.825838529 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 56396511933 ps |
| CPU time | 1103.17 seconds |
| Started | Jul 12 07:37:51 PM PDT 24 |
| Finished | Jul 12 07:56:18 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-71dfa789-a152-4c23-a52d-72882265560e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825838529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.825838529 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.468860892 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 315107536 ps |
| CPU time | 27.35 seconds |
| Started | Jul 12 07:37:50 PM PDT 24 |
| Finished | Jul 12 07:38:21 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-95298d54-0f5a-413b-b6b9-efb20478ce6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468860892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_dela ys.468860892 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.2312568816 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 2787031673 ps |
| CPU time | 74.36 seconds |
| Started | Jul 12 07:37:48 PM PDT 24 |
| Finished | Jul 12 07:39:06 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-b76551a9-f548-425f-8c48-155a30d39a26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312568816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.2312568816 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.326532127 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 41698772 ps |
| CPU time | 5.92 seconds |
| Started | Jul 12 07:37:49 PM PDT 24 |
| Finished | Jul 12 07:37:58 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-f10a2e9b-d8aa-4b90-9716-9ae78f8b420f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326532127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.326532127 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.792752805 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 6133765548 ps |
| CPU time | 70.66 seconds |
| Started | Jul 12 07:37:52 PM PDT 24 |
| Finished | Jul 12 07:39:06 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-67eef664-c729-49ce-ac64-1a16cd8776af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792752805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.792752805 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.625179481 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 5558627268 ps |
| CPU time | 95.93 seconds |
| Started | Jul 12 07:37:54 PM PDT 24 |
| Finished | Jul 12 07:39:32 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-4050b3b7-02ed-4028-838c-fc08696d8a19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625179481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.625179481 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.2482577653 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 47008205 ps |
| CPU time | 6.19 seconds |
| Started | Jul 12 07:37:50 PM PDT 24 |
| Finished | Jul 12 07:37:59 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-2790ab47-3a52-4988-8d4c-3ae91355b949 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482577653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay s.2482577653 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.3726776252 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 9013264279 ps |
| CPU time | 399.05 seconds |
| Started | Jul 12 07:37:50 PM PDT 24 |
| Finished | Jul 12 07:44:32 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-4de295cd-2f72-4926-82e5-8925c205d97b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726776252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.3726776252 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.1151191583 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 8628236532 ps |
| CPU time | 347.14 seconds |
| Started | Jul 12 07:38:02 PM PDT 24 |
| Finished | Jul 12 07:43:52 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-349bae52-fc87-490e-a61e-b520ee3afe0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151191583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.1151191583 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.3791731792 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 171510542 ps |
| CPU time | 80.18 seconds |
| Started | Jul 12 07:38:02 PM PDT 24 |
| Finished | Jul 12 07:39:25 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-233d26b6-c2e7-446e-816f-afdc9fae9440 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791731792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.3791731792 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.1201165702 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 184472030 ps |
| CPU time | 121.05 seconds |
| Started | Jul 12 07:38:05 PM PDT 24 |
| Finished | Jul 12 07:40:10 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-2c1c5938-4a79-41ed-8a38-a6f5e3557d2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201165702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_al l_with_reset_error.1201165702 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.1358615482 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 437905836 ps |
| CPU time | 22 seconds |
| Started | Jul 12 07:37:52 PM PDT 24 |
| Finished | Jul 12 07:38:17 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-46c7c499-61f7-4e11-9956-ea7ac6b2de3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358615482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.1358615482 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.2719600456 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 4825744480 ps |
| CPU time | 319.07 seconds |
| Started | Jul 12 07:25:05 PM PDT 24 |
| Finished | Jul 12 07:30:27 PM PDT 24 |
| Peak memory | 596744 kb |
| Host | smart-804c03b2-6f0a-4b9a-8d07-be3c9efabac1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719600456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.2719600456 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.982254874 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 15791961846 ps |
| CPU time | 1987.79 seconds |
| Started | Jul 12 07:24:55 PM PDT 24 |
| Finished | Jul 12 07:58:06 PM PDT 24 |
| Peak memory | 593072 kb |
| Host | smart-302995ec-9027-4518-87c9-f1cd76992d0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982254874 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 9.chip_same_csr_outstanding.982254874 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.1713375529 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 3587076060 ps |
| CPU time | 155.08 seconds |
| Started | Jul 12 07:24:57 PM PDT 24 |
| Finished | Jul 12 07:27:36 PM PDT 24 |
| Peak memory | 598592 kb |
| Host | smart-7ed8fc75-c718-4094-8e3a-824a7b530ab1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713375529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.1713375529 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.1447059845 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 721032511 ps |
| CPU time | 58.69 seconds |
| Started | Jul 12 07:25:16 PM PDT 24 |
| Finished | Jul 12 07:26:18 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-fade4548-5c78-4610-8f80-244ec19e7421 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447059845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 1447059845 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.257533024 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 52161854029 ps |
| CPU time | 872.25 seconds |
| Started | Jul 12 07:25:07 PM PDT 24 |
| Finished | Jul 12 07:39:42 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-f91ec867-7ea1-4ea8-a138-16773bff8c99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257533024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_de vice_slow_rsp.257533024 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.2733979239 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 895667420 ps |
| CPU time | 37.44 seconds |
| Started | Jul 12 07:25:10 PM PDT 24 |
| Finished | Jul 12 07:25:50 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-3c972cc4-d4fd-4c6f-aae7-cecef2a4f0dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733979239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .2733979239 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.3981213357 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 536801279 ps |
| CPU time | 45.18 seconds |
| Started | Jul 12 07:25:07 PM PDT 24 |
| Finished | Jul 12 07:25:55 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-594c5a1b-e503-43f6-93ce-fe64c1408726 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981213357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3981213357 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.2841531793 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 932425798 ps |
| CPU time | 31.4 seconds |
| Started | Jul 12 07:25:08 PM PDT 24 |
| Finished | Jul 12 07:25:42 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-172a4f8b-0650-4f60-81ad-6e5723155770 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841531793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.2841531793 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.4253349948 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 55463378922 ps |
| CPU time | 612.44 seconds |
| Started | Jul 12 07:25:07 PM PDT 24 |
| Finished | Jul 12 07:35:22 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-9e5e954f-00da-4540-8572-36c647541264 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253349948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.4253349948 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.2021206665 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 13997904572 ps |
| CPU time | 238.36 seconds |
| Started | Jul 12 07:25:06 PM PDT 24 |
| Finished | Jul 12 07:29:07 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-c74aa0aa-b483-4cc5-a75a-cf51423729e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021206665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2021206665 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.3445614598 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 643112012 ps |
| CPU time | 49.87 seconds |
| Started | Jul 12 07:25:16 PM PDT 24 |
| Finished | Jul 12 07:26:09 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-f9bbf084-e4b8-48fe-ba7e-4d18109f3f86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445614598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.3445614598 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.3687202447 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 2755812363 ps |
| CPU time | 84.18 seconds |
| Started | Jul 12 07:25:08 PM PDT 24 |
| Finished | Jul 12 07:26:35 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-3ccaba61-ded2-4142-b0c7-e5859f77088f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687202447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3687202447 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.706124371 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 224954422 ps |
| CPU time | 9.75 seconds |
| Started | Jul 12 07:24:54 PM PDT 24 |
| Finished | Jul 12 07:25:08 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-87038dab-d4ee-41a1-a9de-bc94a2280103 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706124371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.706124371 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.2091205447 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 7885523977 ps |
| CPU time | 86.07 seconds |
| Started | Jul 12 07:25:06 PM PDT 24 |
| Finished | Jul 12 07:26:35 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-95d27c55-dd9c-4027-8c57-76182d1f308a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091205447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2091205447 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.1862135273 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 5791130758 ps |
| CPU time | 102.27 seconds |
| Started | Jul 12 07:25:09 PM PDT 24 |
| Finished | Jul 12 07:26:54 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-ae3c1c6c-0aac-4294-a09c-367ecb7705c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862135273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1862135273 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2097104136 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 58957215 ps |
| CPU time | 6.48 seconds |
| Started | Jul 12 07:25:07 PM PDT 24 |
| Finished | Jul 12 07:25:16 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-4aa31ce2-dd03-4c9d-9f48-33906d519f14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097104136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays .2097104136 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.623011570 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 1275125721 ps |
| CPU time | 106.44 seconds |
| Started | Jul 12 07:25:15 PM PDT 24 |
| Finished | Jul 12 07:27:04 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-4c48f4ae-0277-4bfc-9bdd-37dddf37d140 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623011570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.623011570 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.862035468 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 913304875 ps |
| CPU time | 80.27 seconds |
| Started | Jul 12 07:25:10 PM PDT 24 |
| Finished | Jul 12 07:26:32 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-36f671ac-bae9-4025-99d2-9a053f592b23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862035468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.862035468 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.2991284175 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 116338652 ps |
| CPU time | 84.88 seconds |
| Started | Jul 12 07:25:07 PM PDT 24 |
| Finished | Jul 12 07:26:34 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-e74d4cd7-a017-4f63-941d-8cee4b8d6755 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991284175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.2991284175 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.3951049682 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 229839085 ps |
| CPU time | 82.66 seconds |
| Started | Jul 12 07:25:08 PM PDT 24 |
| Finished | Jul 12 07:26:33 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-a922b821-7409-4b74-b86e-90dbd2a6fcac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951049682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all _with_reset_error.3951049682 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.2558151082 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 235612696 ps |
| CPU time | 29.52 seconds |
| Started | Jul 12 07:25:06 PM PDT 24 |
| Finished | Jul 12 07:25:38 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-80e9e1be-7886-4fcb-ac85-7bce00befc58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558151082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2558151082 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.141980924 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 1866800199 ps |
| CPU time | 75.68 seconds |
| Started | Jul 12 07:38:02 PM PDT 24 |
| Finished | Jul 12 07:39:20 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-33b04818-ace2-4b3f-a701-a2f81a8bb966 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141980924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device. 141980924 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.1350077177 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 123535542493 ps |
| CPU time | 2390.56 seconds |
| Started | Jul 12 07:38:10 PM PDT 24 |
| Finished | Jul 12 08:18:07 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-4c998100-efc0-4113-8459-bb515f18e8be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350077177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_ device_slow_rsp.1350077177 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.90608906 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 59569508 ps |
| CPU time | 8.82 seconds |
| Started | Jul 12 07:38:01 PM PDT 24 |
| Finished | Jul 12 07:38:12 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-65f4518e-dc3f-4712-aaca-83bd85c9238a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90608906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_addr.90608906 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.1165655760 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 486451272 ps |
| CPU time | 33.19 seconds |
| Started | Jul 12 07:38:01 PM PDT 24 |
| Finished | Jul 12 07:38:36 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-9e3f1fad-5e99-47ef-b068-063d727ee0fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165655760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.1165655760 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.4056632482 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 1174076929 ps |
| CPU time | 48.74 seconds |
| Started | Jul 12 07:38:05 PM PDT 24 |
| Finished | Jul 12 07:38:58 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-6faf816e-6eb8-4967-9a3e-546cd7ae4a4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056632482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.4056632482 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.1639322940 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 90570854242 ps |
| CPU time | 1125.89 seconds |
| Started | Jul 12 07:38:11 PM PDT 24 |
| Finished | Jul 12 07:57:03 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-edf5fab0-aa3f-4f5d-aa70-0492a284b2e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639322940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.1639322940 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.1962779473 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 16942550136 ps |
| CPU time | 287.68 seconds |
| Started | Jul 12 07:38:01 PM PDT 24 |
| Finished | Jul 12 07:42:51 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-027f4186-bc2e-43a2-8d1b-53d9af054475 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962779473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.1962779473 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.1673565496 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 326633285 ps |
| CPU time | 26.86 seconds |
| Started | Jul 12 07:38:00 PM PDT 24 |
| Finished | Jul 12 07:38:29 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-e1d81078-a7b4-4051-a088-2f2bf8640f8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673565496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.1673565496 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.2289091820 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 2496157586 ps |
| CPU time | 80.35 seconds |
| Started | Jul 12 07:38:01 PM PDT 24 |
| Finished | Jul 12 07:39:23 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-de11cbe9-201a-430f-ad69-6b3a36ef36a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289091820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.2289091820 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.1570267102 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 203239083 ps |
| CPU time | 9.25 seconds |
| Started | Jul 12 07:38:03 PM PDT 24 |
| Finished | Jul 12 07:38:14 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-969da2fd-e14a-4625-994f-d4ce5950667e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570267102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.1570267102 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.3937083658 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 10417466188 ps |
| CPU time | 107.45 seconds |
| Started | Jul 12 07:38:05 PM PDT 24 |
| Finished | Jul 12 07:39:57 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-83995475-8ea7-42e6-9c7a-c4bd9923203d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937083658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.3937083658 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.1925909245 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 3582202798 ps |
| CPU time | 67.01 seconds |
| Started | Jul 12 07:38:01 PM PDT 24 |
| Finished | Jul 12 07:39:09 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-36d44b9e-f4c0-4655-84dd-ce1bf1149b06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925909245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.1925909245 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.1914892743 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 49903473 ps |
| CPU time | 6.02 seconds |
| Started | Jul 12 07:38:01 PM PDT 24 |
| Finished | Jul 12 07:38:08 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-fd33f875-4986-4b7a-8472-f5132944ee6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914892743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.1914892743 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.2376530304 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 3332682615 ps |
| CPU time | 107.12 seconds |
| Started | Jul 12 07:38:11 PM PDT 24 |
| Finished | Jul 12 07:40:04 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-ce2fd011-f868-47c0-9f06-4043f88a9b90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376530304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.2376530304 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.2417159817 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 122102298 ps |
| CPU time | 15.32 seconds |
| Started | Jul 12 07:38:00 PM PDT 24 |
| Finished | Jul 12 07:38:17 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-95a6fab6-01a2-4ea3-aacd-3249f93d25d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417159817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.2417159817 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.733495248 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 1850806800 ps |
| CPU time | 119.31 seconds |
| Started | Jul 12 07:38:06 PM PDT 24 |
| Finished | Jul 12 07:40:10 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-41ae902b-08d7-4994-b9e2-15d606d027a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733495248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_ with_rand_reset.733495248 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.3710372710 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 183165650 ps |
| CPU time | 31.71 seconds |
| Started | Jul 12 07:38:03 PM PDT 24 |
| Finished | Jul 12 07:38:37 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-5a968dde-f231-4a78-9be2-cd2eb12e0fe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710372710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al l_with_reset_error.3710372710 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.3078727848 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 576485725 ps |
| CPU time | 25.83 seconds |
| Started | Jul 12 07:38:03 PM PDT 24 |
| Finished | Jul 12 07:38:31 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-ceaa0f3e-c38a-44ba-b106-d1a31bf1debf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078727848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.3078727848 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.3890792739 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 2150264107 ps |
| CPU time | 94.16 seconds |
| Started | Jul 12 07:38:19 PM PDT 24 |
| Finished | Jul 12 07:39:56 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-f164be37-f32b-40bc-8120-ee1ffe5d2e6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890792739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .3890792739 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.3238312207 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 94136955630 ps |
| CPU time | 1863.81 seconds |
| Started | Jul 12 07:38:14 PM PDT 24 |
| Finished | Jul 12 08:09:23 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-8254ebb5-5f3e-4d34-abc5-a8d7da898f13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238312207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.3238312207 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.904121696 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 35601958 ps |
| CPU time | 6.57 seconds |
| Started | Jul 12 07:38:17 PM PDT 24 |
| Finished | Jul 12 07:38:27 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-a290bab8-084e-4d0c-8920-3e46165e2484 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904121696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_addr .904121696 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.3265698019 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 1152956448 ps |
| CPU time | 37.38 seconds |
| Started | Jul 12 07:38:14 PM PDT 24 |
| Finished | Jul 12 07:38:56 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-032e8c5b-7da6-4bfe-91a5-d9d8626c9c00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265698019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.3265698019 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.1274480292 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 627363456 ps |
| CPU time | 47.67 seconds |
| Started | Jul 12 07:38:22 PM PDT 24 |
| Finished | Jul 12 07:39:12 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-ff761141-fd4a-4b2b-ac29-1ac6ac2a5bd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274480292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.1274480292 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.2928450469 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 52242425441 ps |
| CPU time | 599.9 seconds |
| Started | Jul 12 07:38:14 PM PDT 24 |
| Finished | Jul 12 07:48:19 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-ba5b310c-fbdd-43c8-b1c4-4da813dbf408 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928450469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.2928450469 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.1149137246 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 33674348378 ps |
| CPU time | 618.02 seconds |
| Started | Jul 12 07:38:22 PM PDT 24 |
| Finished | Jul 12 07:48:42 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-a936b053-40e1-4022-9ecb-579b3a65ca70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149137246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.1149137246 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.3450446880 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 39567373 ps |
| CPU time | 6.21 seconds |
| Started | Jul 12 07:38:13 PM PDT 24 |
| Finished | Jul 12 07:38:24 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-42688f2b-8a5e-4168-8666-d4a3601c84de |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450446880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.3450446880 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.1019098733 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1725797993 ps |
| CPU time | 53.03 seconds |
| Started | Jul 12 07:38:19 PM PDT 24 |
| Finished | Jul 12 07:39:14 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-c30a0da8-2ab8-45ea-b0bf-666a7b9c4f3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019098733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.1019098733 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.3407760514 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 161637158 ps |
| CPU time | 7.73 seconds |
| Started | Jul 12 07:38:14 PM PDT 24 |
| Finished | Jul 12 07:38:27 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-1e95f85d-f70d-4edb-8758-229fce13fee4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407760514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.3407760514 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.14871727 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 9257813321 ps |
| CPU time | 105.88 seconds |
| Started | Jul 12 07:38:14 PM PDT 24 |
| Finished | Jul 12 07:40:05 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-6a908401-52f1-4417-b183-a3f94b549e41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14871727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.14871727 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.37610859 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 6547249076 ps |
| CPU time | 112.39 seconds |
| Started | Jul 12 07:38:14 PM PDT 24 |
| Finished | Jul 12 07:40:12 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-0ef66470-e241-4c45-9931-61b28e5766b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37610859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.37610859 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.2667104758 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 38166260 ps |
| CPU time | 5.54 seconds |
| Started | Jul 12 07:38:22 PM PDT 24 |
| Finished | Jul 12 07:38:30 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-71d54748-dd38-48a8-b073-c93c51c69982 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667104758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay s.2667104758 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.1619557226 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 3379640900 ps |
| CPU time | 256.24 seconds |
| Started | Jul 12 07:38:14 PM PDT 24 |
| Finished | Jul 12 07:42:36 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-38133588-6a08-4ab8-83a3-73db56cf4c7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619557226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.1619557226 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.785373127 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 1578267341 ps |
| CPU time | 100.96 seconds |
| Started | Jul 12 07:38:11 PM PDT 24 |
| Finished | Jul 12 07:39:58 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-6aec1a51-106b-41b1-9ae1-82f28dce0d98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785373127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.785373127 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.2945715174 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 807636573 ps |
| CPU time | 217.69 seconds |
| Started | Jul 12 07:38:16 PM PDT 24 |
| Finished | Jul 12 07:41:58 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-3f740d72-f8c3-45e9-8561-d7606392bdde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945715174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_rand_reset.2945715174 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.3100717983 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 650961660 ps |
| CPU time | 30.12 seconds |
| Started | Jul 12 07:38:12 PM PDT 24 |
| Finished | Jul 12 07:38:48 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-89f658b6-bc56-4528-8baf-1fe463419344 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100717983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.3100717983 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.1460023191 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 144368774 ps |
| CPU time | 27.22 seconds |
| Started | Jul 12 07:38:23 PM PDT 24 |
| Finished | Jul 12 07:38:52 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-e36fd53d-6f82-4f7f-aa1f-de58d3f70681 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460023191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .1460023191 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.149017252 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 44746586221 ps |
| CPU time | 860.79 seconds |
| Started | Jul 12 07:38:22 PM PDT 24 |
| Finished | Jul 12 07:52:45 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-47c03538-a6b9-4239-94a2-68443b62b292 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149017252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_d evice_slow_rsp.149017252 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.1539168556 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 937340678 ps |
| CPU time | 35.44 seconds |
| Started | Jul 12 07:38:31 PM PDT 24 |
| Finished | Jul 12 07:39:09 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-3bdd5a65-a648-4db4-bd40-3581ea0b4999 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539168556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.1539168556 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.2542208831 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 1354098478 ps |
| CPU time | 45.08 seconds |
| Started | Jul 12 07:38:24 PM PDT 24 |
| Finished | Jul 12 07:39:12 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-bb8da957-a2d0-43e7-888e-0e6a82f19577 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542208831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.2542208831 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.1460645816 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 550948905 ps |
| CPU time | 48.03 seconds |
| Started | Jul 12 07:38:24 PM PDT 24 |
| Finished | Jul 12 07:39:15 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-e39f53c9-c089-401d-871b-5816628a0f7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460645816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.1460645816 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.3350623559 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 46650338090 ps |
| CPU time | 558.72 seconds |
| Started | Jul 12 07:38:26 PM PDT 24 |
| Finished | Jul 12 07:47:48 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-fb0c4fe9-bb6f-47de-993e-5e2d60058ee2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350623559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.3350623559 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.647252088 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 27581811686 ps |
| CPU time | 479.07 seconds |
| Started | Jul 12 07:38:26 PM PDT 24 |
| Finished | Jul 12 07:46:29 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-10b991d0-962c-488e-ad05-ffdbe09df284 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647252088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.647252088 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.2489287055 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 539916631 ps |
| CPU time | 49.64 seconds |
| Started | Jul 12 07:38:25 PM PDT 24 |
| Finished | Jul 12 07:39:18 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-f15032b0-f7bb-455f-baf5-94b59415090c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489287055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del ays.2489287055 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.2694849572 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 549769475 ps |
| CPU time | 39.99 seconds |
| Started | Jul 12 07:38:28 PM PDT 24 |
| Finished | Jul 12 07:39:12 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-be022335-6b59-456a-877e-553aac7adfb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694849572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.2694849572 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.901003177 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 143138732 ps |
| CPU time | 7.7 seconds |
| Started | Jul 12 07:38:12 PM PDT 24 |
| Finished | Jul 12 07:38:26 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-a36e2f0c-da2b-4ed6-922a-eb99cfaf8a0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901003177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.901003177 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.885960815 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 5759652010 ps |
| CPU time | 65.4 seconds |
| Started | Jul 12 07:38:31 PM PDT 24 |
| Finished | Jul 12 07:39:38 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-09956a73-29ef-45d1-aa83-b3c1279661b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885960815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.885960815 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.2173823044 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 5576983018 ps |
| CPU time | 98.92 seconds |
| Started | Jul 12 07:38:24 PM PDT 24 |
| Finished | Jul 12 07:40:06 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-8277b8d2-c810-4c2d-87b8-de36f11afc02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173823044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.2173823044 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.2121440469 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 49035515 ps |
| CPU time | 6.81 seconds |
| Started | Jul 12 07:38:23 PM PDT 24 |
| Finished | Jul 12 07:38:33 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-b686de8c-7d43-4460-9a29-2acf9216d62c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121440469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.2121440469 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.3579554364 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 3204819756 ps |
| CPU time | 265.63 seconds |
| Started | Jul 12 07:38:24 PM PDT 24 |
| Finished | Jul 12 07:42:54 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-17cf8e5d-f496-4669-b41a-80cafb724d0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579554364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.3579554364 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.2591514717 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 2082125467 ps |
| CPU time | 155.56 seconds |
| Started | Jul 12 07:39:55 PM PDT 24 |
| Finished | Jul 12 07:42:32 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-09da19b2-37ec-40a0-a9cb-305541afa776 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591514717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.2591514717 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.2752156239 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 3151852674 ps |
| CPU time | 335.03 seconds |
| Started | Jul 12 07:38:28 PM PDT 24 |
| Finished | Jul 12 07:44:07 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-eeefcc88-d045-4d5c-bcd6-dddfec5c540b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752156239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_rand_reset.2752156239 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.2094147561 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 6573549146 ps |
| CPU time | 409.16 seconds |
| Started | Jul 12 07:38:24 PM PDT 24 |
| Finished | Jul 12 07:45:17 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-88798a2e-fa7c-44a7-af37-dbe067df0a21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094147561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.2094147561 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.2658323090 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 309099937 ps |
| CPU time | 33.55 seconds |
| Started | Jul 12 07:38:23 PM PDT 24 |
| Finished | Jul 12 07:38:59 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-d23fb878-679c-4a48-8c98-139f5ea57566 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658323090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.2658323090 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.2189147655 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 456164150 ps |
| CPU time | 27.06 seconds |
| Started | Jul 12 07:38:36 PM PDT 24 |
| Finished | Jul 12 07:39:06 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-cd9fe20f-924b-4f2d-83af-9f3f54a5de75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189147655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .2189147655 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.305549145 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 147541340467 ps |
| CPU time | 3032.08 seconds |
| Started | Jul 12 07:38:46 PM PDT 24 |
| Finished | Jul 12 08:29:20 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-8e3d85fe-98ff-4aa2-958d-145b58295a2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305549145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_d evice_slow_rsp.305549145 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.169248111 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 326034205 ps |
| CPU time | 13.82 seconds |
| Started | Jul 12 07:38:41 PM PDT 24 |
| Finished | Jul 12 07:38:56 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-102d1afa-52d9-4406-9af4-99b5aab171f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169248111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_addr .169248111 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.3817175037 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 791146655 ps |
| CPU time | 26.01 seconds |
| Started | Jul 12 07:38:36 PM PDT 24 |
| Finished | Jul 12 07:39:04 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-e23c1d07-6f99-4fce-b338-278eb19ecc66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817175037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.3817175037 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.3493235123 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1249741855 ps |
| CPU time | 41.96 seconds |
| Started | Jul 12 07:38:36 PM PDT 24 |
| Finished | Jul 12 07:39:20 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-738daa80-bd90-4c0f-b013-cea683b3ec40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493235123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.3493235123 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.1199662579 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 84225001150 ps |
| CPU time | 1036.51 seconds |
| Started | Jul 12 07:38:37 PM PDT 24 |
| Finished | Jul 12 07:55:56 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-bbb3c67f-54fe-4ae0-b34f-830f7c3a0d21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199662579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.1199662579 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.279689014 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 59684398932 ps |
| CPU time | 1080.97 seconds |
| Started | Jul 12 07:38:46 PM PDT 24 |
| Finished | Jul 12 07:56:48 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-77add5ea-3c11-44fa-81cb-acd04466958f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279689014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.279689014 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.906027554 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 279885166 ps |
| CPU time | 26.34 seconds |
| Started | Jul 12 07:38:39 PM PDT 24 |
| Finished | Jul 12 07:39:07 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-a234bf99-1031-4a79-8c57-3b2fc98bed36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906027554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_dela ys.906027554 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.982123960 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 1015354701 ps |
| CPU time | 31.87 seconds |
| Started | Jul 12 07:38:39 PM PDT 24 |
| Finished | Jul 12 07:39:12 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-99f5f2dd-440d-47fd-9751-65a85e96e6be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982123960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.982123960 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.1181324548 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 197072480 ps |
| CPU time | 8.73 seconds |
| Started | Jul 12 07:38:29 PM PDT 24 |
| Finished | Jul 12 07:38:41 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-799ecf8f-ef2c-4755-8dd1-a434efa14954 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181324548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.1181324548 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.2962303881 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 8378650088 ps |
| CPU time | 88.73 seconds |
| Started | Jul 12 07:38:41 PM PDT 24 |
| Finished | Jul 12 07:40:12 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-16cf30f5-52c5-40fb-badf-88a40b79e756 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962303881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.2962303881 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.3917681956 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 5265212157 ps |
| CPU time | 88.31 seconds |
| Started | Jul 12 07:38:35 PM PDT 24 |
| Finished | Jul 12 07:40:05 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-ca2ab243-0277-4f22-9b31-786df5707a62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917681956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.3917681956 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.2585804621 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 40048567 ps |
| CPU time | 5.98 seconds |
| Started | Jul 12 07:38:35 PM PDT 24 |
| Finished | Jul 12 07:38:42 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-19536ed6-3df9-4114-b060-d2f4627b2bea |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585804621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay s.2585804621 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.3506148645 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 2578778869 ps |
| CPU time | 246.2 seconds |
| Started | Jul 12 07:38:36 PM PDT 24 |
| Finished | Jul 12 07:42:45 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-93adabd3-1e92-4489-af52-77b05f6106a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506148645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.3506148645 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.4216712684 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 10314512971 ps |
| CPU time | 379.65 seconds |
| Started | Jul 12 07:38:36 PM PDT 24 |
| Finished | Jul 12 07:44:57 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-8bc8be46-64ce-4c65-ab2c-a64e6dc7a7f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216712684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.4216712684 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.1308136486 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 4008725557 ps |
| CPU time | 378.62 seconds |
| Started | Jul 12 07:38:36 PM PDT 24 |
| Finished | Jul 12 07:44:57 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-c6032b67-178b-425b-8da4-fdfe3d6adeff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308136486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al l_with_reset_error.1308136486 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.227474464 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 1159821513 ps |
| CPU time | 47.25 seconds |
| Started | Jul 12 07:38:41 PM PDT 24 |
| Finished | Jul 12 07:39:30 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-d8e72ea4-e899-4ec6-a1e7-f44d52052c39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227474464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.227474464 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.1952640351 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 668892984 ps |
| CPU time | 52.26 seconds |
| Started | Jul 12 07:38:42 PM PDT 24 |
| Finished | Jul 12 07:39:36 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-c8ee94cb-9013-4c3f-9012-55305e34d5c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952640351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .1952640351 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.2586134310 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 80856012230 ps |
| CPU time | 1458.14 seconds |
| Started | Jul 12 07:38:53 PM PDT 24 |
| Finished | Jul 12 08:03:12 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-abfa54a9-0a18-49df-b31b-a1112b1011f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586134310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.2586134310 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.1434316790 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 193001597 ps |
| CPU time | 19.17 seconds |
| Started | Jul 12 07:38:48 PM PDT 24 |
| Finished | Jul 12 07:39:09 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-d0d72a0d-0f7c-43f2-be20-ec7af702fff5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434316790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add r.1434316790 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.762566543 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 308176965 ps |
| CPU time | 25.93 seconds |
| Started | Jul 12 07:38:57 PM PDT 24 |
| Finished | Jul 12 07:39:25 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-87529321-c3ef-40d4-acfc-d8943ebfbdb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762566543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.762566543 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.4285091258 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 422028782 ps |
| CPU time | 39.13 seconds |
| Started | Jul 12 07:38:37 PM PDT 24 |
| Finished | Jul 12 07:39:18 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-3c9d2d2e-6911-4715-ac58-e8458781310e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285091258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.4285091258 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.224982429 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 108811742874 ps |
| CPU time | 1312.07 seconds |
| Started | Jul 12 07:38:35 PM PDT 24 |
| Finished | Jul 12 08:00:29 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-9d6fde3c-a6a4-4906-bf12-d36dd47365b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224982429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.224982429 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.1006124069 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 29233437428 ps |
| CPU time | 522.89 seconds |
| Started | Jul 12 07:38:38 PM PDT 24 |
| Finished | Jul 12 07:47:23 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-f7ae356a-e819-4618-849f-38510929e33f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006124069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.1006124069 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.4157735450 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 239890619 ps |
| CPU time | 22.31 seconds |
| Started | Jul 12 07:38:36 PM PDT 24 |
| Finished | Jul 12 07:39:01 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-b2267aac-1d38-4a93-a9b9-f39d1a27a23c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157735450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.4157735450 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.3128526991 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 577677051 ps |
| CPU time | 39.15 seconds |
| Started | Jul 12 07:38:48 PM PDT 24 |
| Finished | Jul 12 07:39:29 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-3a157597-957d-4274-b3d3-5a8ece7478a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128526991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.3128526991 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.1459645698 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 41047889 ps |
| CPU time | 6.33 seconds |
| Started | Jul 12 07:38:40 PM PDT 24 |
| Finished | Jul 12 07:38:47 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-437834a7-fc95-4a9b-bfe0-93660a20b239 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459645698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.1459645698 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.2180399615 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 9298142167 ps |
| CPU time | 102.99 seconds |
| Started | Jul 12 07:38:41 PM PDT 24 |
| Finished | Jul 12 07:40:25 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-26ac0746-92aa-435f-ba31-6a56f27c1d14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180399615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.2180399615 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.4242905098 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 4734847278 ps |
| CPU time | 78.91 seconds |
| Started | Jul 12 07:38:40 PM PDT 24 |
| Finished | Jul 12 07:40:00 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-7dbc484b-5e67-4b7f-8c73-913928afefa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242905098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.4242905098 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.2969191389 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 41376254 ps |
| CPU time | 5.76 seconds |
| Started | Jul 12 07:38:36 PM PDT 24 |
| Finished | Jul 12 07:38:43 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-3a9246dd-5130-4e3d-acea-96fa711625a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969191389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay s.2969191389 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.3756619260 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 15903197117 ps |
| CPU time | 693.76 seconds |
| Started | Jul 12 07:38:51 PM PDT 24 |
| Finished | Jul 12 07:50:26 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-d406dbe6-cc16-44d2-b993-d21c80fe701c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756619260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.3756619260 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.2976795731 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 9439902561 ps |
| CPU time | 378.58 seconds |
| Started | Jul 12 07:38:51 PM PDT 24 |
| Finished | Jul 12 07:45:12 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-f97ef436-d8dd-4cc3-afd7-02efb23eef37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976795731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.2976795731 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.4162977831 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 872093085 ps |
| CPU time | 140.77 seconds |
| Started | Jul 12 07:38:50 PM PDT 24 |
| Finished | Jul 12 07:41:12 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-d769b78d-52f3-49d7-a89c-df204366ccb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162977831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.4162977831 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.3515259604 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 2912336869 ps |
| CPU time | 417.81 seconds |
| Started | Jul 12 07:38:50 PM PDT 24 |
| Finished | Jul 12 07:45:50 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-91013c86-43ba-419f-87bd-30ab99890a21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515259604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al l_with_reset_error.3515259604 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.4221031463 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 1210034831 ps |
| CPU time | 51.67 seconds |
| Started | Jul 12 07:38:52 PM PDT 24 |
| Finished | Jul 12 07:39:45 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-fec96673-b2b4-4caa-8cf5-b15982255902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221031463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.4221031463 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.510487170 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 3655959880 ps |
| CPU time | 138.1 seconds |
| Started | Jul 12 07:39:01 PM PDT 24 |
| Finished | Jul 12 07:41:21 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-20895497-8a42-4750-bb28-d62b81d4a2d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510487170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device. 510487170 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.1619432242 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 35121889957 ps |
| CPU time | 666.48 seconds |
| Started | Jul 12 07:38:58 PM PDT 24 |
| Finished | Jul 12 07:50:07 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-17a6ce34-75ea-4c93-9df0-a02e1d14ed42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619432242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_ device_slow_rsp.1619432242 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.3426742431 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 39794396 ps |
| CPU time | 6.63 seconds |
| Started | Jul 12 07:39:06 PM PDT 24 |
| Finished | Jul 12 07:39:14 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-65d75a9a-d52b-4831-81da-59b115a17eaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426742431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.3426742431 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.1232191401 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 2459753174 ps |
| CPU time | 77.02 seconds |
| Started | Jul 12 07:39:01 PM PDT 24 |
| Finished | Jul 12 07:40:21 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-85a1e800-2621-40c2-bdb7-eb4e1fea9ab8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232191401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.1232191401 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.62982177 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 502264990 ps |
| CPU time | 22.1 seconds |
| Started | Jul 12 07:38:49 PM PDT 24 |
| Finished | Jul 12 07:39:13 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-8a28c616-4ea4-4427-aa47-332235abc3be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62982177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.62982177 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.2764080959 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 69669310565 ps |
| CPU time | 787.76 seconds |
| Started | Jul 12 07:38:50 PM PDT 24 |
| Finished | Jul 12 07:51:59 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-2fedbbde-deb0-423d-aadc-f6cd272da2f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764080959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.2764080959 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.4059513455 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 18403930918 ps |
| CPU time | 340.06 seconds |
| Started | Jul 12 07:38:49 PM PDT 24 |
| Finished | Jul 12 07:44:31 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-fe802500-fa63-4e38-addc-09efd4b16bbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059513455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.4059513455 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.729059459 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 549305213 ps |
| CPU time | 45.07 seconds |
| Started | Jul 12 07:38:57 PM PDT 24 |
| Finished | Jul 12 07:39:44 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-c9da5843-a34f-4a02-a6a7-30cce0ae9424 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729059459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_dela ys.729059459 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.209948592 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 2130056046 ps |
| CPU time | 58.17 seconds |
| Started | Jul 12 07:39:04 PM PDT 24 |
| Finished | Jul 12 07:40:04 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-822c4c2d-e72d-4163-a013-ae0ab281222b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209948592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.209948592 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.1824485994 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 41872424 ps |
| CPU time | 5.88 seconds |
| Started | Jul 12 07:38:51 PM PDT 24 |
| Finished | Jul 12 07:38:59 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-c5b772c3-712b-44b2-9c00-82b57b0337a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824485994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.1824485994 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.3745789910 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 10026153547 ps |
| CPU time | 118.5 seconds |
| Started | Jul 12 07:38:51 PM PDT 24 |
| Finished | Jul 12 07:40:51 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-bc74f4c7-18bf-4863-b363-175b011990e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745789910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.3745789910 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.2954623443 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 3684511680 ps |
| CPU time | 66.68 seconds |
| Started | Jul 12 07:38:54 PM PDT 24 |
| Finished | Jul 12 07:40:01 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-8c3c84ac-09a6-49f2-8957-805e0ce8c6e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954623443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.2954623443 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.808817462 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 48981080 ps |
| CPU time | 6.71 seconds |
| Started | Jul 12 07:38:49 PM PDT 24 |
| Finished | Jul 12 07:38:58 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-ff579a56-1522-458e-b2d2-e4b27ab4a28c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808817462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delays .808817462 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.985843221 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 11148839716 ps |
| CPU time | 450.64 seconds |
| Started | Jul 12 07:39:08 PM PDT 24 |
| Finished | Jul 12 07:46:40 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-858ea3a2-edb0-42c7-b9d8-95534d1d7341 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985843221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.985843221 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.2140041144 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 12805397782 ps |
| CPU time | 563.2 seconds |
| Started | Jul 12 07:39:01 PM PDT 24 |
| Finished | Jul 12 07:48:28 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-d9ea332b-4aa0-4a23-bc8c-fc34dc9b7253 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140041144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.2140041144 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.1196869221 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 271406600 ps |
| CPU time | 97.23 seconds |
| Started | Jul 12 07:39:03 PM PDT 24 |
| Finished | Jul 12 07:40:43 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-9324297d-bf46-4c3b-b6c6-9e399d08095b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196869221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.1196869221 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.1575227428 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 29596526 ps |
| CPU time | 19.28 seconds |
| Started | Jul 12 07:39:01 PM PDT 24 |
| Finished | Jul 12 07:39:23 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-89971c9c-d864-47b9-9810-2903851644b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575227428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.1575227428 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.477126049 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 1301937319 ps |
| CPU time | 56.82 seconds |
| Started | Jul 12 07:39:01 PM PDT 24 |
| Finished | Jul 12 07:40:00 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-c7d1dbcc-e32b-44d4-a6e1-e72746505360 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477126049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.477126049 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.3191238872 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 1022100925 ps |
| CPU time | 47.26 seconds |
| Started | Jul 12 07:39:01 PM PDT 24 |
| Finished | Jul 12 07:39:51 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-aad761c2-2f2b-4bff-9b85-eb4b31c2fe79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191238872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .3191238872 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.3471910461 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 10241921317 ps |
| CPU time | 178.09 seconds |
| Started | Jul 12 07:39:01 PM PDT 24 |
| Finished | Jul 12 07:42:01 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-32a2d2df-c667-41c6-be2b-b62f413cfb43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471910461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.3471910461 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.1694166358 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 252417135 ps |
| CPU time | 13.45 seconds |
| Started | Jul 12 07:39:01 PM PDT 24 |
| Finished | Jul 12 07:39:17 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-28b30133-3911-4a2d-b440-802c84437830 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694166358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.1694166358 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.2407815336 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 1133747087 ps |
| CPU time | 38.93 seconds |
| Started | Jul 12 07:39:03 PM PDT 24 |
| Finished | Jul 12 07:39:44 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-978e3fd5-89ce-43a5-883f-562e17184b84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407815336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.2407815336 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.1812452412 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 1097493585 ps |
| CPU time | 37.89 seconds |
| Started | Jul 12 07:39:12 PM PDT 24 |
| Finished | Jul 12 07:39:52 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-bd29941a-1d2e-4116-831a-5b71b5031686 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812452412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.1812452412 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.3323228662 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 41004470430 ps |
| CPU time | 450.67 seconds |
| Started | Jul 12 07:39:01 PM PDT 24 |
| Finished | Jul 12 07:46:33 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-007491f8-8679-4b95-a449-ccde49097c92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323228662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.3323228662 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.553905469 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 18787147561 ps |
| CPU time | 324.56 seconds |
| Started | Jul 12 07:39:02 PM PDT 24 |
| Finished | Jul 12 07:44:30 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-8bdb8f39-d56a-403f-aef1-dcd96980e7b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553905469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.553905469 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.308371058 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 423520639 ps |
| CPU time | 34.15 seconds |
| Started | Jul 12 07:39:13 PM PDT 24 |
| Finished | Jul 12 07:39:49 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-a06208db-1b22-44c0-b777-5b44413dbfd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308371058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_dela ys.308371058 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.3645791758 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 1980664693 ps |
| CPU time | 56.6 seconds |
| Started | Jul 12 07:39:03 PM PDT 24 |
| Finished | Jul 12 07:40:02 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-d9da61d3-70b9-47c0-b1d9-150e20ef5c42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645791758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.3645791758 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.4117382811 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 198393008 ps |
| CPU time | 8.89 seconds |
| Started | Jul 12 07:39:01 PM PDT 24 |
| Finished | Jul 12 07:39:12 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-9645968e-9d4b-46d9-9f0d-570cbca927d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117382811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.4117382811 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.3423457296 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 9630432137 ps |
| CPU time | 101.06 seconds |
| Started | Jul 12 07:38:59 PM PDT 24 |
| Finished | Jul 12 07:40:41 PM PDT 24 |
| Peak memory | 574036 kb |
| Host | smart-8a7b200e-160a-4510-a48f-7837d91443cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423457296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.3423457296 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.4122101884 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 4407172043 ps |
| CPU time | 80.17 seconds |
| Started | Jul 12 07:39:02 PM PDT 24 |
| Finished | Jul 12 07:40:25 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-448bb6a6-9fdf-496d-833b-ea10c4a289c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122101884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.4122101884 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.3172744484 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 42670817 ps |
| CPU time | 6.33 seconds |
| Started | Jul 12 07:39:00 PM PDT 24 |
| Finished | Jul 12 07:39:08 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-1b3a2586-d108-4ce5-ac44-67c18ce6af6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172744484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.3172744484 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.63291415 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 5472189412 ps |
| CPU time | 184.12 seconds |
| Started | Jul 12 07:39:04 PM PDT 24 |
| Finished | Jul 12 07:42:10 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-e44766e1-2b69-4649-9d84-475c60af0fd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63291415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.63291415 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.2551637315 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 13561820933 ps |
| CPU time | 537.65 seconds |
| Started | Jul 12 07:39:11 PM PDT 24 |
| Finished | Jul 12 07:48:11 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-bc57b6e0-d51d-4bd8-8f3d-166cbf9dbadc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551637315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.2551637315 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.715751844 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 8851009801 ps |
| CPU time | 558.82 seconds |
| Started | Jul 12 07:39:14 PM PDT 24 |
| Finished | Jul 12 07:48:35 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-07d170d3-3683-4700-b451-8f5433d8316e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715751844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_ with_rand_reset.715751844 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.3523185528 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 177878659 ps |
| CPU time | 65.12 seconds |
| Started | Jul 12 07:39:12 PM PDT 24 |
| Finished | Jul 12 07:40:20 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-6a3f877c-abc8-4bc6-be9b-2f57411b2ce3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523185528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al l_with_reset_error.3523185528 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.2365471242 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 98143119 ps |
| CPU time | 14.13 seconds |
| Started | Jul 12 07:39:13 PM PDT 24 |
| Finished | Jul 12 07:39:29 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-3eab946b-1cf1-4715-a573-763d45757300 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365471242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.2365471242 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.843165332 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 3115633311 ps |
| CPU time | 114.81 seconds |
| Started | Jul 12 07:39:16 PM PDT 24 |
| Finished | Jul 12 07:41:12 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-41ec88e4-2f6e-4607-be4e-51df5d5f97c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843165332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device. 843165332 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.1825722265 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 30881220758 ps |
| CPU time | 572.8 seconds |
| Started | Jul 12 07:39:20 PM PDT 24 |
| Finished | Jul 12 07:48:54 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-c2c581c8-0db8-4124-9024-f9de88ed9b8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825722265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.1825722265 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.4149644572 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 1184425206 ps |
| CPU time | 49.45 seconds |
| Started | Jul 12 07:39:27 PM PDT 24 |
| Finished | Jul 12 07:40:18 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-eb5bae16-995a-4a4c-8bc2-ec9d30f432de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149644572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.4149644572 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.753873819 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 239085678 ps |
| CPU time | 20.01 seconds |
| Started | Jul 12 07:39:23 PM PDT 24 |
| Finished | Jul 12 07:39:45 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-b17d984f-7867-4d06-9540-61b030972fea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753873819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.753873819 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.4251298339 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 498115732 ps |
| CPU time | 40.02 seconds |
| Started | Jul 12 07:39:16 PM PDT 24 |
| Finished | Jul 12 07:39:57 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-d6a39530-43c6-4eb0-b387-d03fcf949898 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251298339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.4251298339 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.625574978 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 110334288341 ps |
| CPU time | 1289.62 seconds |
| Started | Jul 12 07:39:09 PM PDT 24 |
| Finished | Jul 12 08:00:40 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-bebc38f3-6db1-4aeb-8d65-1afe97bb0670 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625574978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.625574978 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.2376279177 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 33871940967 ps |
| CPU time | 681.96 seconds |
| Started | Jul 12 07:39:11 PM PDT 24 |
| Finished | Jul 12 07:50:34 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-68ac60c3-d07a-4bf9-bbc5-266c64361bf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376279177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.2376279177 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.383185949 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 575499452 ps |
| CPU time | 51.61 seconds |
| Started | Jul 12 07:39:10 PM PDT 24 |
| Finished | Jul 12 07:40:04 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-c8e35363-bced-4ffd-8158-359d3625e50a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383185949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_dela ys.383185949 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.853329724 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 459560432 ps |
| CPU time | 15.56 seconds |
| Started | Jul 12 07:39:24 PM PDT 24 |
| Finished | Jul 12 07:39:41 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-62386d50-fd8e-494f-9f34-4362ebeb5778 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853329724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.853329724 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.2500868235 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 163439874 ps |
| CPU time | 7.83 seconds |
| Started | Jul 12 07:39:12 PM PDT 24 |
| Finished | Jul 12 07:39:21 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-9abbf7cf-71f1-44e4-91b7-4e473bcef84b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500868235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.2500868235 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.496986945 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 8997925526 ps |
| CPU time | 104.35 seconds |
| Started | Jul 12 07:39:12 PM PDT 24 |
| Finished | Jul 12 07:40:59 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-80d53c15-2295-4981-9e41-28daf5ab3171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496986945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.496986945 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.966384274 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 5178976826 ps |
| CPU time | 88.91 seconds |
| Started | Jul 12 07:39:10 PM PDT 24 |
| Finished | Jul 12 07:40:40 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-2d488470-1d69-4d9d-9e7f-c1919abc77a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966384274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.966384274 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.1645272074 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 49179600 ps |
| CPU time | 6.01 seconds |
| Started | Jul 12 07:39:13 PM PDT 24 |
| Finished | Jul 12 07:39:21 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-610ef88c-7296-4121-b9b9-028cbaa84212 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645272074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.1645272074 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.3025564277 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 12833147702 ps |
| CPU time | 495.21 seconds |
| Started | Jul 12 07:39:24 PM PDT 24 |
| Finished | Jul 12 07:47:41 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-799e06e8-aa21-4f58-8518-4c58d9facc13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025564277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.3025564277 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.1926578803 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 290942943 ps |
| CPU time | 12.06 seconds |
| Started | Jul 12 07:39:24 PM PDT 24 |
| Finished | Jul 12 07:39:38 PM PDT 24 |
| Peak memory | 575148 kb |
| Host | smart-ce7e2102-63bc-429b-9796-e9938f5497fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926578803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.1926578803 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.1996174046 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 7861188346 ps |
| CPU time | 916.45 seconds |
| Started | Jul 12 07:39:25 PM PDT 24 |
| Finished | Jul 12 07:54:43 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-cba3fe57-9b7f-4587-ba22-398277b2b911 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996174046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.1996174046 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.821566938 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 339425433 ps |
| CPU time | 104.09 seconds |
| Started | Jul 12 07:39:26 PM PDT 24 |
| Finished | Jul 12 07:41:11 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-8bb23944-4042-4136-913a-22138b3ec0c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821566938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_reset_error.821566938 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.614772894 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 133433992 ps |
| CPU time | 17.19 seconds |
| Started | Jul 12 07:39:29 PM PDT 24 |
| Finished | Jul 12 07:39:47 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-2fb7e693-567c-4962-8a6e-a20fc7eb6152 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614772894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.614772894 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.116420935 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 272936912 ps |
| CPU time | 20.78 seconds |
| Started | Jul 12 07:39:24 PM PDT 24 |
| Finished | Jul 12 07:39:46 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-fa389a59-4f60-4351-9e05-db75d990b644 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116420935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device. 116420935 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.2765640794 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 63133471160 ps |
| CPU time | 1282.08 seconds |
| Started | Jul 12 07:39:22 PM PDT 24 |
| Finished | Jul 12 08:00:46 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-5c93f6a8-e76a-4cf6-a0b5-2f6b0bfdd4d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765640794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_ device_slow_rsp.2765640794 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.197606962 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 106758599 ps |
| CPU time | 14.34 seconds |
| Started | Jul 12 07:39:24 PM PDT 24 |
| Finished | Jul 12 07:39:40 PM PDT 24 |
| Peak memory | 575164 kb |
| Host | smart-ca725882-9681-45e5-b96f-f4e07bb847ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197606962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_addr .197606962 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.687612398 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 944951135 ps |
| CPU time | 32.64 seconds |
| Started | Jul 12 07:39:26 PM PDT 24 |
| Finished | Jul 12 07:40:00 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-0b677bfb-f5e8-4293-a417-4ecfbace6948 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687612398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.687612398 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.1791471548 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 2521875993 ps |
| CPU time | 102.23 seconds |
| Started | Jul 12 07:39:24 PM PDT 24 |
| Finished | Jul 12 07:41:08 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-17cae2ae-4e05-48a6-8113-6017ccad3f2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791471548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.1791471548 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.3900547545 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 6533090501 ps |
| CPU time | 74.04 seconds |
| Started | Jul 12 07:39:23 PM PDT 24 |
| Finished | Jul 12 07:40:39 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-f7a74ef4-c49f-444f-b0f8-d788b3b29483 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900547545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.3900547545 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.3060182498 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 26392364297 ps |
| CPU time | 494.36 seconds |
| Started | Jul 12 07:39:23 PM PDT 24 |
| Finished | Jul 12 07:47:39 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-c07b3dd9-cdd9-4f63-9688-3d6067b36daa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060182498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.3060182498 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.1394096322 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 308271439 ps |
| CPU time | 31.84 seconds |
| Started | Jul 12 07:39:22 PM PDT 24 |
| Finished | Jul 12 07:39:56 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-b85e4d12-52e7-4504-aa58-26ac4602acaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394096322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.1394096322 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.2692632938 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 1588900419 ps |
| CPU time | 47.84 seconds |
| Started | Jul 12 07:39:23 PM PDT 24 |
| Finished | Jul 12 07:40:13 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-5f5b4056-ec49-4c02-9b14-788a80f84307 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692632938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.2692632938 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.43107090 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 48409329 ps |
| CPU time | 6.16 seconds |
| Started | Jul 12 07:39:27 PM PDT 24 |
| Finished | Jul 12 07:39:35 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-256a9343-1caf-4d48-822b-6b24d7b8e944 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43107090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.43107090 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.2076460389 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 8941323896 ps |
| CPU time | 102.02 seconds |
| Started | Jul 12 07:39:22 PM PDT 24 |
| Finished | Jul 12 07:41:06 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-4270d5e9-56a0-4916-a21d-423f6a0e23fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076460389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.2076460389 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.73293548 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 5306891870 ps |
| CPU time | 97.02 seconds |
| Started | Jul 12 07:39:22 PM PDT 24 |
| Finished | Jul 12 07:41:01 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-9540448a-5717-41ce-8891-bea920445a5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73293548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.73293548 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.2826724570 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 42855416 ps |
| CPU time | 6.06 seconds |
| Started | Jul 12 07:39:22 PM PDT 24 |
| Finished | Jul 12 07:39:30 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-9aed9366-5c20-4a28-bc7a-7285325f3d42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826724570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay s.2826724570 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.3728080649 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 1436741087 ps |
| CPU time | 108.56 seconds |
| Started | Jul 12 07:39:23 PM PDT 24 |
| Finished | Jul 12 07:41:13 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-6f8d7124-fe31-43a1-9691-8b16749f69c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728080649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.3728080649 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.587734526 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 2793007706 ps |
| CPU time | 236.41 seconds |
| Started | Jul 12 07:39:23 PM PDT 24 |
| Finished | Jul 12 07:43:22 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-66fd030e-060c-451f-ab88-296c76d1e9dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587734526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.587734526 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.2648689345 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 152864800 ps |
| CPU time | 78.6 seconds |
| Started | Jul 12 07:39:27 PM PDT 24 |
| Finished | Jul 12 07:40:47 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-83f55b71-820f-4768-a374-9e51a1d3cbb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648689345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.2648689345 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.677934336 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 5773084382 ps |
| CPU time | 578.15 seconds |
| Started | Jul 12 07:39:28 PM PDT 24 |
| Finished | Jul 12 07:49:08 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-1dec1d04-87e5-450f-8f43-4a645059f919 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677934336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_reset_error.677934336 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.2471606859 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 191346529 ps |
| CPU time | 11.02 seconds |
| Started | Jul 12 07:39:27 PM PDT 24 |
| Finished | Jul 12 07:39:39 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-e0eedac8-8466-46f9-ba2d-9ad35e971860 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471606859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.2471606859 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.1260832995 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 3400034166 ps |
| CPU time | 140.82 seconds |
| Started | Jul 12 07:39:34 PM PDT 24 |
| Finished | Jul 12 07:41:57 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-8bdb3b81-1d73-4901-9498-df9dd8aec693 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260832995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device .1260832995 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.819530010 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 112729857471 ps |
| CPU time | 2330.81 seconds |
| Started | Jul 12 07:39:34 PM PDT 24 |
| Finished | Jul 12 08:18:27 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-93cb00cc-cdd5-43ec-928f-ef380507704d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819530010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_d evice_slow_rsp.819530010 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.154385666 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 201362083 ps |
| CPU time | 11.28 seconds |
| Started | Jul 12 07:39:36 PM PDT 24 |
| Finished | Jul 12 07:39:49 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-20c933e4-5842-41da-9900-98e84c25a0b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154385666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_addr .154385666 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.1235644108 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 1268110850 ps |
| CPU time | 40.32 seconds |
| Started | Jul 12 07:39:35 PM PDT 24 |
| Finished | Jul 12 07:40:17 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-fa95311d-5298-493a-a6b4-ce1250b87f77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235644108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.1235644108 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.2221756060 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 911231184 ps |
| CPU time | 37.39 seconds |
| Started | Jul 12 07:39:34 PM PDT 24 |
| Finished | Jul 12 07:40:14 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-b00bf2c9-1da9-45aa-acf6-ad5c5abe3189 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221756060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.2221756060 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.3402764186 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 94584482272 ps |
| CPU time | 1165.14 seconds |
| Started | Jul 12 07:39:34 PM PDT 24 |
| Finished | Jul 12 07:59:01 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-6641c18c-cebd-46ca-a8b5-f33d3bde2081 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402764186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.3402764186 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.722757145 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 17520732062 ps |
| CPU time | 325.38 seconds |
| Started | Jul 12 07:39:35 PM PDT 24 |
| Finished | Jul 12 07:45:03 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-10616f36-b0f3-4bc4-8c4a-37fd68723d91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722757145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.722757145 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.2306783297 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 607528804 ps |
| CPU time | 51.36 seconds |
| Started | Jul 12 07:39:45 PM PDT 24 |
| Finished | Jul 12 07:40:37 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-67ce979f-381b-4765-9ba2-d6235e28ba6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306783297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.2306783297 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.4034280202 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 260071262 ps |
| CPU time | 20.62 seconds |
| Started | Jul 12 07:39:34 PM PDT 24 |
| Finished | Jul 12 07:39:57 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-04ac2a5e-4718-415e-a422-b1a3892f8372 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034280202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.4034280202 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.3453514349 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 220821082 ps |
| CPU time | 10.84 seconds |
| Started | Jul 12 07:39:27 PM PDT 24 |
| Finished | Jul 12 07:39:39 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-1dd3a153-181f-4243-a892-54e660f0ecad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453514349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.3453514349 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.3191992430 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 7486037234 ps |
| CPU time | 85.49 seconds |
| Started | Jul 12 07:39:36 PM PDT 24 |
| Finished | Jul 12 07:41:03 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-7d225095-3611-4ac9-9f33-c9d13117d526 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191992430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.3191992430 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.4062867062 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 6055714217 ps |
| CPU time | 103.09 seconds |
| Started | Jul 12 07:39:34 PM PDT 24 |
| Finished | Jul 12 07:41:20 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-a0fb99ef-6daf-4ba2-8121-afb64b329468 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062867062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.4062867062 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.1521618608 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 35561136 ps |
| CPU time | 6.06 seconds |
| Started | Jul 12 07:39:26 PM PDT 24 |
| Finished | Jul 12 07:39:33 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-dfaebbcd-feeb-4775-8416-275e64c5db8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521618608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay s.1521618608 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.1717295800 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 6833943086 ps |
| CPU time | 264.99 seconds |
| Started | Jul 12 07:39:34 PM PDT 24 |
| Finished | Jul 12 07:44:01 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-f7dc8dfd-cc83-41bc-9ce8-95a09b1d4f4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717295800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.1717295800 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.2513106011 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 247951068 ps |
| CPU time | 51.85 seconds |
| Started | Jul 12 07:39:35 PM PDT 24 |
| Finished | Jul 12 07:40:29 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-4872bc41-bb02-42a4-a993-62abd07e15ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513106011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_rand_reset.2513106011 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.953812216 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 16217405023 ps |
| CPU time | 910.47 seconds |
| Started | Jul 12 07:39:34 PM PDT 24 |
| Finished | Jul 12 07:54:47 PM PDT 24 |
| Peak memory | 576424 kb |
| Host | smart-3424d1be-e294-4def-9a9c-7c9feaf07537 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953812216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_reset_error.953812216 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.317796550 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 1238878035 ps |
| CPU time | 55.18 seconds |
| Started | Jul 12 07:39:34 PM PDT 24 |
| Finished | Jul 12 07:40:31 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-0470ca3b-52ff-4af8-8464-662593116da7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317796550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.317796550 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.2924772853 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 13792144360 ps |
| CPU time | 1395.36 seconds |
| Started | Jul 12 07:41:37 PM PDT 24 |
| Finished | Jul 12 08:04:55 PM PDT 24 |
| Peak memory | 608372 kb |
| Host | smart-a703bfed-3029-4c73-a92c-a4b31da6115a |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924772853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.2 924772853 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3419627420 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 4508215352 ps |
| CPU time | 509.4 seconds |
| Started | Jul 12 07:51:57 PM PDT 24 |
| Finished | Jul 12 08:00:28 PM PDT 24 |
| Peak memory | 620220 kb |
| Host | smart-25b20c26-0fcf-4444-a8b4-dbd9af415ed6 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 419627420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.3419627420 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.2073124740 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 3340648640 ps |
| CPU time | 279.04 seconds |
| Started | Jul 12 07:47:02 PM PDT 24 |
| Finished | Jul 12 07:51:42 PM PDT 24 |
| Peak memory | 609708 kb |
| Host | smart-fdf638a8-1630-4899-a0c3-5ee87a325275 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2073124740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.2073124740 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.4137528716 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 2718946904 ps |
| CPU time | 262.21 seconds |
| Started | Jul 12 07:50:30 PM PDT 24 |
| Finished | Jul 12 07:54:53 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-d9decc96-bd1e-4fc6-93e0-47656d0d00a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137528716 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.4137528716 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1189059871 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 2177759392 ps |
| CPU time | 210.5 seconds |
| Started | Jul 12 07:49:20 PM PDT 24 |
| Finished | Jul 12 07:52:51 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-58b161f8-523a-45ba-8baa-a15565c359d3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189 059871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.1189059871 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3129229135 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 2669463389 ps |
| CPU time | 192.24 seconds |
| Started | Jul 12 07:49:11 PM PDT 24 |
| Finished | Jul 12 07:52:24 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-828861f8-9fb4-4b08-aac7-03c254724977 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129229135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.3129229135 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.1878260505 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 3301308664 ps |
| CPU time | 316.58 seconds |
| Started | Jul 12 07:51:22 PM PDT 24 |
| Finished | Jul 12 07:56:41 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-86eec3d6-d955-425f-acf7-a52edc23a280 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878260505 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.1878260505 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.501512168 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 3162691444 ps |
| CPU time | 329.45 seconds |
| Started | Jul 12 07:48:56 PM PDT 24 |
| Finished | Jul 12 07:54:26 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-728d8db7-f994-48a4-bba5-823cb66ad26b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501512168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.501512168 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.3621656530 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 3547923186 ps |
| CPU time | 294.95 seconds |
| Started | Jul 12 07:47:43 PM PDT 24 |
| Finished | Jul 12 07:52:38 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-6a27cf95-e4ad-4e3d-b769-4b59aaf4dff6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621656530 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.3621656530 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.2273090565 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 2402072000 ps |
| CPU time | 247.71 seconds |
| Started | Jul 12 07:50:52 PM PDT 24 |
| Finished | Jul 12 07:55:01 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-650170eb-6e16-4343-b79f-54c42839eee5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273090565 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.2273090565 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.2127856720 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 3396879555 ps |
| CPU time | 248.8 seconds |
| Started | Jul 12 07:48:25 PM PDT 24 |
| Finished | Jul 12 07:52:35 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-4f3c9e02-0dcb-45f3-87f4-0444e342383e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2127856720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.2127856720 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3962559885 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 5301059940 ps |
| CPU time | 570.2 seconds |
| Started | Jul 12 07:49:03 PM PDT 24 |
| Finished | Jul 12 07:58:34 PM PDT 24 |
| Peak memory | 619664 kb |
| Host | smart-62992ae7-80ea-4277-80ed-05784657cdcc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3962559885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.3962559885 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2897925754 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 8014154560 ps |
| CPU time | 2216.37 seconds |
| Started | Jul 12 07:51:10 PM PDT 24 |
| Finished | Jul 12 08:28:08 PM PDT 24 |
| Peak memory | 610768 kb |
| Host | smart-2e26fa8c-9bab-4bd5-b686-bf24863681a4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897925754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.2897925754 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.835350599 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 9310532600 ps |
| CPU time | 1085.8 seconds |
| Started | Jul 12 07:48:53 PM PDT 24 |
| Finished | Jul 12 08:06:59 PM PDT 24 |
| Peak memory | 611224 kb |
| Host | smart-488e3ef8-26f7-45ab-b828-4bdcdc2b0d9a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835350599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.835350599 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3908735190 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 8471914832 ps |
| CPU time | 1549.69 seconds |
| Started | Jul 12 07:49:40 PM PDT 24 |
| Finished | Jul 12 08:15:31 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-db4f4ed6-dc63-4017-a330-18ce29762bf2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3908735190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.3908735190 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.4109098113 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 2968733800 ps |
| CPU time | 308.64 seconds |
| Started | Jul 12 07:54:21 PM PDT 24 |
| Finished | Jul 12 07:59:31 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-4dce1411-5c59-4276-a2d3-e2e7018b5ae7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4109098113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.4109098113 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2415616243 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 255004190344 ps |
| CPU time | 11874.7 seconds |
| Started | Jul 12 07:48:29 PM PDT 24 |
| Finished | Jul 12 11:06:26 PM PDT 24 |
| Peak memory | 611280 kb |
| Host | smart-80befb23-8f6c-4740-b83c-c789f50fce2c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2415616243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2415616243 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.1096616805 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 3428607500 ps |
| CPU time | 379.52 seconds |
| Started | Jul 12 07:58:41 PM PDT 24 |
| Finished | Jul 12 08:05:01 PM PDT 24 |
| Peak memory | 610172 kb |
| Host | smart-d0d0fedf-1873-4627-9a76-ed049357b176 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096616805 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.1096616805 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1222861198 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 6951069800 ps |
| CPU time | 510.46 seconds |
| Started | Jul 12 07:50:17 PM PDT 24 |
| Finished | Jul 12 07:58:49 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-f1df21fd-1591-4219-b1d6-f9397106018f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1222861198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1222861198 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1399275004 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 2871648040 ps |
| CPU time | 241.47 seconds |
| Started | Jul 12 07:54:47 PM PDT 24 |
| Finished | Jul 12 07:58:50 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-fd609c52-b803-4b70-adb4-84de5c3d6a90 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399275004 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_aon_timer_smoketest.1399275004 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1512083738 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 10486133864 ps |
| CPU time | 1010.47 seconds |
| Started | Jul 12 07:56:34 PM PDT 24 |
| Finished | Jul 12 08:13:26 PM PDT 24 |
| Peak memory | 609924 kb |
| Host | smart-00c78150-c7c1-45f3-8878-196af19d444f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1512083738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.1512083738 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2545171059 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 4744447518 ps |
| CPU time | 680.9 seconds |
| Started | Jul 12 07:50:32 PM PDT 24 |
| Finished | Jul 12 08:01:54 PM PDT 24 |
| Peak memory | 611116 kb |
| Host | smart-20162efd-6a87-4220-bdc9-8418245b7264 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2545171059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.2545171059 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.2313663134 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 7478110190 ps |
| CPU time | 829.2 seconds |
| Started | Jul 12 07:50:49 PM PDT 24 |
| Finished | Jul 12 08:04:40 PM PDT 24 |
| Peak memory | 617200 kb |
| Host | smart-2df54899-de81-42c4-a24b-933598ee8661 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313663134 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.2313663134 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3845689381 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 4835388315 ps |
| CPU time | 547.58 seconds |
| Started | Jul 12 07:50:16 PM PDT 24 |
| Finished | Jul 12 07:59:25 PM PDT 24 |
| Peak memory | 621720 kb |
| Host | smart-272a7143-728c-4a88-a383-77f1bd8eb703 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3845689381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.3845689381 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2455308727 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 4158987144 ps |
| CPU time | 851.94 seconds |
| Started | Jul 12 07:49:57 PM PDT 24 |
| Finished | Jul 12 08:04:10 PM PDT 24 |
| Peak memory | 613248 kb |
| Host | smart-e5405d88-ce22-4294-9b6e-37128e7dd151 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455308727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.2455308727 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2269379014 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 3979710094 ps |
| CPU time | 720.3 seconds |
| Started | Jul 12 07:51:45 PM PDT 24 |
| Finished | Jul 12 08:03:47 PM PDT 24 |
| Peak memory | 613340 kb |
| Host | smart-d28c99c6-27f8-466a-8e63-ca11f151a578 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269379014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2269379014 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1662777540 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 5324055102 ps |
| CPU time | 657.06 seconds |
| Started | Jul 12 07:52:10 PM PDT 24 |
| Finished | Jul 12 08:03:08 PM PDT 24 |
| Peak memory | 613112 kb |
| Host | smart-33bbdec4-6def-4ea3-a438-7c5da6d5707a |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662777540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1662777540 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.979600430 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 5084011080 ps |
| CPU time | 751.83 seconds |
| Started | Jul 12 07:50:16 PM PDT 24 |
| Finished | Jul 12 08:02:49 PM PDT 24 |
| Peak memory | 613312 kb |
| Host | smart-e982bea3-f88a-4a0c-9287-f05ee230d75f |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979600430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_slow_rma.979600430 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2281822744 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 5045603238 ps |
| CPU time | 834.66 seconds |
| Started | Jul 12 07:49:19 PM PDT 24 |
| Finished | Jul 12 08:03:14 PM PDT 24 |
| Peak memory | 613344 kb |
| Host | smart-23ba4e00-e81e-45b3-b587-b719cf5173af |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281822744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2281822744 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.2898129342 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 2216295777 ps |
| CPU time | 215.86 seconds |
| Started | Jul 12 07:50:33 PM PDT 24 |
| Finished | Jul 12 07:54:10 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-8ca1cb8b-0f2d-40b6-bcbf-43338014cb76 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898129342 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.2898129342 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1500000360 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 3800374866 ps |
| CPU time | 411.18 seconds |
| Started | Jul 12 07:49:13 PM PDT 24 |
| Finished | Jul 12 07:56:05 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-96e09b12-c2ba-4a70-a830-ee2ec6757b6e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500000360 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.1500000360 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1726199019 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 3343386797 ps |
| CPU time | 239.22 seconds |
| Started | Jul 12 07:52:58 PM PDT 24 |
| Finished | Jul 12 07:56:58 PM PDT 24 |
| Peak memory | 609668 kb |
| Host | smart-2d3adf92-adfa-46cb-8f27-be36b018ef51 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726199019 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.1726199019 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3204003497 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 4474084956 ps |
| CPU time | 478.04 seconds |
| Started | Jul 12 07:54:28 PM PDT 24 |
| Finished | Jul 12 08:02:26 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-f6f69d26-2a95-466a-b36e-7a06e6ac8e90 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204003497 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.3204003497 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2166223783 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 4458268710 ps |
| CPU time | 370.46 seconds |
| Started | Jul 12 07:51:39 PM PDT 24 |
| Finished | Jul 12 07:57:50 PM PDT 24 |
| Peak memory | 610720 kb |
| Host | smart-170b9f4d-29d0-479d-a253-6fccbfe860b8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166223783 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.2166223783 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.791669332 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 4695094964 ps |
| CPU time | 392.54 seconds |
| Started | Jul 12 07:50:14 PM PDT 24 |
| Finished | Jul 12 07:56:48 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-18add839-3494-46b5-8859-593c727b4c20 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791669332 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.791669332 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2242554495 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 3980304750 ps |
| CPU time | 410.97 seconds |
| Started | Jul 12 07:51:10 PM PDT 24 |
| Finished | Jul 12 07:58:03 PM PDT 24 |
| Peak memory | 610428 kb |
| Host | smart-4cf652af-917c-45d3-b609-98707574441b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242554495 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.2242554495 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2895800937 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 11292376376 ps |
| CPU time | 1257.87 seconds |
| Started | Jul 12 07:50:25 PM PDT 24 |
| Finished | Jul 12 08:11:24 PM PDT 24 |
| Peak memory | 610988 kb |
| Host | smart-0d0f9e7c-9566-4de1-9c3d-08785b7a5854 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895800937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.2895800937 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2585336558 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 3329325932 ps |
| CPU time | 299.99 seconds |
| Started | Jul 12 07:49:17 PM PDT 24 |
| Finished | Jul 12 07:54:18 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-3c122d5f-f979-4b41-bab8-2061e6627252 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585336558 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.2585336558 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3637316666 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 4584971552 ps |
| CPU time | 720.38 seconds |
| Started | Jul 12 07:50:50 PM PDT 24 |
| Finished | Jul 12 08:02:52 PM PDT 24 |
| Peak memory | 610476 kb |
| Host | smart-b29e445d-a9a0-45eb-b66d-d7f975cb0e11 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637316666 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.3637316666 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.113822512 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 2669610104 ps |
| CPU time | 221.82 seconds |
| Started | Jul 12 07:51:56 PM PDT 24 |
| Finished | Jul 12 07:55:40 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-f198873a-aafb-4306-bd7a-9b286602f6f3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113822512 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_clkmgr_smoketest.113822512 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_coremark.2476447262 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 70926874298 ps |
| CPU time | 14147.8 seconds |
| Started | Jul 12 07:48:44 PM PDT 24 |
| Finished | Jul 12 11:44:34 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-a231ae76-8565-4c60-89ce-edbe05b76ea0 |
| User | root |
| Command | /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2476447262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.2476447262 |
| Directory | /workspace/0.chip_sw_coremark/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2750945041 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 16100268914 ps |
| CPU time | 4820.74 seconds |
| Started | Jul 12 07:49:21 PM PDT 24 |
| Finished | Jul 12 09:09:43 PM PDT 24 |
| Peak memory | 609704 kb |
| Host | smart-c029d663-8500-4a65-a647-0e34616b4272 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750945041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.2750945041 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3784629915 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 4896634326 ps |
| CPU time | 496.95 seconds |
| Started | Jul 12 07:48:49 PM PDT 24 |
| Finished | Jul 12 07:57:07 PM PDT 24 |
| Peak memory | 609844 kb |
| Host | smart-8eab43ed-88b2-4489-9922-e9c79d1b1cae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37846 29915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.3784629915 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.3197027302 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 2613629422 ps |
| CPU time | 204.74 seconds |
| Started | Jul 12 07:49:44 PM PDT 24 |
| Finished | Jul 12 07:53:09 PM PDT 24 |
| Peak memory | 609652 kb |
| Host | smart-294ea34a-49d0-4b98-8c79-1bbf467d238d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197027302 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.3197027302 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.72752141 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 7301216316 ps |
| CPU time | 638.85 seconds |
| Started | Jul 12 07:49:47 PM PDT 24 |
| Finished | Jul 12 08:00:27 PM PDT 24 |
| Peak memory | 611696 kb |
| Host | smart-b68e60cb-0d8c-49e8-b2bd-6024ce06b175 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72752141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_lc _hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng _lc_hw_debug_en_test.72752141 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.1314810161 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 2695582452 ps |
| CPU time | 220.64 seconds |
| Started | Jul 12 07:53:02 PM PDT 24 |
| Finished | Jul 12 07:56:44 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-2d9c4ca6-6e6b-4538-ba76-82d171e9f82f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314810161 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.1314810161 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.3037365754 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 4551073480 ps |
| CPU time | 597.83 seconds |
| Started | Jul 12 07:46:39 PM PDT 24 |
| Finished | Jul 12 07:56:38 PM PDT 24 |
| Peak memory | 611264 kb |
| Host | smart-f5341d01-ddad-4183-9845-81f3964a1912 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3037365754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.3037365754 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.3406603105 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 4033871216 ps |
| CPU time | 966.75 seconds |
| Started | Jul 12 07:51:21 PM PDT 24 |
| Finished | Jul 12 08:07:28 PM PDT 24 |
| Peak memory | 609352 kb |
| Host | smart-80f89cbe-4673-4627-9961-04ba1e03c125 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406603105 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ auto_mode.3406603105 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1699122518 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 6132465572 ps |
| CPU time | 1068.06 seconds |
| Started | Jul 12 07:48:02 PM PDT 24 |
| Finished | Jul 12 08:05:51 PM PDT 24 |
| Peak memory | 611392 kb |
| Host | smart-d973d6e5-2807-47d2-b2a1-d2f47b985f70 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1699122518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.1699122518 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.4001252321 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 3583807402 ps |
| CPU time | 601.08 seconds |
| Started | Jul 12 07:48:47 PM PDT 24 |
| Finished | Jul 12 07:58:49 PM PDT 24 |
| Peak memory | 616020 kb |
| Host | smart-bb1a15f9-9d50-49ce-97bf-3f27d220b930 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001252321 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.4001252321 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.1672566507 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 7506596280 ps |
| CPU time | 1766.45 seconds |
| Started | Jul 12 07:51:25 PM PDT 24 |
| Finished | Jul 12 08:20:52 PM PDT 24 |
| Peak memory | 609696 kb |
| Host | smart-5f022312-6e59-4243-8704-c730a5f3b2ce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672566507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.1672566507 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1063456739 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 3294719092 ps |
| CPU time | 283.12 seconds |
| Started | Jul 12 07:48:24 PM PDT 24 |
| Finished | Jul 12 07:53:08 PM PDT 24 |
| Peak memory | 609668 kb |
| Host | smart-63f4ccba-2a81-4cec-8cad-ca294d46d882 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10 63456739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.1063456739 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.4149473008 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 7339357592 ps |
| CPU time | 1526.2 seconds |
| Started | Jul 12 07:48:49 PM PDT 24 |
| Finished | Jul 12 08:14:16 PM PDT 24 |
| Peak memory | 609804 kb |
| Host | smart-332af2ac-4751-47dc-b4c6-a31e230c6f45 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4149473008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.4149473008 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.481495585 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 2700649386 ps |
| CPU time | 187.93 seconds |
| Started | Jul 12 07:49:43 PM PDT 24 |
| Finished | Jul 12 07:52:52 PM PDT 24 |
| Peak memory | 609688 kb |
| Host | smart-f3f9dc9d-eb06-4fbe-9ad8-50ef16c63e63 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481495585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.481495585 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3737005831 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 3925094624 ps |
| CPU time | 484.96 seconds |
| Started | Jul 12 07:52:34 PM PDT 24 |
| Finished | Jul 12 08:00:40 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-53ee909b-9918-47f3-ac49-2842646deefe |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3737005831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.3737005831 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.216235204 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 2530809032 ps |
| CPU time | 203.25 seconds |
| Started | Jul 12 07:46:23 PM PDT 24 |
| Finished | Jul 12 07:49:47 PM PDT 24 |
| Peak memory | 608964 kb |
| Host | smart-d775318d-e2fc-4c3a-9585-09e9413f9597 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216235204 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_concurrency.216235204 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.3731681033 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 3177020776 ps |
| CPU time | 252 seconds |
| Started | Jul 12 07:49:21 PM PDT 24 |
| Finished | Jul 12 07:53:35 PM PDT 24 |
| Peak memory | 608928 kb |
| Host | smart-8a217fa7-d3a7-48f6-a6dc-e5d0255a80b5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731681033 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.3731681033 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.3279351586 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 2615191946 ps |
| CPU time | 312.25 seconds |
| Started | Jul 12 07:48:39 PM PDT 24 |
| Finished | Jul 12 07:53:53 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-0a71f71a-291c-4f30-9499-16a5e7b86450 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279351586 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.3279351586 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.425374662 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 1803474984 ps |
| CPU time | 110.31 seconds |
| Started | Jul 12 07:46:15 PM PDT 24 |
| Finished | Jul 12 07:48:06 PM PDT 24 |
| Peak memory | 610668 kb |
| Host | smart-9e6e2530-2c97-46bb-9024-da503282fe4f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425374662 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_example_rom.425374662 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1993328908 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 60323866541 ps |
| CPU time | 10880 seconds |
| Started | Jul 12 07:47:27 PM PDT 24 |
| Finished | Jul 12 10:48:49 PM PDT 24 |
| Peak memory | 625212 kb |
| Host | smart-ecb65a34-f17f-4a90-9cf9-4a05d39b7ef0 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1993328908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.1993328908 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.2364781631 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 4589374660 ps |
| CPU time | 729.24 seconds |
| Started | Jul 12 07:50:31 PM PDT 24 |
| Finished | Jul 12 08:02:42 PM PDT 24 |
| Peak memory | 611336 kb |
| Host | smart-b4c7be7e-76d0-440e-a06c-a2b78d98f5e0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2364781631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.2364781631 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3912531515 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 5680195280 ps |
| CPU time | 1090.91 seconds |
| Started | Jul 12 07:46:32 PM PDT 24 |
| Finished | Jul 12 08:04:44 PM PDT 24 |
| Peak memory | 610420 kb |
| Host | smart-0bbece07-15d0-46e2-a114-e999730b00b5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912531515 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.3912531515 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1241750317 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 6231466098 ps |
| CPU time | 1183.08 seconds |
| Started | Jul 12 07:47:34 PM PDT 24 |
| Finished | Jul 12 08:07:18 PM PDT 24 |
| Peak memory | 610520 kb |
| Host | smart-b5db7dd6-0db7-4515-8fb7-5eb41df8d1b9 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241750317 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.1241750317 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1856020582 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 7585288888 ps |
| CPU time | 1199.58 seconds |
| Started | Jul 12 07:49:50 PM PDT 24 |
| Finished | Jul 12 08:09:51 PM PDT 24 |
| Peak memory | 610240 kb |
| Host | smart-412803b6-99d5-4606-9d95-2b792e31fca2 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856020582 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1856020582 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1859023932 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 6284502589 ps |
| CPU time | 933.72 seconds |
| Started | Jul 12 07:46:56 PM PDT 24 |
| Finished | Jul 12 08:02:30 PM PDT 24 |
| Peak memory | 609208 kb |
| Host | smart-b75e706b-fd96-47a4-8746-ee4d46a6febf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859023932 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.1859023932 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3454592210 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 2975645532 ps |
| CPU time | 315.01 seconds |
| Started | Jul 12 07:48:38 PM PDT 24 |
| Finished | Jul 12 07:53:53 PM PDT 24 |
| Peak memory | 610204 kb |
| Host | smart-47eab2d1-2645-427a-94e2-8b8c63eee837 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454592210 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.3454592210 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.610819919 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 5626869462 ps |
| CPU time | 1272.32 seconds |
| Started | Jul 12 07:49:52 PM PDT 24 |
| Finished | Jul 12 08:11:05 PM PDT 24 |
| Peak memory | 610564 kb |
| Host | smart-68d3b05a-ded1-44f5-b25e-2f766325c8e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610819919 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.610819919 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2029436243 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 4330978003 ps |
| CPU time | 753.58 seconds |
| Started | Jul 12 07:47:44 PM PDT 24 |
| Finished | Jul 12 08:00:18 PM PDT 24 |
| Peak memory | 610780 kb |
| Host | smart-58084c86-a952-44b6-9a2c-a84adc9203a6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2029436243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.2029436243 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2717765844 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3498397640 ps |
| CPU time | 309.42 seconds |
| Started | Jul 12 07:49:37 PM PDT 24 |
| Finished | Jul 12 07:54:47 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-1bdd8aca-e4ea-4aac-a9b6-7267777301fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717765 844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.2717765844 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3136384430 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 24811489530 ps |
| CPU time | 2069.58 seconds |
| Started | Jul 12 07:49:00 PM PDT 24 |
| Finished | Jul 12 08:23:31 PM PDT 24 |
| Peak memory | 612592 kb |
| Host | smart-bb517a3e-7de9-404a-8a28-6181e756cdc4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3136384430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.3136384430 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3742670488 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 2846987024 ps |
| CPU time | 243.98 seconds |
| Started | Jul 12 07:56:04 PM PDT 24 |
| Finished | Jul 12 08:00:09 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-2d41b152-e54f-4e10-ac16-32be7e2b6912 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3742670488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.3742670488 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.2155419328 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 3634241386 ps |
| CPU time | 378.23 seconds |
| Started | Jul 12 07:52:32 PM PDT 24 |
| Finished | Jul 12 07:58:52 PM PDT 24 |
| Peak memory | 610540 kb |
| Host | smart-282a8778-27a0-40ba-bea8-359dbab8cd88 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155419328 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.2155419328 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.3176836097 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 2662923224 ps |
| CPU time | 191.11 seconds |
| Started | Jul 12 07:49:01 PM PDT 24 |
| Finished | Jul 12 07:52:13 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-fbb78253-9d64-4744-a531-52d434395d81 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176836097 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_hmac_enc_idle.3176836097 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.48953525 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3073983600 ps |
| CPU time | 290.57 seconds |
| Started | Jul 12 07:48:51 PM PDT 24 |
| Finished | Jul 12 07:53:43 PM PDT 24 |
| Peak memory | 609668 kb |
| Host | smart-adb3f765-95e0-4b35-a9ee-e3fe17b1bd50 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48953525 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.48953525 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.63727424 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 3074441098 ps |
| CPU time | 355.64 seconds |
| Started | Jul 12 07:50:37 PM PDT 24 |
| Finished | Jul 12 07:56:34 PM PDT 24 |
| Peak memory | 609664 kb |
| Host | smart-c63cf166-3a36-4d13-bf50-4d3d07557c19 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63727424 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.63727424 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.1430971406 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 7992899704 ps |
| CPU time | 2064.95 seconds |
| Started | Jul 12 07:51:11 PM PDT 24 |
| Finished | Jul 12 08:25:37 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-85ba9be3-0824-4a77-bece-1d1168a87914 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430971406 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.1430971406 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.2666242906 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 3251825964 ps |
| CPU time | 373.35 seconds |
| Started | Jul 12 07:50:48 PM PDT 24 |
| Finished | Jul 12 07:57:02 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-1e1c79d3-2e14-49ed-893f-cac2cac516ab |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666242906 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.2666242906 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.2660055086 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 3605960754 ps |
| CPU time | 378.76 seconds |
| Started | Jul 12 07:54:16 PM PDT 24 |
| Finished | Jul 12 08:00:36 PM PDT 24 |
| Peak memory | 609964 kb |
| Host | smart-0410bf74-704b-4cf2-88bf-4dd37a011504 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660055086 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.2660055086 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2885490549 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 4957199694 ps |
| CPU time | 835.92 seconds |
| Started | Jul 12 07:47:23 PM PDT 24 |
| Finished | Jul 12 08:01:20 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-fb42a23b-bba1-4f5b-b947-3e9a887f9d4d |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885490549 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.2885490549 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1282911299 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 4932812246 ps |
| CPU time | 848.43 seconds |
| Started | Jul 12 07:51:04 PM PDT 24 |
| Finished | Jul 12 08:05:13 PM PDT 24 |
| Peak memory | 609852 kb |
| Host | smart-3837bd3e-8622-47a7-a311-a16b35487a2c |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282911299 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.1282911299 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.3371818059 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 64367373982 ps |
| CPU time | 12578.3 seconds |
| Started | Jul 12 07:50:46 PM PDT 24 |
| Finished | Jul 12 11:20:26 PM PDT 24 |
| Peak memory | 625128 kb |
| Host | smart-42e5ae33-f506-4f30-b312-c16bb71c185d |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3371818059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.3371818059 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3581362449 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 7764038040 ps |
| CPU time | 2070.41 seconds |
| Started | Jul 12 07:49:10 PM PDT 24 |
| Finished | Jul 12 08:23:42 PM PDT 24 |
| Peak memory | 617140 kb |
| Host | smart-a427bc5b-f80e-4280-9c37-450308eaa6e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581 362449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.3581362449 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2916349076 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 8128251931 ps |
| CPU time | 1202.59 seconds |
| Started | Jul 12 07:49:30 PM PDT 24 |
| Finished | Jul 12 08:09:33 PM PDT 24 |
| Peak memory | 618196 kb |
| Host | smart-bd85a902-62be-430b-beac-9ccc6fad47ab |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2916349076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.2916349076 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2930500806 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 8033159969 ps |
| CPU time | 1500.14 seconds |
| Started | Jul 12 07:53:11 PM PDT 24 |
| Finished | Jul 12 08:18:12 PM PDT 24 |
| Peak memory | 617908 kb |
| Host | smart-f2473f69-d89a-4151-a384-6c538190827b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2930500806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2930500806 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3031697803 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 11105313434 ps |
| CPU time | 2622.11 seconds |
| Started | Jul 12 07:48:42 PM PDT 24 |
| Finished | Jul 12 08:32:25 PM PDT 24 |
| Peak memory | 617896 kb |
| Host | smart-088d37c3-4d3a-4cee-809a-50a9396a4bf9 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3031697803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.3031697803 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3756530933 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 11574311352 ps |
| CPU time | 2612.53 seconds |
| Started | Jul 12 07:52:59 PM PDT 24 |
| Finished | Jul 12 08:36:32 PM PDT 24 |
| Peak memory | 611320 kb |
| Host | smart-0a3565bd-1d88-41aa-b5be-07ced7f005db |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37565 30933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.3756530933 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.582822995 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 2350882616 ps |
| CPU time | 260.54 seconds |
| Started | Jul 12 07:49:06 PM PDT 24 |
| Finished | Jul 12 07:53:28 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-dd2d53e2-3579-4518-a3ba-b82b45deae8b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582822995 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_kmac_app_rom.582822995 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.3670407842 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 3675212088 ps |
| CPU time | 276.48 seconds |
| Started | Jul 12 07:47:37 PM PDT 24 |
| Finished | Jul 12 07:52:14 PM PDT 24 |
| Peak memory | 608948 kb |
| Host | smart-25cdc341-d06f-4d4c-a5be-cad9b951c62c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670407842 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_entropy.3670407842 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.1806143727 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 2676470446 ps |
| CPU time | 254.47 seconds |
| Started | Jul 12 07:49:55 PM PDT 24 |
| Finished | Jul 12 07:54:11 PM PDT 24 |
| Peak memory | 609880 kb |
| Host | smart-56fe7dca-00a3-4e04-b3f9-5b55db034171 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806143727 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.1806143727 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.415548741 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 2589126520 ps |
| CPU time | 278.95 seconds |
| Started | Jul 12 07:50:30 PM PDT 24 |
| Finished | Jul 12 07:55:11 PM PDT 24 |
| Peak memory | 608996 kb |
| Host | smart-c83b24ca-39ae-4fe0-ac0d-38b8fb3651b6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415548741 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_kmac_mode_cshake.415548741 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3790162657 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 2622941318 ps |
| CPU time | 363.08 seconds |
| Started | Jul 12 07:49:24 PM PDT 24 |
| Finished | Jul 12 07:55:28 PM PDT 24 |
| Peak memory | 608940 kb |
| Host | smart-c4cdedc8-3dab-441e-af68-e63ef43b4e86 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790162657 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.3790162657 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2235325738 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 2956423026 ps |
| CPU time | 351.95 seconds |
| Started | Jul 12 07:48:30 PM PDT 24 |
| Finished | Jul 12 07:54:24 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-2b8decf7-d607-49c0-8e6e-58c3e681fb69 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235325738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.2235325738 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3241505230 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 3580186639 ps |
| CPU time | 293.11 seconds |
| Started | Jul 12 07:49:49 PM PDT 24 |
| Finished | Jul 12 07:54:44 PM PDT 24 |
| Peak memory | 609788 kb |
| Host | smart-26e4f6a4-7c3b-48c4-837e-c7a0a87ec808 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32415052 30 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3241505230 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.1282123289 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 3310750720 ps |
| CPU time | 340.32 seconds |
| Started | Jul 12 07:53:12 PM PDT 24 |
| Finished | Jul 12 07:58:53 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-417de54d-d448-4a56-83d5-13c3a55b8771 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282123289 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.1282123289 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2434140044 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2840634524 ps |
| CPU time | 306.31 seconds |
| Started | Jul 12 07:47:05 PM PDT 24 |
| Finished | Jul 12 07:52:12 PM PDT 24 |
| Peak memory | 608924 kb |
| Host | smart-3e161713-7813-4df0-bbdd-baaf1edde4e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434140044 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.2434140044 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2898080045 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 3515620294 ps |
| CPU time | 170.63 seconds |
| Started | Jul 12 07:48:34 PM PDT 24 |
| Finished | Jul 12 07:51:26 PM PDT 24 |
| Peak memory | 620664 kb |
| Host | smart-9c90af2e-3427-425c-9b5f-dc0d3d4f09be |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28980800 45 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.2898080045 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.4194063828 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 3078554478 ps |
| CPU time | 151.08 seconds |
| Started | Jul 12 07:46:55 PM PDT 24 |
| Finished | Jul 12 07:49:27 PM PDT 24 |
| Peak memory | 620540 kb |
| Host | smart-8e72a3e8-d9b6-4605-8067-a0a18d12ae59 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194063828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.4194063828 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3228243656 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 2670022034 ps |
| CPU time | 152.29 seconds |
| Started | Jul 12 07:50:19 PM PDT 24 |
| Finished | Jul 12 07:52:52 PM PDT 24 |
| Peak memory | 621068 kb |
| Host | smart-b39aaba0-c112-4d37-8407-c02c5c5b2ee0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228243656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.3228243656 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1123554983 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 3478171372 ps |
| CPU time | 156.68 seconds |
| Started | Jul 12 07:47:06 PM PDT 24 |
| Finished | Jul 12 07:49:43 PM PDT 24 |
| Peak memory | 620528 kb |
| Host | smart-535a7ea6-f7db-49da-a157-af43c87dd033 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1123554983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.1123554983 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1456100675 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 5849915813 ps |
| CPU time | 520.96 seconds |
| Started | Jul 12 07:47:49 PM PDT 24 |
| Finished | Jul 12 07:56:31 PM PDT 24 |
| Peak memory | 620480 kb |
| Host | smart-52c67ef2-19c3-4c71-a4bb-13b165396f73 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456100675 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.1456100675 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2322346462 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 1914542366 ps |
| CPU time | 117.02 seconds |
| Started | Jul 12 07:48:31 PM PDT 24 |
| Finished | Jul 12 07:50:30 PM PDT 24 |
| Peak memory | 615436 kb |
| Host | smart-3881cbd8-d966-4e4c-9bbc-82a619b6aa2e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2322346462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.2322346462 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1904300410 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 2086486819 ps |
| CPU time | 107.27 seconds |
| Started | Jul 12 07:50:06 PM PDT 24 |
| Finished | Jul 12 07:51:56 PM PDT 24 |
| Peak memory | 618248 kb |
| Host | smart-5ff40db1-ffd1-4908-a4d4-4924978d89a5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904300410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1904300410 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1710967863 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 48939257120 ps |
| CPU time | 5853.97 seconds |
| Started | Jul 12 07:50:20 PM PDT 24 |
| Finished | Jul 12 09:27:55 PM PDT 24 |
| Peak memory | 618908 kb |
| Host | smart-ffcbf79d-205d-438f-9b15-facb4c223e48 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710967863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_lc_walkthrough_prod.1710967863 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3921682379 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 9392380220 ps |
| CPU time | 938.38 seconds |
| Started | Jul 12 07:47:56 PM PDT 24 |
| Finished | Jul 12 08:03:36 PM PDT 24 |
| Peak memory | 620472 kb |
| Host | smart-b328d124-12ee-46ad-b20e-7b366f54d73a |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921682379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.3921682379 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3619900983 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 46065482956 ps |
| CPU time | 5090.15 seconds |
| Started | Jul 12 07:51:48 PM PDT 24 |
| Finished | Jul 12 09:16:40 PM PDT 24 |
| Peak memory | 619612 kb |
| Host | smart-d0f66289-62d1-4ac7-9b2d-f92674138cdf |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619900983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.3619900983 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3608844793 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 20758513340 ps |
| CPU time | 2034.21 seconds |
| Started | Jul 12 07:47:57 PM PDT 24 |
| Finished | Jul 12 08:21:53 PM PDT 24 |
| Peak memory | 620008 kb |
| Host | smart-253324be-498c-41cd-b191-3275e83f8a1a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3608844793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.3608844793 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.125938598 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 18813929510 ps |
| CPU time | 3734.92 seconds |
| Started | Jul 12 07:48:18 PM PDT 24 |
| Finished | Jul 12 08:50:35 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-ea6302bf-020c-42f6-b3fd-06436a7c1927 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=125938598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.125938598 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3814844256 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 25009220752 ps |
| CPU time | 4086.47 seconds |
| Started | Jul 12 07:50:44 PM PDT 24 |
| Finished | Jul 12 08:58:52 PM PDT 24 |
| Peak memory | 610964 kb |
| Host | smart-99ae3142-8355-46f3-b723-1c01da6d531a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814844256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3814844256 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.4221551102 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 4002889800 ps |
| CPU time | 501.98 seconds |
| Started | Jul 12 07:48:36 PM PDT 24 |
| Finished | Jul 12 07:56:59 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-8e836ae7-76e4-4a48-bfbc-bf5b2e662b2a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221551102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.4221551102 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.2687636888 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 5939115000 ps |
| CPU time | 1081.44 seconds |
| Started | Jul 12 07:48:25 PM PDT 24 |
| Finished | Jul 12 08:06:27 PM PDT 24 |
| Peak memory | 610892 kb |
| Host | smart-c2bd9ece-e92b-46a1-a7ef-d5be148af94a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2687636888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.2687636888 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.3234584227 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 8573504044 ps |
| CPU time | 1986.36 seconds |
| Started | Jul 12 07:51:19 PM PDT 24 |
| Finished | Jul 12 08:24:27 PM PDT 24 |
| Peak memory | 610536 kb |
| Host | smart-e69c0f21-72d3-41ad-b7c0-29c3e1fad8e7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234584227 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.3234584227 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.520437642 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 3592898583 ps |
| CPU time | 290.16 seconds |
| Started | Jul 12 07:48:22 PM PDT 24 |
| Finished | Jul 12 07:53:14 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-cd4c0dfe-7006-45fe-89d4-28a294e2f8ab |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520437642 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.520437642 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3232689814 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 6978595590 ps |
| CPU time | 1062.23 seconds |
| Started | Jul 12 07:49:43 PM PDT 24 |
| Finished | Jul 12 08:07:27 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-80ef2f51-23ea-444e-851f-cdd216d7e579 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3232689814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.3232689814 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.750391972 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 7739954414 ps |
| CPU time | 1599.84 seconds |
| Started | Jul 12 07:47:14 PM PDT 24 |
| Finished | Jul 12 08:13:55 PM PDT 24 |
| Peak memory | 610936 kb |
| Host | smart-90996097-9591-4684-835b-ef2d585d357a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=750391972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.750391972 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2110179495 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 8735388640 ps |
| CPU time | 1496.75 seconds |
| Started | Jul 12 07:47:57 PM PDT 24 |
| Finished | Jul 12 08:12:54 PM PDT 24 |
| Peak memory | 610956 kb |
| Host | smart-436c3986-d40d-49b7-8e73-230e01b3536b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2110179495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.2110179495 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.347907053 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 3966830680 ps |
| CPU time | 772.37 seconds |
| Started | Jul 12 07:48:20 PM PDT 24 |
| Finished | Jul 12 08:01:14 PM PDT 24 |
| Peak memory | 609892 kb |
| Host | smart-464f7f69-f8d8-4ded-9358-a672be95a6ce |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=347907053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.347907053 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3624080534 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 2822139192 ps |
| CPU time | 266.69 seconds |
| Started | Jul 12 07:54:54 PM PDT 24 |
| Finished | Jul 12 07:59:21 PM PDT 24 |
| Peak memory | 608992 kb |
| Host | smart-668aa296-3bdf-4164-a690-25dc0191008d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624080534 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.3624080534 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.2705416008 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 2753712040 ps |
| CPU time | 275.62 seconds |
| Started | Jul 12 07:49:21 PM PDT 24 |
| Finished | Jul 12 07:53:58 PM PDT 24 |
| Peak memory | 610720 kb |
| Host | smart-8fef52fa-ca69-432b-8f15-7ba5d2194ba7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705416008 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.2705416008 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.601828308 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 2659802900 ps |
| CPU time | 205.21 seconds |
| Started | Jul 12 07:50:27 PM PDT 24 |
| Finished | Jul 12 07:53:53 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-661e244e-e208-4667-b655-fd2fee9ab3db |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601828308 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_plic_sw_irq.601828308 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.3980255892 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 10511775800 ps |
| CPU time | 546.3 seconds |
| Started | Jul 12 07:53:36 PM PDT 24 |
| Finished | Jul 12 08:02:43 PM PDT 24 |
| Peak memory | 610980 kb |
| Host | smart-d76e9e9d-2cf4-48fa-8e92-ba4eec367b4a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980255892 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.3980255892 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1005133233 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 10376825365 ps |
| CPU time | 1699.57 seconds |
| Started | Jul 12 07:47:49 PM PDT 24 |
| Finished | Jul 12 08:16:10 PM PDT 24 |
| Peak memory | 611676 kb |
| Host | smart-83ab2fe9-41b3-447f-9b28-9ce80af901b0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005 133233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.1005133233 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.4141540853 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 30013723072 ps |
| CPU time | 2331.56 seconds |
| Started | Jul 12 07:50:15 PM PDT 24 |
| Finished | Jul 12 08:29:08 PM PDT 24 |
| Peak memory | 611316 kb |
| Host | smart-0992d967-5871-465a-b6f5-d6aa1edc0af6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414 1540853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.4141540853 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3274675474 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 16978972149 ps |
| CPU time | 1902.18 seconds |
| Started | Jul 12 07:49:12 PM PDT 24 |
| Finished | Jul 12 08:20:55 PM PDT 24 |
| Peak memory | 611576 kb |
| Host | smart-1d115725-ab2e-4267-889c-5f4c186ab489 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3274675474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3274675474 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.87761770 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 8306935644 ps |
| CPU time | 917.85 seconds |
| Started | Jul 12 07:47:26 PM PDT 24 |
| Finished | Jul 12 08:02:44 PM PDT 24 |
| Peak memory | 611012 kb |
| Host | smart-a3353d4f-8024-4c7f-9b88-fae5e1e5a9dd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87761770 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.87761770 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.33397962 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 7720143972 ps |
| CPU time | 645.31 seconds |
| Started | Jul 12 07:47:46 PM PDT 24 |
| Finished | Jul 12 07:58:33 PM PDT 24 |
| Peak memory | 617812 kb |
| Host | smart-f304f52a-b2f5-4c35-a899-da57918fbc86 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=33397962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.33397962 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3782558369 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 4815612048 ps |
| CPU time | 595.88 seconds |
| Started | Jul 12 07:48:51 PM PDT 24 |
| Finished | Jul 12 07:58:49 PM PDT 24 |
| Peak memory | 616700 kb |
| Host | smart-0d21ba56-9961-4f80-9de2-ba0ddf53c9d4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3782558369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.3782558369 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2216806300 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 5392750954 ps |
| CPU time | 642.28 seconds |
| Started | Jul 12 07:48:10 PM PDT 24 |
| Finished | Jul 12 07:58:53 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-d82e3480-7dfc-4e55-8a79-a111eccb2ef6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216806300 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.2216806300 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4047430611 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 24285192458 ps |
| CPU time | 2372.83 seconds |
| Started | Jul 12 07:47:48 PM PDT 24 |
| Finished | Jul 12 08:27:23 PM PDT 24 |
| Peak memory | 611672 kb |
| Host | smart-6c4f7347-2074-4603-9726-db3306a9cc72 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4047430611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4047430611 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.25510730 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 24048214808 ps |
| CPU time | 1384.7 seconds |
| Started | Jul 12 07:53:09 PM PDT 24 |
| Finished | Jul 12 08:16:15 PM PDT 24 |
| Peak memory | 611208 kb |
| Host | smart-5b4b30d5-2c03-4139-849b-78871cce0f4d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=25510730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.25510730 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2586973687 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 28546794660 ps |
| CPU time | 2764.88 seconds |
| Started | Jul 12 07:53:16 PM PDT 24 |
| Finished | Jul 12 08:39:22 PM PDT 24 |
| Peak memory | 611836 kb |
| Host | smart-70296c01-4159-4716-899d-c526a10b8532 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586973687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2586973687 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3272784633 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 2638091460 ps |
| CPU time | 220.56 seconds |
| Started | Jul 12 07:49:16 PM PDT 24 |
| Finished | Jul 12 07:52:58 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-2e84b02a-f6c7-470e-90bc-b9e2acb0f61b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272784633 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.3272784633 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2963049186 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 6472933966 ps |
| CPU time | 520.61 seconds |
| Started | Jul 12 07:47:51 PM PDT 24 |
| Finished | Jul 12 07:56:32 PM PDT 24 |
| Peak memory | 616936 kb |
| Host | smart-4301508c-f4dd-4e0e-8a39-3128284d3d57 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2963049186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.2963049186 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2751996576 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 5841447150 ps |
| CPU time | 612.75 seconds |
| Started | Jul 12 07:48:37 PM PDT 24 |
| Finished | Jul 12 07:58:50 PM PDT 24 |
| Peak memory | 611168 kb |
| Host | smart-c977230c-b8e4-45ec-bb8b-3c2c2ea51e00 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2751996576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.2751996576 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2631156557 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 5579554400 ps |
| CPU time | 492.69 seconds |
| Started | Jul 12 07:52:29 PM PDT 24 |
| Finished | Jul 12 08:00:43 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-e3555af8-c381-41b0-a0fb-34ff4ba3875b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631156557 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.2631156557 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.4092683253 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 6925546598 ps |
| CPU time | 1100.8 seconds |
| Started | Jul 12 07:50:18 PM PDT 24 |
| Finished | Jul 12 08:08:40 PM PDT 24 |
| Peak memory | 611096 kb |
| Host | smart-0a467582-7a7c-4f04-bd3d-258aea832711 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092683253 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.4092683253 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2695390262 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 4904638200 ps |
| CPU time | 507.91 seconds |
| Started | Jul 12 07:51:16 PM PDT 24 |
| Finished | Jul 12 07:59:45 PM PDT 24 |
| Peak memory | 610752 kb |
| Host | smart-71b0e961-f94f-4b79-a36b-fe9fd30fdecb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695390262 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2695390262 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3728269029 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 5416296738 ps |
| CPU time | 544.48 seconds |
| Started | Jul 12 07:52:47 PM PDT 24 |
| Finished | Jul 12 08:01:52 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-0159e7bf-03fe-4331-8401-1eed5ce88bf6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728269029 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.3728269029 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3222419912 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 3456389264 ps |
| CPU time | 579.91 seconds |
| Started | Jul 12 07:50:49 PM PDT 24 |
| Finished | Jul 12 08:00:30 PM PDT 24 |
| Peak memory | 610436 kb |
| Host | smart-6d69c04b-dba7-456d-a249-97a51edcaddc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322 2419912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.3222419912 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2583531382 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 9691093217 ps |
| CPU time | 569.21 seconds |
| Started | Jul 12 07:49:18 PM PDT 24 |
| Finished | Jul 12 07:58:49 PM PDT 24 |
| Peak memory | 625104 kb |
| Host | smart-052f49a3-9c67-4251-9419-8dc822326c02 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583531382 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.2583531382 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.41573227 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 6412704232 ps |
| CPU time | 565.22 seconds |
| Started | Jul 12 07:51:18 PM PDT 24 |
| Finished | Jul 12 08:00:44 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-9f90b9c3-ddd8-462a-9294-073c7b258531 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41573227 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_cpu_info.41573227 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.517001336 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 5027316632 ps |
| CPU time | 819.4 seconds |
| Started | Jul 12 07:46:59 PM PDT 24 |
| Finished | Jul 12 08:00:39 PM PDT 24 |
| Peak memory | 641740 kb |
| Host | smart-ed298f29-7679-44d9-bf3c-e97c5db2653e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 517001336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.517001336 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2465726520 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 2875044720 ps |
| CPU time | 195.77 seconds |
| Started | Jul 12 07:51:46 PM PDT 24 |
| Finished | Jul 12 07:55:03 PM PDT 24 |
| Peak memory | 610044 kb |
| Host | smart-0c9b4cb4-a10c-440d-885d-5db9d13b5f31 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465726520 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.2465726520 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.4021140128 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 4618870928 ps |
| CPU time | 389.98 seconds |
| Started | Jul 12 07:47:50 PM PDT 24 |
| Finished | Jul 12 07:54:20 PM PDT 24 |
| Peak memory | 609396 kb |
| Host | smart-fd984384-d156-414c-8928-986b1ec077f9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021140128 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.4021140128 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3473545242 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 2633692852 ps |
| CPU time | 278.51 seconds |
| Started | Jul 12 07:47:15 PM PDT 24 |
| Finished | Jul 12 07:51:54 PM PDT 24 |
| Peak memory | 610316 kb |
| Host | smart-4125b413-4b6a-4ca4-9baa-d8717afa1004 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473545242 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.3473545242 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2951342678 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 2915737346 ps |
| CPU time | 238.38 seconds |
| Started | Jul 12 07:50:57 PM PDT 24 |
| Finished | Jul 12 07:54:56 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-69b2d223-33f8-487b-b983-c275ba95cc8e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951342678 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.2951342678 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.421747654 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 5507696600 ps |
| CPU time | 1146.4 seconds |
| Started | Jul 12 07:50:38 PM PDT 24 |
| Finished | Jul 12 08:09:46 PM PDT 24 |
| Peak memory | 610608 kb |
| Host | smart-73cd2849-7243-42ee-914c-c809f2103bbe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=421747654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.421747654 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.960462620 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 6272487990 ps |
| CPU time | 497.44 seconds |
| Started | Jul 12 07:49:31 PM PDT 24 |
| Finished | Jul 12 07:57:49 PM PDT 24 |
| Peak memory | 620460 kb |
| Host | smart-12f881d3-54d9-4fce-a928-b005b344fb7c |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960462620 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.960462620 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1358577842 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 3083427528 ps |
| CPU time | 198.71 seconds |
| Started | Jul 12 07:54:33 PM PDT 24 |
| Finished | Jul 12 07:57:53 PM PDT 24 |
| Peak memory | 608924 kb |
| Host | smart-3abcfd5e-f158-4fdd-97ac-4f6764f2097a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358577842 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.1358577842 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.713548041 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 3093330428 ps |
| CPU time | 332.97 seconds |
| Started | Jul 12 07:50:44 PM PDT 24 |
| Finished | Jul 12 07:56:19 PM PDT 24 |
| Peak memory | 609004 kb |
| Host | smart-df72420a-938b-44f5-bb2c-04fb0e1b954b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713548041 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_timer_irq.713548041 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1726396721 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 2778864230 ps |
| CPU time | 270.73 seconds |
| Started | Jul 12 07:53:46 PM PDT 24 |
| Finished | Jul 12 07:58:18 PM PDT 24 |
| Peak memory | 610292 kb |
| Host | smart-0d2a5805-00c8-4bf0-913c-9cad39e88088 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726396721 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.1726396721 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3343587459 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 3574054805 ps |
| CPU time | 241.4 seconds |
| Started | Jul 12 07:49:09 PM PDT 24 |
| Finished | Jul 12 07:53:11 PM PDT 24 |
| Peak memory | 610952 kb |
| Host | smart-af08dfb7-c2bb-415d-a90a-ca5b5d203835 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343587 459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.3343587459 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.183703910 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 8963023560 ps |
| CPU time | 1579.03 seconds |
| Started | Jul 12 07:49:22 PM PDT 24 |
| Finished | Jul 12 08:15:43 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-00f458df-11d4-41b4-9b13-04ca5cce35fa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183703910 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.183703910 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1344207561 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 6961413120 ps |
| CPU time | 613.3 seconds |
| Started | Jul 12 07:54:39 PM PDT 24 |
| Finished | Jul 12 08:04:53 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-f5f58b65-6cc3-41c9-9551-8e9d86979680 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344207561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.1344207561 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.145189668 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 7502955118 ps |
| CPU time | 801.13 seconds |
| Started | Jul 12 07:49:40 PM PDT 24 |
| Finished | Jul 12 08:03:02 PM PDT 24 |
| Peak memory | 611132 kb |
| Host | smart-a154c655-47fc-436a-acd9-e323df396de4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145189668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_ sram_ret_contents_scramble.145189668 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.2965292696 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 6961012890 ps |
| CPU time | 722.17 seconds |
| Started | Jul 12 07:49:37 PM PDT 24 |
| Finished | Jul 12 08:01:41 PM PDT 24 |
| Peak memory | 625252 kb |
| Host | smart-d882c967-23dd-4216-ba32-0d6a337d97f1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965292696 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.2965292696 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.1882894015 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3455222036 ps |
| CPU time | 319.8 seconds |
| Started | Jul 12 07:46:36 PM PDT 24 |
| Finished | Jul 12 07:51:57 PM PDT 24 |
| Peak memory | 618336 kb |
| Host | smart-2bc1db01-5746-474a-b1c1-85d251179ef8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882894015 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.1882894015 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.677375733 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3138418640 ps |
| CPU time | 253.7 seconds |
| Started | Jul 12 07:47:36 PM PDT 24 |
| Finished | Jul 12 07:51:51 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-efab93cf-a682-40f3-a447-6b191550f267 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677375733 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.677375733 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.528180526 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 5915973550 ps |
| CPU time | 596.29 seconds |
| Started | Jul 12 07:49:49 PM PDT 24 |
| Finished | Jul 12 07:59:46 PM PDT 24 |
| Peak memory | 611196 kb |
| Host | smart-e2d8da35-f005-49cb-bf4f-0545b0922a0d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528180526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ sram_ctrl_scrambled_access.528180526 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2314326307 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 5601794953 ps |
| CPU time | 843.52 seconds |
| Started | Jul 12 07:49:16 PM PDT 24 |
| Finished | Jul 12 08:03:20 PM PDT 24 |
| Peak memory | 611344 kb |
| Host | smart-7976d236-02c9-49f9-ab3a-66b7f0771cad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314326307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2314326307 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3455611189 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 3066915850 ps |
| CPU time | 217.44 seconds |
| Started | Jul 12 07:50:35 PM PDT 24 |
| Finished | Jul 12 07:54:13 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-e1b38d91-1e17-4d05-9248-b23afb3f5f29 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455611189 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.3455611189 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1215072169 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 20696275205 ps |
| CPU time | 3665.38 seconds |
| Started | Jul 12 07:50:06 PM PDT 24 |
| Finished | Jul 12 08:51:13 PM PDT 24 |
| Peak memory | 609812 kb |
| Host | smart-f14c7cf6-acf3-4188-ad18-e72e8727da03 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215072169 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.1215072169 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1298327674 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 4664834792 ps |
| CPU time | 725.5 seconds |
| Started | Jul 12 07:48:58 PM PDT 24 |
| Finished | Jul 12 08:01:06 PM PDT 24 |
| Peak memory | 614200 kb |
| Host | smart-8034dc01-fca6-4e57-aeb7-8734f7af2792 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298327674 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.1298327674 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3884511200 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 2893433300 ps |
| CPU time | 302.9 seconds |
| Started | Jul 12 07:48:28 PM PDT 24 |
| Finished | Jul 12 07:53:33 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-faf327a2-8445-4fcc-b00a-46374da2edc1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884511200 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.3884511200 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3247482175 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 6531569400 ps |
| CPU time | 530.37 seconds |
| Started | Jul 12 07:52:18 PM PDT 24 |
| Finished | Jul 12 08:01:10 PM PDT 24 |
| Peak memory | 611020 kb |
| Host | smart-203764e9-53bf-44a6-b040-674f9b28b8d4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247482175 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3247482175 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.51256210 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 3162182748 ps |
| CPU time | 259.02 seconds |
| Started | Jul 12 07:52:05 PM PDT 24 |
| Finished | Jul 12 07:56:25 PM PDT 24 |
| Peak memory | 616224 kb |
| Host | smart-fc0054df-6d14-46c2-bf73-4d2706efebf4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51256210 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_uart_smoketest.51256210 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.4262430824 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 3893920276 ps |
| CPU time | 696.77 seconds |
| Started | Jul 12 07:47:46 PM PDT 24 |
| Finished | Jul 12 07:59:24 PM PDT 24 |
| Peak memory | 624108 kb |
| Host | smart-ee2eb5ad-0ed0-4ba1-ab18-44ec7ac3235b |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262430824 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.4262430824 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1768777207 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 7779335702 ps |
| CPU time | 1882.5 seconds |
| Started | Jul 12 07:47:17 PM PDT 24 |
| Finished | Jul 12 08:18:40 PM PDT 24 |
| Peak memory | 625128 kb |
| Host | smart-8365224d-0b72-4d62-b0ab-656a00cf8375 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768777207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq.1768777207 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1902351176 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 3644617584 ps |
| CPU time | 602.21 seconds |
| Started | Jul 12 07:47:37 PM PDT 24 |
| Finished | Jul 12 07:57:40 PM PDT 24 |
| Peak memory | 625068 kb |
| Host | smart-8b6908e4-e972-450a-a7d8-107cc028b115 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902351176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1902351176 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1802303453 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 3536635442 ps |
| CPU time | 673.11 seconds |
| Started | Jul 12 07:48:01 PM PDT 24 |
| Finished | Jul 12 07:59:15 PM PDT 24 |
| Peak memory | 622812 kb |
| Host | smart-1cc39fe6-b665-4c1b-9ddc-76509edbacc6 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802303453 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.1802303453 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.126082688 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 4389534250 ps |
| CPU time | 608.86 seconds |
| Started | Jul 12 07:47:59 PM PDT 24 |
| Finished | Jul 12 07:58:09 PM PDT 24 |
| Peak memory | 624108 kb |
| Host | smart-3289c2a5-4537-4419-bbf3-b70e6d40bffb |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126082688 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.126082688 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2570079062 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 3464102740 ps |
| CPU time | 654.94 seconds |
| Started | Jul 12 07:47:18 PM PDT 24 |
| Finished | Jul 12 07:58:14 PM PDT 24 |
| Peak memory | 624148 kb |
| Host | smart-167e8c5a-eb55-4ad1-8655-cb76b3d986fe |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570079062 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.2570079062 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1629027948 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 3079983631 ps |
| CPU time | 336.48 seconds |
| Started | Jul 12 07:50:23 PM PDT 24 |
| Finished | Jul 12 07:56:00 PM PDT 24 |
| Peak memory | 609544 kb |
| Host | smart-7bcb6e61-0f77-4c43-97ed-d47b75604091 |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629027948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.1629027948 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.1136716994 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 7828438956 ps |
| CPU time | 2162.32 seconds |
| Started | Jul 12 07:49:30 PM PDT 24 |
| Finished | Jul 12 08:25:34 PM PDT 24 |
| Peak memory | 609696 kb |
| Host | smart-089c0285-14b3-41d4-84e1-3b18b6eed6cf |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11367 16994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.1136716994 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.865099196 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 12139541002 ps |
| CPU time | 2935.39 seconds |
| Started | Jul 12 07:48:20 PM PDT 24 |
| Finished | Jul 12 08:37:18 PM PDT 24 |
| Peak memory | 609728 kb |
| Host | smart-0212c14b-ecbd-4d2d-93d3-976a37bc0006 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=865099196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.865099196 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.3713876567 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 3017362636 ps |
| CPU time | 268.67 seconds |
| Started | Jul 12 07:49:18 PM PDT 24 |
| Finished | Jul 12 07:53:49 PM PDT 24 |
| Peak memory | 609668 kb |
| Host | smart-622c21a5-9726-46b2-8f6c-ae72530a4ac9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713876567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.3713876567 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2823979855 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 4071980064 ps |
| CPU time | 583.23 seconds |
| Started | Jul 12 07:47:40 PM PDT 24 |
| Finished | Jul 12 07:57:24 PM PDT 24 |
| Peak memory | 609668 kb |
| Host | smart-a90ccf51-1508-41ea-8b8d-a89f00ae209b |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282397985 5 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.2823979855 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.3537184913 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 18211072312 ps |
| CPU time | 4335.79 seconds |
| Started | Jul 12 07:49:26 PM PDT 24 |
| Finished | Jul 12 09:01:43 PM PDT 24 |
| Peak memory | 610864 kb |
| Host | smart-d5871cdb-6df7-4178-921c-ccd730ddce40 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=3537184913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.3537184913 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.979630088 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 3191291808 ps |
| CPU time | 286.69 seconds |
| Started | Jul 12 07:46:36 PM PDT 24 |
| Finished | Jul 12 07:51:24 PM PDT 24 |
| Peak memory | 609688 kb |
| Host | smart-91e8a052-ff63-49d8-89e0-9bca514c5152 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979630088 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.979630088 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.3603755886 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 8778940895 ps |
| CPU time | 979.99 seconds |
| Started | Jul 12 07:49:55 PM PDT 24 |
| Finished | Jul 12 08:06:16 PM PDT 24 |
| Peak memory | 621428 kb |
| Host | smart-3bde362f-8bad-428e-945e-e2803c4121bb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603755886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.3603755886 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.2540333611 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 16142178124 ps |
| CPU time | 4000.32 seconds |
| Started | Jul 12 07:57:07 PM PDT 24 |
| Finished | Jul 12 09:03:49 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-e9126674-e41f-4362-9411-51073ed46dee |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540333611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.2540333611 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.374790958 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 16172499580 ps |
| CPU time | 3758.77 seconds |
| Started | Jul 12 07:54:34 PM PDT 24 |
| Finished | Jul 12 08:57:14 PM PDT 24 |
| Peak memory | 611616 kb |
| Host | smart-045d3222-feb1-4750-961e-8ad4ecfd30f1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374790958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.374790958 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2894826274 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 15244149195 ps |
| CPU time | 3726.33 seconds |
| Started | Jul 12 07:56:40 PM PDT 24 |
| Finished | Jul 12 08:58:47 PM PDT 24 |
| Peak memory | 610444 kb |
| Host | smart-01b50f8e-26fc-4381-bcd0-b98b0beda52c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894826274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.2894826274 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.144517273 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 14098662756 ps |
| CPU time | 4385.52 seconds |
| Started | Jul 12 07:59:31 PM PDT 24 |
| Finished | Jul 12 09:12:38 PM PDT 24 |
| Peak memory | 611900 kb |
| Host | smart-62f460ae-3dd4-4f4a-a7bc-36f8bfc7749b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144517273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .rom_e2e_asm_init_rma.144517273 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.684897662 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 11418461944 ps |
| CPU time | 3421.65 seconds |
| Started | Jul 12 07:58:17 PM PDT 24 |
| Finished | Jul 12 08:55:20 PM PDT 24 |
| Peak memory | 611996 kb |
| Host | smart-a41102d1-898e-49fb-9688-6376d376239c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684897662 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.rom_e2e_asm_init_test_unlocked0.684897662 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.24498301 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 23730699424 ps |
| CPU time | 6088.55 seconds |
| Started | Jul 12 07:57:18 PM PDT 24 |
| Finished | Jul 12 09:38:49 PM PDT 24 |
| Peak memory | 609832 kb |
| Host | smart-a63324c1-36be-4e75-a59e-a6bc94d90a2a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=24498301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.24498301 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2320331476 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 23897314200 ps |
| CPU time | 6251.66 seconds |
| Started | Jul 12 07:57:28 PM PDT 24 |
| Finished | Jul 12 09:41:42 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-baff98ef-fa3e-4611-bdd1-17cd7229f140 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2320331476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2320331476 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2932179683 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 23016340224 ps |
| CPU time | 5856.85 seconds |
| Started | Jul 12 07:56:15 PM PDT 24 |
| Finished | Jul 12 09:33:54 PM PDT 24 |
| Peak memory | 611640 kb |
| Host | smart-aeee8730-7ab3-4724-87fd-7b1d7bec0cdb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2932179683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2932179683 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2544188349 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 17907285160 ps |
| CPU time | 5396.76 seconds |
| Started | Jul 12 07:59:39 PM PDT 24 |
| Finished | Jul 12 09:29:38 PM PDT 24 |
| Peak memory | 609816 kb |
| Host | smart-b63a0bef-4f57-490a-ae00-12fb4c576b45 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544188349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2544188349 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2040390244 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 15297682360 ps |
| CPU time | 4385.49 seconds |
| Started | Jul 12 07:58:29 PM PDT 24 |
| Finished | Jul 12 09:11:35 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-080cc525-c354-4f9c-b896-fb7fe5361f0d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2040390244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2040390244 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3882199536 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 15422444318 ps |
| CPU time | 3436.48 seconds |
| Started | Jul 12 07:56:25 PM PDT 24 |
| Finished | Jul 12 08:53:43 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-7b5d4926-1d33-47eb-a215-c7c0afc2657f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3882199536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3882199536 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3143270482 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 15541357120 ps |
| CPU time | 3605.09 seconds |
| Started | Jul 12 07:57:15 PM PDT 24 |
| Finished | Jul 12 08:57:22 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-ef66dcd7-e9d4-4604-9621-824d279cfc8c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3143270482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3143270482 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3661670884 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 14756386824 ps |
| CPU time | 3506.9 seconds |
| Started | Jul 12 07:59:30 PM PDT 24 |
| Finished | Jul 12 08:57:58 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-8f4ae1a0-9c31-4bda-ac3b-7ab76eef50ef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3661670884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3661670884 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3757286381 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 10996543026 ps |
| CPU time | 3221.74 seconds |
| Started | Jul 12 07:56:11 PM PDT 24 |
| Finished | Jul 12 08:49:55 PM PDT 24 |
| Peak memory | 609848 kb |
| Host | smart-83c60843-841e-4677-b496-af2890b411f6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757286381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3757286381 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2850777355 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 15554963980 ps |
| CPU time | 3814.54 seconds |
| Started | Jul 12 07:58:17 PM PDT 24 |
| Finished | Jul 12 09:01:53 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-bba73140-c6f6-4900-a437-33dbf4aee424 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850777355 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2850777355 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2312215328 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 15846362354 ps |
| CPU time | 3785.1 seconds |
| Started | Jul 12 07:55:46 PM PDT 24 |
| Finished | Jul 12 08:58:52 PM PDT 24 |
| Peak memory | 609832 kb |
| Host | smart-b46ad7bb-7250-4e69-8136-2bf7996a2644 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312215328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2312215328 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.70256497 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 16150144180 ps |
| CPU time | 3743.44 seconds |
| Started | Jul 12 07:55:45 PM PDT 24 |
| Finished | Jul 12 08:58:09 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-dbd5a88f-6334-459a-877e-273776766c29 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702564 97 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.70256497 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.222269520 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 14763287020 ps |
| CPU time | 3365.15 seconds |
| Started | Jul 12 07:56:46 PM PDT 24 |
| Finished | Jul 12 08:52:52 PM PDT 24 |
| Peak memory | 609856 kb |
| Host | smart-6556bd84-ccd4-40d0-80e8-dbc5909bf78d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222269520 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.222269520 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3438929534 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 11308441796 ps |
| CPU time | 2827.54 seconds |
| Started | Jul 12 07:56:19 PM PDT 24 |
| Finished | Jul 12 08:43:28 PM PDT 24 |
| Peak memory | 609812 kb |
| Host | smart-01e0f181-0c1d-4a8f-ae67-f3ebaaab6418 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3438929534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3438929534 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.3694009764 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 10707453234 ps |
| CPU time | 1598.45 seconds |
| Started | Jul 12 07:50:57 PM PDT 24 |
| Finished | Jul 12 08:17:37 PM PDT 24 |
| Peak memory | 624808 kb |
| Host | smart-a1802165-33b9-4e64-a960-089a82fa6bc4 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36940 09764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.3694009764 |
| Directory | /workspace/0.rom_e2e_jtag_debug_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.1922394899 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 10828484792 ps |
| CPU time | 2210.91 seconds |
| Started | Jul 12 07:54:21 PM PDT 24 |
| Finished | Jul 12 08:31:13 PM PDT 24 |
| Peak memory | 624728 kb |
| Host | smart-bc150e0a-3f3d-46b8-9d1d-950a4be1030e |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19223 94899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.1922394899 |
| Directory | /workspace/0.rom_e2e_jtag_debug_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3449280877 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 10925278148 ps |
| CPU time | 2003.73 seconds |
| Started | Jul 12 07:51:21 PM PDT 24 |
| Finished | Jul 12 08:24:47 PM PDT 24 |
| Peak memory | 624676 kb |
| Host | smart-5be820fc-4f17-4f85-88ed-dac8e93bb84b |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3449280877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.3449280877 |
| Directory | /workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3808265361 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 24577988994 ps |
| CPU time | 2234.52 seconds |
| Started | Jul 12 07:51:40 PM PDT 24 |
| Finished | Jul 12 08:28:56 PM PDT 24 |
| Peak memory | 620928 kb |
| Host | smart-65562493-aa3f-407e-9faa-86fa04da9895 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3808265361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.3808265361 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.1194791316 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 22844843657 ps |
| CPU time | 2819.65 seconds |
| Started | Jul 12 07:55:10 PM PDT 24 |
| Finished | Jul 12 08:42:11 PM PDT 24 |
| Peak memory | 620944 kb |
| Host | smart-390126dc-27ce-4876-b751-24cb5fb75a18 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1194791316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.1194791316 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.4139882633 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 27570749146 ps |
| CPU time | 2550.35 seconds |
| Started | Jul 12 07:52:54 PM PDT 24 |
| Finished | Jul 12 08:35:25 PM PDT 24 |
| Peak memory | 620964 kb |
| Host | smart-465ae16f-852e-4c99-833a-7b2a9404b000 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139882633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_ inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject _test_unlocked0.4139882633 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.4181056289 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 14701169446 ps |
| CPU time | 3551.15 seconds |
| Started | Jul 12 07:56:20 PM PDT 24 |
| Finished | Jul 12 08:55:32 PM PDT 24 |
| Peak memory | 610752 kb |
| Host | smart-5b30a7ee-8457-420f-9c44-77da0341a03e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181056289 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.4181056289 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1810381537 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 15734978982 ps |
| CPU time | 4104.02 seconds |
| Started | Jul 12 07:56:59 PM PDT 24 |
| Finished | Jul 12 09:05:24 PM PDT 24 |
| Peak memory | 610720 kb |
| Host | smart-600786ee-d929-4a7c-985c-4b1b936a79e6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810381537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.1810381537 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2195049743 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 14981601160 ps |
| CPU time | 3591.85 seconds |
| Started | Jul 12 07:57:07 PM PDT 24 |
| Finished | Jul 12 08:57:01 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-7b626f31-584e-4f8c-a86f-4fc72378f3d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195049743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.2195049743 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.2223479922 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 23284017513 ps |
| CPU time | 3381.41 seconds |
| Started | Jul 12 07:55:27 PM PDT 24 |
| Finished | Jul 12 08:51:50 PM PDT 24 |
| Peak memory | 611700 kb |
| Host | smart-fb40cad5-6903-4a16-b064-51df2125eb17 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223479922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.2223479922 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2650027503 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 23717242877 ps |
| CPU time | 5502.06 seconds |
| Started | Jul 12 07:58:18 PM PDT 24 |
| Finished | Jul 12 09:30:02 PM PDT 24 |
| Peak memory | 611840 kb |
| Host | smart-e7010b18-236a-4c83-8849-8420063ff502 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2650027503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b ad_dev.2650027503 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1460714164 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 23215827247 ps |
| CPU time | 6566.41 seconds |
| Started | Jul 12 07:59:31 PM PDT 24 |
| Finished | Jul 12 09:49:00 PM PDT 24 |
| Peak memory | 610844 kb |
| Host | smart-d06a0ee2-137c-4f60-82d2-112b3f970f5e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1460714164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_ b_bad_prod.1460714164 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2637398729 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 24016683200 ps |
| CPU time | 5977.47 seconds |
| Started | Jul 12 08:00:03 PM PDT 24 |
| Finished | Jul 12 09:39:42 PM PDT 24 |
| Peak memory | 611772 kb |
| Host | smart-77356061-2b93-461c-bf18-69c3ebf891c6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2637398729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_ bad_b_bad_prod_end.2637398729 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3194989828 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 22690778862 ps |
| CPU time | 6191.14 seconds |
| Started | Jul 12 08:00:05 PM PDT 24 |
| Finished | Jul 12 09:43:17 PM PDT 24 |
| Peak memory | 609844 kb |
| Host | smart-347e0dae-7bdb-421e-b498-b5a3f5128990 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3194989828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b _bad_rma.3194989828 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1432742088 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 18142624799 ps |
| CPU time | 4606.25 seconds |
| Started | Jul 12 07:59:51 PM PDT 24 |
| Finished | Jul 12 09:16:39 PM PDT 24 |
| Peak memory | 611828 kb |
| Host | smart-37828927-6b3c-4b11-9786-37bf5653550b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1432742088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b _bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw ays_a_bad_b_bad_test_unlocked0.1432742088 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.434349098 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 14886100940 ps |
| CPU time | 4170.08 seconds |
| Started | Jul 12 08:00:40 PM PDT 24 |
| Finished | Jul 12 09:10:11 PM PDT 24 |
| Peak memory | 609852 kb |
| Host | smart-88615639-188f-4cf3-a4db-259ac152104f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434349098 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.434349098 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3813855245 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 14565482683 ps |
| CPU time | 4044.7 seconds |
| Started | Jul 12 07:55:45 PM PDT 24 |
| Finished | Jul 12 09:03:11 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-f3f0fa49-23f8-4703-91fe-912cff2529d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813855245 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3813855245 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2489853852 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 14802053338 ps |
| CPU time | 3657.76 seconds |
| Started | Jul 12 07:56:55 PM PDT 24 |
| Finished | Jul 12 08:57:54 PM PDT 24 |
| Peak memory | 609884 kb |
| Host | smart-d52d58d3-3278-4870-8307-8d0b8ab8bf78 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489853852 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2489853852 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.855657804 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 13681397522 ps |
| CPU time | 3729.23 seconds |
| Started | Jul 12 07:55:05 PM PDT 24 |
| Finished | Jul 12 08:57:16 PM PDT 24 |
| Peak memory | 609868 kb |
| Host | smart-bd599e9f-9914-4f72-9e35-544c511c3fb3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855657804 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.855657804 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3746997444 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 11686790140 ps |
| CPU time | 2133.69 seconds |
| Started | Jul 12 07:57:57 PM PDT 24 |
| Finished | Jul 12 08:33:32 PM PDT 24 |
| Peak memory | 609860 kb |
| Host | smart-f0da86a3-8fdd-41a4-92c7-a570cc413daf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746997444 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3746997444 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3328321081 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 15049904123 ps |
| CPU time | 3823.37 seconds |
| Started | Jul 12 07:56:28 PM PDT 24 |
| Finished | Jul 12 09:00:13 PM PDT 24 |
| Peak memory | 609836 kb |
| Host | smart-71db681e-cab2-4072-b40b-527c16acaf38 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328321081 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3328321081 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3084380968 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 14892104480 ps |
| CPU time | 3421.5 seconds |
| Started | Jul 12 07:57:32 PM PDT 24 |
| Finished | Jul 12 08:54:35 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-4effcb56-80d7-4f66-af7d-30845db39af8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084380968 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3084380968 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.44123815 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 14191947422 ps |
| CPU time | 4557.55 seconds |
| Started | Jul 12 07:56:38 PM PDT 24 |
| Finished | Jul 12 09:12:38 PM PDT 24 |
| Peak memory | 609880 kb |
| Host | smart-6410c1f0-39d2-4ed4-b3c3-313fe5576c85 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44123815 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.44123815 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2888713313 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 14652166151 ps |
| CPU time | 4764.05 seconds |
| Started | Jul 12 07:58:55 PM PDT 24 |
| Finished | Jul 12 09:18:21 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-db3319ce-4636-4161-9190-0fe211fade1c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888713313 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2888713313 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2496332732 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11477132952 ps |
| CPU time | 2697.6 seconds |
| Started | Jul 12 07:56:19 PM PDT 24 |
| Finished | Jul 12 08:41:18 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-8d80b36e-58e9-4e08-9481-2c6822282134 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496332732 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2496332732 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.4158583611 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 15790956632 ps |
| CPU time | 3711.09 seconds |
| Started | Jul 12 07:53:33 PM PDT 24 |
| Finished | Jul 12 08:55:25 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-29943317-1798-4d72-bb5d-d2d10c310288 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=4158583611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.4158583611 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.3292707 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 16743695688 ps |
| CPU time | 4521.91 seconds |
| Started | Jul 12 07:57:05 PM PDT 24 |
| Finished | Jul 12 09:12:28 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-90bbac39-696c-48fb-bd8b-e92990f088a2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.3292707 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.3812448986 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 4911464754 ps |
| CPU time | 521.76 seconds |
| Started | Jul 12 07:52:27 PM PDT 24 |
| Finished | Jul 12 08:01:09 PM PDT 24 |
| Peak memory | 609912 kb |
| Host | smart-ea6935e4-33ab-4fa4-b3ae-f30b34a1c359 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812448986 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.3812448986 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_raw_unlock.4284101994 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 6032910825 ps |
| CPU time | 277.88 seconds |
| Started | Jul 12 07:53:03 PM PDT 24 |
| Finished | Jul 12 07:57:42 PM PDT 24 |
| Peak memory | 624256 kb |
| Host | smart-f6bb7b55-6ea8-43e7-b0ba-9590d5d67338 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4284101994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.4284101994 |
| Directory | /workspace/0.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.2305100339 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 2584394155 ps |
| CPU time | 100.87 seconds |
| Started | Jul 12 07:52:08 PM PDT 24 |
| Finished | Jul 12 07:53:50 PM PDT 24 |
| Peak memory | 618252 kb |
| Host | smart-eabee70c-94f2-48be-bd44-ff718031d516 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305100339 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.2305100339 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.2650864353 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 13582538970 ps |
| CPU time | 1618.21 seconds |
| Started | Jul 12 07:53:02 PM PDT 24 |
| Finished | Jul 12 08:20:01 PM PDT 24 |
| Peak memory | 608400 kb |
| Host | smart-f3330bd2-f78c-4c02-bd95-dbb72aba27ba |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650864353 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.2 650864353 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3333703853 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3526891776 ps |
| CPU time | 411.29 seconds |
| Started | Jul 12 08:00:48 PM PDT 24 |
| Finished | Jul 12 08:07:40 PM PDT 24 |
| Peak memory | 620320 kb |
| Host | smart-7ca5f517-59d0-42ae-a873-a5f541ab8fe8 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 333703853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.3333703853 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.1473090756 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 3035009188 ps |
| CPU time | 288.2 seconds |
| Started | Jul 12 07:52:14 PM PDT 24 |
| Finished | Jul 12 07:57:03 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-4b026b84-6dfe-4146-9dc9-14eb3c316f7b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1473090756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.1473090756 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4054149555 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 19256114344 ps |
| CPU time | 698.18 seconds |
| Started | Jul 12 07:58:45 PM PDT 24 |
| Finished | Jul 12 08:10:25 PM PDT 24 |
| Peak memory | 619576 kb |
| Host | smart-b7de34b6-b381-4ee1-b69a-c2c55755ed7e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4054149555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4054149555 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.2462211002 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 3515918980 ps |
| CPU time | 294.92 seconds |
| Started | Jul 12 07:57:18 PM PDT 24 |
| Finished | Jul 12 08:02:14 PM PDT 24 |
| Peak memory | 609676 kb |
| Host | smart-8717a591-93dc-4ca1-804d-18ae0d0a4f35 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462211002 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.2462211002 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.979956587 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 2775409283 ps |
| CPU time | 274.22 seconds |
| Started | Jul 12 07:57:33 PM PDT 24 |
| Finished | Jul 12 08:02:08 PM PDT 24 |
| Peak memory | 609648 kb |
| Host | smart-706fcee9-00f1-4d2a-aab4-68f40d84307e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9799 56587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.979956587 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.4064266582 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 3589856137 ps |
| CPU time | 297.13 seconds |
| Started | Jul 12 08:02:23 PM PDT 24 |
| Finished | Jul 12 08:07:21 PM PDT 24 |
| Peak memory | 610596 kb |
| Host | smart-7ece0556-fb1d-4b33-83ea-acea19dedcf6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064266582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.4064266582 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.1391939566 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 2786549960 ps |
| CPU time | 233.38 seconds |
| Started | Jul 12 07:56:55 PM PDT 24 |
| Finished | Jul 12 08:00:50 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-14381b61-b104-4b52-88d8-606f8660bd6a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391939566 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.1391939566 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.205843920 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 2727550576 ps |
| CPU time | 275.16 seconds |
| Started | Jul 12 07:55:43 PM PDT 24 |
| Finished | Jul 12 08:00:18 PM PDT 24 |
| Peak memory | 610380 kb |
| Host | smart-8552ae8c-a22b-4281-971e-bdcf63b2d5ab |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205843920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.205843920 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.989476008 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 2889235213 ps |
| CPU time | 249.93 seconds |
| Started | Jul 12 07:57:27 PM PDT 24 |
| Finished | Jul 12 08:01:38 PM PDT 24 |
| Peak memory | 610276 kb |
| Host | smart-1eac03a0-52bb-4a9c-bc9a-edc3836793d0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989476008 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.989476008 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.2877405761 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 3094801524 ps |
| CPU time | 326.58 seconds |
| Started | Jul 12 08:15:19 PM PDT 24 |
| Finished | Jul 12 08:20:47 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-2ec9e4cc-5aac-49cc-a1e0-9451c88c32a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877405761 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.2877405761 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.205099274 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 3762813234 ps |
| CPU time | 338.62 seconds |
| Started | Jul 12 07:58:05 PM PDT 24 |
| Finished | Jul 12 08:03:45 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-f771bc60-dda9-45f9-8edc-303ed58420a6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=205099274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.205099274 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.3261654388 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 4625740968 ps |
| CPU time | 598.84 seconds |
| Started | Jul 12 07:56:48 PM PDT 24 |
| Finished | Jul 12 08:06:48 PM PDT 24 |
| Peak memory | 619828 kb |
| Host | smart-bbbf5e39-ba4f-475f-ae45-384a93db9983 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3261654388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.3261654388 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.56357938 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 8204853744 ps |
| CPU time | 1732.37 seconds |
| Started | Jul 12 07:57:17 PM PDT 24 |
| Finished | Jul 12 08:26:11 PM PDT 24 |
| Peak memory | 610720 kb |
| Host | smart-f50fe66e-b367-4179-80e9-775a1e9624cf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=56357938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.56357938 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2149892756 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 9068052496 ps |
| CPU time | 2002.23 seconds |
| Started | Jul 12 08:00:25 PM PDT 24 |
| Finished | Jul 12 08:33:48 PM PDT 24 |
| Peak memory | 610800 kb |
| Host | smart-f4e30727-3654-4ddc-a266-9bb864633e40 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149892756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.2149892756 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2284645986 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 8268057336 ps |
| CPU time | 1268.54 seconds |
| Started | Jul 12 07:55:36 PM PDT 24 |
| Finished | Jul 12 08:16:46 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-abc7a1bb-9dad-4cdf-a708-846c81bac06c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2284645986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.2284645986 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.669654266 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 5758590440 ps |
| CPU time | 563.69 seconds |
| Started | Jul 12 07:57:32 PM PDT 24 |
| Finished | Jul 12 08:06:57 PM PDT 24 |
| Peak memory | 610664 kb |
| Host | smart-2f090d1b-92ec-4a4e-8d03-f7a9fd8691a2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=669654266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.669654266 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1472364281 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 256158880476 ps |
| CPU time | 12158.3 seconds |
| Started | Jul 12 07:55:51 PM PDT 24 |
| Finished | Jul 12 11:18:32 PM PDT 24 |
| Peak memory | 611120 kb |
| Host | smart-17ac0a37-8b7c-4845-9649-0ac7af577742 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1472364281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1472364281 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.1765055106 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3126311060 ps |
| CPU time | 312 seconds |
| Started | Jul 12 07:56:44 PM PDT 24 |
| Finished | Jul 12 08:01:58 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-813ca4ad-2164-470b-910e-6e49a076c260 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765055106 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.1765055106 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.3866504122 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 3431765220 ps |
| CPU time | 392.99 seconds |
| Started | Jul 12 07:57:11 PM PDT 24 |
| Finished | Jul 12 08:03:45 PM PDT 24 |
| Peak memory | 609688 kb |
| Host | smart-5cbd1fba-80c5-4ed9-a053-295246150203 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866504122 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.3866504122 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.577967707 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 7106622690 ps |
| CPU time | 397.91 seconds |
| Started | Jul 12 07:57:04 PM PDT 24 |
| Finished | Jul 12 08:03:43 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-0d4d2510-b222-490e-8490-a3c1bcad726b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=577967707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.577967707 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.695295524 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 3108020736 ps |
| CPU time | 244.1 seconds |
| Started | Jul 12 08:15:30 PM PDT 24 |
| Finished | Jul 12 08:19:35 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-6dad0b25-6a65-4869-ae4d-1c117aec4b28 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695295524 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_aon_timer_smoketest.695295524 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3226705908 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 8926029880 ps |
| CPU time | 776.17 seconds |
| Started | Jul 12 07:55:25 PM PDT 24 |
| Finished | Jul 12 08:08:22 PM PDT 24 |
| Peak memory | 610916 kb |
| Host | smart-8c0de359-0017-429f-b4b3-eee191a3ddd5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3226705908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.3226705908 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.4252977711 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 4723360000 ps |
| CPU time | 429.28 seconds |
| Started | Jul 12 07:55:39 PM PDT 24 |
| Finished | Jul 12 08:02:49 PM PDT 24 |
| Peak memory | 611112 kb |
| Host | smart-c1d4a61c-5405-44cd-95f3-79ecb3dbfec7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =4252977711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.4252977711 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.3116361282 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 6881818970 ps |
| CPU time | 1131.41 seconds |
| Started | Jul 12 08:00:46 PM PDT 24 |
| Finished | Jul 12 08:19:39 PM PDT 24 |
| Peak memory | 616444 kb |
| Host | smart-b7aaedbc-4e54-4c64-9500-ba3dee81ed16 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116361282 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.3116361282 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2935113334 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 6513060661 ps |
| CPU time | 589.48 seconds |
| Started | Jul 12 07:59:33 PM PDT 24 |
| Finished | Jul 12 08:09:23 PM PDT 24 |
| Peak memory | 621764 kb |
| Host | smart-ef3d8a73-57ac-4fc3-a291-4f16fc72930f |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2935113334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.2935113334 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.917859952 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 4434449048 ps |
| CPU time | 654.13 seconds |
| Started | Jul 12 07:59:33 PM PDT 24 |
| Finished | Jul 12 08:10:28 PM PDT 24 |
| Peak memory | 612984 kb |
| Host | smart-23abe126-44c2-4b62-b136-bcfc0f27044d |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917859952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.917859952 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2172760496 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 4038176616 ps |
| CPU time | 657.99 seconds |
| Started | Jul 12 08:00:14 PM PDT 24 |
| Finished | Jul 12 08:11:14 PM PDT 24 |
| Peak memory | 613280 kb |
| Host | smart-044154e5-045a-440d-9027-e162e9903629 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172760496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2172760496 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.411347928 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 3891130280 ps |
| CPU time | 633.27 seconds |
| Started | Jul 12 08:03:05 PM PDT 24 |
| Finished | Jul 12 08:13:38 PM PDT 24 |
| Peak memory | 613356 kb |
| Host | smart-472800fa-bfed-4c2a-9239-ce8524229aa3 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411347928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.411347928 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3699220561 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 4199556774 ps |
| CPU time | 797.4 seconds |
| Started | Jul 12 07:59:49 PM PDT 24 |
| Finished | Jul 12 08:13:07 PM PDT 24 |
| Peak memory | 613308 kb |
| Host | smart-5eee390b-c03f-4145-8ccb-3634455915e2 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699220561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.3699220561 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1948668743 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 4609030656 ps |
| CPU time | 616.16 seconds |
| Started | Jul 12 07:59:57 PM PDT 24 |
| Finished | Jul 12 08:10:14 PM PDT 24 |
| Peak memory | 612916 kb |
| Host | smart-b838b44b-e94b-4b80-a2f7-b5ae2562204c |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948668743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.1948668743 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1741780440 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 5037564720 ps |
| CPU time | 630.53 seconds |
| Started | Jul 12 07:59:39 PM PDT 24 |
| Finished | Jul 12 08:10:11 PM PDT 24 |
| Peak memory | 613264 kb |
| Host | smart-5a0de88a-c727-494b-a86a-1f01a3679ff6 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741780440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1741780440 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.787819309 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 3075699873 ps |
| CPU time | 222.06 seconds |
| Started | Jul 12 07:59:53 PM PDT 24 |
| Finished | Jul 12 08:03:36 PM PDT 24 |
| Peak memory | 608948 kb |
| Host | smart-e632304d-8e33-4612-afe3-4fcef9970b1a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787819309 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_clkmgr_jitter.787819309 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.161833428 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 3970067460 ps |
| CPU time | 484.88 seconds |
| Started | Jul 12 07:59:37 PM PDT 24 |
| Finished | Jul 12 08:07:43 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-0e1dbee5-a44f-4f05-99a1-e720c881cc16 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161833428 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.161833428 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.4156717311 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 2978235708 ps |
| CPU time | 150.52 seconds |
| Started | Jul 12 08:00:40 PM PDT 24 |
| Finished | Jul 12 08:03:11 PM PDT 24 |
| Peak memory | 609908 kb |
| Host | smart-5872310c-a927-48d3-a6b8-25d1d8fdd560 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156717311 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.4156717311 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1540988894 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 4056641800 ps |
| CPU time | 649.58 seconds |
| Started | Jul 12 07:58:16 PM PDT 24 |
| Finished | Jul 12 08:09:06 PM PDT 24 |
| Peak memory | 610308 kb |
| Host | smart-a9b508cc-ebb9-4b47-b770-fd7a04c5c54f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540988894 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.1540988894 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3226994866 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 3650896684 ps |
| CPU time | 446.88 seconds |
| Started | Jul 12 07:59:35 PM PDT 24 |
| Finished | Jul 12 08:07:03 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-fcc6bdd7-b5fe-4f39-86fe-1ee6308ab6d4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226994866 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.3226994866 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.785254110 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 4982169216 ps |
| CPU time | 503.54 seconds |
| Started | Jul 12 07:58:44 PM PDT 24 |
| Finished | Jul 12 08:07:08 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-b004ac52-f2aa-4473-a662-3762eba62d9e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785254110 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.785254110 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.476326614 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 4558720458 ps |
| CPU time | 395.64 seconds |
| Started | Jul 12 08:00:54 PM PDT 24 |
| Finished | Jul 12 08:07:30 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-7be4b480-cb97-44fc-a049-5a89928af1f3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476326614 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.476326614 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.593769375 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 9540004472 ps |
| CPU time | 1239.83 seconds |
| Started | Jul 12 08:02:27 PM PDT 24 |
| Finished | Jul 12 08:23:09 PM PDT 24 |
| Peak memory | 611148 kb |
| Host | smart-7580036a-f978-4a34-89ae-4808a5fc4a7d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593769375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.593769375 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3908058762 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 3914387700 ps |
| CPU time | 498.67 seconds |
| Started | Jul 12 08:00:02 PM PDT 24 |
| Finished | Jul 12 08:08:22 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-4635b8bf-ebe5-4365-8423-ba9f05d8a3ad |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908058762 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.3908058762 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2401055906 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 5011837132 ps |
| CPU time | 721.96 seconds |
| Started | Jul 12 08:00:33 PM PDT 24 |
| Finished | Jul 12 08:12:36 PM PDT 24 |
| Peak memory | 610528 kb |
| Host | smart-61f54f11-d6c4-4e1d-b9d9-e46ac6049e5d |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401055906 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.2401055906 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2655568347 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 2536498886 ps |
| CPU time | 283.65 seconds |
| Started | Jul 12 08:14:12 PM PDT 24 |
| Finished | Jul 12 08:19:00 PM PDT 24 |
| Peak memory | 610004 kb |
| Host | smart-7e2037db-0970-4af4-a2c3-498427f09e70 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655568347 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.2655568347 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.86750555 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 16590021352 ps |
| CPU time | 3594.26 seconds |
| Started | Jul 12 07:57:45 PM PDT 24 |
| Finished | Jul 12 08:57:40 PM PDT 24 |
| Peak memory | 610716 kb |
| Host | smart-d9ed35de-b17d-41ed-8127-eae26c076026 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86750555 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.86750555 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.169348140 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 26445869282 ps |
| CPU time | 4196.52 seconds |
| Started | Jul 12 08:01:55 PM PDT 24 |
| Finished | Jul 12 09:11:52 PM PDT 24 |
| Peak memory | 610916 kb |
| Host | smart-e2321811-485f-44a9-a4a6-2fd9957f3631 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=169348140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.169348140 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.4266818212 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 4147242420 ps |
| CPU time | 567.62 seconds |
| Started | Jul 12 07:58:37 PM PDT 24 |
| Finished | Jul 12 08:08:06 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-439effae-159d-4fdc-836b-af5fe80559b3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42668 18212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.4266818212 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.2522059631 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 2637572380 ps |
| CPU time | 217.27 seconds |
| Started | Jul 12 07:58:08 PM PDT 24 |
| Finished | Jul 12 08:01:46 PM PDT 24 |
| Peak memory | 610232 kb |
| Host | smart-2b95328d-6931-4fb5-99f5-b7fafc590912 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522059631 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.2522059631 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.909309671 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 6339616255 ps |
| CPU time | 653.56 seconds |
| Started | Jul 12 07:59:43 PM PDT 24 |
| Finished | Jul 12 08:10:38 PM PDT 24 |
| Peak memory | 611712 kb |
| Host | smart-872ccad1-ad80-4719-817e-e84a3ec96933 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909309671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrn g_lc_hw_debug_en_test.909309671 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.100530327 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 2408992672 ps |
| CPU time | 298.66 seconds |
| Started | Jul 12 08:02:22 PM PDT 24 |
| Finished | Jul 12 08:07:21 PM PDT 24 |
| Peak memory | 610020 kb |
| Host | smart-ccf56786-915e-4b6b-822d-983c87852b10 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100530327 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_csrng_smoketest.100530327 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.910886711 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 5280068104 ps |
| CPU time | 674.31 seconds |
| Started | Jul 12 07:54:35 PM PDT 24 |
| Finished | Jul 12 08:05:51 PM PDT 24 |
| Peak memory | 611224 kb |
| Host | smart-05db06b7-ad05-4d28-b27e-bccd4e9e7141 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=910886711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.910886711 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.3456518126 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 6157995296 ps |
| CPU time | 1933.17 seconds |
| Started | Jul 12 07:58:55 PM PDT 24 |
| Finished | Jul 12 08:31:10 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-b8aaad2d-3e7c-49d2-86d3-6628a5182697 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456518126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.3456518126 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.3278666173 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 3298493598 ps |
| CPU time | 560.08 seconds |
| Started | Jul 12 08:03:32 PM PDT 24 |
| Finished | Jul 12 08:12:53 PM PDT 24 |
| Peak memory | 610664 kb |
| Host | smart-41031a86-5fd3-4f84-a0af-12af3b7d29e1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278666173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ boot_mode.3278666173 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.431854917 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 6936139791 ps |
| CPU time | 1032.37 seconds |
| Started | Jul 12 07:57:20 PM PDT 24 |
| Finished | Jul 12 08:14:34 PM PDT 24 |
| Peak memory | 611388 kb |
| Host | smart-915bb6df-e8e1-4d58-bc04-0a86a6118d60 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431854917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.431854917 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.2275231969 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 3151886042 ps |
| CPU time | 848.88 seconds |
| Started | Jul 12 07:59:10 PM PDT 24 |
| Finished | Jul 12 08:13:20 PM PDT 24 |
| Peak memory | 616960 kb |
| Host | smart-cda4d4d2-053d-4443-a98d-8bfed8268160 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275231969 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.2275231969 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.417162712 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 7548742160 ps |
| CPU time | 1636.97 seconds |
| Started | Jul 12 07:59:17 PM PDT 24 |
| Finished | Jul 12 08:26:36 PM PDT 24 |
| Peak memory | 609696 kb |
| Host | smart-166c317e-2831-40a4-afed-5536cea55af3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417162712 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.417162712 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2659295450 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 3034283840 ps |
| CPU time | 196.68 seconds |
| Started | Jul 12 07:58:00 PM PDT 24 |
| Finished | Jul 12 08:01:17 PM PDT 24 |
| Peak memory | 609664 kb |
| Host | smart-27770078-f971-4848-b7f4-50ee5e4df418 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26 59295450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.2659295450 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.3066237732 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 3311314960 ps |
| CPU time | 288.62 seconds |
| Started | Jul 12 07:57:28 PM PDT 24 |
| Finished | Jul 12 08:02:18 PM PDT 24 |
| Peak memory | 609068 kb |
| Host | smart-978bccc8-927a-404b-a3da-7a87a7463d78 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066237732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.3066237732 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.843816048 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 3367456184 ps |
| CPU time | 439.16 seconds |
| Started | Jul 12 08:02:23 PM PDT 24 |
| Finished | Jul 12 08:09:43 PM PDT 24 |
| Peak memory | 609648 kb |
| Host | smart-319eb3b6-6f51-4bc5-9340-440b57e4a662 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=843816048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.843816048 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.2172905975 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 2848782944 ps |
| CPU time | 259.97 seconds |
| Started | Jul 12 07:54:35 PM PDT 24 |
| Finished | Jul 12 07:58:55 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-64a56ed4-efaf-47a8-b445-5f2b9bc88e59 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172905975 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.2172905975 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.689759116 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 2988191344 ps |
| CPU time | 241.79 seconds |
| Started | Jul 12 07:52:13 PM PDT 24 |
| Finished | Jul 12 07:56:16 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-5fa45259-9a82-4c0d-8326-2cc97600596a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689759116 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.689759116 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.413614335 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 3455981698 ps |
| CPU time | 258.57 seconds |
| Started | Jul 12 07:57:24 PM PDT 24 |
| Finished | Jul 12 08:01:44 PM PDT 24 |
| Peak memory | 610084 kb |
| Host | smart-e07c859c-647e-4f09-878e-fe99af7e78a2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413614335 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_example_manufacturer.413614335 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.697998745 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 2305309574 ps |
| CPU time | 139.4 seconds |
| Started | Jul 12 07:54:14 PM PDT 24 |
| Finished | Jul 12 07:56:36 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-0842ebc0-efbd-4663-87dc-d93d54a58f92 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697998745 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_example_rom.697998745 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2326289860 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 59424384463 ps |
| CPU time | 11246.1 seconds |
| Started | Jul 12 07:56:43 PM PDT 24 |
| Finished | Jul 12 11:04:12 PM PDT 24 |
| Peak memory | 625228 kb |
| Host | smart-86b96f7d-0e1a-4054-8886-0eac4c4380d1 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2326289860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.2326289860 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.418929671 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 4766082588 ps |
| CPU time | 815.35 seconds |
| Started | Jul 12 08:01:03 PM PDT 24 |
| Finished | Jul 12 08:14:39 PM PDT 24 |
| Peak memory | 611272 kb |
| Host | smart-551a1b6e-f330-4f4b-baa2-922c347b9b11 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=418929671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.418929671 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.2675284403 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 6029390050 ps |
| CPU time | 1026.92 seconds |
| Started | Jul 12 07:53:58 PM PDT 24 |
| Finished | Jul 12 08:11:06 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-bd424519-fab4-413d-9d07-861803e3dfa0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675284403 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.2675284403 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1443460330 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 5534095698 ps |
| CPU time | 1182.04 seconds |
| Started | Jul 12 07:55:24 PM PDT 24 |
| Finished | Jul 12 08:15:07 PM PDT 24 |
| Peak memory | 610420 kb |
| Host | smart-9a076dc2-7950-49c4-869d-51adc6c0fba2 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443460330 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.1443460330 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1678839459 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 7542365257 ps |
| CPU time | 1169.34 seconds |
| Started | Jul 12 08:00:41 PM PDT 24 |
| Finished | Jul 12 08:20:12 PM PDT 24 |
| Peak memory | 609652 kb |
| Host | smart-0302c7bf-1006-4042-993d-890043d24418 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678839459 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1678839459 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.265922209 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 6074646973 ps |
| CPU time | 1383.12 seconds |
| Started | Jul 12 07:58:02 PM PDT 24 |
| Finished | Jul 12 08:21:07 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-8c6cff75-7610-4f8b-aaf4-886b61daeed2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265922209 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.265922209 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2382597325 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 3539011280 ps |
| CPU time | 495.72 seconds |
| Started | Jul 12 07:55:30 PM PDT 24 |
| Finished | Jul 12 08:03:48 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-250fdd34-8024-49d0-ba5f-cf9a421bed72 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382597325 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.2382597325 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1655379220 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 5342147441 ps |
| CPU time | 410.37 seconds |
| Started | Jul 12 07:53:11 PM PDT 24 |
| Finished | Jul 12 08:00:03 PM PDT 24 |
| Peak memory | 611100 kb |
| Host | smart-12b7cdd4-0398-49ae-8b62-5b217cfb4665 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16 55379220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.1655379220 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2032652597 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 5393276736 ps |
| CPU time | 1358.72 seconds |
| Started | Jul 12 08:03:47 PM PDT 24 |
| Finished | Jul 12 08:26:28 PM PDT 24 |
| Peak memory | 610424 kb |
| Host | smart-6028db7d-3ce2-4692-8809-db603f028a6c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032652597 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.2032652597 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1108275368 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4105175288 ps |
| CPU time | 672.47 seconds |
| Started | Jul 12 07:53:07 PM PDT 24 |
| Finished | Jul 12 08:04:20 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-43fa7773-0963-4c15-9c60-14d3b8f1c73c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108275368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.1108275368 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3129289795 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 4089284420 ps |
| CPU time | 686.35 seconds |
| Started | Jul 12 07:54:18 PM PDT 24 |
| Finished | Jul 12 08:05:45 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-556c3360-d391-4ca7-8d09-767f8a0cee16 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3129289795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.3129289795 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3874054739 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 4785923096 ps |
| CPU time | 716.47 seconds |
| Started | Jul 12 08:01:11 PM PDT 24 |
| Finished | Jul 12 08:13:08 PM PDT 24 |
| Peak memory | 610572 kb |
| Host | smart-0f1b250d-6a53-4382-b1ae-1c7c9646ec1d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3874054739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3874054739 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.140736475 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 3305873890 ps |
| CPU time | 354.8 seconds |
| Started | Jul 12 08:01:25 PM PDT 24 |
| Finished | Jul 12 08:07:20 PM PDT 24 |
| Peak memory | 608948 kb |
| Host | smart-9c93051c-b569-45b5-ad41-837e9f4185e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407364 75 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.140736475 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.3273414496 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 23714904760 ps |
| CPU time | 1823.04 seconds |
| Started | Jul 12 07:53:26 PM PDT 24 |
| Finished | Jul 12 08:23:51 PM PDT 24 |
| Peak memory | 613592 kb |
| Host | smart-d9cd419d-285a-4361-b5d8-ac76d465dc9d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273414496 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.3273414496 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2837299457 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 23913904667 ps |
| CPU time | 2037.69 seconds |
| Started | Jul 12 08:00:25 PM PDT 24 |
| Finished | Jul 12 08:34:24 PM PDT 24 |
| Peak memory | 616428 kb |
| Host | smart-16dfef95-2d64-4288-be46-366898f67704 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2837299457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.2837299457 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.384008850 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 2662762200 ps |
| CPU time | 253.24 seconds |
| Started | Jul 12 08:07:41 PM PDT 24 |
| Finished | Jul 12 08:11:55 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-659ce0e2-721c-412d-828f-36da42bec495 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=384008850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.384008850 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.2567363897 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 4421624181 ps |
| CPU time | 476 seconds |
| Started | Jul 12 07:53:36 PM PDT 24 |
| Finished | Jul 12 08:01:33 PM PDT 24 |
| Peak memory | 609652 kb |
| Host | smart-d287cb28-13ae-45e5-88a9-0cb12f56c849 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567363897 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.2567363897 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.1117611786 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 2428125216 ps |
| CPU time | 231.52 seconds |
| Started | Jul 12 08:02:55 PM PDT 24 |
| Finished | Jul 12 08:06:47 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-fe895af7-7a65-4ada-9c26-7c627b8186ec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117611786 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.1117611786 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.2136233912 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 2869823820 ps |
| CPU time | 283.8 seconds |
| Started | Jul 12 07:57:24 PM PDT 24 |
| Finished | Jul 12 08:02:09 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-46a82580-72e5-4591-8944-b48e5a8cb257 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136233912 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.2136233912 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.2914437455 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 3522383160 ps |
| CPU time | 220.49 seconds |
| Started | Jul 12 07:58:04 PM PDT 24 |
| Finished | Jul 12 08:01:46 PM PDT 24 |
| Peak memory | 608956 kb |
| Host | smart-cb35953a-5696-4e39-967a-a2d0842767a5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914437455 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.2914437455 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1511244120 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2889213906 ps |
| CPU time | 230.77 seconds |
| Started | Jul 12 07:59:30 PM PDT 24 |
| Finished | Jul 12 08:03:21 PM PDT 24 |
| Peak memory | 609720 kb |
| Host | smart-c16b3517-ad86-4932-a898-53daf962cb38 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511244120 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.1511244120 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.284341309 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 2428493108 ps |
| CPU time | 235.56 seconds |
| Started | Jul 12 08:02:32 PM PDT 24 |
| Finished | Jul 12 08:06:28 PM PDT 24 |
| Peak memory | 609696 kb |
| Host | smart-e1552973-5c59-495b-9151-8238007928af |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284341309 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.284341309 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.761691889 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 8199148914 ps |
| CPU time | 2286.78 seconds |
| Started | Jul 12 07:59:20 PM PDT 24 |
| Finished | Jul 12 08:37:29 PM PDT 24 |
| Peak memory | 609200 kb |
| Host | smart-e4829385-c4e4-4c0d-ac5d-e8ab1c807c5d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761691889 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_hmac_multistream.761691889 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.3158124047 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 2630338040 ps |
| CPU time | 290.8 seconds |
| Started | Jul 12 08:03:02 PM PDT 24 |
| Finished | Jul 12 08:07:54 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-27f6014d-966a-4ec6-88cf-07b307b4ecd3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158124047 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.3158124047 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.354901402 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 2875684140 ps |
| CPU time | 318.84 seconds |
| Started | Jul 12 08:02:10 PM PDT 24 |
| Finished | Jul 12 08:07:30 PM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-9941730c-0160-47b0-b093-6ebaa1aaca37 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354901402 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_smoketest.354901402 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1930413952 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 3960029338 ps |
| CPU time | 584.46 seconds |
| Started | Jul 12 07:53:22 PM PDT 24 |
| Finished | Jul 12 08:03:08 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-5ac5aff1-7416-48a6-ad39-f973eca47f69 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930413952 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.1930413952 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.4079871607 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 5772876022 ps |
| CPU time | 1091.98 seconds |
| Started | Jul 12 07:55:52 PM PDT 24 |
| Finished | Jul 12 08:14:05 PM PDT 24 |
| Peak memory | 609756 kb |
| Host | smart-f29d25f2-70e6-4667-9bbe-3e17ddb84324 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079871607 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.4079871607 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1026364484 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 5507137652 ps |
| CPU time | 873.15 seconds |
| Started | Jul 12 07:57:19 PM PDT 24 |
| Finished | Jul 12 08:11:54 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-5abaa454-4927-44ef-98bf-eabfa2657313 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026364484 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.1026364484 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3251682106 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 4265053656 ps |
| CPU time | 902.88 seconds |
| Started | Jul 12 07:55:27 PM PDT 24 |
| Finished | Jul 12 08:10:31 PM PDT 24 |
| Peak memory | 609900 kb |
| Host | smart-90835bee-695e-4b0b-8272-0379c71857c8 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251682106 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.3251682106 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.2724020294 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 64917306448 ps |
| CPU time | 12289.3 seconds |
| Started | Jul 12 07:55:07 PM PDT 24 |
| Finished | Jul 12 11:19:58 PM PDT 24 |
| Peak memory | 624712 kb |
| Host | smart-1585ad0b-629c-472c-94fb-22b867c20ea3 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2724020294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.2724020294 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3289883265 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 10469376440 ps |
| CPU time | 2412.45 seconds |
| Started | Jul 12 07:59:09 PM PDT 24 |
| Finished | Jul 12 08:39:23 PM PDT 24 |
| Peak memory | 617856 kb |
| Host | smart-e6d2728f-10ff-482b-b2e1-f6e5e75e4fa3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289 883265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.3289883265 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.4238504593 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 12378003795 ps |
| CPU time | 2362.8 seconds |
| Started | Jul 12 07:56:53 PM PDT 24 |
| Finished | Jul 12 08:36:17 PM PDT 24 |
| Peak memory | 618208 kb |
| Host | smart-9274148f-596a-4ce5-a09b-0d56b4d8ba2a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4238504593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.4238504593 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2001763136 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 7627778291 ps |
| CPU time | 895.26 seconds |
| Started | Jul 12 08:01:50 PM PDT 24 |
| Finished | Jul 12 08:16:46 PM PDT 24 |
| Peak memory | 618156 kb |
| Host | smart-4c25eae1-fca3-43d5-b8e3-5f75457bf3f0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2001763136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2001763136 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1993088617 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 12148935496 ps |
| CPU time | 1716.77 seconds |
| Started | Jul 12 07:56:34 PM PDT 24 |
| Finished | Jul 12 08:25:12 PM PDT 24 |
| Peak memory | 618108 kb |
| Host | smart-1ef21582-ffb5-4381-b78a-76136d1fbba7 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1993088617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.1993088617 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3047625203 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 10595346964 ps |
| CPU time | 1862.82 seconds |
| Started | Jul 12 08:03:26 PM PDT 24 |
| Finished | Jul 12 08:34:30 PM PDT 24 |
| Peak memory | 611428 kb |
| Host | smart-6dedaab0-d9ed-4b86-a75a-f4e001f70dd6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304762 5203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.3047625203 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.746022156 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 7989891636 ps |
| CPU time | 1977.75 seconds |
| Started | Jul 12 07:58:11 PM PDT 24 |
| Finished | Jul 12 08:31:09 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-7921ab1f-8acb-4e02-a170-4d4746d22cdf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74602 2156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.746022156 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.193215615 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 16298881300 ps |
| CPU time | 4514.3 seconds |
| Started | Jul 12 08:02:49 PM PDT 24 |
| Finished | Jul 12 09:18:04 PM PDT 24 |
| Peak memory | 610352 kb |
| Host | smart-7fdf51d7-cc07-4534-a67e-27291732e8b2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19321 5615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.193215615 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.2615973266 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 2479582050 ps |
| CPU time | 224.63 seconds |
| Started | Jul 12 07:58:00 PM PDT 24 |
| Finished | Jul 12 08:01:45 PM PDT 24 |
| Peak memory | 608972 kb |
| Host | smart-9fcabc0d-2204-4498-903a-195bd00536db |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615973266 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.2615973266 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.2213210317 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 2741504596 ps |
| CPU time | 344.54 seconds |
| Started | Jul 12 07:54:41 PM PDT 24 |
| Finished | Jul 12 08:00:26 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-706e2f82-0d19-4dad-9021-f279c7b2676b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213210317 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.2213210317 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.1543638272 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 2730091344 ps |
| CPU time | 332.48 seconds |
| Started | Jul 12 07:58:51 PM PDT 24 |
| Finished | Jul 12 08:04:24 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-1fb172cc-d2ad-47db-8b66-bdc85da3ed86 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543638272 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.1543638272 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2149943944 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 2367071710 ps |
| CPU time | 208.53 seconds |
| Started | Jul 12 08:00:12 PM PDT 24 |
| Finished | Jul 12 08:03:42 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-fa3550a1-ac7a-475c-8743-9a039a6cf710 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149943944 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.2149943944 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2162324010 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 3055189060 ps |
| CPU time | 291.51 seconds |
| Started | Jul 12 07:58:21 PM PDT 24 |
| Finished | Jul 12 08:03:14 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-9be8899d-f551-4b97-8f8e-2953e014b7a7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162324010 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.2162324010 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.914611245 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 3278538995 ps |
| CPU time | 333.88 seconds |
| Started | Jul 12 07:58:38 PM PDT 24 |
| Finished | Jul 12 08:04:13 PM PDT 24 |
| Peak memory | 609676 kb |
| Host | smart-02194f02-ce89-472b-999f-a397fa665300 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914611245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.914611245 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1262694787 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 3365112179 ps |
| CPU time | 283.19 seconds |
| Started | Jul 12 08:01:43 PM PDT 24 |
| Finished | Jul 12 08:06:26 PM PDT 24 |
| Peak memory | 609712 kb |
| Host | smart-86045978-2b1f-4844-9a30-071b68a7e3b0 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12626947 87 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1262694787 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.3571780188 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 2458516450 ps |
| CPU time | 224.88 seconds |
| Started | Jul 12 08:02:53 PM PDT 24 |
| Finished | Jul 12 08:06:39 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-4afbbad8-e3a6-47a6-a6b8-a6b2e08c16ff |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571780188 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.3571780188 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2901270744 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 2387434192 ps |
| CPU time | 269.68 seconds |
| Started | Jul 12 07:54:58 PM PDT 24 |
| Finished | Jul 12 07:59:29 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-1e6ce759-2e3a-47d3-b8de-5d6d8f4eff92 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901270744 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.2901270744 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.2429683978 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 4349423912 ps |
| CPU time | 457.35 seconds |
| Started | Jul 12 08:00:07 PM PDT 24 |
| Finished | Jul 12 08:07:46 PM PDT 24 |
| Peak memory | 610948 kb |
| Host | smart-cc35ab84-07e1-4525-84f8-3a13a94573ce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2429683978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.2429683978 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1325388151 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 8963350057 ps |
| CPU time | 1047 seconds |
| Started | Jul 12 07:55:15 PM PDT 24 |
| Finished | Jul 12 08:12:43 PM PDT 24 |
| Peak memory | 622536 kb |
| Host | smart-1ee5c85f-f564-4f58-ac12-2195fc5ef577 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325388151 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.1325388151 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.2358648796 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 3173795967 ps |
| CPU time | 106.06 seconds |
| Started | Jul 12 07:55:11 PM PDT 24 |
| Finished | Jul 12 07:56:58 PM PDT 24 |
| Peak memory | 615432 kb |
| Host | smart-0f388ce4-3b5a-4c90-8838-1c26f039830d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2358648796 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.2358648796 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3848164623 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 2627334819 ps |
| CPU time | 120.37 seconds |
| Started | Jul 12 07:56:02 PM PDT 24 |
| Finished | Jul 12 07:58:03 PM PDT 24 |
| Peak memory | 618312 kb |
| Host | smart-5343cda0-d173-4c1b-bd5c-f1e85cc1ca13 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848164623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3848164623 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1809208719 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 52518833188 ps |
| CPU time | 5478.46 seconds |
| Started | Jul 12 07:55:56 PM PDT 24 |
| Finished | Jul 12 09:27:16 PM PDT 24 |
| Peak memory | 620656 kb |
| Host | smart-e3217237-c5d8-4936-afa8-82d2a69b7a50 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809208719 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_dev.1809208719 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2162937430 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 10174052060 ps |
| CPU time | 926.42 seconds |
| Started | Jul 12 07:54:23 PM PDT 24 |
| Finished | Jul 12 08:09:51 PM PDT 24 |
| Peak memory | 619416 kb |
| Host | smart-9a43b626-15ba-4be7-b36d-258d32706cf3 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162937430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.2162937430 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.2620609759 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 48190168900 ps |
| CPU time | 5992.02 seconds |
| Started | Jul 12 07:54:36 PM PDT 24 |
| Finished | Jul 12 09:34:29 PM PDT 24 |
| Peak memory | 619424 kb |
| Host | smart-628e3713-b3c1-45a8-9e1b-30aedc915472 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620609759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.2620609759 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.418301029 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 34573105734 ps |
| CPU time | 1987.5 seconds |
| Started | Jul 12 07:53:54 PM PDT 24 |
| Finished | Jul 12 08:27:02 PM PDT 24 |
| Peak memory | 620888 kb |
| Host | smart-3fd83952-fe88-4e51-ac9f-92c19dc3150c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=418301029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testunl ocks.418301029 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2463639535 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 17747053436 ps |
| CPU time | 4014.41 seconds |
| Started | Jul 12 07:56:13 PM PDT 24 |
| Finished | Jul 12 09:03:09 PM PDT 24 |
| Peak memory | 610664 kb |
| Host | smart-32e7dc4d-bf56-4041-a3d1-234110f8d0d6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2463639535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.2463639535 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3017318116 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 18781459637 ps |
| CPU time | 2795.68 seconds |
| Started | Jul 12 07:56:45 PM PDT 24 |
| Finished | Jul 12 08:43:22 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-b9c16929-5e53-4cae-a5e9-6d52d0b4ecb2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3017318116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3017318116 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.953856780 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 25054055971 ps |
| CPU time | 4238.63 seconds |
| Started | Jul 12 08:00:53 PM PDT 24 |
| Finished | Jul 12 09:11:33 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-e9c576aa-5799-433a-a2d3-cf33fd1fbcba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953856780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.953856780 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.55486689 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 4067848052 ps |
| CPU time | 608.47 seconds |
| Started | Jul 12 07:58:34 PM PDT 24 |
| Finished | Jul 12 08:08:44 PM PDT 24 |
| Peak memory | 610384 kb |
| Host | smart-b4d8fb95-fbd2-400d-bc02-00e19c6a7deb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55486689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.55486689 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.3765015212 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 5591526000 ps |
| CPU time | 911.34 seconds |
| Started | Jul 12 07:57:31 PM PDT 24 |
| Finished | Jul 12 08:12:44 PM PDT 24 |
| Peak memory | 610956 kb |
| Host | smart-f8bcc19c-42a2-4a40-bf49-efcccdec301c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3765015212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.3765015212 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.2462611575 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 5762380360 ps |
| CPU time | 1263.78 seconds |
| Started | Jul 12 08:02:36 PM PDT 24 |
| Finished | Jul 12 08:23:41 PM PDT 24 |
| Peak memory | 610524 kb |
| Host | smart-a8d07780-365c-4795-b454-e75109081b56 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462611575 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.2462611575 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.3399323822 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 2809775290 ps |
| CPU time | 291.99 seconds |
| Started | Jul 12 07:59:33 PM PDT 24 |
| Finished | Jul 12 08:04:27 PM PDT 24 |
| Peak memory | 610228 kb |
| Host | smart-02ee2e94-e09d-413d-88b8-6ff45ce76398 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399323822 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.3399323822 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1078159006 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 7021915544 ps |
| CPU time | 1158.6 seconds |
| Started | Jul 12 07:58:58 PM PDT 24 |
| Finished | Jul 12 08:18:19 PM PDT 24 |
| Peak memory | 610924 kb |
| Host | smart-9b0b8764-8bb5-4f91-85a0-09c5ef38e8f3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1078159006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.1078159006 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3233924350 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 8221715160 ps |
| CPU time | 1292 seconds |
| Started | Jul 12 07:54:38 PM PDT 24 |
| Finished | Jul 12 08:16:10 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-8319e981-b34b-4748-91a7-c9e40f76cb77 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3233924350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.3233924350 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3659192179 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 6477972296 ps |
| CPU time | 1175.57 seconds |
| Started | Jul 12 07:56:37 PM PDT 24 |
| Finished | Jul 12 08:16:14 PM PDT 24 |
| Peak memory | 610960 kb |
| Host | smart-a2ba60a9-6190-4d40-b0f6-c6659662b47d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3659192179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.3659192179 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.512511507 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 4583819716 ps |
| CPU time | 667.73 seconds |
| Started | Jul 12 07:59:11 PM PDT 24 |
| Finished | Jul 12 08:10:21 PM PDT 24 |
| Peak memory | 609692 kb |
| Host | smart-4f85585e-d162-472d-aed0-395ed6cc498a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=512511507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.512511507 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.190735890 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 2375163868 ps |
| CPU time | 225.44 seconds |
| Started | Jul 12 08:15:26 PM PDT 24 |
| Finished | Jul 12 08:19:12 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-24089e90-fb9f-446a-9cbb-6696a983d936 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190735890 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_otp_ctrl_smoketest.190735890 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.2895059282 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 2740425040 ps |
| CPU time | 221.31 seconds |
| Started | Jul 12 07:52:56 PM PDT 24 |
| Finished | Jul 12 07:56:38 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-85607b91-f463-4e65-a3e8-42dedd43d877 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895059282 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.2895059282 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.1290952080 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 2963906256 ps |
| CPU time | 301.24 seconds |
| Started | Jul 12 07:59:00 PM PDT 24 |
| Finished | Jul 12 08:04:03 PM PDT 24 |
| Peak memory | 610128 kb |
| Host | smart-9f47b827-5ba1-47ae-8a18-fc724d610fb6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290952080 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.1290952080 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.373269462 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 4115885842 ps |
| CPU time | 619.02 seconds |
| Started | Jul 12 08:02:31 PM PDT 24 |
| Finished | Jul 12 08:12:51 PM PDT 24 |
| Peak memory | 609420 kb |
| Host | smart-9b5045f0-f16f-405e-a14a-708467438687 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373269462 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.373269462 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.3038730504 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 10545052808 ps |
| CPU time | 673.46 seconds |
| Started | Jul 12 08:02:01 PM PDT 24 |
| Finished | Jul 12 08:13:15 PM PDT 24 |
| Peak memory | 610960 kb |
| Host | smart-6d10c07d-eb89-4724-a6c6-41df21eb26d4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038730504 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.3038730504 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2651627031 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 10171803301 ps |
| CPU time | 1806.56 seconds |
| Started | Jul 12 07:55:23 PM PDT 24 |
| Finished | Jul 12 08:25:31 PM PDT 24 |
| Peak memory | 611420 kb |
| Host | smart-ad4cfb92-e190-40fd-b760-4dc0ca075880 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651 627031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.2651627031 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1764568724 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 21296913999 ps |
| CPU time | 2689.84 seconds |
| Started | Jul 12 08:00:32 PM PDT 24 |
| Finished | Jul 12 08:45:23 PM PDT 24 |
| Peak memory | 611364 kb |
| Host | smart-03467bf6-a902-4c93-8f11-aac52f81714d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176 4568724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.1764568724 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.929905270 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 14907953831 ps |
| CPU time | 1459.06 seconds |
| Started | Jul 12 07:55:02 PM PDT 24 |
| Finished | Jul 12 08:19:22 PM PDT 24 |
| Peak memory | 611632 kb |
| Host | smart-84d7bce3-801c-43d4-b3be-80fe8a9f1275 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=929905270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.929905270 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1190252291 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 21566040572 ps |
| CPU time | 1777.01 seconds |
| Started | Jul 12 08:00:46 PM PDT 24 |
| Finished | Jul 12 08:30:24 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-6e2f12e3-be2a-4f8c-9751-11ab0a2099e4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1190252291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1190252291 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2994847190 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 7805529458 ps |
| CPU time | 763.12 seconds |
| Started | Jul 12 07:56:40 PM PDT 24 |
| Finished | Jul 12 08:09:24 PM PDT 24 |
| Peak memory | 610836 kb |
| Host | smart-a40cafe2-eb5e-4e2a-9335-dd8048d64d1e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994847190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.2994847190 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2817977089 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 8037318744 ps |
| CPU time | 685.23 seconds |
| Started | Jul 12 07:56:33 PM PDT 24 |
| Finished | Jul 12 08:08:00 PM PDT 24 |
| Peak memory | 616564 kb |
| Host | smart-0c94f71d-1f88-4dd9-befa-8020afedb7ad |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2817977089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2817977089 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.4131873053 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 8544342932 ps |
| CPU time | 506.6 seconds |
| Started | Jul 12 07:54:52 PM PDT 24 |
| Finished | Jul 12 08:03:20 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-857526ad-8af8-4371-bb57-199ab0a5eecf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131873053 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.4131873053 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3441632937 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 3895997204 ps |
| CPU time | 314.69 seconds |
| Started | Jul 12 07:55:29 PM PDT 24 |
| Finished | Jul 12 08:00:45 PM PDT 24 |
| Peak memory | 616444 kb |
| Host | smart-f0a3bd28-a4e8-4a88-a100-14024aa30bfc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3441632937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.3441632937 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.318786320 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 9889009668 ps |
| CPU time | 1366.83 seconds |
| Started | Jul 12 07:55:50 PM PDT 24 |
| Finished | Jul 12 08:18:38 PM PDT 24 |
| Peak memory | 611672 kb |
| Host | smart-79384288-336c-482e-b459-1c73a8c1a672 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318786320 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.318786320 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.494276005 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 7055913280 ps |
| CPU time | 379.6 seconds |
| Started | Jul 12 08:00:49 PM PDT 24 |
| Finished | Jul 12 08:07:10 PM PDT 24 |
| Peak memory | 610828 kb |
| Host | smart-f790bbbd-27c6-42e7-bd5e-022e08e14371 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494276005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.494276005 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1623085230 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 6445257728 ps |
| CPU time | 882.02 seconds |
| Started | Jul 12 07:56:33 PM PDT 24 |
| Finished | Jul 12 08:11:17 PM PDT 24 |
| Peak memory | 610844 kb |
| Host | smart-0b3371b0-b298-450e-a827-7bc2d6b63608 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623085230 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.1623085230 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1285297900 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 26772795175 ps |
| CPU time | 2673.77 seconds |
| Started | Jul 12 07:55:03 PM PDT 24 |
| Finished | Jul 12 08:39:37 PM PDT 24 |
| Peak memory | 611660 kb |
| Host | smart-b6fc3a8c-378e-4d4a-85ad-55d6c47f38f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1285297900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1285297900 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2531905256 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 21408724132 ps |
| CPU time | 1399.69 seconds |
| Started | Jul 12 08:00:56 PM PDT 24 |
| Finished | Jul 12 08:24:17 PM PDT 24 |
| Peak memory | 610952 kb |
| Host | smart-1bed409b-ae4b-4216-b8ef-7cadbc70236c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2531905256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2531905256 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3193546957 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 6324785242 ps |
| CPU time | 370.16 seconds |
| Started | Jul 12 08:00:31 PM PDT 24 |
| Finished | Jul 12 08:06:42 PM PDT 24 |
| Peak memory | 610924 kb |
| Host | smart-e043f0f8-b43a-40b6-9e92-fa96348b1e1b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3193546957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3193546957 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2595131401 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 3504801384 ps |
| CPU time | 286 seconds |
| Started | Jul 12 07:56:24 PM PDT 24 |
| Finished | Jul 12 08:01:11 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-6c78353d-02bd-4a1d-8a99-1a86402b385d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595131401 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.2595131401 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1132876719 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 6882871615 ps |
| CPU time | 640.4 seconds |
| Started | Jul 12 07:57:28 PM PDT 24 |
| Finished | Jul 12 08:08:10 PM PDT 24 |
| Peak memory | 616680 kb |
| Host | smart-882281bb-f013-4d65-9522-d4debc003908 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1132876719 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.1132876719 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4234743678 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 5164889246 ps |
| CPU time | 450.18 seconds |
| Started | Jul 12 07:59:51 PM PDT 24 |
| Finished | Jul 12 08:07:22 PM PDT 24 |
| Peak memory | 609696 kb |
| Host | smart-a111fb05-e115-4dcb-ad58-cb9d549fa212 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42347436 78 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4234743678 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1581655868 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 6257430036 ps |
| CPU time | 484.97 seconds |
| Started | Jul 12 08:03:37 PM PDT 24 |
| Finished | Jul 12 08:11:43 PM PDT 24 |
| Peak memory | 611144 kb |
| Host | smart-c04b4912-85a7-4f05-96e4-09f167553add |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1581655868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.1581655868 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1067868490 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 5096441784 ps |
| CPU time | 464.95 seconds |
| Started | Jul 12 08:13:54 PM PDT 24 |
| Finished | Jul 12 08:21:43 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-752cace3-a9b7-4f98-aa3d-eb6c36d81ed3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067868490 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.1067868490 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.503975533 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 6925672193 ps |
| CPU time | 939.07 seconds |
| Started | Jul 12 07:54:43 PM PDT 24 |
| Finished | Jul 12 08:10:23 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-f8d1737c-0540-4318-93bc-73c9874d1574 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503975533 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.503975533 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2240094482 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 3964593628 ps |
| CPU time | 386.86 seconds |
| Started | Jul 12 07:55:49 PM PDT 24 |
| Finished | Jul 12 08:02:18 PM PDT 24 |
| Peak memory | 609712 kb |
| Host | smart-72d6232c-253e-423b-8a36-d535874aa686 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240094482 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2240094482 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1220081739 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 6299904200 ps |
| CPU time | 413.13 seconds |
| Started | Jul 12 08:04:35 PM PDT 24 |
| Finished | Jul 12 08:11:30 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-93116210-d579-4ce7-b8c1-255962faeeee |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220081739 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.1220081739 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1054460477 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 4587962984 ps |
| CPU time | 484.96 seconds |
| Started | Jul 12 07:55:49 PM PDT 24 |
| Finished | Jul 12 08:03:54 PM PDT 24 |
| Peak memory | 610976 kb |
| Host | smart-c12d5b54-760d-4c71-ab7d-91333f7ff131 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105 4460477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.1054460477 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.389567200 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 8925936755 ps |
| CPU time | 560.06 seconds |
| Started | Jul 12 07:58:26 PM PDT 24 |
| Finished | Jul 12 08:07:47 PM PDT 24 |
| Peak memory | 625148 kb |
| Host | smart-347a7955-9aa2-4308-91b1-50094a80bab1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389567200 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.389567200 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.32960734 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 5079672336 ps |
| CPU time | 648.82 seconds |
| Started | Jul 12 07:55:44 PM PDT 24 |
| Finished | Jul 12 08:06:34 PM PDT 24 |
| Peak memory | 609696 kb |
| Host | smart-fe8990b6-4f42-483d-ba8e-b127c337c4b7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32960734 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_cpu_info.32960734 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3112198557 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 4583812868 ps |
| CPU time | 623.8 seconds |
| Started | Jul 12 07:53:06 PM PDT 24 |
| Finished | Jul 12 08:03:30 PM PDT 24 |
| Peak memory | 641460 kb |
| Host | smart-70a6c2b9-42f4-45a0-9078-cbfb926314c6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3112198557 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.3112198557 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.289976999 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 2735938840 ps |
| CPU time | 233.54 seconds |
| Started | Jul 12 08:04:14 PM PDT 24 |
| Finished | Jul 12 08:08:09 PM PDT 24 |
| Peak memory | 610228 kb |
| Host | smart-30f82fc3-2f82-432e-acd5-5409a0e9d2b3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289976999 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_rstmgr_smoketest.289976999 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1925134778 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 4902898162 ps |
| CPU time | 392.56 seconds |
| Started | Jul 12 07:55:51 PM PDT 24 |
| Finished | Jul 12 08:02:24 PM PDT 24 |
| Peak memory | 610808 kb |
| Host | smart-37312fdf-1171-4d49-85b4-fbde4bfdca39 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925134778 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.1925134778 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2989472993 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 3531699740 ps |
| CPU time | 275.05 seconds |
| Started | Jul 12 07:55:06 PM PDT 24 |
| Finished | Jul 12 07:59:42 PM PDT 24 |
| Peak memory | 610208 kb |
| Host | smart-772922ec-2537-4b93-af4b-a418ad392fd7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989472993 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.2989472993 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1394843102 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3250082950 ps |
| CPU time | 314.23 seconds |
| Started | Jul 12 08:03:47 PM PDT 24 |
| Finished | Jul 12 08:09:03 PM PDT 24 |
| Peak memory | 609664 kb |
| Host | smart-817bd498-22fc-442b-8f82-0f96d1f8e86b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1394843102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.1394843102 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1195402586 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 2733096092 ps |
| CPU time | 273.14 seconds |
| Started | Jul 12 08:00:56 PM PDT 24 |
| Finished | Jul 12 08:05:30 PM PDT 24 |
| Peak memory | 610320 kb |
| Host | smart-af804159-e744-40da-85c2-64d9f2467d31 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195402586 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.1195402586 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.452527905 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1838680080 ps |
| CPU time | 141.37 seconds |
| Started | Jul 12 08:03:55 PM PDT 24 |
| Finished | Jul 12 08:06:17 PM PDT 24 |
| Peak memory | 610084 kb |
| Host | smart-9893cbcb-aa78-40f2-af3a-242fa46521e1 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452527905 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.452527905 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1463960074 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 5189503646 ps |
| CPU time | 942.26 seconds |
| Started | Jul 12 07:57:42 PM PDT 24 |
| Finished | Jul 12 08:13:25 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-d1c32411-c3b8-4e33-a6e7-6c7c67f1f1c7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14639 60074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.1463960074 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.556895388 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 5461801616 ps |
| CPU time | 987.04 seconds |
| Started | Jul 12 07:55:26 PM PDT 24 |
| Finished | Jul 12 08:11:54 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-b3d5292b-6b78-4eef-8413-1778db0830d3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=556895388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.556895388 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1393912031 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 5349594951 ps |
| CPU time | 523.06 seconds |
| Started | Jul 12 08:03:32 PM PDT 24 |
| Finished | Jul 12 08:12:16 PM PDT 24 |
| Peak memory | 624224 kb |
| Host | smart-9ee913bf-d8a5-49f8-b523-1e2812272125 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393912031 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.1393912031 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3558221054 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 6282463984 ps |
| CPU time | 610.63 seconds |
| Started | Jul 12 08:00:47 PM PDT 24 |
| Finished | Jul 12 08:10:59 PM PDT 24 |
| Peak memory | 620716 kb |
| Host | smart-a63208d9-3176-4f94-93af-4a7af516c910 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558221054 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.3558221054 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.360589574 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 5067264376 ps |
| CPU time | 464.08 seconds |
| Started | Jul 12 08:01:00 PM PDT 24 |
| Finished | Jul 12 08:08:45 PM PDT 24 |
| Peak memory | 619664 kb |
| Host | smart-5f97291b-c212-4089-9e9e-d067abf5bbc3 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360589 574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.360589574 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.4144682478 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 2305170952 ps |
| CPU time | 200.9 seconds |
| Started | Jul 12 08:03:32 PM PDT 24 |
| Finished | Jul 12 08:06:55 PM PDT 24 |
| Peak memory | 609020 kb |
| Host | smart-71b8eec6-4e3b-4351-9280-7f1cc83126df |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144682478 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.4144682478 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.2662073032 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 3213681352 ps |
| CPU time | 275.35 seconds |
| Started | Jul 12 07:56:30 PM PDT 24 |
| Finished | Jul 12 08:01:06 PM PDT 24 |
| Peak memory | 609012 kb |
| Host | smart-60aa17b5-2993-47b9-9630-858e494031d0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662073032 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.2662073032 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3425388136 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 3138956696 ps |
| CPU time | 283.71 seconds |
| Started | Jul 12 08:04:11 PM PDT 24 |
| Finished | Jul 12 08:08:56 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-e8700f31-57ed-4357-9e0a-f2a475340606 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425388136 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.3425388136 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.758148117 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 7421035312 ps |
| CPU time | 945.56 seconds |
| Started | Jul 12 07:58:54 PM PDT 24 |
| Finished | Jul 12 08:14:40 PM PDT 24 |
| Peak memory | 610724 kb |
| Host | smart-9f003b3b-abca-42bc-bd5c-dcb6bca505f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75814811 7 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.758148117 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1104008138 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 2322584478 ps |
| CPU time | 189.32 seconds |
| Started | Jul 12 07:59:34 PM PDT 24 |
| Finished | Jul 12 08:02:44 PM PDT 24 |
| Peak memory | 610740 kb |
| Host | smart-397237eb-c01a-454c-8ee3-aa243a4b6a36 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104008 138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.1104008138 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.3048512934 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4600255250 ps |
| CPU time | 293.21 seconds |
| Started | Jul 12 07:55:05 PM PDT 24 |
| Finished | Jul 12 07:59:59 PM PDT 24 |
| Peak memory | 609512 kb |
| Host | smart-a7624472-4476-4cbb-b710-31428d3120da |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048512934 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.3048512934 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2010246542 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 9999137056 ps |
| CPU time | 1549.91 seconds |
| Started | Jul 12 07:54:58 PM PDT 24 |
| Finished | Jul 12 08:20:49 PM PDT 24 |
| Peak memory | 611056 kb |
| Host | smart-b733a806-de96-4711-b3c5-31e6920dc57b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010246542 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.2010246542 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.4289643918 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 8895866170 ps |
| CPU time | 792.74 seconds |
| Started | Jul 12 07:59:21 PM PDT 24 |
| Finished | Jul 12 08:12:35 PM PDT 24 |
| Peak memory | 611080 kb |
| Host | smart-50a12a4f-1a84-4f96-a2e5-b8acf0ae2db5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289643918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl eep_sram_ret_contents_no_scramble.4289643918 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1671842295 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 7837442120 ps |
| CPU time | 629.29 seconds |
| Started | Jul 12 07:59:09 PM PDT 24 |
| Finished | Jul 12 08:09:40 PM PDT 24 |
| Peak memory | 611084 kb |
| Host | smart-148a3bf4-d93a-4bd0-a27d-038bdadad393 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671842295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.1671842295 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.1943638893 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 8120342477 ps |
| CPU time | 947.26 seconds |
| Started | Jul 12 07:54:21 PM PDT 24 |
| Finished | Jul 12 08:10:09 PM PDT 24 |
| Peak memory | 625268 kb |
| Host | smart-f9f4d0f1-0f68-4fde-9cb2-c67913c30305 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943638893 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.1943638893 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1686556415 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 4071294797 ps |
| CPU time | 564.67 seconds |
| Started | Jul 12 07:53:28 PM PDT 24 |
| Finished | Jul 12 08:02:54 PM PDT 24 |
| Peak memory | 625244 kb |
| Host | smart-c6550b88-b9af-44db-a246-bcfd5d1dface |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686556415 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.1686556415 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.60982573 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3476384233 ps |
| CPU time | 293.1 seconds |
| Started | Jul 12 07:54:10 PM PDT 24 |
| Finished | Jul 12 07:59:04 PM PDT 24 |
| Peak memory | 618632 kb |
| Host | smart-a9f1c094-f07a-453b-9c84-7cc51bad993a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60982573 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.60982573 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1759212841 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 9808980600 ps |
| CPU time | 932.78 seconds |
| Started | Jul 12 07:58:40 PM PDT 24 |
| Finished | Jul 12 08:14:14 PM PDT 24 |
| Peak memory | 610980 kb |
| Host | smart-ff8514e6-1ce6-4fae-b09c-7bb131af06b7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759212841 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.1759212841 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.4249301131 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 5100697768 ps |
| CPU time | 763.2 seconds |
| Started | Jul 12 07:57:22 PM PDT 24 |
| Finished | Jul 12 08:10:07 PM PDT 24 |
| Peak memory | 611208 kb |
| Host | smart-0c82bd1a-a047-44fe-9c3f-faa5a3174898 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249301131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.4249301131 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.529107739 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3536070042 ps |
| CPU time | 576.72 seconds |
| Started | Jul 12 08:03:53 PM PDT 24 |
| Finished | Jul 12 08:13:31 PM PDT 24 |
| Peak memory | 611004 kb |
| Host | smart-4c94bfa6-9408-403b-9bd4-8b1194a26869 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529107739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.529107739 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2310183647 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 5013332011 ps |
| CPU time | 795.41 seconds |
| Started | Jul 12 08:01:42 PM PDT 24 |
| Finished | Jul 12 08:14:58 PM PDT 24 |
| Peak memory | 611288 kb |
| Host | smart-bade4b5e-eb9e-4209-82c1-82ee90ea011a |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310183647 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2310183647 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3643905848 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 2538027398 ps |
| CPU time | 226.18 seconds |
| Started | Jul 12 08:03:37 PM PDT 24 |
| Finished | Jul 12 08:07:24 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-2cb87754-bde4-4ef0-837c-cf414e1acfc0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643905848 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.3643905848 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2467604973 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 20189826409 ps |
| CPU time | 3497.51 seconds |
| Started | Jul 12 07:56:42 PM PDT 24 |
| Finished | Jul 12 08:55:02 PM PDT 24 |
| Peak memory | 609856 kb |
| Host | smart-3cb5a85e-8f94-4847-8000-b3fc04a77b50 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467604973 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.2467604973 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3143507910 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 4765514728 ps |
| CPU time | 662.79 seconds |
| Started | Jul 12 07:54:28 PM PDT 24 |
| Finished | Jul 12 08:05:34 PM PDT 24 |
| Peak memory | 613844 kb |
| Host | smart-8ab38759-51f5-45d5-ba32-46b377bf86de |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143507910 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.3143507910 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2625086927 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 2933546002 ps |
| CPU time | 233.22 seconds |
| Started | Jul 12 07:56:22 PM PDT 24 |
| Finished | Jul 12 08:00:16 PM PDT 24 |
| Peak memory | 613792 kb |
| Host | smart-7a3d744c-4f72-4a8f-849e-acbfb0eea791 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625086927 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.2625086927 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.198834838 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 3215468260 ps |
| CPU time | 370.64 seconds |
| Started | Jul 12 07:55:50 PM PDT 24 |
| Finished | Jul 12 08:02:02 PM PDT 24 |
| Peak memory | 609664 kb |
| Host | smart-bc33a6f9-c444-45ec-b70b-1dde232fbdc5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198834838 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.198834838 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3245946823 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 24325684912 ps |
| CPU time | 1637.9 seconds |
| Started | Jul 12 07:57:07 PM PDT 24 |
| Finished | Jul 12 08:24:27 PM PDT 24 |
| Peak memory | 614324 kb |
| Host | smart-b5bdc8bf-097d-4f0b-948a-fb3a29705058 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32459468 23 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.3245946823 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2959174189 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 5860029014 ps |
| CPU time | 573.67 seconds |
| Started | Jul 12 07:56:55 PM PDT 24 |
| Finished | Jul 12 08:06:30 PM PDT 24 |
| Peak memory | 611080 kb |
| Host | smart-61abcacb-7f9e-4983-a60f-0dcc8cca9c46 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959174189 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2959174189 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.2106687144 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 2867529658 ps |
| CPU time | 264.44 seconds |
| Started | Jul 12 08:05:25 PM PDT 24 |
| Finished | Jul 12 08:09:50 PM PDT 24 |
| Peak memory | 616236 kb |
| Host | smart-dacaa29b-545e-4c5c-a679-597eeb2ebf51 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106687144 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_uart_smoketest.2106687144 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.983449237 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 3572403344 ps |
| CPU time | 676.48 seconds |
| Started | Jul 12 07:57:36 PM PDT 24 |
| Finished | Jul 12 08:08:53 PM PDT 24 |
| Peak memory | 622824 kb |
| Host | smart-f1402f44-3d10-41fa-ab4c-41826d72979c |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983449237 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.983449237 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.675447129 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 4335558362 ps |
| CPU time | 688.54 seconds |
| Started | Jul 12 07:53:10 PM PDT 24 |
| Finished | Jul 12 08:04:40 PM PDT 24 |
| Peak memory | 625088 kb |
| Host | smart-0af385a5-ea24-451a-8e78-0a258508776d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675447129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_ alt_clk_freq.675447129 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.722247694 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 4410850863 ps |
| CPU time | 705.42 seconds |
| Started | Jul 12 07:52:30 PM PDT 24 |
| Finished | Jul 12 08:04:17 PM PDT 24 |
| Peak memory | 625064 kb |
| Host | smart-17a4687e-8c23-4fdf-a9ef-6d102cb9b281 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722247694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.722247694 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2136080438 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 78859640823 ps |
| CPU time | 13596.8 seconds |
| Started | Jul 12 07:52:31 PM PDT 24 |
| Finished | Jul 12 11:39:10 PM PDT 24 |
| Peak memory | 634452 kb |
| Host | smart-a49385ef-c959-41c0-89f2-d8a6c998bace |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2136080438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.2136080438 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3648253560 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 4623473064 ps |
| CPU time | 718.55 seconds |
| Started | Jul 12 07:57:21 PM PDT 24 |
| Finished | Jul 12 08:09:21 PM PDT 24 |
| Peak memory | 624448 kb |
| Host | smart-2aaa6d12-2b4b-4eb2-b19e-f871d499de4c |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648253560 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.3648253560 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1507633576 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 4659828600 ps |
| CPU time | 629.96 seconds |
| Started | Jul 12 07:52:56 PM PDT 24 |
| Finished | Jul 12 08:03:27 PM PDT 24 |
| Peak memory | 623108 kb |
| Host | smart-4ab2b0ef-492a-4d40-88ff-c848bd83ddd2 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507633576 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.1507633576 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.4189214341 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 4559543710 ps |
| CPU time | 651.79 seconds |
| Started | Jul 12 07:54:52 PM PDT 24 |
| Finished | Jul 12 08:05:44 PM PDT 24 |
| Peak memory | 624424 kb |
| Host | smart-ca20ee52-a509-409d-a96e-86051ad4a4cb |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189214341 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.4189214341 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.3285094605 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 17448071269 ps |
| CPU time | 2112.47 seconds |
| Started | Jul 12 07:59:39 PM PDT 24 |
| Finished | Jul 12 08:34:53 PM PDT 24 |
| Peak memory | 621424 kb |
| Host | smart-eb811cc5-399c-4ffc-bdd9-8c74dc89264f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3285094605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.3285094605 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.511441115 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 6792709423 ps |
| CPU time | 586.52 seconds |
| Started | Jul 12 07:59:44 PM PDT 24 |
| Finished | Jul 12 08:09:31 PM PDT 24 |
| Peak memory | 621416 kb |
| Host | smart-fe7075ba-e55c-48d8-8b3e-91382c1cfb3c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511441115 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.511441115 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_testunlock0.4094026312 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 2011475980 ps |
| CPU time | 125.74 seconds |
| Started | Jul 12 07:59:46 PM PDT 24 |
| Finished | Jul 12 08:01:53 PM PDT 24 |
| Peak memory | 612732 kb |
| Host | smart-31665cef-67c2-4585-97e4-236997a5b0a0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4094026312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.4094026312 |
| Directory | /workspace/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.4273151622 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 15214143166 ps |
| CPU time | 4524.72 seconds |
| Started | Jul 12 08:05:51 PM PDT 24 |
| Finished | Jul 12 09:21:17 PM PDT 24 |
| Peak memory | 611556 kb |
| Host | smart-c7906a98-8839-4379-b49e-0bee6fc619f3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273151622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.4273151622 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.3931634378 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 15375562303 ps |
| CPU time | 3795.11 seconds |
| Started | Jul 12 08:17:41 PM PDT 24 |
| Finished | Jul 12 09:20:57 PM PDT 24 |
| Peak memory | 611540 kb |
| Host | smart-a9db5155-7294-45dd-b5f0-26e0a0e500c7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931634378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.3931634378 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3732769110 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 15157009531 ps |
| CPU time | 3634.03 seconds |
| Started | Jul 12 08:06:10 PM PDT 24 |
| Finished | Jul 12 09:06:46 PM PDT 24 |
| Peak memory | 611536 kb |
| Host | smart-fae9a396-f208-48b7-a01f-c5d843130a53 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732769110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.3732769110 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.1144967006 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 15343870602 ps |
| CPU time | 4734.79 seconds |
| Started | Jul 12 08:05:16 PM PDT 24 |
| Finished | Jul 12 09:24:12 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-50684c91-4213-4e1e-8d4f-ccd7bb714586 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144967006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.1144967006 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1281834472 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 10948597752 ps |
| CPU time | 2708.6 seconds |
| Started | Jul 12 08:17:24 PM PDT 24 |
| Finished | Jul 12 09:02:35 PM PDT 24 |
| Peak memory | 610976 kb |
| Host | smart-2817d57d-b21c-42d7-b4ca-3cc73b88c6cf |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281834472 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_test_unlocked0.1281834472 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3326755901 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 15491764790 ps |
| CPU time | 3449.77 seconds |
| Started | Jul 12 08:06:45 PM PDT 24 |
| Finished | Jul 12 09:04:16 PM PDT 24 |
| Peak memory | 610772 kb |
| Host | smart-497132cc-2a0e-4413-8634-dd4110a116e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326755901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3326755901 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1883079684 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 15005685864 ps |
| CPU time | 3941.12 seconds |
| Started | Jul 12 08:19:10 PM PDT 24 |
| Finished | Jul 12 09:24:52 PM PDT 24 |
| Peak memory | 610716 kb |
| Host | smart-22cd6494-2899-4700-a174-0564ead5d838 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883079684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.1883079684 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1817236598 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 14801770554 ps |
| CPU time | 3811.77 seconds |
| Started | Jul 12 08:07:18 PM PDT 24 |
| Finished | Jul 12 09:10:52 PM PDT 24 |
| Peak memory | 610764 kb |
| Host | smart-9be4c300-fcda-44d7-8db1-f92cbbbd4bed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817236598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext _no_meas.1817236598 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.830972893 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 14422097246 ps |
| CPU time | 3706.84 seconds |
| Started | Jul 12 08:05:54 PM PDT 24 |
| Finished | Jul 12 09:07:42 PM PDT 24 |
| Peak memory | 611472 kb |
| Host | smart-7ed141ed-2653-48fe-b5bd-e37aa33f0073 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830972893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shut down_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_s hutdown_exception_c.830972893 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.3719428008 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 26561202335 ps |
| CPU time | 3359.59 seconds |
| Started | Jul 12 08:05:36 PM PDT 24 |
| Finished | Jul 12 09:01:36 PM PDT 24 |
| Peak memory | 613048 kb |
| Host | smart-9bc3e532-dc50-4bf0-9c52-03c51408e206 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719428008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.3719428008 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.1056304223 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 14880383840 ps |
| CPU time | 3893.29 seconds |
| Started | Jul 12 08:17:39 PM PDT 24 |
| Finished | Jul 12 09:22:34 PM PDT 24 |
| Peak memory | 610504 kb |
| Host | smart-f5269d5e-bca8-4db7-b4c4-280c2f0b9251 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1056304223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.1056304223 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.1454965632 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 17436095136 ps |
| CPU time | 4294.05 seconds |
| Started | Jul 12 08:17:59 PM PDT 24 |
| Finished | Jul 12 09:29:35 PM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-28f424af-eaa7-4218-86d0-3bd528380171 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454965632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.1454965632 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.48640518 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 5147393374 ps |
| CPU time | 863.83 seconds |
| Started | Jul 12 08:15:03 PM PDT 24 |
| Finished | Jul 12 08:29:29 PM PDT 24 |
| Peak memory | 609832 kb |
| Host | smart-85c3ad4a-02f7-4e42-ad5f-a3e10c5848aa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48640518 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.48640518 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_raw_unlock.2841834580 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 5867089691 ps |
| CPU time | 266.42 seconds |
| Started | Jul 12 08:02:47 PM PDT 24 |
| Finished | Jul 12 08:07:14 PM PDT 24 |
| Peak memory | 624268 kb |
| Host | smart-e0283434-f010-46d6-937e-10c1e9b092bf |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2841834580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.2841834580 |
| Directory | /workspace/1.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.2159248449 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 2613176449 ps |
| CPU time | 106.31 seconds |
| Started | Jul 12 08:02:01 PM PDT 24 |
| Finished | Jul 12 08:03:48 PM PDT 24 |
| Peak memory | 616924 kb |
| Host | smart-2133232b-e2ab-4e47-8b3b-817723e7a06a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159248449 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.2159248449 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1093932864 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 6295285486 ps |
| CPU time | 577.23 seconds |
| Started | Jul 12 08:18:53 PM PDT 24 |
| Finished | Jul 12 08:28:31 PM PDT 24 |
| Peak memory | 621744 kb |
| Host | smart-0c926e4f-7558-435c-b36a-a59a5bbeb018 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093932864 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.1093932864 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1205617113 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 4031503936 ps |
| CPU time | 694.6 seconds |
| Started | Jul 12 08:16:24 PM PDT 24 |
| Finished | Jul 12 08:28:00 PM PDT 24 |
| Peak memory | 618984 kb |
| Host | smart-315363a6-39c9-408c-ad67-39051b17efa3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1205617113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.1205617113 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1193320154 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 12187235005 ps |
| CPU time | 1145.43 seconds |
| Started | Jul 12 08:16:23 PM PDT 24 |
| Finished | Jul 12 08:35:30 PM PDT 24 |
| Peak memory | 625200 kb |
| Host | smart-449788d1-b242-41a6-91a2-af2e756bd3d5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193320154 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.1193320154 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.11722730 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 4117050700 ps |
| CPU time | 503.2 seconds |
| Started | Jul 12 08:16:40 PM PDT 24 |
| Finished | Jul 12 08:25:03 PM PDT 24 |
| Peak memory | 619160 kb |
| Host | smart-6cc2e95c-6cae-42d9-aa41-004de56dba5c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=11722730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.11722730 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.1054463912 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 6060970958 ps |
| CPU time | 544 seconds |
| Started | Jul 12 08:16:43 PM PDT 24 |
| Finished | Jul 12 08:25:49 PM PDT 24 |
| Peak memory | 650080 kb |
| Host | smart-24124454-6740-4ee4-9e6f-064653369920 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1054463912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.1054463912 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3068798862 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 5266817891 ps |
| CPU time | 509.54 seconds |
| Started | Jul 12 08:17:08 PM PDT 24 |
| Finished | Jul 12 08:25:38 PM PDT 24 |
| Peak memory | 621744 kb |
| Host | smart-af44f497-06f5-4e29-8ff7-54d9b6bc5b52 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068798862 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.3068798862 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.105500080 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 4428337540 ps |
| CPU time | 610.8 seconds |
| Started | Jul 12 08:18:35 PM PDT 24 |
| Finished | Jul 12 08:28:47 PM PDT 24 |
| Peak memory | 619112 kb |
| Host | smart-068e2fd7-cd90-4526-b4f2-6750ff6d56c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=105500080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.105500080 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.420934662 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 6403621340 ps |
| CPU time | 458.98 seconds |
| Started | Jul 12 08:17:56 PM PDT 24 |
| Finished | Jul 12 08:25:36 PM PDT 24 |
| Peak memory | 621768 kb |
| Host | smart-d5aa478c-ce7f-40c1-a54e-bb451993a083 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420934662 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.420934662 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.4033552199 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 4581208840 ps |
| CPU time | 558.19 seconds |
| Started | Jul 12 08:17:11 PM PDT 24 |
| Finished | Jul 12 08:26:31 PM PDT 24 |
| Peak memory | 618156 kb |
| Host | smart-cf0681b7-3fa4-4d7d-a050-64dad974a781 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4033552199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.4033552199 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2437390994 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 3163895680 ps |
| CPU time | 358.03 seconds |
| Started | Jul 12 08:17:55 PM PDT 24 |
| Finished | Jul 12 08:23:54 PM PDT 24 |
| Peak memory | 649268 kb |
| Host | smart-024540d0-0ce2-41a6-81a6-ee0b711383b6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437390994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2437390994 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1613091764 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 9922356964 ps |
| CPU time | 1062.04 seconds |
| Started | Jul 12 08:18:36 PM PDT 24 |
| Finished | Jul 12 08:36:19 PM PDT 24 |
| Peak memory | 623436 kb |
| Host | smart-ade10f9f-70cb-426b-b6f0-d7ad05488392 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613091764 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.1613091764 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1058542922 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 4352661050 ps |
| CPU time | 576.61 seconds |
| Started | Jul 12 08:16:53 PM PDT 24 |
| Finished | Jul 12 08:26:31 PM PDT 24 |
| Peak memory | 618996 kb |
| Host | smart-7df6b9df-dab9-4a9c-8cb5-ea07e455e3e3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1058542922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.1058542922 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.2881074904 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 5239727022 ps |
| CPU time | 828.15 seconds |
| Started | Jul 12 08:18:01 PM PDT 24 |
| Finished | Jul 12 08:31:50 PM PDT 24 |
| Peak memory | 617136 kb |
| Host | smart-c1b8f5c0-d035-436d-bf37-c83c4a056925 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2881074904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.2881074904 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2729314011 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 7988836776 ps |
| CPU time | 1655.04 seconds |
| Started | Jul 12 08:17:26 PM PDT 24 |
| Finished | Jul 12 08:45:03 PM PDT 24 |
| Peak memory | 619176 kb |
| Host | smart-e7540fc2-6d60-40a2-9749-969362460493 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2729314011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.2729314011 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.311067899 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 4300436856 ps |
| CPU time | 672.31 seconds |
| Started | Jul 12 08:17:31 PM PDT 24 |
| Finished | Jul 12 08:28:45 PM PDT 24 |
| Peak memory | 618180 kb |
| Host | smart-394de9a4-de63-448e-b2ed-0fed528a1a09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=311067899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.311067899 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1412926715 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 7600240842 ps |
| CPU time | 1305.95 seconds |
| Started | Jul 12 08:18:00 PM PDT 24 |
| Finished | Jul 12 08:39:47 PM PDT 24 |
| Peak memory | 618824 kb |
| Host | smart-c81709f4-24b8-4823-83c0-799738b6265f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1412926715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.1412926715 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1906085125 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 3593014360 ps |
| CPU time | 418.59 seconds |
| Started | Jul 12 08:20:58 PM PDT 24 |
| Finished | Jul 12 08:27:58 PM PDT 24 |
| Peak memory | 649124 kb |
| Host | smart-93275601-0040-45a3-a5d7-a05ac24ae3ec |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906085125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1906085125 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3777399618 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 7586987088 ps |
| CPU time | 1208.32 seconds |
| Started | Jul 12 08:19:09 PM PDT 24 |
| Finished | Jul 12 08:39:18 PM PDT 24 |
| Peak memory | 619172 kb |
| Host | smart-a886a836-f828-4d0c-ba86-2345eb2d4dc8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3777399618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.3777399618 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.429622343 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 12812019444 ps |
| CPU time | 2289.15 seconds |
| Started | Jul 12 08:17:05 PM PDT 24 |
| Finished | Jul 12 08:55:15 PM PDT 24 |
| Peak memory | 618812 kb |
| Host | smart-e6aaac1e-793c-471d-a5da-932bef79b6b8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=429622343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.429622343 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.3257131600 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 14189037086 ps |
| CPU time | 1708.67 seconds |
| Started | Jul 12 08:03:25 PM PDT 24 |
| Finished | Jul 12 08:31:54 PM PDT 24 |
| Peak memory | 608380 kb |
| Host | smart-317a2135-2905-42d1-83c4-9dbe807fca5a |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257131600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.3 257131600 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3891967902 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4283071186 ps |
| CPU time | 453.87 seconds |
| Started | Jul 12 08:14:21 PM PDT 24 |
| Finished | Jul 12 08:21:57 PM PDT 24 |
| Peak memory | 619212 kb |
| Host | smart-5007b238-2866-44d8-b6f4-f35e0fd4d009 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 891967902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.3891967902 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.4277275548 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 3183098344 ps |
| CPU time | 376.98 seconds |
| Started | Jul 12 08:03:50 PM PDT 24 |
| Finished | Jul 12 08:10:08 PM PDT 24 |
| Peak memory | 609688 kb |
| Host | smart-063d8e84-9c99-4655-9286-c2cc97acece0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=4277275548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.4277275548 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2557420934 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 18774986050 ps |
| CPU time | 784.05 seconds |
| Started | Jul 12 08:08:06 PM PDT 24 |
| Finished | Jul 12 08:21:11 PM PDT 24 |
| Peak memory | 619548 kb |
| Host | smart-7029625c-a046-44c8-a2a6-dea6d3c5417c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2557420934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2557420934 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.1446835955 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 3231032168 ps |
| CPU time | 257.24 seconds |
| Started | Jul 12 08:07:23 PM PDT 24 |
| Finished | Jul 12 08:11:41 PM PDT 24 |
| Peak memory | 609632 kb |
| Host | smart-b453dc8c-25ab-4fb4-847a-7a4853eef5d6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446835955 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.1446835955 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2840670856 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 3373289497 ps |
| CPU time | 320.76 seconds |
| Started | Jul 12 08:10:37 PM PDT 24 |
| Finished | Jul 12 08:15:59 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-5604bb0d-9e04-481c-8b36-9dfa96860a54 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840 670856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.2840670856 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.872472003 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 3236526284 ps |
| CPU time | 296.36 seconds |
| Started | Jul 12 08:12:12 PM PDT 24 |
| Finished | Jul 12 08:17:09 PM PDT 24 |
| Peak memory | 609664 kb |
| Host | smart-15fd24ba-89c7-48bb-9a2a-71c988c5fb20 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872472003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.872472003 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.209507060 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 3320973608 ps |
| CPU time | 278.57 seconds |
| Started | Jul 12 08:09:33 PM PDT 24 |
| Finished | Jul 12 08:14:13 PM PDT 24 |
| Peak memory | 609720 kb |
| Host | smart-23894e57-9690-485a-8127-2dbbf117201a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209507060 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.209507060 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.1118242717 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 2741091300 ps |
| CPU time | 299.93 seconds |
| Started | Jul 12 08:07:57 PM PDT 24 |
| Finished | Jul 12 08:12:59 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-e3d1c5d8-550c-4daf-8072-73832a0895b5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118242717 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.1118242717 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.1962495474 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 3394857069 ps |
| CPU time | 389.41 seconds |
| Started | Jul 12 08:07:08 PM PDT 24 |
| Finished | Jul 12 08:13:38 PM PDT 24 |
| Peak memory | 610836 kb |
| Host | smart-3916a49b-be64-4068-b8e7-3aac186187c0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962495474 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.1962495474 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.1320089933 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 3521178848 ps |
| CPU time | 331.64 seconds |
| Started | Jul 12 08:19:12 PM PDT 24 |
| Finished | Jul 12 08:24:45 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-536e3ed1-a18a-44af-bf80-d66ef08907a7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320089933 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.1320089933 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.1916749363 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 3138831730 ps |
| CPU time | 299.71 seconds |
| Started | Jul 12 08:09:09 PM PDT 24 |
| Finished | Jul 12 08:14:10 PM PDT 24 |
| Peak memory | 610212 kb |
| Host | smart-11fe7993-70b7-4f01-8bb8-ddd72e616645 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1916749363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.1916749363 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2912904863 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 4843438584 ps |
| CPU time | 706.94 seconds |
| Started | Jul 12 08:08:35 PM PDT 24 |
| Finished | Jul 12 08:20:23 PM PDT 24 |
| Peak memory | 619592 kb |
| Host | smart-cb606288-766d-415a-b643-62aff9f3c0d2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2912904863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.2912904863 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.613528219 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 9492629674 ps |
| CPU time | 2112.93 seconds |
| Started | Jul 12 08:09:46 PM PDT 24 |
| Finished | Jul 12 08:45:01 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-b760898c-cc7c-4103-9280-7f6d54674785 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=613528219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.613528219 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1881331367 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 7943104982 ps |
| CPU time | 1624.92 seconds |
| Started | Jul 12 08:09:20 PM PDT 24 |
| Finished | Jul 12 08:36:26 PM PDT 24 |
| Peak memory | 610816 kb |
| Host | smart-39fcf65e-37a8-4331-b924-744454119c14 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881331367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.1881331367 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.854634217 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 3552633360 ps |
| CPU time | 340.52 seconds |
| Started | Jul 12 08:08:29 PM PDT 24 |
| Finished | Jul 12 08:14:11 PM PDT 24 |
| Peak memory | 648904 kb |
| Host | smart-1053d0d4-d7f5-465a-b14d-306d4e020c4c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854634217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _alert_handler_lpg_sleep_mode_alerts.854634217 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1692550534 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 11159047670 ps |
| CPU time | 1394.96 seconds |
| Started | Jul 12 08:09:01 PM PDT 24 |
| Finished | Jul 12 08:32:17 PM PDT 24 |
| Peak memory | 611300 kb |
| Host | smart-41875aea-5b73-4a70-a399-454a2d3ff7a5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692550534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.1692550534 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.626818428 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 8375258116 ps |
| CPU time | 1338.56 seconds |
| Started | Jul 12 08:08:46 PM PDT 24 |
| Finished | Jul 12 08:31:05 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-3d4e8e78-0e96-4b1c-b0d9-539ae5787269 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=626818428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.626818428 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1258188914 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 3160547210 ps |
| CPU time | 408.56 seconds |
| Started | Jul 12 08:07:49 PM PDT 24 |
| Finished | Jul 12 08:14:38 PM PDT 24 |
| Peak memory | 609664 kb |
| Host | smart-99bf6000-ec7b-45cb-abc7-3a7cfc6f154d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1258188914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.1258188914 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2479286310 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 254406240740 ps |
| CPU time | 11095.7 seconds |
| Started | Jul 12 08:09:06 PM PDT 24 |
| Finished | Jul 12 11:14:04 PM PDT 24 |
| Peak memory | 611172 kb |
| Host | smart-e344f554-dc93-4026-a387-657d790b8564 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2479286310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2479286310 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.3026793306 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 5135694920 ps |
| CPU time | 535.57 seconds |
| Started | Jul 12 08:03:08 PM PDT 24 |
| Finished | Jul 12 08:12:04 PM PDT 24 |
| Peak memory | 650300 kb |
| Host | smart-5216a224-1980-43a4-8539-43b5e0e93efa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3026793306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.3026793306 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.3298653866 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 3936234440 ps |
| CPU time | 540.9 seconds |
| Started | Jul 12 08:08:25 PM PDT 24 |
| Finished | Jul 12 08:17:28 PM PDT 24 |
| Peak memory | 609668 kb |
| Host | smart-f21342d8-7586-4884-a53e-18aa16cd02d3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298653866 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.3298653866 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3296702897 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 6425458666 ps |
| CPU time | 454.78 seconds |
| Started | Jul 12 08:08:35 PM PDT 24 |
| Finished | Jul 12 08:16:11 PM PDT 24 |
| Peak memory | 610944 kb |
| Host | smart-124f8042-7a39-4c7b-9af9-2c69049b8c15 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3296702897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3296702897 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1783036529 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 2816660294 ps |
| CPU time | 219.64 seconds |
| Started | Jul 12 08:13:13 PM PDT 24 |
| Finished | Jul 12 08:16:55 PM PDT 24 |
| Peak memory | 608944 kb |
| Host | smart-7419be7a-dd2d-4011-8711-5983cc334572 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783036529 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.1783036529 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2381469400 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 9191777388 ps |
| CPU time | 749.06 seconds |
| Started | Jul 12 08:07:41 PM PDT 24 |
| Finished | Jul 12 08:20:11 PM PDT 24 |
| Peak memory | 610940 kb |
| Host | smart-cecc9a50-9c01-45b9-b9cc-786738ba8f45 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2381469400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.2381469400 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1821000438 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 4301081168 ps |
| CPU time | 512.48 seconds |
| Started | Jul 12 08:07:11 PM PDT 24 |
| Finished | Jul 12 08:15:44 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-cb6f6c20-ede3-49ba-a747-ef332c4cb0fd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1821000438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.1821000438 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.1729544668 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 7535350764 ps |
| CPU time | 1013.73 seconds |
| Started | Jul 12 08:10:30 PM PDT 24 |
| Finished | Jul 12 08:27:25 PM PDT 24 |
| Peak memory | 617484 kb |
| Host | smart-504a3a62-e1fc-4012-a725-5786427a8c86 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729544668 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.1729544668 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.621353182 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 6343386721 ps |
| CPU time | 641.91 seconds |
| Started | Jul 12 08:15:16 PM PDT 24 |
| Finished | Jul 12 08:25:59 PM PDT 24 |
| Peak memory | 621840 kb |
| Host | smart-7c6d6694-a8a6-4081-bfbb-8b8096aa120a |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=621353182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.621353182 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3766753423 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 4033403272 ps |
| CPU time | 588.01 seconds |
| Started | Jul 12 08:10:12 PM PDT 24 |
| Finished | Jul 12 08:20:01 PM PDT 24 |
| Peak memory | 613268 kb |
| Host | smart-70da24bb-af64-4ee7-acb1-b50ecbe8b740 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766753423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3766753423 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2565108109 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 4221346594 ps |
| CPU time | 725.34 seconds |
| Started | Jul 12 08:09:58 PM PDT 24 |
| Finished | Jul 12 08:22:05 PM PDT 24 |
| Peak memory | 613076 kb |
| Host | smart-6324f48f-6781-45ae-9c84-876261291372 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565108109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2565108109 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.537296422 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 3652593120 ps |
| CPU time | 769.97 seconds |
| Started | Jul 12 08:10:37 PM PDT 24 |
| Finished | Jul 12 08:23:28 PM PDT 24 |
| Peak memory | 613308 kb |
| Host | smart-71b76555-41bf-4fd1-bf4e-b6f22c21d567 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537296422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.537296422 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2516432421 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 4903956852 ps |
| CPU time | 682.21 seconds |
| Started | Jul 12 08:10:47 PM PDT 24 |
| Finished | Jul 12 08:22:11 PM PDT 24 |
| Peak memory | 613012 kb |
| Host | smart-717db0fa-e734-4580-86e0-8cb9665660f4 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516432421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2516432421 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.701584682 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 4570642000 ps |
| CPU time | 752.15 seconds |
| Started | Jul 12 08:15:51 PM PDT 24 |
| Finished | Jul 12 08:28:25 PM PDT 24 |
| Peak memory | 613408 kb |
| Host | smart-bd6c0fa4-c54b-4c11-bac4-5c3691df680e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701584682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_slow_rma.701584682 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1565799655 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 4497676220 ps |
| CPU time | 769.48 seconds |
| Started | Jul 12 08:11:20 PM PDT 24 |
| Finished | Jul 12 08:24:10 PM PDT 24 |
| Peak memory | 613304 kb |
| Host | smart-e810b6ac-3d38-47bd-9b9d-b0d526886de8 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565799655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1565799655 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.1589491598 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 2590908395 ps |
| CPU time | 170.05 seconds |
| Started | Jul 12 08:10:19 PM PDT 24 |
| Finished | Jul 12 08:13:10 PM PDT 24 |
| Peak memory | 609632 kb |
| Host | smart-2072692f-5766-4f9a-b6c8-35c3cbc38a24 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589491598 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.1589491598 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2010305987 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 3429736504 ps |
| CPU time | 392.09 seconds |
| Started | Jul 12 08:12:34 PM PDT 24 |
| Finished | Jul 12 08:19:07 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-0da7174c-49b5-4a79-80ea-b49c764c133f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010305987 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.2010305987 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2485684156 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 2762753033 ps |
| CPU time | 173.01 seconds |
| Started | Jul 12 08:12:08 PM PDT 24 |
| Finished | Jul 12 08:15:02 PM PDT 24 |
| Peak memory | 609716 kb |
| Host | smart-48d7f60f-cf94-477c-b591-74f031c53359 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485684156 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.2485684156 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2562902181 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 5013734452 ps |
| CPU time | 548.51 seconds |
| Started | Jul 12 08:09:58 PM PDT 24 |
| Finished | Jul 12 08:19:08 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-de14fc9e-38b6-430b-8a97-6a529b987e99 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562902181 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.2562902181 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3209172823 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 3629331080 ps |
| CPU time | 368.51 seconds |
| Started | Jul 12 08:09:33 PM PDT 24 |
| Finished | Jul 12 08:15:43 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-14c30d03-9eac-4248-859e-90bd93199069 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209172823 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.3209172823 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2129373183 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 4276411960 ps |
| CPU time | 382.61 seconds |
| Started | Jul 12 08:10:09 PM PDT 24 |
| Finished | Jul 12 08:16:33 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-43fc3e1e-2882-4369-ab61-bc4148bfcec0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129373183 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.2129373183 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1453689966 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 5592420516 ps |
| CPU time | 488.97 seconds |
| Started | Jul 12 08:12:37 PM PDT 24 |
| Finished | Jul 12 08:20:47 PM PDT 24 |
| Peak memory | 610680 kb |
| Host | smart-18bd4bab-a091-4081-8cd0-e37475df85b3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453689966 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.1453689966 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1259800631 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 12388384952 ps |
| CPU time | 1465.67 seconds |
| Started | Jul 12 08:13:29 PM PDT 24 |
| Finished | Jul 12 08:37:56 PM PDT 24 |
| Peak memory | 611120 kb |
| Host | smart-dbf85d8d-1e9d-4024-a9cd-77c32be6aa8d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259800631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.1259800631 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1275852498 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 3624107642 ps |
| CPU time | 546.91 seconds |
| Started | Jul 12 08:10:44 PM PDT 24 |
| Finished | Jul 12 08:19:52 PM PDT 24 |
| Peak memory | 610272 kb |
| Host | smart-60dc71b0-dfcd-49c4-836d-85d7c89d05bb |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275852498 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.1275852498 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2631481029 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 4802592312 ps |
| CPU time | 760.52 seconds |
| Started | Jul 12 08:10:50 PM PDT 24 |
| Finished | Jul 12 08:23:32 PM PDT 24 |
| Peak memory | 610536 kb |
| Host | smart-e7338982-ff09-4ae7-9657-41945e4fc2a2 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631481029 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.2631481029 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1987066853 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 2465268450 ps |
| CPU time | 228.94 seconds |
| Started | Jul 12 08:11:40 PM PDT 24 |
| Finished | Jul 12 08:15:30 PM PDT 24 |
| Peak memory | 609668 kb |
| Host | smart-da7b4abf-838a-4752-9aa9-8b52bbf4c6a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987066853 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.1987066853 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3359044661 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 23520112520 ps |
| CPU time | 4463.59 seconds |
| Started | Jul 12 08:08:40 PM PDT 24 |
| Finished | Jul 12 09:23:05 PM PDT 24 |
| Peak memory | 610972 kb |
| Host | smart-2b3c874c-a8c4-4295-a8de-0df963cc1d2c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359044661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.3359044661 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.712300011 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 83563711214 ps |
| CPU time | 11808.4 seconds |
| Started | Jul 12 08:12:46 PM PDT 24 |
| Finished | Jul 12 11:29:38 PM PDT 24 |
| Peak memory | 610676 kb |
| Host | smart-1dad77e4-bdf9-42b8-a980-9a612844bb60 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=712300011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.712300011 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2138911739 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 4448496552 ps |
| CPU time | 617.97 seconds |
| Started | Jul 12 08:09:52 PM PDT 24 |
| Finished | Jul 12 08:20:11 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-058f302f-8c64-4c86-a1dc-b8e43b84b84c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21389 11739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.2138911739 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.652951875 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 2607907276 ps |
| CPU time | 206.86 seconds |
| Started | Jul 12 08:08:31 PM PDT 24 |
| Finished | Jul 12 08:11:59 PM PDT 24 |
| Peak memory | 609668 kb |
| Host | smart-a74e779c-aaf7-4e85-b59f-69ecfa857cde |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652951875 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.652951875 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.6572205 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 3409962712 ps |
| CPU time | 365.77 seconds |
| Started | Jul 12 08:12:39 PM PDT 24 |
| Finished | Jul 12 08:18:46 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-64592970-6e4d-49e0-9c4c-0c3398d36349 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6572205 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_smoketest.6572205 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.2582800401 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 5020155116 ps |
| CPU time | 869.42 seconds |
| Started | Jul 12 08:03:34 PM PDT 24 |
| Finished | Jul 12 08:18:04 PM PDT 24 |
| Peak memory | 611292 kb |
| Host | smart-a27bcfea-bfb0-48d1-b832-3332125f6e74 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2582800401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.2582800401 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.2403474943 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 3382003960 ps |
| CPU time | 668.23 seconds |
| Started | Jul 12 08:08:25 PM PDT 24 |
| Finished | Jul 12 08:19:35 PM PDT 24 |
| Peak memory | 610632 kb |
| Host | smart-acb49f14-2eb7-4dbf-b2d6-a99b19fe55b2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403474943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ boot_mode.2403474943 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3909186287 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 6925233526 ps |
| CPU time | 1083.64 seconds |
| Started | Jul 12 08:08:45 PM PDT 24 |
| Finished | Jul 12 08:26:49 PM PDT 24 |
| Peak memory | 611416 kb |
| Host | smart-448fa2f7-9bf3-4d3d-81bc-5cdbc0722227 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3909186287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.3909186287 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3825773380 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 7194196180 ps |
| CPU time | 1056.48 seconds |
| Started | Jul 12 08:09:36 PM PDT 24 |
| Finished | Jul 12 08:27:14 PM PDT 24 |
| Peak memory | 611420 kb |
| Host | smart-e0dd7214-7bf2-45dc-af85-5cc34a76a8a5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825773380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.3825773380 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.3500322416 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 3415227594 ps |
| CPU time | 768.65 seconds |
| Started | Jul 12 08:09:34 PM PDT 24 |
| Finished | Jul 12 08:22:24 PM PDT 24 |
| Peak memory | 617016 kb |
| Host | smart-e99d494b-7f77-4cfb-953c-d3dbebf43d2d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500322416 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_edn_kat.3500322416 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.4285585211 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 6690142824 ps |
| CPU time | 1315.85 seconds |
| Started | Jul 12 08:09:06 PM PDT 24 |
| Finished | Jul 12 08:31:03 PM PDT 24 |
| Peak memory | 609704 kb |
| Host | smart-a77bd1f2-de1f-47cb-afdf-6cb4bd646688 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285585211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.4285585211 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1749932261 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 2278066968 ps |
| CPU time | 279.48 seconds |
| Started | Jul 12 08:09:08 PM PDT 24 |
| Finished | Jul 12 08:13:48 PM PDT 24 |
| Peak memory | 609716 kb |
| Host | smart-5fd16f4e-ef46-434b-a13e-a56304b9b062 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17 49932261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.1749932261 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.996106603 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 7833956712 ps |
| CPU time | 1556.15 seconds |
| Started | Jul 12 08:08:32 PM PDT 24 |
| Finished | Jul 12 08:34:29 PM PDT 24 |
| Peak memory | 610928 kb |
| Host | smart-4b653beb-b10b-47c7-b8a1-bdbc38667ab9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=996106603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.996106603 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3353517172 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 2859731136 ps |
| CPU time | 239.95 seconds |
| Started | Jul 12 08:07:32 PM PDT 24 |
| Finished | Jul 12 08:11:33 PM PDT 24 |
| Peak memory | 609604 kb |
| Host | smart-676b6005-64ec-4ce7-9a92-170665f54dae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353517172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.3353517172 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.664263303 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 3249862950 ps |
| CPU time | 483.71 seconds |
| Started | Jul 12 08:12:48 PM PDT 24 |
| Finished | Jul 12 08:20:53 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-6c0d63b0-f2b7-4546-834a-8532b3ea91dd |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=664263303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.664263303 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.2327825118 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 3414463120 ps |
| CPU time | 316.68 seconds |
| Started | Jul 12 08:03:41 PM PDT 24 |
| Finished | Jul 12 08:08:59 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-4a960023-d9ca-46aa-bb2e-18c7716dabc9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327825118 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.2327825118 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.4206079463 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 2152768384 ps |
| CPU time | 196.55 seconds |
| Started | Jul 12 08:03:30 PM PDT 24 |
| Finished | Jul 12 08:06:47 PM PDT 24 |
| Peak memory | 610244 kb |
| Host | smart-23a9cff4-61e4-4797-9463-9fe85f392fa2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206079463 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.4206079463 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.1872622743 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 2549174040 ps |
| CPU time | 184.79 seconds |
| Started | Jul 12 08:03:24 PM PDT 24 |
| Finished | Jul 12 08:06:29 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-1d442442-23a3-46c8-8eae-6262ca877f39 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872622743 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.1872622743 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.1168512924 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 2696319078 ps |
| CPU time | 133.94 seconds |
| Started | Jul 12 08:03:40 PM PDT 24 |
| Finished | Jul 12 08:05:54 PM PDT 24 |
| Peak memory | 609884 kb |
| Host | smart-82d0b91e-6bd0-421f-90f0-489fbfd4ff44 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168512924 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.1168512924 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.4157788665 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 59989068344 ps |
| CPU time | 10561.5 seconds |
| Started | Jul 12 08:04:45 PM PDT 24 |
| Finished | Jul 12 11:00:49 PM PDT 24 |
| Peak memory | 624228 kb |
| Host | smart-09f9453f-0435-4218-999e-548d8c514092 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=4157788665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.4157788665 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.1518042759 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 5617851536 ps |
| CPU time | 850.42 seconds |
| Started | Jul 12 08:11:54 PM PDT 24 |
| Finished | Jul 12 08:26:06 PM PDT 24 |
| Peak memory | 611236 kb |
| Host | smart-97ce114c-73e3-4006-aeb5-37eda8ac5ef2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1518042759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.1518042759 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.1779569699 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 5559494958 ps |
| CPU time | 1072.75 seconds |
| Started | Jul 12 08:09:37 PM PDT 24 |
| Finished | Jul 12 08:27:31 PM PDT 24 |
| Peak memory | 610464 kb |
| Host | smart-257d06e0-37d3-4f6e-8692-6c3a87437d75 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779569699 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.1779569699 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1540065816 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 6663685266 ps |
| CPU time | 1208.92 seconds |
| Started | Jul 12 08:06:01 PM PDT 24 |
| Finished | Jul 12 08:26:11 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-89b4389c-8fa7-4fd5-abea-1422352d2778 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540065816 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.1540065816 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.607007615 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 7418147809 ps |
| CPU time | 1221.07 seconds |
| Started | Jul 12 08:12:06 PM PDT 24 |
| Finished | Jul 12 08:32:28 PM PDT 24 |
| Peak memory | 609676 kb |
| Host | smart-a5112567-3e21-410f-be9e-9b39fe63b4f9 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607007615 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.607007615 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.751017561 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 6277465644 ps |
| CPU time | 1286.99 seconds |
| Started | Jul 12 08:06:09 PM PDT 24 |
| Finished | Jul 12 08:27:37 PM PDT 24 |
| Peak memory | 609252 kb |
| Host | smart-51f0577d-aefd-425d-b72b-d033031a0a99 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751017561 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.751017561 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.4238730263 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 3764411802 ps |
| CPU time | 424.61 seconds |
| Started | Jul 12 08:05:40 PM PDT 24 |
| Finished | Jul 12 08:12:46 PM PDT 24 |
| Peak memory | 610188 kb |
| Host | smart-e62edd6e-04b8-437c-b04f-ba2978a0fc40 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238730263 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.4238730263 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1637005689 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 5162563182 ps |
| CPU time | 522.47 seconds |
| Started | Jul 12 08:04:46 PM PDT 24 |
| Finished | Jul 12 08:13:30 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-01c8e47f-9881-458f-a9a0-26b176d7459b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16 37005689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.1637005689 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2164811658 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 5324925830 ps |
| CPU time | 1234.2 seconds |
| Started | Jul 12 08:11:20 PM PDT 24 |
| Finished | Jul 12 08:31:55 PM PDT 24 |
| Peak memory | 609636 kb |
| Host | smart-3bdf2fd5-2821-4646-bba8-97d24bc32e67 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164811658 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.2164811658 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.32246244 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 4069872400 ps |
| CPU time | 527.07 seconds |
| Started | Jul 12 08:06:18 PM PDT 24 |
| Finished | Jul 12 08:15:05 PM PDT 24 |
| Peak memory | 610304 kb |
| Host | smart-4eb00c49-bb05-4f82-a31c-77a6e06bacf1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32246244 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.32246244 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.4019325548 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 4278858951 ps |
| CPU time | 635.76 seconds |
| Started | Jul 12 08:09:35 PM PDT 24 |
| Finished | Jul 12 08:20:12 PM PDT 24 |
| Peak memory | 610568 kb |
| Host | smart-509c75ea-bf52-4955-b7f0-794593affe0c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=4019325548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.4019325548 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1341875066 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 5129268333 ps |
| CPU time | 737.34 seconds |
| Started | Jul 12 08:11:22 PM PDT 24 |
| Finished | Jul 12 08:23:41 PM PDT 24 |
| Peak memory | 609624 kb |
| Host | smart-51c4471d-9810-48ca-9ca0-a57cf2e94cc8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1341875066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1341875066 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.376615183 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 2732123652 ps |
| CPU time | 276.77 seconds |
| Started | Jul 12 08:10:41 PM PDT 24 |
| Finished | Jul 12 08:15:20 PM PDT 24 |
| Peak memory | 610044 kb |
| Host | smart-b554c6b1-083c-4aef-8326-ffe2774c0729 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766151 83 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.376615183 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.1506602338 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 25309199129 ps |
| CPU time | 2279.07 seconds |
| Started | Jul 12 08:03:46 PM PDT 24 |
| Finished | Jul 12 08:41:47 PM PDT 24 |
| Peak memory | 615408 kb |
| Host | smart-0e0d9e46-e4c8-4509-9db2-1f67df14dcf8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506602338 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.1506602338 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1178117314 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 21561485783 ps |
| CPU time | 1910.66 seconds |
| Started | Jul 12 08:11:42 PM PDT 24 |
| Finished | Jul 12 08:43:33 PM PDT 24 |
| Peak memory | 617452 kb |
| Host | smart-b91f6b63-9d70-484c-81ad-bb61f6e0ae21 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1178117314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.1178117314 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.245129758 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 2758787528 ps |
| CPU time | 180.85 seconds |
| Started | Jul 12 08:16:51 PM PDT 24 |
| Finished | Jul 12 08:19:53 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-6cfc64de-e335-4d58-bffb-6dbcf95c6049 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=245129758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.245129758 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.3316947021 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 3233894308 ps |
| CPU time | 366.63 seconds |
| Started | Jul 12 08:12:32 PM PDT 24 |
| Finished | Jul 12 08:18:40 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-95f8edec-f9f1-4131-bcce-6f289b06df71 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316947021 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.3316947021 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.3255389483 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 3062982660 ps |
| CPU time | 317.25 seconds |
| Started | Jul 12 08:10:12 PM PDT 24 |
| Finished | Jul 12 08:15:30 PM PDT 24 |
| Peak memory | 609652 kb |
| Host | smart-1a28ac3c-b9d4-4590-8459-cff7ee173f62 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255389483 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.3255389483 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.48480772 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 2425849584 ps |
| CPU time | 263.1 seconds |
| Started | Jul 12 08:08:50 PM PDT 24 |
| Finished | Jul 12 08:13:14 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-ef486539-df43-4ede-adaa-dc08cae4be5c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48480772 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_hmac_enc_idle.48480772 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3703207641 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 2832092843 ps |
| CPU time | 372.75 seconds |
| Started | Jul 12 08:09:34 PM PDT 24 |
| Finished | Jul 12 08:15:48 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-1a007597-090a-461a-b355-09447b910986 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703207641 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.3703207641 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1404030141 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 3185972237 ps |
| CPU time | 246.42 seconds |
| Started | Jul 12 08:12:07 PM PDT 24 |
| Finished | Jul 12 08:16:14 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-bb33709d-f9a6-473b-aa19-7a25334891ef |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404030141 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.1404030141 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.2156362800 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 8465585432 ps |
| CPU time | 1967.05 seconds |
| Started | Jul 12 08:09:44 PM PDT 24 |
| Finished | Jul 12 08:42:32 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-c28b493b-6709-4baf-8b97-a9a23d224c6f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156362800 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_multistream.2156362800 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.731212507 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 2656362804 ps |
| CPU time | 295.43 seconds |
| Started | Jul 12 08:09:33 PM PDT 24 |
| Finished | Jul 12 08:14:29 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-74212dcf-4cd9-4f9c-a2bf-dcfa08c0cd2c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731212507 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.731212507 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.1087592729 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 3203505600 ps |
| CPU time | 361.39 seconds |
| Started | Jul 12 08:13:09 PM PDT 24 |
| Finished | Jul 12 08:19:11 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-932187e9-d2f7-454e-9baa-7eb116de7164 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087592729 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.1087592729 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1507958218 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3651213268 ps |
| CPU time | 496.92 seconds |
| Started | Jul 12 08:04:42 PM PDT 24 |
| Finished | Jul 12 08:13:00 PM PDT 24 |
| Peak memory | 611156 kb |
| Host | smart-ac09052e-e063-4f45-a0ab-6fb5431b76c0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507958218 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.1507958218 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3879329788 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 5518933404 ps |
| CPU time | 1047.9 seconds |
| Started | Jul 12 08:04:12 PM PDT 24 |
| Finished | Jul 12 08:21:41 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-cc13e597-b07b-4a46-a698-da35d2443b19 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879329788 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.3879329788 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3066631098 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 5704163944 ps |
| CPU time | 1088.12 seconds |
| Started | Jul 12 08:04:28 PM PDT 24 |
| Finished | Jul 12 08:22:37 PM PDT 24 |
| Peak memory | 609652 kb |
| Host | smart-3957dabd-0d2e-4b1b-a654-cf50aa8d3ac3 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066631098 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.3066631098 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.4095569414 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 5608397096 ps |
| CPU time | 921.68 seconds |
| Started | Jul 12 08:05:23 PM PDT 24 |
| Finished | Jul 12 08:20:46 PM PDT 24 |
| Peak memory | 609868 kb |
| Host | smart-31be3d37-5d4b-43df-a7f7-f054582d7fc4 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095569414 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.4095569414 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.3190611459 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 63300837458 ps |
| CPU time | 10997.2 seconds |
| Started | Jul 12 08:03:55 PM PDT 24 |
| Finished | Jul 12 11:07:15 PM PDT 24 |
| Peak memory | 625120 kb |
| Host | smart-159cf06e-a0a2-45cd-b850-23d97f65f737 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3190611459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.3190611459 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.172192270 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 8065995206 ps |
| CPU time | 1531.28 seconds |
| Started | Jul 12 08:09:51 PM PDT 24 |
| Finished | Jul 12 08:35:24 PM PDT 24 |
| Peak memory | 617112 kb |
| Host | smart-ba3acb1c-c0f8-4849-9990-c11bd63d000d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721 92270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.172192270 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2215763780 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 8889153738 ps |
| CPU time | 1465.73 seconds |
| Started | Jul 12 08:08:29 PM PDT 24 |
| Finished | Jul 12 08:32:56 PM PDT 24 |
| Peak memory | 618160 kb |
| Host | smart-61f74fe9-4452-4539-9b13-640540ccac86 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2215763780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.2215763780 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2333960553 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 7901285962 ps |
| CPU time | 1123.63 seconds |
| Started | Jul 12 08:13:35 PM PDT 24 |
| Finished | Jul 12 08:32:20 PM PDT 24 |
| Peak memory | 617232 kb |
| Host | smart-2ad699e6-5d59-4e65-893d-835da408bfe5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2333960553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2333960553 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2450797767 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 7143485944 ps |
| CPU time | 1363 seconds |
| Started | Jul 12 08:09:01 PM PDT 24 |
| Finished | Jul 12 08:31:45 PM PDT 24 |
| Peak memory | 611680 kb |
| Host | smart-da2ce2ef-8820-4157-b388-6979035d70d7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245079 7767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.2450797767 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1102673430 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 14286354226 ps |
| CPU time | 4252.79 seconds |
| Started | Jul 12 08:09:08 PM PDT 24 |
| Finished | Jul 12 09:20:02 PM PDT 24 |
| Peak memory | 610352 kb |
| Host | smart-5a1fe68e-e6d6-49fb-b8a8-765ed6ab59dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11026 73430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.1102673430 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.1608942359 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 2530798648 ps |
| CPU time | 216.99 seconds |
| Started | Jul 12 08:09:05 PM PDT 24 |
| Finished | Jul 12 08:12:43 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-858816a8-8843-4fb5-ac77-ce010f8e1212 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608942359 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.1608942359 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.2758074928 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 3121544010 ps |
| CPU time | 250.2 seconds |
| Started | Jul 12 08:04:32 PM PDT 24 |
| Finished | Jul 12 08:08:43 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-27cbb668-330a-40ad-b354-130bb75a4679 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758074928 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.2758074928 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.1377158996 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 3072960752 ps |
| CPU time | 350.48 seconds |
| Started | Jul 12 08:09:17 PM PDT 24 |
| Finished | Jul 12 08:15:09 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-04f376aa-649d-4471-8205-fc2e87bbd57e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377158996 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.1377158996 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3335143982 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 2713696380 ps |
| CPU time | 210.96 seconds |
| Started | Jul 12 08:09:58 PM PDT 24 |
| Finished | Jul 12 08:13:30 PM PDT 24 |
| Peak memory | 609028 kb |
| Host | smart-37078513-86de-4892-a502-d9ff10cd53bc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335143982 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.3335143982 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3935870313 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 2726830312 ps |
| CPU time | 257.21 seconds |
| Started | Jul 12 08:08:53 PM PDT 24 |
| Finished | Jul 12 08:13:11 PM PDT 24 |
| Peak memory | 610252 kb |
| Host | smart-cda8d395-1246-4c2f-bce6-075e7019f0a7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935870313 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.3935870313 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3506111897 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 3387382259 ps |
| CPU time | 318.65 seconds |
| Started | Jul 12 08:09:24 PM PDT 24 |
| Finished | Jul 12 08:14:43 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-023d7d09-7c68-4779-ad15-c0254a44c15a |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506111897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.3506111897 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3082325757 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 3549593449 ps |
| CPU time | 229.66 seconds |
| Started | Jul 12 08:12:19 PM PDT 24 |
| Finished | Jul 12 08:16:09 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-5b580353-724b-4e46-aa1d-8f99eefcbd1b |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30823257 57 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3082325757 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.3155517240 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 2910716736 ps |
| CPU time | 305.11 seconds |
| Started | Jul 12 08:14:45 PM PDT 24 |
| Finished | Jul 12 08:19:51 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-3e946d06-ca9c-4f4f-a0ed-cecfd8506571 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155517240 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.3155517240 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.420344763 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 3137887320 ps |
| CPU time | 319.13 seconds |
| Started | Jul 12 08:05:41 PM PDT 24 |
| Finished | Jul 12 08:11:02 PM PDT 24 |
| Peak memory | 610228 kb |
| Host | smart-c3734e4b-c772-4811-9080-dda3bf57fe36 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420344763 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.420344763 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.4284316388 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 5111226798 ps |
| CPU time | 607.91 seconds |
| Started | Jul 12 08:11:58 PM PDT 24 |
| Finished | Jul 12 08:22:06 PM PDT 24 |
| Peak memory | 611000 kb |
| Host | smart-17675236-efb4-49d4-86fa-42500c6f3c70 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4284316388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.4284316388 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3582294625 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 3986079159 ps |
| CPU time | 179.05 seconds |
| Started | Jul 12 08:07:08 PM PDT 24 |
| Finished | Jul 12 08:10:08 PM PDT 24 |
| Peak memory | 620576 kb |
| Host | smart-5b7e0929-40da-41f3-8ea8-fed6d2c7bf42 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35822946 25 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.3582294625 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3036285931 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 5564461699 ps |
| CPU time | 493.86 seconds |
| Started | Jul 12 08:06:05 PM PDT 24 |
| Finished | Jul 12 08:14:19 PM PDT 24 |
| Peak memory | 620484 kb |
| Host | smart-b38afddb-0e3f-4258-ae15-b585fe26e756 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036285931 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.3036285931 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2128577557 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 2536462128 ps |
| CPU time | 118.26 seconds |
| Started | Jul 12 08:07:11 PM PDT 24 |
| Finished | Jul 12 08:09:10 PM PDT 24 |
| Peak memory | 615496 kb |
| Host | smart-7c3b39c6-1e3b-4998-9e0b-586e2b3f450c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2128577557 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.2128577557 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.668526500 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 2520639189 ps |
| CPU time | 119.1 seconds |
| Started | Jul 12 08:06:33 PM PDT 24 |
| Finished | Jul 12 08:08:34 PM PDT 24 |
| Peak memory | 618296 kb |
| Host | smart-f9d15423-9d87-4d15-95b0-c429a73e2ba4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668526500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.668526500 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1587282705 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 49711859403 ps |
| CPU time | 4831.38 seconds |
| Started | Jul 12 08:07:16 PM PDT 24 |
| Finished | Jul 12 09:27:49 PM PDT 24 |
| Peak memory | 619988 kb |
| Host | smart-61905c55-eb7f-4fe2-85fc-911b8566291a |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587282705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_dev.1587282705 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.3530288766 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 8788256898 ps |
| CPU time | 854.85 seconds |
| Started | Jul 12 08:06:53 PM PDT 24 |
| Finished | Jul 12 08:21:09 PM PDT 24 |
| Peak memory | 619460 kb |
| Host | smart-28df7b59-d53d-48a8-88db-d2fd447eb1d1 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530288766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.3530288766 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3278761730 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 49068141850 ps |
| CPU time | 5513.96 seconds |
| Started | Jul 12 08:08:05 PM PDT 24 |
| Finished | Jul 12 09:40:01 PM PDT 24 |
| Peak memory | 620640 kb |
| Host | smart-41bd1d53-18e6-4d04-8300-1b70ec64fd6c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278761730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.3278761730 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1234040954 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 35431146240 ps |
| CPU time | 2761.14 seconds |
| Started | Jul 12 08:05:37 PM PDT 24 |
| Finished | Jul 12 08:51:40 PM PDT 24 |
| Peak memory | 620868 kb |
| Host | smart-99bfebe7-2154-4ee3-adf5-a14300f64083 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1234040954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.1234040954 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.203748907 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 17370479392 ps |
| CPU time | 3578.84 seconds |
| Started | Jul 12 08:09:57 PM PDT 24 |
| Finished | Jul 12 09:09:37 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-a2b159a9-e2f5-43be-b254-262af3071052 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=203748907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.203748907 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3925098574 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 19153040802 ps |
| CPU time | 3778.66 seconds |
| Started | Jul 12 08:06:47 PM PDT 24 |
| Finished | Jul 12 09:09:47 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-dc8e7a1a-0b5f-4a34-b411-9233a0f9b7c7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3925098574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3925098574 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2965727549 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 24789250247 ps |
| CPU time | 3764.45 seconds |
| Started | Jul 12 08:12:20 PM PDT 24 |
| Finished | Jul 12 09:15:06 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-a33bb835-597e-4388-8df6-4ee7ebc7f7a8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965727549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.2965727549 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1245365262 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 3736201352 ps |
| CPU time | 542.62 seconds |
| Started | Jul 12 08:08:25 PM PDT 24 |
| Finished | Jul 12 08:17:30 PM PDT 24 |
| Peak memory | 610228 kb |
| Host | smart-0575680c-d362-47d9-9373-e2cef1ea2f3d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245365262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.1245365262 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.3820612121 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 5814015784 ps |
| CPU time | 1137.49 seconds |
| Started | Jul 12 08:06:40 PM PDT 24 |
| Finished | Jul 12 08:25:38 PM PDT 24 |
| Peak memory | 610892 kb |
| Host | smart-015ab22e-1e75-442b-9e30-cf2e85d25a89 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3820612121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.3820612121 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.125064120 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 3364014111 ps |
| CPU time | 316.9 seconds |
| Started | Jul 12 08:05:30 PM PDT 24 |
| Finished | Jul 12 08:10:48 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-00ed39a7-1085-4cd1-8e94-aad08a21b147 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125064120 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.125064120 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2307258800 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 9588518264 ps |
| CPU time | 1535 seconds |
| Started | Jul 12 08:05:27 PM PDT 24 |
| Finished | Jul 12 08:31:03 PM PDT 24 |
| Peak memory | 610904 kb |
| Host | smart-350f4398-46ff-4d74-a6a7-87bb3591d964 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2307258800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.2307258800 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.950482083 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 9119015712 ps |
| CPU time | 1335.16 seconds |
| Started | Jul 12 08:05:28 PM PDT 24 |
| Finished | Jul 12 08:27:44 PM PDT 24 |
| Peak memory | 610852 kb |
| Host | smart-3b857f31-acd8-48d4-b080-5accad4dca79 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=950482083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.950482083 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2409659359 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 7180338230 ps |
| CPU time | 1475.25 seconds |
| Started | Jul 12 08:07:45 PM PDT 24 |
| Finished | Jul 12 08:32:22 PM PDT 24 |
| Peak memory | 610952 kb |
| Host | smart-5ff0d3b2-4ede-4342-8caa-090e73867633 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2409659359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.2409659359 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1968709641 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 4421723696 ps |
| CPU time | 632.18 seconds |
| Started | Jul 12 08:04:54 PM PDT 24 |
| Finished | Jul 12 08:15:27 PM PDT 24 |
| Peak memory | 610428 kb |
| Host | smart-bf834072-ffc8-4c34-836b-f20e25a9e9ed |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1968709641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1968709641 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.4172439676 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 2969003606 ps |
| CPU time | 290.68 seconds |
| Started | Jul 12 08:13:51 PM PDT 24 |
| Finished | Jul 12 08:18:43 PM PDT 24 |
| Peak memory | 610224 kb |
| Host | smart-3720eaa5-e8e1-4873-9431-78642974145d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172439676 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.4172439676 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.2329832404 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 2820743296 ps |
| CPU time | 325.04 seconds |
| Started | Jul 12 08:15:07 PM PDT 24 |
| Finished | Jul 12 08:20:33 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-8e18875d-8a23-453d-9700-a4bc90fef18b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329832404 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.2329832404 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.479881665 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 4853685500 ps |
| CPU time | 618.44 seconds |
| Started | Jul 12 08:13:17 PM PDT 24 |
| Finished | Jul 12 08:23:37 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-c92d6f18-6ec3-463a-988d-37600bf4fe7b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479881665 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.479881665 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.3568679040 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 10817135600 ps |
| CPU time | 612.3 seconds |
| Started | Jul 12 08:11:54 PM PDT 24 |
| Finished | Jul 12 08:22:08 PM PDT 24 |
| Peak memory | 611228 kb |
| Host | smart-c5203c27-b2ac-44d5-a989-d4b71a836fb1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568679040 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.3568679040 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3421998447 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 9984512066 ps |
| CPU time | 1813.82 seconds |
| Started | Jul 12 08:06:12 PM PDT 24 |
| Finished | Jul 12 08:36:27 PM PDT 24 |
| Peak memory | 611364 kb |
| Host | smart-31336829-0de8-4383-b38d-a4d1c4395d20 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421 998447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.3421998447 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1251326409 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 28578232260 ps |
| CPU time | 1981.84 seconds |
| Started | Jul 12 08:12:51 PM PDT 24 |
| Finished | Jul 12 08:45:56 PM PDT 24 |
| Peak memory | 611104 kb |
| Host | smart-e91f0749-0b41-48db-a222-1cc864c31914 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125 1326409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.1251326409 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1952809966 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 13222266781 ps |
| CPU time | 1519.14 seconds |
| Started | Jul 12 08:07:21 PM PDT 24 |
| Finished | Jul 12 08:32:41 PM PDT 24 |
| Peak memory | 611420 kb |
| Host | smart-10e0327f-59d2-4152-8237-c5d605da2e82 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1952809966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1952809966 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3946452244 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 24749522440 ps |
| CPU time | 1603.66 seconds |
| Started | Jul 12 08:11:50 PM PDT 24 |
| Finished | Jul 12 08:38:34 PM PDT 24 |
| Peak memory | 611148 kb |
| Host | smart-f8236827-9c4b-4dd8-abc2-516256fa522f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3946452244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3946452244 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3285982097 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 7689251412 ps |
| CPU time | 627.43 seconds |
| Started | Jul 12 08:08:00 PM PDT 24 |
| Finished | Jul 12 08:18:29 PM PDT 24 |
| Peak memory | 609844 kb |
| Host | smart-6fa073c2-a32d-4a46-a988-fe8bce8bdca4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285982097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.3285982097 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3739593036 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 5819344590 ps |
| CPU time | 427.96 seconds |
| Started | Jul 12 08:07:18 PM PDT 24 |
| Finished | Jul 12 08:14:27 PM PDT 24 |
| Peak memory | 616268 kb |
| Host | smart-7c5bb87d-b462-40aa-83ac-069f2860d99e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3739593036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3739593036 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3426362565 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 6285055395 ps |
| CPU time | 614.47 seconds |
| Started | Jul 12 08:07:18 PM PDT 24 |
| Finished | Jul 12 08:17:34 PM PDT 24 |
| Peak memory | 611012 kb |
| Host | smart-dc2cd037-9b30-4053-a5c4-f09cb6fb278f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426362565 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.3426362565 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1352667884 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 3120121716 ps |
| CPU time | 506.63 seconds |
| Started | Jul 12 08:11:06 PM PDT 24 |
| Finished | Jul 12 08:19:34 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-a2e17fa3-601c-4474-995c-1923b931491f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352667884 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.1352667884 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1639680282 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 3446401520 ps |
| CPU time | 353.48 seconds |
| Started | Jul 12 08:05:47 PM PDT 24 |
| Finished | Jul 12 08:11:41 PM PDT 24 |
| Peak memory | 616172 kb |
| Host | smart-9127e84b-2227-4876-a0a0-e7ab57c69fdc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1639680282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.1639680282 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1423941023 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 11381440598 ps |
| CPU time | 1532.24 seconds |
| Started | Jul 12 08:07:55 PM PDT 24 |
| Finished | Jul 12 08:33:28 PM PDT 24 |
| Peak memory | 611392 kb |
| Host | smart-909dd676-4b57-49ac-9a00-d14189892afb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423941023 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1423941023 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2480495018 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 6943492902 ps |
| CPU time | 499.96 seconds |
| Started | Jul 12 08:10:18 PM PDT 24 |
| Finished | Jul 12 08:18:38 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-66c0e7fa-7442-4178-8d98-9bbc9ab27bfe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480495018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2480495018 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2848737015 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 5642129137 ps |
| CPU time | 565.71 seconds |
| Started | Jul 12 08:06:41 PM PDT 24 |
| Finished | Jul 12 08:16:08 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-7bb71f0c-9f93-4552-a26e-89d3254e344f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848737015 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.2848737015 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3860687544 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 19855001614 ps |
| CPU time | 2313.75 seconds |
| Started | Jul 12 08:07:17 PM PDT 24 |
| Finished | Jul 12 08:45:52 PM PDT 24 |
| Peak memory | 611624 kb |
| Host | smart-0b7a7c07-fab9-4dcf-b23a-33eddb21fdcd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3860687544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3860687544 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.682831356 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 20356161712 ps |
| CPU time | 980.07 seconds |
| Started | Jul 12 08:12:18 PM PDT 24 |
| Finished | Jul 12 08:28:39 PM PDT 24 |
| Peak memory | 611184 kb |
| Host | smart-8d2ea219-0de2-4375-87cf-8f23a610ae8c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=682831356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.682831356 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.69996147 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 41744328608 ps |
| CPU time | 2745.21 seconds |
| Started | Jul 12 08:06:28 PM PDT 24 |
| Finished | Jul 12 08:52:14 PM PDT 24 |
| Peak memory | 612144 kb |
| Host | smart-39a02fed-1e03-4f10-9164-d69870173284 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69996147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitch _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sle ep_power_glitch_reset.69996147 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1252708556 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 6734264172 ps |
| CPU time | 666.41 seconds |
| Started | Jul 12 08:10:42 PM PDT 24 |
| Finished | Jul 12 08:21:50 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-3cf76bf1-5962-4186-921b-199886f950de |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1252708556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.1252708556 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3519586595 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 3441311398 ps |
| CPU time | 281.56 seconds |
| Started | Jul 12 08:06:48 PM PDT 24 |
| Finished | Jul 12 08:11:31 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-2f9db8e2-4b01-4ebf-81cb-b08d797a5ccb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519586595 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.3519586595 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1512123968 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 6523689184 ps |
| CPU time | 625.32 seconds |
| Started | Jul 12 08:07:15 PM PDT 24 |
| Finished | Jul 12 08:17:42 PM PDT 24 |
| Peak memory | 617940 kb |
| Host | smart-1c400766-e18f-48eb-9eac-fe1c1f5d2f8f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1512123968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.1512123968 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.427334183 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 5877622504 ps |
| CPU time | 540.53 seconds |
| Started | Jul 12 08:12:42 PM PDT 24 |
| Finished | Jul 12 08:21:43 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-2690c56a-97c9-44f3-a578-0fa0475b1520 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42733418 3 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.427334183 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.4031796223 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 6321574420 ps |
| CPU time | 595.97 seconds |
| Started | Jul 12 08:13:42 PM PDT 24 |
| Finished | Jul 12 08:23:40 PM PDT 24 |
| Peak memory | 611164 kb |
| Host | smart-ce3d14a8-845f-42bb-b6f0-725eebee4329 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4031796223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.4031796223 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2129484762 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 6558293020 ps |
| CPU time | 592.8 seconds |
| Started | Jul 12 08:15:25 PM PDT 24 |
| Finished | Jul 12 08:25:19 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-8a7b66c7-1ccb-4214-b7f1-c10afa7dadf3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129484762 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.2129484762 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3190337451 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 8445847332 ps |
| CPU time | 1199.31 seconds |
| Started | Jul 12 08:06:48 PM PDT 24 |
| Finished | Jul 12 08:26:49 PM PDT 24 |
| Peak memory | 610940 kb |
| Host | smart-3af56254-986d-4f02-95db-aea066e53867 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190337451 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.3190337451 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1062618787 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 4055430600 ps |
| CPU time | 460.17 seconds |
| Started | Jul 12 08:06:39 PM PDT 24 |
| Finished | Jul 12 08:14:20 PM PDT 24 |
| Peak memory | 610424 kb |
| Host | smart-86acbd62-df14-4678-a2a0-d4873079bbc9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062618787 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1062618787 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3428959645 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 5895805296 ps |
| CPU time | 370.05 seconds |
| Started | Jul 12 08:12:55 PM PDT 24 |
| Finished | Jul 12 08:19:07 PM PDT 24 |
| Peak memory | 610660 kb |
| Host | smart-54f38290-d7bc-4809-9ee7-84523fb1e79d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428959645 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.3428959645 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1930102229 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 4369536244 ps |
| CPU time | 591.27 seconds |
| Started | Jul 12 08:06:57 PM PDT 24 |
| Finished | Jul 12 08:16:50 PM PDT 24 |
| Peak memory | 610984 kb |
| Host | smart-970d891c-3641-4327-9144-51350b4164f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193 0102229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.1930102229 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3628274687 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 9165283063 ps |
| CPU time | 509.48 seconds |
| Started | Jul 12 08:09:37 PM PDT 24 |
| Finished | Jul 12 08:18:08 PM PDT 24 |
| Peak memory | 625012 kb |
| Host | smart-f32ef75c-a542-4e2e-bb3b-8874d6732e4a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628274687 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.3628274687 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2722904861 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 11631567288 ps |
| CPU time | 1889.15 seconds |
| Started | Jul 12 08:05:55 PM PDT 24 |
| Finished | Jul 12 08:37:26 PM PDT 24 |
| Peak memory | 611412 kb |
| Host | smart-5ddd9118-bc7c-42b1-a12b-6a459e9b34c6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2722904861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.2722904861 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.833038031 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 5390578400 ps |
| CPU time | 717.28 seconds |
| Started | Jul 12 08:07:50 PM PDT 24 |
| Finished | Jul 12 08:19:48 PM PDT 24 |
| Peak memory | 610772 kb |
| Host | smart-d2c45495-3e7e-41ef-a5e5-c0b0ed4ed4dc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833038031 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_rstmgr_cpu_info.833038031 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1846862188 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 4463674528 ps |
| CPU time | 603.28 seconds |
| Started | Jul 12 08:03:28 PM PDT 24 |
| Finished | Jul 12 08:13:32 PM PDT 24 |
| Peak memory | 641720 kb |
| Host | smart-a92ba439-6cdb-4e0c-be38-df92ded76c75 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1846862188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.1846862188 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.4152350654 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 2980766520 ps |
| CPU time | 242.29 seconds |
| Started | Jul 12 08:16:13 PM PDT 24 |
| Finished | Jul 12 08:20:17 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-58af8f17-7747-441b-836c-55dc0b32dc06 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152350654 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.4152350654 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.175843307 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 3482354502 ps |
| CPU time | 372.27 seconds |
| Started | Jul 12 08:05:34 PM PDT 24 |
| Finished | Jul 12 08:11:47 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-33fe2a6f-d307-4a7d-a985-32c4c024ce7f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175843307 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rstmgr_sw_req.175843307 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2543231239 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 2910123768 ps |
| CPU time | 217.05 seconds |
| Started | Jul 12 08:07:12 PM PDT 24 |
| Finished | Jul 12 08:10:50 PM PDT 24 |
| Peak memory | 610240 kb |
| Host | smart-237a9a8c-d5f2-4e6e-8579-a7b2ffab418d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543231239 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.2543231239 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2996560126 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2531626090 ps |
| CPU time | 258.2 seconds |
| Started | Jul 12 08:12:14 PM PDT 24 |
| Finished | Jul 12 08:16:33 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-b0a307dd-0585-400f-9c81-6d8a3664e0df |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2996560126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.2996560126 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2842385948 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 3165988093 ps |
| CPU time | 270.37 seconds |
| Started | Jul 12 08:12:04 PM PDT 24 |
| Finished | Jul 12 08:16:36 PM PDT 24 |
| Peak memory | 610556 kb |
| Host | smart-84403532-6e67-4829-9dfa-2afc56e35c51 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842385948 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.2842385948 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3056452111 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 5191762942 ps |
| CPU time | 878.54 seconds |
| Started | Jul 12 08:10:09 PM PDT 24 |
| Finished | Jul 12 08:24:49 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-dfa5f131-ae9e-42b0-8887-6fe454c5ea3f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30564 52111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.3056452111 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.445566092 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 5714375056 ps |
| CPU time | 1139.64 seconds |
| Started | Jul 12 08:08:42 PM PDT 24 |
| Finished | Jul 12 08:27:43 PM PDT 24 |
| Peak memory | 609696 kb |
| Host | smart-5c20fabd-b31e-49af-923a-6dde7c3c2e6a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=445566092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.445566092 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.847924968 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 4071985116 ps |
| CPU time | 585.91 seconds |
| Started | Jul 12 08:17:13 PM PDT 24 |
| Finished | Jul 12 08:27:01 PM PDT 24 |
| Peak memory | 624688 kb |
| Host | smart-4d75ee82-92fa-4de9-95bc-f1b636ffb697 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847924968 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.847924968 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3711059913 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 6242824688 ps |
| CPU time | 610.86 seconds |
| Started | Jul 12 08:10:59 PM PDT 24 |
| Finished | Jul 12 08:21:12 PM PDT 24 |
| Peak memory | 620792 kb |
| Host | smart-1b677ff9-43e9-47b8-8fe0-85f431747df5 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711059913 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.3711059913 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2887926993 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 4097652136 ps |
| CPU time | 468.42 seconds |
| Started | Jul 12 08:10:42 PM PDT 24 |
| Finished | Jul 12 08:18:32 PM PDT 24 |
| Peak memory | 620476 kb |
| Host | smart-df30b1c6-f15d-4647-bd6e-f11cde65d8f9 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288792 6993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2887926993 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.893522656 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 3160120500 ps |
| CPU time | 257.1 seconds |
| Started | Jul 12 08:15:03 PM PDT 24 |
| Finished | Jul 12 08:19:21 PM PDT 24 |
| Peak memory | 610208 kb |
| Host | smart-c9a7eabd-8b65-4950-bce5-3b07765da956 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893522656 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rv_plic_smoketest.893522656 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.3359785800 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2899696548 ps |
| CPU time | 261.14 seconds |
| Started | Jul 12 08:06:41 PM PDT 24 |
| Finished | Jul 12 08:11:03 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-123a8cbe-d0f0-47d8-b42c-878c3ad8dfe4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359785800 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.3359785800 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3371500895 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 2901276876 ps |
| CPU time | 252.55 seconds |
| Started | Jul 12 08:13:07 PM PDT 24 |
| Finished | Jul 12 08:17:21 PM PDT 24 |
| Peak memory | 609000 kb |
| Host | smart-bec72495-7f11-4a1f-9b5f-aade3f0b2231 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371500895 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.3371500895 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1811869528 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 2660540454 ps |
| CPU time | 262.63 seconds |
| Started | Jul 12 08:10:08 PM PDT 24 |
| Finished | Jul 12 08:14:31 PM PDT 24 |
| Peak memory | 610716 kb |
| Host | smart-3d8fde50-0783-406e-ae0f-ce348e7279ac |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811869 528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.1811869528 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1656986636 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3802919776 ps |
| CPU time | 350.87 seconds |
| Started | Jul 12 08:04:34 PM PDT 24 |
| Finished | Jul 12 08:10:25 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-a5152485-9af1-42e2-9e0c-d437d5219160 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656986636 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.1656986636 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.742398492 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 3043611148 ps |
| CPU time | 257.33 seconds |
| Started | Jul 12 08:03:38 PM PDT 24 |
| Finished | Jul 12 08:07:56 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-53ce13a2-602e-4c56-af68-298f933bc714 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742398492 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.742398492 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1276010936 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 9298195910 ps |
| CPU time | 1348.09 seconds |
| Started | Jul 12 08:04:20 PM PDT 24 |
| Finished | Jul 12 08:26:49 PM PDT 24 |
| Peak memory | 611092 kb |
| Host | smart-71834691-165a-4b98-868c-77c1370a8503 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276010936 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.1276010936 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2820901621 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 7892801128 ps |
| CPU time | 649.73 seconds |
| Started | Jul 12 08:11:07 PM PDT 24 |
| Finished | Jul 12 08:21:58 PM PDT 24 |
| Peak memory | 611096 kb |
| Host | smart-7687ee09-b615-4623-bc25-2315f03d9bc2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820901621 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.2820901621 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1219802078 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 8213303382 ps |
| CPU time | 898.36 seconds |
| Started | Jul 12 08:09:59 PM PDT 24 |
| Finished | Jul 12 08:24:59 PM PDT 24 |
| Peak memory | 610872 kb |
| Host | smart-82a70341-1577-4773-8692-2e25ddb646de |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219802078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep _sram_ret_contents_scramble.1219802078 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3785964239 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 8029450430 ps |
| CPU time | 941.28 seconds |
| Started | Jul 12 08:09:29 PM PDT 24 |
| Finished | Jul 12 08:25:13 PM PDT 24 |
| Peak memory | 625308 kb |
| Host | smart-c27a55d8-e53f-440f-8db1-5845adf15a52 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785964239 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.3785964239 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2703701332 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 4300984057 ps |
| CPU time | 480.57 seconds |
| Started | Jul 12 08:04:07 PM PDT 24 |
| Finished | Jul 12 08:12:09 PM PDT 24 |
| Peak memory | 625284 kb |
| Host | smart-77531245-2d28-42de-a0c2-e03faf38ecfb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703701332 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.2703701332 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.1908503108 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3551720969 ps |
| CPU time | 506.12 seconds |
| Started | Jul 12 08:05:54 PM PDT 24 |
| Finished | Jul 12 08:14:21 PM PDT 24 |
| Peak memory | 619984 kb |
| Host | smart-b5919469-ef2e-4c37-b55c-587cad91cfb1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908503108 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.1908503108 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3259521602 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2555230232 ps |
| CPU time | 295.62 seconds |
| Started | Jul 12 08:09:33 PM PDT 24 |
| Finished | Jul 12 08:14:30 PM PDT 24 |
| Peak memory | 610796 kb |
| Host | smart-2ada75fc-ed84-4c04-bea3-9b8834e79771 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259521602 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.3259521602 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3048252915 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 9729814875 ps |
| CPU time | 1036.42 seconds |
| Started | Jul 12 08:12:25 PM PDT 24 |
| Finished | Jul 12 08:29:43 PM PDT 24 |
| Peak memory | 610980 kb |
| Host | smart-d69bbc58-631f-401b-9575-7f4c64f1abb5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048252915 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.3048252915 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2832119004 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 4967765912 ps |
| CPU time | 616.74 seconds |
| Started | Jul 12 08:09:57 PM PDT 24 |
| Finished | Jul 12 08:20:15 PM PDT 24 |
| Peak memory | 611248 kb |
| Host | smart-cfce5992-7653-4bd9-bd04-14dee4f99654 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832119004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _sram_ctrl_scrambled_access.2832119004 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3953189802 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 5514468937 ps |
| CPU time | 631.62 seconds |
| Started | Jul 12 08:11:05 PM PDT 24 |
| Finished | Jul 12 08:21:38 PM PDT 24 |
| Peak memory | 611268 kb |
| Host | smart-7406cf67-8cd4-418f-9a77-3c69717e05b5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953189802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3953189802 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2974775982 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 5156327642 ps |
| CPU time | 506.11 seconds |
| Started | Jul 12 08:12:27 PM PDT 24 |
| Finished | Jul 12 08:20:55 PM PDT 24 |
| Peak memory | 611292 kb |
| Host | smart-670abe6e-4c73-4810-887b-dd96c5f3b51c |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974775982 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2974775982 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2248642318 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 3412418392 ps |
| CPU time | 266.2 seconds |
| Started | Jul 12 08:13:31 PM PDT 24 |
| Finished | Jul 12 08:17:59 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-f45e7cc7-af9d-4a06-b465-d67bca1fca51 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248642318 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.2248642318 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.4081739426 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 20443946505 ps |
| CPU time | 3285.44 seconds |
| Started | Jul 12 08:06:46 PM PDT 24 |
| Finished | Jul 12 09:01:33 PM PDT 24 |
| Peak memory | 610832 kb |
| Host | smart-144c28b2-c155-4f1e-b993-a643f83fd5af |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081739426 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.4081739426 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2329866196 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 4174266079 ps |
| CPU time | 714.06 seconds |
| Started | Jul 12 08:06:47 PM PDT 24 |
| Finished | Jul 12 08:18:43 PM PDT 24 |
| Peak memory | 613812 kb |
| Host | smart-27fc5f43-7090-40db-a24c-c6985736a579 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329866196 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.2329866196 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1681063831 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 2746983278 ps |
| CPU time | 273.68 seconds |
| Started | Jul 12 08:08:41 PM PDT 24 |
| Finished | Jul 12 08:13:16 PM PDT 24 |
| Peak memory | 613520 kb |
| Host | smart-29b14a43-d077-43fc-881a-e4b8996e9285 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681063831 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.1681063831 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2826677783 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 4038489152 ps |
| CPU time | 402.9 seconds |
| Started | Jul 12 08:07:08 PM PDT 24 |
| Finished | Jul 12 08:13:52 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-63afb449-7643-420e-97f5-afd8534f652a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826677783 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.2826677783 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.773995969 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 24074800186 ps |
| CPU time | 2043.55 seconds |
| Started | Jul 12 08:06:56 PM PDT 24 |
| Finished | Jul 12 08:41:00 PM PDT 24 |
| Peak memory | 614816 kb |
| Host | smart-ad26d2f7-8d90-40b2-a402-25100999f8bf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77399596 9 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.773995969 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1693490668 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 5851377640 ps |
| CPU time | 500.83 seconds |
| Started | Jul 12 08:06:43 PM PDT 24 |
| Finished | Jul 12 08:15:05 PM PDT 24 |
| Peak memory | 611048 kb |
| Host | smart-4efaac1a-a20d-4ca4-b418-038ea115fa56 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693490668 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1693490668 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1877653090 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 4211370520 ps |
| CPU time | 588.05 seconds |
| Started | Jul 12 08:05:35 PM PDT 24 |
| Finished | Jul 12 08:15:24 PM PDT 24 |
| Peak memory | 619436 kb |
| Host | smart-f993cd00-8682-4e4b-b89e-ab09cb9f23a5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1877653090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.1877653090 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.610777520 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 2996460900 ps |
| CPU time | 229.25 seconds |
| Started | Jul 12 08:14:51 PM PDT 24 |
| Finished | Jul 12 08:18:42 PM PDT 24 |
| Peak memory | 616688 kb |
| Host | smart-e0ebe435-2d26-4ecd-8783-32214cc25182 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610777520 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_uart_smoketest.610777520 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.2045787082 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 4541950324 ps |
| CPU time | 600.07 seconds |
| Started | Jul 12 08:04:13 PM PDT 24 |
| Finished | Jul 12 08:14:16 PM PDT 24 |
| Peak memory | 624416 kb |
| Host | smart-240f4cd5-20e1-4dac-b50b-330ea77eceae |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045787082 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.2045787082 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1639537622 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 4206938675 ps |
| CPU time | 698.49 seconds |
| Started | Jul 12 08:04:56 PM PDT 24 |
| Finished | Jul 12 08:16:36 PM PDT 24 |
| Peak memory | 625092 kb |
| Host | smart-37b27706-773d-425a-a128-3fa237d2942f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639537622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.1639537622 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3395888059 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 4534334805 ps |
| CPU time | 606.29 seconds |
| Started | Jul 12 08:05:17 PM PDT 24 |
| Finished | Jul 12 08:15:24 PM PDT 24 |
| Peak memory | 618992 kb |
| Host | smart-e15ce9ad-588d-489b-ac84-67088c24115a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395888059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3395888059 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2206977994 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 78301758749 ps |
| CPU time | 13581.2 seconds |
| Started | Jul 12 08:04:28 PM PDT 24 |
| Finished | Jul 12 11:50:51 PM PDT 24 |
| Peak memory | 634392 kb |
| Host | smart-63ec85b7-18f9-49cb-adf3-47841e29346c |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2206977994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.2206977994 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2886334920 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 3689731960 ps |
| CPU time | 488.98 seconds |
| Started | Jul 12 08:03:44 PM PDT 24 |
| Finished | Jul 12 08:11:54 PM PDT 24 |
| Peak memory | 624096 kb |
| Host | smart-a0c4ec72-09d4-4f45-a3d2-625efb8999c9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886334920 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.2886334920 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.4028281207 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 4592876432 ps |
| CPU time | 707.91 seconds |
| Started | Jul 12 08:03:58 PM PDT 24 |
| Finished | Jul 12 08:15:47 PM PDT 24 |
| Peak memory | 624404 kb |
| Host | smart-49e7170a-ca3a-4ca9-a07c-ab971e18d2a8 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028281207 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.4028281207 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.848268232 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 4689330040 ps |
| CPU time | 927.73 seconds |
| Started | Jul 12 08:03:55 PM PDT 24 |
| Finished | Jul 12 08:19:24 PM PDT 24 |
| Peak memory | 624360 kb |
| Host | smart-d1a76cc9-7bd5-4266-9ece-88c093bd96a7 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848268232 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.848268232 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.869425045 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 9289891908 ps |
| CPU time | 1100.51 seconds |
| Started | Jul 12 08:11:11 PM PDT 24 |
| Finished | Jul 12 08:29:33 PM PDT 24 |
| Peak memory | 621436 kb |
| Host | smart-c6d2a465-26b3-40b8-a56d-93490444dabe |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=869425045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.869425045 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.1557605270 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 2363582014 ps |
| CPU time | 160.36 seconds |
| Started | Jul 12 08:11:06 PM PDT 24 |
| Finished | Jul 12 08:13:47 PM PDT 24 |
| Peak memory | 620440 kb |
| Host | smart-0c224c72-e812-4ddd-bb02-c49daa724c14 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557605270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.1557605270 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_rma.1722375869 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 3207636858 ps |
| CPU time | 203.81 seconds |
| Started | Jul 12 08:10:11 PM PDT 24 |
| Finished | Jul 12 08:13:36 PM PDT 24 |
| Peak memory | 621424 kb |
| Host | smart-3850b2a7-26be-40f0-abda-f795224bb63f |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722375869 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.1722375869 |
| Directory | /workspace/2.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_testunlock0.3533677348 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 4505925859 ps |
| CPU time | 466.19 seconds |
| Started | Jul 12 08:10:07 PM PDT 24 |
| Finished | Jul 12 08:17:54 PM PDT 24 |
| Peak memory | 621424 kb |
| Host | smart-dbf6c11d-58b7-4a00-8254-558e997830c1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3533677348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.3533677348 |
| Directory | /workspace/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.4028956779 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 15069014902 ps |
| CPU time | 3998.74 seconds |
| Started | Jul 12 08:16:23 PM PDT 24 |
| Finished | Jul 12 09:23:03 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-b45eec36-63a9-4bc3-86d9-9da77fe794f6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028956779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.4028956779 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.1270346324 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 15763467778 ps |
| CPU time | 3782.13 seconds |
| Started | Jul 12 08:22:52 PM PDT 24 |
| Finished | Jul 12 09:25:56 PM PDT 24 |
| Peak memory | 610504 kb |
| Host | smart-b6520015-51ca-4355-8b4d-5301e368280a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270346324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.1270346324 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.624444741 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 16019416744 ps |
| CPU time | 3253.74 seconds |
| Started | Jul 12 08:16:03 PM PDT 24 |
| Finished | Jul 12 09:10:18 PM PDT 24 |
| Peak memory | 611516 kb |
| Host | smart-8f62650a-512e-425f-ae0b-0f47f4d24502 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624444741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.rom_e2e_asm_init_prod_end.624444741 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.1839898139 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 14652106567 ps |
| CPU time | 3056.13 seconds |
| Started | Jul 12 08:16:11 PM PDT 24 |
| Finished | Jul 12 09:07:09 PM PDT 24 |
| Peak memory | 611576 kb |
| Host | smart-99f47513-72fe-490d-926a-82e3be2f2af8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839898139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.1839898139 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3635781217 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 11375403463 ps |
| CPU time | 2993.92 seconds |
| Started | Jul 12 08:15:20 PM PDT 24 |
| Finished | Jul 12 09:05:15 PM PDT 24 |
| Peak memory | 612056 kb |
| Host | smart-b0aaa190-674b-4726-a512-74419db38fc8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635781217 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_test_unlocked0.3635781217 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3381369016 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 14544879810 ps |
| CPU time | 3321.2 seconds |
| Started | Jul 12 08:17:19 PM PDT 24 |
| Finished | Jul 12 09:12:42 PM PDT 24 |
| Peak memory | 610824 kb |
| Host | smart-538c1064-844a-4fa0-98c3-2df156e6c3f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381369016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3381369016 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1937881730 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 14961224216 ps |
| CPU time | 3187.81 seconds |
| Started | Jul 12 08:16:46 PM PDT 24 |
| Finished | Jul 12 09:09:56 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-e76d82a4-34e6-41a2-b7f4-9d6ad07455cc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937881730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.1937881730 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3064952306 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 14587437024 ps |
| CPU time | 2935.94 seconds |
| Started | Jul 12 08:17:07 PM PDT 24 |
| Finished | Jul 12 09:06:04 PM PDT 24 |
| Peak memory | 610760 kb |
| Host | smart-40c27f37-3477-4d19-bebc-b8dab583c062 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064952306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.3064952306 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.660324690 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 14655206708 ps |
| CPU time | 3402.15 seconds |
| Started | Jul 12 08:23:14 PM PDT 24 |
| Finished | Jul 12 09:19:58 PM PDT 24 |
| Peak memory | 611704 kb |
| Host | smart-39ba267e-339f-4e17-961a-d42698647c26 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660324690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shut down_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_s hutdown_exception_c.660324690 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.1078222800 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 26593209388 ps |
| CPU time | 3393.41 seconds |
| Started | Jul 12 08:18:29 PM PDT 24 |
| Finished | Jul 12 09:15:04 PM PDT 24 |
| Peak memory | 612064 kb |
| Host | smart-2764b5ec-0533-4ae6-ac34-79175d150e0b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078222800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.1078222800 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.560190977 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 15220867616 ps |
| CPU time | 4178.72 seconds |
| Started | Jul 12 08:15:40 PM PDT 24 |
| Finished | Jul 12 09:25:20 PM PDT 24 |
| Peak memory | 610536 kb |
| Host | smart-8d4f9379-ac53-4c5b-8e73-94b3d0328630 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=560190977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.560190977 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.1853753221 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 17604074032 ps |
| CPU time | 3998.64 seconds |
| Started | Jul 12 08:18:41 PM PDT 24 |
| Finished | Jul 12 09:25:21 PM PDT 24 |
| Peak memory | 610800 kb |
| Host | smart-b138da1b-45d1-42ab-b214-e6b7c68d72e0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853753221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.1853753221 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.2429015731 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 4790674120 ps |
| CPU time | 693.18 seconds |
| Started | Jul 12 08:13:44 PM PDT 24 |
| Finished | Jul 12 08:25:19 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-43732508-42f7-4ade-a6c2-6573e809b5ad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429015731 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.2429015731 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_raw_unlock.1865559467 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 6019670686 ps |
| CPU time | 259.37 seconds |
| Started | Jul 12 08:12:39 PM PDT 24 |
| Finished | Jul 12 08:16:59 PM PDT 24 |
| Peak memory | 619796 kb |
| Host | smart-a7e8892b-4b44-4569-9bd5-ca5eece940fb |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1865559467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.1865559467 |
| Directory | /workspace/2.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.685584406 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 3061100279 ps |
| CPU time | 130.99 seconds |
| Started | Jul 12 08:13:17 PM PDT 24 |
| Finished | Jul 12 08:15:31 PM PDT 24 |
| Peak memory | 617312 kb |
| Host | smart-563cf043-4d06-437a-964e-7ad50d2c780a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685584406 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.685584406 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.1236507479 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 5432232470 ps |
| CPU time | 584.98 seconds |
| Started | Jul 12 08:19:32 PM PDT 24 |
| Finished | Jul 12 08:29:18 PM PDT 24 |
| Peak memory | 650080 kb |
| Host | smart-0ef86cab-9407-454a-9fff-6e1b48d76608 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1236507479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.1236507479 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.880927587 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 5567471220 ps |
| CPU time | 561.03 seconds |
| Started | Jul 12 08:18:54 PM PDT 24 |
| Finished | Jul 12 08:28:15 PM PDT 24 |
| Peak memory | 650192 kb |
| Host | smart-88945737-38f9-498e-ac84-0d7cf08229f4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 880927587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.880927587 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1394062251 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 4204645416 ps |
| CPU time | 310 seconds |
| Started | Jul 12 08:21:47 PM PDT 24 |
| Finished | Jul 12 08:26:58 PM PDT 24 |
| Peak memory | 648812 kb |
| Host | smart-901dc270-6396-46b4-ae4e-99863ac9380b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394062251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1394062251 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2365929419 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 4337272182 ps |
| CPU time | 341.49 seconds |
| Started | Jul 12 08:18:30 PM PDT 24 |
| Finished | Jul 12 08:24:12 PM PDT 24 |
| Peak memory | 648952 kb |
| Host | smart-970ebabe-18af-44a2-b5a0-c5f0cb8f0567 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365929419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2365929419 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3730638685 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 4563170300 ps |
| CPU time | 521.85 seconds |
| Started | Jul 12 08:19:17 PM PDT 24 |
| Finished | Jul 12 08:28:00 PM PDT 24 |
| Peak memory | 649116 kb |
| Host | smart-5c0a1725-4f63-4a3a-97a6-70ef47e5fd61 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730638685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3730638685 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2022430493 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 3811539590 ps |
| CPU time | 543.04 seconds |
| Started | Jul 12 08:18:12 PM PDT 24 |
| Finished | Jul 12 08:27:15 PM PDT 24 |
| Peak memory | 648604 kb |
| Host | smart-61043bdc-6120-46fc-ac4e-8a77141315db |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022430493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2022430493 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2974015839 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 6631838240 ps |
| CPU time | 633.56 seconds |
| Started | Jul 12 08:13:59 PM PDT 24 |
| Finished | Jul 12 08:24:34 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-ded65821-0a32-4dac-abc4-11d1be976098 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2974015839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2974015839 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1232971980 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 16414710640 ps |
| CPU time | 3832.85 seconds |
| Started | Jul 12 08:13:44 PM PDT 24 |
| Finished | Jul 12 09:17:39 PM PDT 24 |
| Peak memory | 610956 kb |
| Host | smart-5aa758ca-f7d9-4574-9b99-30280171cf18 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232971980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.1232971980 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.586746774 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 5784037047 ps |
| CPU time | 775.13 seconds |
| Started | Jul 12 08:14:34 PM PDT 24 |
| Finished | Jul 12 08:27:30 PM PDT 24 |
| Peak memory | 620468 kb |
| Host | smart-b422de38-5790-4ff3-b0d7-128edbee7061 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586746774 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.586746774 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.153304633 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 8281919656 ps |
| CPU time | 957.16 seconds |
| Started | Jul 12 08:14:40 PM PDT 24 |
| Finished | Jul 12 08:30:38 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-e8544853-4b8b-4864-9932-7a6562edd3fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15330463 3 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.153304633 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3271891680 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 7894331290 ps |
| CPU time | 1518.02 seconds |
| Started | Jul 12 08:14:21 PM PDT 24 |
| Finished | Jul 12 08:39:42 PM PDT 24 |
| Peak memory | 619128 kb |
| Host | smart-fb195723-fa97-4494-bcd6-57ea15e06fcd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3271891680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.3271891680 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.1813884469 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 4847211484 ps |
| CPU time | 722.19 seconds |
| Started | Jul 12 08:15:11 PM PDT 24 |
| Finished | Jul 12 08:27:14 PM PDT 24 |
| Peak memory | 623112 kb |
| Host | smart-cd6f90ac-beb3-4849-8211-3dec040ffade |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813884469 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.1813884469 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3430051541 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 3789685571 ps |
| CPU time | 663.72 seconds |
| Started | Jul 12 08:13:29 PM PDT 24 |
| Finished | Jul 12 08:24:34 PM PDT 24 |
| Peak memory | 625120 kb |
| Host | smart-63537c4d-6336-449b-92e1-6c21a63f74e1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430051541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.3430051541 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.285511228 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 3882761269 ps |
| CPU time | 560.56 seconds |
| Started | Jul 12 08:14:02 PM PDT 24 |
| Finished | Jul 12 08:23:24 PM PDT 24 |
| Peak memory | 625088 kb |
| Host | smart-fd34913f-48be-4a06-9f55-00ec50736522 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285511228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.285511228 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.4049032356 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 4253603376 ps |
| CPU time | 687.31 seconds |
| Started | Jul 12 08:13:51 PM PDT 24 |
| Finished | Jul 12 08:25:20 PM PDT 24 |
| Peak memory | 624128 kb |
| Host | smart-046ed806-551e-4d40-9c55-e70bb6452727 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049032356 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.4049032356 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3157077900 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 4610500400 ps |
| CPU time | 755.06 seconds |
| Started | Jul 12 08:13:53 PM PDT 24 |
| Finished | Jul 12 08:26:29 PM PDT 24 |
| Peak memory | 624388 kb |
| Host | smart-a1b7c3f6-9687-4f38-84c7-88352949bed3 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157077900 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.3157077900 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.517230594 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 4022555056 ps |
| CPU time | 655.58 seconds |
| Started | Jul 12 08:13:29 PM PDT 24 |
| Finished | Jul 12 08:24:26 PM PDT 24 |
| Peak memory | 622808 kb |
| Host | smart-0afe3025-7ac6-4141-8710-03eaadc591ed |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517230594 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.517230594 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.1613698660 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 3670718434 ps |
| CPU time | 286.21 seconds |
| Started | Jul 12 08:15:54 PM PDT 24 |
| Finished | Jul 12 08:20:41 PM PDT 24 |
| Peak memory | 622320 kb |
| Host | smart-1fe83595-b1f2-418d-a952-5c59b4448c4f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1613698660 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.1613698660 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.565255203 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 12832334663 ps |
| CPU time | 1191.65 seconds |
| Started | Jul 12 08:13:42 PM PDT 24 |
| Finished | Jul 12 08:33:35 PM PDT 24 |
| Peak memory | 621412 kb |
| Host | smart-84e9793b-7348-4268-a40a-7c3f63baf592 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565255203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.565255203 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_testunlock0.2371864787 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 5373425015 ps |
| CPU time | 547.65 seconds |
| Started | Jul 12 08:13:56 PM PDT 24 |
| Finished | Jul 12 08:23:06 PM PDT 24 |
| Peak memory | 621400 kb |
| Host | smart-dae93131-50d2-4078-bda7-97f2efd3ca6f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2371864787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.2371864787 |
| Directory | /workspace/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3778770845 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 3177563036 ps |
| CPU time | 550.62 seconds |
| Started | Jul 12 08:19:33 PM PDT 24 |
| Finished | Jul 12 08:28:45 PM PDT 24 |
| Peak memory | 648992 kb |
| Host | smart-168b94f6-4153-4c32-b5b3-c16c2b5b62a2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778770845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3778770845 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1880856281 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 3504128648 ps |
| CPU time | 367.58 seconds |
| Started | Jul 12 08:22:01 PM PDT 24 |
| Finished | Jul 12 08:28:09 PM PDT 24 |
| Peak memory | 648892 kb |
| Host | smart-5ab1ce42-d8ea-4b5c-8fcb-f33f08933a45 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880856281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1880856281 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.1499712207 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 5598001942 ps |
| CPU time | 600.08 seconds |
| Started | Jul 12 08:20:54 PM PDT 24 |
| Finished | Jul 12 08:30:56 PM PDT 24 |
| Peak memory | 650464 kb |
| Host | smart-e2b7b1a3-04ac-44e1-9463-884c626ba73d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1499712207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.1499712207 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1854963726 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 4337355528 ps |
| CPU time | 347.67 seconds |
| Started | Jul 12 08:20:50 PM PDT 24 |
| Finished | Jul 12 08:26:39 PM PDT 24 |
| Peak memory | 649204 kb |
| Host | smart-d7917247-9738-4f28-bba9-064aeed9fc41 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854963726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1854963726 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.3339937247 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 4744671938 ps |
| CPU time | 629.64 seconds |
| Started | Jul 12 08:18:56 PM PDT 24 |
| Finished | Jul 12 08:29:27 PM PDT 24 |
| Peak memory | 617092 kb |
| Host | smart-85f77a8e-ea2b-483a-9527-c2578e33114c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3339937247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.3339937247 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.3601622992 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 4956048216 ps |
| CPU time | 753.65 seconds |
| Started | Jul 12 08:20:00 PM PDT 24 |
| Finished | Jul 12 08:32:34 PM PDT 24 |
| Peak memory | 650356 kb |
| Host | smart-f88b3787-47af-4fd1-94d9-fbc7ee5339fc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3601622992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.3601622992 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2961359681 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3410015296 ps |
| CPU time | 360.7 seconds |
| Started | Jul 12 08:21:25 PM PDT 24 |
| Finished | Jul 12 08:27:26 PM PDT 24 |
| Peak memory | 648956 kb |
| Host | smart-6b186ada-1f0f-44f2-b369-868b7a234d5e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961359681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2961359681 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1035405284 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 3337225624 ps |
| CPU time | 404.38 seconds |
| Started | Jul 12 08:21:12 PM PDT 24 |
| Finished | Jul 12 08:27:58 PM PDT 24 |
| Peak memory | 649032 kb |
| Host | smart-f62bb0ee-2156-4cf8-aa55-73e8460ed125 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035405284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1035405284 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.1542833116 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 4032968150 ps |
| CPU time | 525.55 seconds |
| Started | Jul 12 08:19:30 PM PDT 24 |
| Finished | Jul 12 08:28:17 PM PDT 24 |
| Peak memory | 649556 kb |
| Host | smart-1f5c1ba3-c0bb-494b-9e24-08df5288733f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1542833116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.1542833116 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.4068729021 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 3456874400 ps |
| CPU time | 387.68 seconds |
| Started | Jul 12 08:15:14 PM PDT 24 |
| Finished | Jul 12 08:21:44 PM PDT 24 |
| Peak memory | 649144 kb |
| Host | smart-31a8ee1a-34bd-4fac-bc4e-2fa8036cb4b8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068729021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.4068729021 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3871121037 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 6143523960 ps |
| CPU time | 350.94 seconds |
| Started | Jul 12 08:15:10 PM PDT 24 |
| Finished | Jul 12 08:21:02 PM PDT 24 |
| Peak memory | 609644 kb |
| Host | smart-e36a4680-4ab1-4d0a-8752-4a6053276055 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3871121037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3871121037 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.680437926 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 23476814912 ps |
| CPU time | 4801.09 seconds |
| Started | Jul 12 08:14:43 PM PDT 24 |
| Finished | Jul 12 09:34:45 PM PDT 24 |
| Peak memory | 610940 kb |
| Host | smart-460a6c12-3a36-4056-ae75-dde360267255 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680437926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.680437926 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2657249760 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 5446505672 ps |
| CPU time | 900.19 seconds |
| Started | Jul 12 08:16:23 PM PDT 24 |
| Finished | Jul 12 08:31:25 PM PDT 24 |
| Peak memory | 611028 kb |
| Host | smart-70d3f76f-1c53-47b4-bedd-a9b142c23dfe |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2657249760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.2657249760 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1809562181 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 5867650000 ps |
| CPU time | 473.12 seconds |
| Started | Jul 12 08:15:13 PM PDT 24 |
| Finished | Jul 12 08:23:09 PM PDT 24 |
| Peak memory | 620452 kb |
| Host | smart-3581b734-53cb-4ed6-a8a3-9453fd74f92e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809562181 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.1809562181 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.373540720 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 7427050474 ps |
| CPU time | 1056.34 seconds |
| Started | Jul 12 08:15:29 PM PDT 24 |
| Finished | Jul 12 08:33:07 PM PDT 24 |
| Peak memory | 611080 kb |
| Host | smart-be5ed7df-d6dd-462e-a866-622b016df7a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37354072 0 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.373540720 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3765918110 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 8127117510 ps |
| CPU time | 1501.89 seconds |
| Started | Jul 12 08:14:44 PM PDT 24 |
| Finished | Jul 12 08:39:48 PM PDT 24 |
| Peak memory | 619068 kb |
| Host | smart-44b50bbe-bfd2-4a90-a9d6-1f4b3ccf85bb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3765918110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.3765918110 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.301489934 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 3799748848 ps |
| CPU time | 561.25 seconds |
| Started | Jul 12 08:14:21 PM PDT 24 |
| Finished | Jul 12 08:23:45 PM PDT 24 |
| Peak memory | 624152 kb |
| Host | smart-ff724f05-d902-4109-b9a5-34f57439d42c |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301489934 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.301489934 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4168690282 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 3705336708 ps |
| CPU time | 524.98 seconds |
| Started | Jul 12 08:16:43 PM PDT 24 |
| Finished | Jul 12 08:25:30 PM PDT 24 |
| Peak memory | 625108 kb |
| Host | smart-3a74d583-4369-43bb-833f-38a227d6db08 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168690282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.4168690282 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.318374093 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 4217499864 ps |
| CPU time | 706.72 seconds |
| Started | Jul 12 08:14:26 PM PDT 24 |
| Finished | Jul 12 08:26:14 PM PDT 24 |
| Peak memory | 624132 kb |
| Host | smart-dea689a6-59ae-425d-ab6d-8ae119c8e4c0 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318374093 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.318374093 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1340943836 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4265668220 ps |
| CPU time | 641.76 seconds |
| Started | Jul 12 08:14:59 PM PDT 24 |
| Finished | Jul 12 08:25:42 PM PDT 24 |
| Peak memory | 624156 kb |
| Host | smart-8e65ac53-7ffc-40b5-a7f5-c64f7e78cc3c |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340943836 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.1340943836 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3874947934 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4505992696 ps |
| CPU time | 699.65 seconds |
| Started | Jul 12 08:14:45 PM PDT 24 |
| Finished | Jul 12 08:26:26 PM PDT 24 |
| Peak memory | 623156 kb |
| Host | smart-241b0817-2214-4d9b-aa88-a674ce4a7730 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874947934 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.3874947934 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.682603867 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 13441335166 ps |
| CPU time | 1653.08 seconds |
| Started | Jul 12 08:14:01 PM PDT 24 |
| Finished | Jul 12 08:41:35 PM PDT 24 |
| Peak memory | 621408 kb |
| Host | smart-8f58e4bf-9129-419d-97eb-6d19ec942019 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=682603867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.682603867 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.2857159403 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 13016315574 ps |
| CPU time | 1263.29 seconds |
| Started | Jul 12 08:15:34 PM PDT 24 |
| Finished | Jul 12 08:36:38 PM PDT 24 |
| Peak memory | 621380 kb |
| Host | smart-0eecb683-529f-4da6-968d-bbc4961427a9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857159403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.2857159403 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.3368160707 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 2916358872 ps |
| CPU time | 229.03 seconds |
| Started | Jul 12 08:15:16 PM PDT 24 |
| Finished | Jul 12 08:19:06 PM PDT 24 |
| Peak memory | 621404 kb |
| Host | smart-5f14b897-ebd5-4bb3-a7fa-35fc649f9775 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368160707 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.3368160707 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.3978166084 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 6244045279 ps |
| CPU time | 536.57 seconds |
| Started | Jul 12 08:15:20 PM PDT 24 |
| Finished | Jul 12 08:24:17 PM PDT 24 |
| Peak memory | 621416 kb |
| Host | smart-12f35e7b-6f3d-49c2-a9d4-5f0f5a2ef681 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3978166084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.3978166084 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3937967006 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 3948236360 ps |
| CPU time | 422.61 seconds |
| Started | Jul 12 08:19:49 PM PDT 24 |
| Finished | Jul 12 08:26:52 PM PDT 24 |
| Peak memory | 619100 kb |
| Host | smart-8c54980b-92e8-4675-ace9-2a5833e226c3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937967006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3937967006 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.4271618981 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 5164108792 ps |
| CPU time | 695.75 seconds |
| Started | Jul 12 08:21:20 PM PDT 24 |
| Finished | Jul 12 08:32:57 PM PDT 24 |
| Peak memory | 617100 kb |
| Host | smart-c331892a-7bdb-4253-8169-e0f6fb39a37e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4271618981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.4271618981 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.2375523262 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 5679765832 ps |
| CPU time | 595.04 seconds |
| Started | Jul 12 08:19:05 PM PDT 24 |
| Finished | Jul 12 08:29:01 PM PDT 24 |
| Peak memory | 650164 kb |
| Host | smart-60605be6-e402-49c1-ae29-4a5fb15f7421 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2375523262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.2375523262 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.2639194660 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 4205654616 ps |
| CPU time | 588.06 seconds |
| Started | Jul 12 08:19:43 PM PDT 24 |
| Finished | Jul 12 08:29:32 PM PDT 24 |
| Peak memory | 649916 kb |
| Host | smart-db3185ad-5083-46c1-bfcd-43be44b26924 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2639194660 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.2639194660 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.4058754710 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 6073475862 ps |
| CPU time | 645.81 seconds |
| Started | Jul 12 08:20:21 PM PDT 24 |
| Finished | Jul 12 08:31:08 PM PDT 24 |
| Peak memory | 649972 kb |
| Host | smart-1186b230-7d57-428e-aca4-379178894760 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4058754710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.4058754710 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3333885957 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 4290720864 ps |
| CPU time | 425.05 seconds |
| Started | Jul 12 08:19:43 PM PDT 24 |
| Finished | Jul 12 08:26:50 PM PDT 24 |
| Peak memory | 648804 kb |
| Host | smart-980879b7-d6cb-427b-bccc-953a960aea98 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333885957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3333885957 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.4282454551 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 5002695672 ps |
| CPU time | 581.9 seconds |
| Started | Jul 12 08:20:19 PM PDT 24 |
| Finished | Jul 12 08:30:02 PM PDT 24 |
| Peak memory | 617116 kb |
| Host | smart-7a774857-d397-428b-bfe5-e9ec0d964026 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4282454551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.4282454551 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1198672870 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 4572388544 ps |
| CPU time | 531.66 seconds |
| Started | Jul 12 08:19:36 PM PDT 24 |
| Finished | Jul 12 08:28:28 PM PDT 24 |
| Peak memory | 649236 kb |
| Host | smart-036b7105-693c-4a0f-a91c-dcdf39ed0085 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198672870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1198672870 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.843775646 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 4928867240 ps |
| CPU time | 648.93 seconds |
| Started | Jul 12 08:20:25 PM PDT 24 |
| Finished | Jul 12 08:31:16 PM PDT 24 |
| Peak memory | 650096 kb |
| Host | smart-e9a99471-342d-461b-9dfe-44400f21af9f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 843775646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.843775646 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3860454683 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 4155874280 ps |
| CPU time | 459.43 seconds |
| Started | Jul 12 08:21:41 PM PDT 24 |
| Finished | Jul 12 08:29:22 PM PDT 24 |
| Peak memory | 648920 kb |
| Host | smart-6cbb9635-5882-4255-9cfe-20f9928d6c96 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860454683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3860454683 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2880084062 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 3885580984 ps |
| CPU time | 415.27 seconds |
| Started | Jul 12 08:19:59 PM PDT 24 |
| Finished | Jul 12 08:26:55 PM PDT 24 |
| Peak memory | 649228 kb |
| Host | smart-bbdc8406-1164-4248-8d81-0bf512fd9721 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880084062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2880084062 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.2285539737 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 5555119274 ps |
| CPU time | 594.15 seconds |
| Started | Jul 12 08:19:50 PM PDT 24 |
| Finished | Jul 12 08:29:45 PM PDT 24 |
| Peak memory | 650344 kb |
| Host | smart-0e346e1b-87cb-4600-ab5a-cb0de1653053 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2285539737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.2285539737 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.4121078559 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 4861672022 ps |
| CPU time | 543.68 seconds |
| Started | Jul 12 08:22:08 PM PDT 24 |
| Finished | Jul 12 08:31:13 PM PDT 24 |
| Peak memory | 617140 kb |
| Host | smart-35af2e86-f924-4382-84f7-18e1b3112ff3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4121078559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.4121078559 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.383192749 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 4211624168 ps |
| CPU time | 426.61 seconds |
| Started | Jul 12 08:15:41 PM PDT 24 |
| Finished | Jul 12 08:22:49 PM PDT 24 |
| Peak memory | 649216 kb |
| Host | smart-e1bbc9a8-811d-4ca0-931f-64e82bb352cb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383192749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw _alert_handler_lpg_sleep_mode_alerts.383192749 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.224949312 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 5669356772 ps |
| CPU time | 775.86 seconds |
| Started | Jul 12 08:15:53 PM PDT 24 |
| Finished | Jul 12 08:28:50 PM PDT 24 |
| Peak memory | 649904 kb |
| Host | smart-a16f96d0-5b25-4171-b299-e89f8dceb3f4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 224949312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.224949312 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2841090686 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 23200320324 ps |
| CPU time | 5087.77 seconds |
| Started | Jul 12 08:17:47 PM PDT 24 |
| Finished | Jul 12 09:42:36 PM PDT 24 |
| Peak memory | 609860 kb |
| Host | smart-95db8c6f-d10e-429b-971f-5976e95defb7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841090686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.2841090686 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.3727551874 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 5905733800 ps |
| CPU time | 637.91 seconds |
| Started | Jul 12 08:15:11 PM PDT 24 |
| Finished | Jul 12 08:25:50 PM PDT 24 |
| Peak memory | 610996 kb |
| Host | smart-5f963801-1cfa-4711-a6c2-d14934855c67 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3727551874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.3727551874 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1472944116 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 7703015576 ps |
| CPU time | 1336.06 seconds |
| Started | Jul 12 08:16:55 PM PDT 24 |
| Finished | Jul 12 08:39:12 PM PDT 24 |
| Peak memory | 619172 kb |
| Host | smart-c2a4eb64-86a8-4f59-a697-8dfc44cdec45 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1472944116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.1472944116 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3373749324 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 4058069584 ps |
| CPU time | 536.36 seconds |
| Started | Jul 12 08:22:16 PM PDT 24 |
| Finished | Jul 12 08:31:14 PM PDT 24 |
| Peak memory | 648672 kb |
| Host | smart-d1628583-47f6-4d5d-9da1-039d1d54ed6a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373749324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3373749324 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.3317637657 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 4479320944 ps |
| CPU time | 597.68 seconds |
| Started | Jul 12 08:22:18 PM PDT 24 |
| Finished | Jul 12 08:32:17 PM PDT 24 |
| Peak memory | 649976 kb |
| Host | smart-d67636b2-d3ec-4bd3-85a4-4507172a6e31 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3317637657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.3317637657 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1609460363 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 3463968680 ps |
| CPU time | 426.81 seconds |
| Started | Jul 12 08:20:57 PM PDT 24 |
| Finished | Jul 12 08:28:05 PM PDT 24 |
| Peak memory | 648904 kb |
| Host | smart-6917257e-4436-4309-8bfc-f73c67366e0a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609460363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1609460363 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.339200719 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3793523952 ps |
| CPU time | 409.64 seconds |
| Started | Jul 12 08:21:40 PM PDT 24 |
| Finished | Jul 12 08:28:31 PM PDT 24 |
| Peak memory | 648936 kb |
| Host | smart-2373719e-2ce3-498b-a455-537a87d00e09 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339200719 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_s w_alert_handler_lpg_sleep_mode_alerts.339200719 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.4048544559 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 5839237696 ps |
| CPU time | 679.88 seconds |
| Started | Jul 12 08:20:17 PM PDT 24 |
| Finished | Jul 12 08:31:38 PM PDT 24 |
| Peak memory | 650224 kb |
| Host | smart-5f44228e-dbfb-489a-8c87-2c9c6a6decb8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4048544559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.4048544559 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1311642044 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 4422683676 ps |
| CPU time | 495.62 seconds |
| Started | Jul 12 08:21:28 PM PDT 24 |
| Finished | Jul 12 08:29:45 PM PDT 24 |
| Peak memory | 619084 kb |
| Host | smart-4dfbb23c-97fc-4764-9550-945002f64a9d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311642044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1311642044 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.287483318 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 4153421246 ps |
| CPU time | 494.93 seconds |
| Started | Jul 12 08:21:52 PM PDT 24 |
| Finished | Jul 12 08:30:08 PM PDT 24 |
| Peak memory | 649708 kb |
| Host | smart-2ab97654-6475-4822-a8f8-16e351e89112 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 287483318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.287483318 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3973411838 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 3681010772 ps |
| CPU time | 464.83 seconds |
| Started | Jul 12 08:22:29 PM PDT 24 |
| Finished | Jul 12 08:30:15 PM PDT 24 |
| Peak memory | 648836 kb |
| Host | smart-e1095401-f75f-443d-9142-9d0bf71530c0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973411838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3973411838 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.2588213272 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 5133179628 ps |
| CPU time | 530.71 seconds |
| Started | Jul 12 08:21:27 PM PDT 24 |
| Finished | Jul 12 08:30:19 PM PDT 24 |
| Peak memory | 650212 kb |
| Host | smart-685d0301-8208-4912-a31a-f71be1622d62 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2588213272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.2588213272 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.475217385 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 3821836662 ps |
| CPU time | 423.53 seconds |
| Started | Jul 12 08:21:25 PM PDT 24 |
| Finished | Jul 12 08:28:30 PM PDT 24 |
| Peak memory | 618824 kb |
| Host | smart-569fbace-dae2-4880-8c30-cdd25dcf28f5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475217385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_s w_alert_handler_lpg_sleep_mode_alerts.475217385 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.71827994 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 5556736700 ps |
| CPU time | 536.82 seconds |
| Started | Jul 12 08:21:31 PM PDT 24 |
| Finished | Jul 12 08:30:29 PM PDT 24 |
| Peak memory | 649888 kb |
| Host | smart-f0912be8-de1f-4521-a50c-da1605559474 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 71827994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.71827994 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1063561640 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 3986478520 ps |
| CPU time | 402.96 seconds |
| Started | Jul 12 08:23:01 PM PDT 24 |
| Finished | Jul 12 08:29:45 PM PDT 24 |
| Peak memory | 649036 kb |
| Host | smart-f92ff7ac-3321-41bd-96ff-ff34a5a22833 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063561640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1063561640 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.2880185742 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 4833704152 ps |
| CPU time | 530.04 seconds |
| Started | Jul 12 08:20:52 PM PDT 24 |
| Finished | Jul 12 08:29:44 PM PDT 24 |
| Peak memory | 650324 kb |
| Host | smart-05f844b3-7254-4c62-b949-71d4a77d4f72 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2880185742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.2880185742 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.3292102569 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 5946273016 ps |
| CPU time | 725.16 seconds |
| Started | Jul 12 08:17:25 PM PDT 24 |
| Finished | Jul 12 08:29:32 PM PDT 24 |
| Peak memory | 649908 kb |
| Host | smart-e029c8b2-c495-4b67-9380-8ff8942796ca |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3292102569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.3292102569 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.738486091 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 15996430232 ps |
| CPU time | 3631.36 seconds |
| Started | Jul 12 08:16:11 PM PDT 24 |
| Finished | Jul 12 09:16:44 PM PDT 24 |
| Peak memory | 611012 kb |
| Host | smart-f8789283-8435-4017-ad7f-a903365bca77 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738486091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.738486091 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.844408990 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 6877187376 ps |
| CPU time | 388.32 seconds |
| Started | Jul 12 08:15:41 PM PDT 24 |
| Finished | Jul 12 08:22:10 PM PDT 24 |
| Peak memory | 620400 kb |
| Host | smart-2c283b48-9a1a-484b-a652-78a0ae28d784 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844408990 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.844408990 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1956324256 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 12819292416 ps |
| CPU time | 2229.17 seconds |
| Started | Jul 12 08:17:33 PM PDT 24 |
| Finished | Jul 12 08:54:44 PM PDT 24 |
| Peak memory | 619152 kb |
| Host | smart-dd9159fa-886b-4ca1-b8bf-0563ea2e71fe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1956324256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.1956324256 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3970527655 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 3677614456 ps |
| CPU time | 409.92 seconds |
| Started | Jul 12 08:22:32 PM PDT 24 |
| Finished | Jul 12 08:29:23 PM PDT 24 |
| Peak memory | 648964 kb |
| Host | smart-3570547b-47da-4962-978a-9e57724bf179 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970527655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3970527655 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.4008691261 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 6209449296 ps |
| CPU time | 751.21 seconds |
| Started | Jul 12 08:21:34 PM PDT 24 |
| Finished | Jul 12 08:34:06 PM PDT 24 |
| Peak memory | 650072 kb |
| Host | smart-ccab0bec-29e6-40d9-808e-68145005441a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4008691261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.4008691261 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.42877510 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 3379584602 ps |
| CPU time | 438.1 seconds |
| Started | Jul 12 08:22:41 PM PDT 24 |
| Finished | Jul 12 08:30:00 PM PDT 24 |
| Peak memory | 648952 kb |
| Host | smart-e9ccb248-ae56-4541-bf4b-db5f75e4cfac |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42877510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw _alert_handler_lpg_sleep_mode_alerts.42877510 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.5619514 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 6165559650 ps |
| CPU time | 717.49 seconds |
| Started | Jul 12 08:21:37 PM PDT 24 |
| Finished | Jul 12 08:33:35 PM PDT 24 |
| Peak memory | 650104 kb |
| Host | smart-f3076d3b-8f0c-4a11-bc62-eb9c3f59f73c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 5619514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.5619514 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3761400547 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 4331579360 ps |
| CPU time | 507.68 seconds |
| Started | Jul 12 08:21:43 PM PDT 24 |
| Finished | Jul 12 08:30:11 PM PDT 24 |
| Peak memory | 649124 kb |
| Host | smart-151643d4-1f5a-4266-aa4a-9b1e8a58d825 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761400547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3761400547 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.829975005 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 3677925386 ps |
| CPU time | 371.11 seconds |
| Started | Jul 12 08:25:09 PM PDT 24 |
| Finished | Jul 12 08:31:22 PM PDT 24 |
| Peak memory | 648716 kb |
| Host | smart-58604dc3-6133-41f7-badf-231129aec846 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829975005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_s w_alert_handler_lpg_sleep_mode_alerts.829975005 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.110618457 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 3484195772 ps |
| CPU time | 407.07 seconds |
| Started | Jul 12 08:23:23 PM PDT 24 |
| Finished | Jul 12 08:30:12 PM PDT 24 |
| Peak memory | 648848 kb |
| Host | smart-307dbe3c-d8f2-488e-b1c0-35426a94978d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110618457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_s w_alert_handler_lpg_sleep_mode_alerts.110618457 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2263990098 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 3447160206 ps |
| CPU time | 366.28 seconds |
| Started | Jul 12 08:24:28 PM PDT 24 |
| Finished | Jul 12 08:30:36 PM PDT 24 |
| Peak memory | 648792 kb |
| Host | smart-36618541-4b44-4e58-97c0-9fca3545dc92 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263990098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2263990098 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.19691718 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 5175478244 ps |
| CPU time | 516.37 seconds |
| Started | Jul 12 08:23:18 PM PDT 24 |
| Finished | Jul 12 08:31:55 PM PDT 24 |
| Peak memory | 617092 kb |
| Host | smart-bf8c9f80-a4b2-45e1-9ace-9625b0a8d3d4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 19691718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.19691718 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3192357946 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 3635001340 ps |
| CPU time | 470.47 seconds |
| Started | Jul 12 08:25:18 PM PDT 24 |
| Finished | Jul 12 08:33:10 PM PDT 24 |
| Peak memory | 649192 kb |
| Host | smart-470c3463-352f-4711-9da0-c09126225e95 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192357946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3192357946 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.91204931 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 3630869712 ps |
| CPU time | 333.93 seconds |
| Started | Jul 12 08:23:56 PM PDT 24 |
| Finished | Jul 12 08:29:31 PM PDT 24 |
| Peak memory | 648900 kb |
| Host | smart-a61319b6-0040-48d9-956a-8ff5fe224c12 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91204931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw _alert_handler_lpg_sleep_mode_alerts.91204931 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.203735764 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 5711816724 ps |
| CPU time | 604.9 seconds |
| Started | Jul 12 08:25:49 PM PDT 24 |
| Finished | Jul 12 08:35:54 PM PDT 24 |
| Peak memory | 650220 kb |
| Host | smart-5582e719-c5db-45d1-b7b9-81f4663188d4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 203735764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.203735764 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.1318719051 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 5543323276 ps |
| CPU time | 529.59 seconds |
| Started | Jul 12 08:22:06 PM PDT 24 |
| Finished | Jul 12 08:30:56 PM PDT 24 |
| Peak memory | 650144 kb |
| Host | smart-5130caa2-0d3e-4a2c-84ff-693133d38b38 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1318719051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.1318719051 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3758498754 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 3355272918 ps |
| CPU time | 385.41 seconds |
| Started | Jul 12 08:25:42 PM PDT 24 |
| Finished | Jul 12 08:32:09 PM PDT 24 |
| Peak memory | 648980 kb |
| Host | smart-020074ba-542d-43d2-bde1-78365f71f7be |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758498754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3758498754 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.1565074607 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 6257967672 ps |
| CPU time | 606.24 seconds |
| Started | Jul 12 08:21:51 PM PDT 24 |
| Finished | Jul 12 08:31:58 PM PDT 24 |
| Peak memory | 651432 kb |
| Host | smart-fbca2056-5fa2-4416-90ef-4cbf70357eb9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1565074607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.1565074607 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.455904448 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 3955915240 ps |
| CPU time | 380.24 seconds |
| Started | Jul 12 08:15:28 PM PDT 24 |
| Finished | Jul 12 08:21:49 PM PDT 24 |
| Peak memory | 649204 kb |
| Host | smart-29c11c66-f620-4b29-b6f9-93f78c244f17 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455904448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw _alert_handler_lpg_sleep_mode_alerts.455904448 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2036689605 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 27374256800 ps |
| CPU time | 5786.26 seconds |
| Started | Jul 12 08:16:45 PM PDT 24 |
| Finished | Jul 12 09:53:14 PM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-d7a400d5-04be-4f28-b550-3385c0ca0b1e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036689605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.2036689605 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1342165591 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 9980367785 ps |
| CPU time | 891.96 seconds |
| Started | Jul 12 08:16:33 PM PDT 24 |
| Finished | Jul 12 08:31:26 PM PDT 24 |
| Peak memory | 623332 kb |
| Host | smart-40ba78ab-f006-470f-9a91-2996c0906531 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342165591 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.1342165591 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3489543619 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 3471578236 ps |
| CPU time | 524.61 seconds |
| Started | Jul 12 08:16:41 PM PDT 24 |
| Finished | Jul 12 08:25:28 PM PDT 24 |
| Peak memory | 618876 kb |
| Host | smart-0f8881d2-5545-4686-add4-204dacd6e487 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3489543619 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.3489543619 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1695459905 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 3390178798 ps |
| CPU time | 346.14 seconds |
| Started | Jul 12 08:22:31 PM PDT 24 |
| Finished | Jul 12 08:28:18 PM PDT 24 |
| Peak memory | 648980 kb |
| Host | smart-f9b5472a-0b46-4a81-8385-59729509ac87 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695459905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1695459905 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1682610476 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 4391436988 ps |
| CPU time | 377.71 seconds |
| Started | Jul 12 08:23:00 PM PDT 24 |
| Finished | Jul 12 08:29:18 PM PDT 24 |
| Peak memory | 649224 kb |
| Host | smart-a55b9773-8f64-4c69-99b0-0b346dcd20ab |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682610476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1682610476 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.1011629330 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 5856320504 ps |
| CPU time | 654.28 seconds |
| Started | Jul 12 08:24:07 PM PDT 24 |
| Finished | Jul 12 08:35:02 PM PDT 24 |
| Peak memory | 649872 kb |
| Host | smart-6aa81250-a47a-41a7-8c75-8636c24ab552 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1011629330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.1011629330 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.4017401635 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 3298740820 ps |
| CPU time | 361.54 seconds |
| Started | Jul 12 08:21:50 PM PDT 24 |
| Finished | Jul 12 08:27:52 PM PDT 24 |
| Peak memory | 648912 kb |
| Host | smart-c7c81eaa-1bc0-4620-b40f-1d5f00a20c8b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017401635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4017401635 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.2423587982 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 5249071420 ps |
| CPU time | 501.29 seconds |
| Started | Jul 12 08:21:47 PM PDT 24 |
| Finished | Jul 12 08:30:09 PM PDT 24 |
| Peak memory | 650268 kb |
| Host | smart-1bc5416f-2856-4d62-9c53-f8b1a25e95ca |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2423587982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.2423587982 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1108300458 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 3521224920 ps |
| CPU time | 425.55 seconds |
| Started | Jul 12 08:23:04 PM PDT 24 |
| Finished | Jul 12 08:30:10 PM PDT 24 |
| Peak memory | 649176 kb |
| Host | smart-b1e23b2a-75b2-4014-9324-9e5b9644ab10 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108300458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1108300458 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.2329849928 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 5590653312 ps |
| CPU time | 628.47 seconds |
| Started | Jul 12 08:22:08 PM PDT 24 |
| Finished | Jul 12 08:32:37 PM PDT 24 |
| Peak memory | 650176 kb |
| Host | smart-76b226f4-cdcc-4c3c-8355-9049508d93e6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2329849928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.2329849928 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4135358288 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 3885286680 ps |
| CPU time | 480.02 seconds |
| Started | Jul 12 08:22:28 PM PDT 24 |
| Finished | Jul 12 08:30:29 PM PDT 24 |
| Peak memory | 648956 kb |
| Host | smart-80955edc-d169-4542-a80a-ca9b21e243c5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135358288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4135358288 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.4285594118 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 6655200882 ps |
| CPU time | 760.79 seconds |
| Started | Jul 12 08:23:58 PM PDT 24 |
| Finished | Jul 12 08:36:40 PM PDT 24 |
| Peak memory | 617100 kb |
| Host | smart-749f4649-de7c-473a-9337-8aae759f0ec0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4285594118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.4285594118 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.931266307 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 3279779572 ps |
| CPU time | 345.25 seconds |
| Started | Jul 12 08:22:30 PM PDT 24 |
| Finished | Jul 12 08:28:17 PM PDT 24 |
| Peak memory | 648968 kb |
| Host | smart-8a607625-cbaf-4936-9cce-92b0e6b5e434 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931266307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_s w_alert_handler_lpg_sleep_mode_alerts.931266307 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1373366235 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 3886666616 ps |
| CPU time | 541.73 seconds |
| Started | Jul 12 08:22:10 PM PDT 24 |
| Finished | Jul 12 08:31:13 PM PDT 24 |
| Peak memory | 648872 kb |
| Host | smart-0ba3f1dd-9131-40a4-8b60-b9a8fa50d6b1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373366235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1373366235 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.3908133946 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4883984920 ps |
| CPU time | 647.36 seconds |
| Started | Jul 12 08:22:54 PM PDT 24 |
| Finished | Jul 12 08:33:42 PM PDT 24 |
| Peak memory | 649936 kb |
| Host | smart-8e4d3295-1d0b-4a5d-8d9e-d5454ae58c84 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3908133946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.3908133946 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1369963475 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 4241533830 ps |
| CPU time | 321.42 seconds |
| Started | Jul 12 08:22:09 PM PDT 24 |
| Finished | Jul 12 08:27:31 PM PDT 24 |
| Peak memory | 649308 kb |
| Host | smart-71949dc2-5b66-4c11-bbff-a015a8cef024 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369963475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1369963475 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.2709201063 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 6302701520 ps |
| CPU time | 571.9 seconds |
| Started | Jul 12 08:24:52 PM PDT 24 |
| Finished | Jul 12 08:34:25 PM PDT 24 |
| Peak memory | 650180 kb |
| Host | smart-5ae97add-f40d-4d91-bf1a-746a7bc3f30c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2709201063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.2709201063 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2626507345 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3942377674 ps |
| CPU time | 372.4 seconds |
| Started | Jul 12 08:23:45 PM PDT 24 |
| Finished | Jul 12 08:29:58 PM PDT 24 |
| Peak memory | 649000 kb |
| Host | smart-82cf2eaa-bfcc-4e28-9ba6-b9dbe8f620da |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626507345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2626507345 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.1856376021 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 4967951400 ps |
| CPU time | 582.01 seconds |
| Started | Jul 12 08:24:47 PM PDT 24 |
| Finished | Jul 12 08:34:30 PM PDT 24 |
| Peak memory | 649940 kb |
| Host | smart-ea4c6a44-4f62-4fa4-a82e-8a164c0d5db8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1856376021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.1856376021 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.543345964 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 4467919038 ps |
| CPU time | 664.91 seconds |
| Started | Jul 12 08:16:42 PM PDT 24 |
| Finished | Jul 12 08:27:48 PM PDT 24 |
| Peak memory | 650180 kb |
| Host | smart-eab1bc8f-19c4-4de7-b6f5-3aab1d47c030 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 543345964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.543345964 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2389154534 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 8889595624 ps |
| CPU time | 1918.37 seconds |
| Started | Jul 12 08:15:53 PM PDT 24 |
| Finished | Jul 12 08:47:53 PM PDT 24 |
| Peak memory | 611044 kb |
| Host | smart-7773d620-ec86-4ba7-b151-e99ada276b17 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389154534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.2389154534 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2058098192 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 6245779731 ps |
| CPU time | 755.89 seconds |
| Started | Jul 12 08:17:39 PM PDT 24 |
| Finished | Jul 12 08:30:17 PM PDT 24 |
| Peak memory | 621720 kb |
| Host | smart-093324f3-8543-412e-91c8-44a7f2f4dc25 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058098192 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.2058098192 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2718879305 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 8315266424 ps |
| CPU time | 1703.5 seconds |
| Started | Jul 12 08:16:15 PM PDT 24 |
| Finished | Jul 12 08:44:40 PM PDT 24 |
| Peak memory | 619224 kb |
| Host | smart-00a066d4-06f0-4eb2-a429-d368dca5dfe4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2718879305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.2718879305 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.492875058 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3391824824 ps |
| CPU time | 353.92 seconds |
| Started | Jul 12 08:23:22 PM PDT 24 |
| Finished | Jul 12 08:29:16 PM PDT 24 |
| Peak memory | 648864 kb |
| Host | smart-8cb510cd-6b9c-480b-a121-7cd742be6afd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492875058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_s w_alert_handler_lpg_sleep_mode_alerts.492875058 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.1677480647 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 5034736810 ps |
| CPU time | 544.33 seconds |
| Started | Jul 12 08:23:09 PM PDT 24 |
| Finished | Jul 12 08:32:14 PM PDT 24 |
| Peak memory | 650112 kb |
| Host | smart-64545c69-0c5e-4d53-bfd9-966842377f91 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1677480647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.1677480647 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.710511454 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 3052872184 ps |
| CPU time | 334.83 seconds |
| Started | Jul 12 08:23:20 PM PDT 24 |
| Finished | Jul 12 08:28:56 PM PDT 24 |
| Peak memory | 648916 kb |
| Host | smart-cae2be93-b2e3-4da3-842c-35165836b0aa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710511454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_s w_alert_handler_lpg_sleep_mode_alerts.710511454 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.2099466797 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 6050442408 ps |
| CPU time | 596.97 seconds |
| Started | Jul 12 08:24:52 PM PDT 24 |
| Finished | Jul 12 08:34:50 PM PDT 24 |
| Peak memory | 650204 kb |
| Host | smart-839c63b4-66e1-4dea-a323-ce9a58c82e8e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2099466797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.2099466797 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1504838663 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 4423539444 ps |
| CPU time | 376.51 seconds |
| Started | Jul 12 08:23:42 PM PDT 24 |
| Finished | Jul 12 08:30:00 PM PDT 24 |
| Peak memory | 649104 kb |
| Host | smart-eae2f5f6-6010-480d-afb5-5508e1815e39 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504838663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1504838663 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.1164349333 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 5938174640 ps |
| CPU time | 695.09 seconds |
| Started | Jul 12 08:22:35 PM PDT 24 |
| Finished | Jul 12 08:34:12 PM PDT 24 |
| Peak memory | 650284 kb |
| Host | smart-50ed113c-30de-4e40-9bb9-43afe4071ab9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1164349333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.1164349333 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.26889001 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 3243757280 ps |
| CPU time | 350.59 seconds |
| Started | Jul 12 08:22:49 PM PDT 24 |
| Finished | Jul 12 08:28:40 PM PDT 24 |
| Peak memory | 648916 kb |
| Host | smart-115db842-fe49-49ab-a524-fd7fc7719e0c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26889001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw _alert_handler_lpg_sleep_mode_alerts.26889001 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3232597370 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 4290911864 ps |
| CPU time | 364.88 seconds |
| Started | Jul 12 08:24:54 PM PDT 24 |
| Finished | Jul 12 08:31:00 PM PDT 24 |
| Peak memory | 648852 kb |
| Host | smart-96d3f03b-79a0-4514-8b4c-dea469cfbd79 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232597370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3232597370 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.652031641 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 4998798744 ps |
| CPU time | 550.38 seconds |
| Started | Jul 12 08:23:59 PM PDT 24 |
| Finished | Jul 12 08:33:10 PM PDT 24 |
| Peak memory | 650376 kb |
| Host | smart-ff135ac0-f72e-409b-8e71-f2ed905a7409 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 652031641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.652031641 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3700699210 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 3781514636 ps |
| CPU time | 449.36 seconds |
| Started | Jul 12 08:22:53 PM PDT 24 |
| Finished | Jul 12 08:30:23 PM PDT 24 |
| Peak memory | 649184 kb |
| Host | smart-51707255-c823-4b08-b22e-8a31e2412c2f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700699210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3700699210 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.1754443847 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 6103258978 ps |
| CPU time | 768.19 seconds |
| Started | Jul 12 08:22:53 PM PDT 24 |
| Finished | Jul 12 08:35:43 PM PDT 24 |
| Peak memory | 650208 kb |
| Host | smart-9717a3f6-857d-4987-b813-b94e145cccce |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1754443847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.1754443847 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.399919407 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 3796593800 ps |
| CPU time | 326.39 seconds |
| Started | Jul 12 08:23:46 PM PDT 24 |
| Finished | Jul 12 08:29:13 PM PDT 24 |
| Peak memory | 619180 kb |
| Host | smart-c648b9df-5af1-4740-af7c-0681ea8934cd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399919407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_s w_alert_handler_lpg_sleep_mode_alerts.399919407 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.2437912146 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 5450784096 ps |
| CPU time | 648.67 seconds |
| Started | Jul 12 08:22:54 PM PDT 24 |
| Finished | Jul 12 08:33:44 PM PDT 24 |
| Peak memory | 650216 kb |
| Host | smart-080e4a4e-9949-4a62-95ea-52178e2be6e2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2437912146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.2437912146 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1658209891 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 4176246770 ps |
| CPU time | 390.67 seconds |
| Started | Jul 12 08:23:38 PM PDT 24 |
| Finished | Jul 12 08:30:10 PM PDT 24 |
| Peak memory | 648764 kb |
| Host | smart-fb7d7b05-9a47-403b-8122-2982690a192d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658209891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1658209891 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2541537107 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 3208409354 ps |
| CPU time | 423.3 seconds |
| Started | Jul 12 08:25:20 PM PDT 24 |
| Finished | Jul 12 08:32:24 PM PDT 24 |
| Peak memory | 649180 kb |
| Host | smart-1dd89b60-a57f-4a37-b8de-72ae99a8c1e7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541537107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2541537107 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.1786728360 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 5566009170 ps |
| CPU time | 577.76 seconds |
| Started | Jul 12 08:24:30 PM PDT 24 |
| Finished | Jul 12 08:34:09 PM PDT 24 |
| Peak memory | 650052 kb |
| Host | smart-631b2518-4ba3-4b7f-aec7-85c4f6a742e4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1786728360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.1786728360 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2271859128 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 3816207794 ps |
| CPU time | 445.45 seconds |
| Started | Jul 12 08:16:30 PM PDT 24 |
| Finished | Jul 12 08:23:56 PM PDT 24 |
| Peak memory | 648616 kb |
| Host | smart-4620480c-cf72-4558-8300-2c869c6b211c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271859128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.2271859128 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.2928745243 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 4630407230 ps |
| CPU time | 554.57 seconds |
| Started | Jul 12 08:17:04 PM PDT 24 |
| Finished | Jul 12 08:26:19 PM PDT 24 |
| Peak memory | 650220 kb |
| Host | smart-09672556-87bf-460d-b96b-de2b3f138ab0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2928745243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.2928745243 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1078969597 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 11047485214 ps |
| CPU time | 2129.65 seconds |
| Started | Jul 12 08:17:46 PM PDT 24 |
| Finished | Jul 12 08:53:16 PM PDT 24 |
| Peak memory | 610948 kb |
| Host | smart-8b5efeb9-934c-4179-a00e-faffef00d731 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078969597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.1078969597 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2218538436 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 5379810132 ps |
| CPU time | 499.74 seconds |
| Started | Jul 12 08:16:30 PM PDT 24 |
| Finished | Jul 12 08:24:51 PM PDT 24 |
| Peak memory | 621776 kb |
| Host | smart-d2f6a384-60af-4954-be8f-01d341f302ee |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218538436 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.2218538436 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1250199587 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 4419648130 ps |
| CPU time | 678.55 seconds |
| Started | Jul 12 08:16:00 PM PDT 24 |
| Finished | Jul 12 08:27:20 PM PDT 24 |
| Peak memory | 619016 kb |
| Host | smart-69b3c5e7-bce4-4a0d-8b62-232f9e140532 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1250199587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.1250199587 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.3585028624 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 5095592940 ps |
| CPU time | 483.8 seconds |
| Started | Jul 12 08:22:40 PM PDT 24 |
| Finished | Jul 12 08:30:44 PM PDT 24 |
| Peak memory | 649924 kb |
| Host | smart-02fd6651-4520-474b-b7e7-fa66d9bf8e4a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3585028624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.3585028624 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.4022164498 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 4512407756 ps |
| CPU time | 429.51 seconds |
| Started | Jul 12 08:24:14 PM PDT 24 |
| Finished | Jul 12 08:31:25 PM PDT 24 |
| Peak memory | 650416 kb |
| Host | smart-ed4ba21e-3e7d-4b2f-bcb8-72c674bf897a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4022164498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.4022164498 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.1144786354 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 5938616512 ps |
| CPU time | 785.31 seconds |
| Started | Jul 12 08:24:21 PM PDT 24 |
| Finished | Jul 12 08:37:27 PM PDT 24 |
| Peak memory | 650080 kb |
| Host | smart-c941b1a8-dd22-4969-a1a9-104a36336aca |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1144786354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.1144786354 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.2287420006 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 5259299846 ps |
| CPU time | 408.04 seconds |
| Started | Jul 12 08:23:02 PM PDT 24 |
| Finished | Jul 12 08:29:50 PM PDT 24 |
| Peak memory | 617088 kb |
| Host | smart-cdea5cfe-3c3d-4977-a285-396dd95eb741 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2287420006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.2287420006 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.3003001931 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 5011069720 ps |
| CPU time | 649.24 seconds |
| Started | Jul 12 08:23:58 PM PDT 24 |
| Finished | Jul 12 08:34:48 PM PDT 24 |
| Peak memory | 649992 kb |
| Host | smart-9e47f5fe-a51a-4c86-ba1b-801eb6b57d6c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3003001931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.3003001931 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.158695198 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 5598060192 ps |
| CPU time | 526.16 seconds |
| Started | Jul 12 08:28:50 PM PDT 24 |
| Finished | Jul 12 08:37:38 PM PDT 24 |
| Peak memory | 650640 kb |
| Host | smart-ba2779d9-c533-4c6f-8db2-62cf80795798 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 158695198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.158695198 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.1913237863 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 6216180930 ps |
| CPU time | 615.84 seconds |
| Started | Jul 12 08:23:39 PM PDT 24 |
| Finished | Jul 12 08:33:57 PM PDT 24 |
| Peak memory | 650508 kb |
| Host | smart-e3fbbcf1-1963-4da8-a245-2eabb93f4beb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1913237863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.1913237863 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.872657198 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 4916675140 ps |
| CPU time | 466.74 seconds |
| Started | Jul 12 08:28:48 PM PDT 24 |
| Finished | Jul 12 08:36:36 PM PDT 24 |
| Peak memory | 650224 kb |
| Host | smart-09f98dad-1f0e-44c9-9dfd-28a6decf834f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 872657198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.872657198 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1600151890 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 5763991608 ps |
| CPU time | 318.3 seconds |
| Started | Jul 12 08:16:52 PM PDT 24 |
| Finished | Jul 12 08:22:12 PM PDT 24 |
| Peak memory | 641424 kb |
| Host | smart-790d587d-d65a-40e9-91c4-96726ae49df2 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600151890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.1600151890 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.60541837 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 5333348844 ps |
| CPU time | 271.87 seconds |
| Started | Jul 12 08:16:47 PM PDT 24 |
| Finished | Jul 12 08:21:21 PM PDT 24 |
| Peak memory | 640664 kb |
| Host | smart-4002170d-e89c-420c-8595-80194e55c006 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60541837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/nu ll -cm_name 1.chip_padctrl_attributes.60541837 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.951468340 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 4526240454 ps |
| CPU time | 365.89 seconds |
| Started | Jul 12 08:17:19 PM PDT 24 |
| Finished | Jul 12 08:23:27 PM PDT 24 |
| Peak memory | 641468 kb |
| Host | smart-883688d7-0348-426b-bf8c-9073eb5ce9b8 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951468340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 2.chip_padctrl_attributes.951468340 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.267002418 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5409166960 ps |
| CPU time | 307.28 seconds |
| Started | Jul 12 08:16:46 PM PDT 24 |
| Finished | Jul 12 08:21:55 PM PDT 24 |
| Peak memory | 641396 kb |
| Host | smart-c7aad25b-352d-4c9c-9198-6e585745075b |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267002418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 4.chip_padctrl_attributes.267002418 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1393735202 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 4351169236 ps |
| CPU time | 329.34 seconds |
| Started | Jul 12 08:17:03 PM PDT 24 |
| Finished | Jul 12 08:22:33 PM PDT 24 |
| Peak memory | 655408 kb |
| Host | smart-62cae0a7-5a5d-4823-b515-bb2ee992c2b8 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393735202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.1393735202 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3343712073 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5014866168 ps |
| CPU time | 260.17 seconds |
| Started | Jul 12 08:16:59 PM PDT 24 |
| Finished | Jul 12 08:21:22 PM PDT 24 |
| Peak memory | 641460 kb |
| Host | smart-727ad0b7-fe1e-41c0-a3b7-db2b68580cf0 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343712073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.3343712073 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2895609645 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 5392556090 ps |
| CPU time | 313.17 seconds |
| Started | Jul 12 08:16:53 PM PDT 24 |
| Finished | Jul 12 08:22:07 PM PDT 24 |
| Peak memory | 649656 kb |
| Host | smart-acc49088-a66c-414b-b097-1d8691d603ae |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895609645 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.2895609645 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1764504416 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 6128850880 ps |
| CPU time | 352.93 seconds |
| Started | Jul 12 08:16:59 PM PDT 24 |
| Finished | Jul 12 08:22:54 PM PDT 24 |
| Peak memory | 657836 kb |
| Host | smart-e87d1ec8-780f-4fd7-a535-3566e8417831 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764504416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.1764504416 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
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