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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.18 95.58 94.06 95.46 94.88 97.53 99.58


Total test records in report: 2902
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T685 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3232597370 Jul 12 08:24:54 PM PDT 24 Jul 12 08:31:00 PM PDT 24 4290911864 ps
T1153 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3699220561 Jul 12 07:59:49 PM PDT 24 Jul 12 08:13:07 PM PDT 24 4199556774 ps
T1154 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3389976966 Jul 12 07:48:51 PM PDT 24 Jul 12 09:26:17 PM PDT 24 48472942020 ps
T1155 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2218538436 Jul 12 08:16:30 PM PDT 24 Jul 12 08:24:51 PM PDT 24 5379810132 ps
T1156 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1311642044 Jul 12 08:21:28 PM PDT 24 Jul 12 08:29:45 PM PDT 24 4422683676 ps
T1157 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2058098192 Jul 12 08:17:39 PM PDT 24 Jul 12 08:30:17 PM PDT 24 6245779731 ps
T1158 /workspace/coverage/default/2.chip_sw_aes_smoketest.1320089933 Jul 12 08:19:12 PM PDT 24 Jul 12 08:24:45 PM PDT 24 3521178848 ps
T1159 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3228243656 Jul 12 07:50:19 PM PDT 24 Jul 12 07:52:52 PM PDT 24 2670022034 ps
T1160 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3737005831 Jul 12 07:52:34 PM PDT 24 Jul 12 08:00:40 PM PDT 24 3925094624 ps
T1161 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1565799655 Jul 12 08:11:20 PM PDT 24 Jul 12 08:24:10 PM PDT 24 4497676220 ps
T1162 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2898080045 Jul 12 07:48:34 PM PDT 24 Jul 12 07:51:26 PM PDT 24 3515620294 ps
T1163 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2333960553 Jul 12 08:13:35 PM PDT 24 Jul 12 08:32:20 PM PDT 24 7901285962 ps
T356 /workspace/coverage/default/18.chip_sw_all_escalation_resets.347609213 Jul 12 08:17:46 PM PDT 24 Jul 12 08:26:59 PM PDT 24 4015804770 ps
T1164 /workspace/coverage/default/2.chip_sw_gpio_smoketest.3316947021 Jul 12 08:12:32 PM PDT 24 Jul 12 08:18:40 PM PDT 24 3233894308 ps
T1165 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3157077900 Jul 12 08:13:53 PM PDT 24 Jul 12 08:26:29 PM PDT 24 4610500400 ps
T1166 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.680437926 Jul 12 08:14:43 PM PDT 24 Jul 12 09:34:45 PM PDT 24 23476814912 ps
T65 /workspace/coverage/default/3.chip_tap_straps_testunlock0.2371864787 Jul 12 08:13:56 PM PDT 24 Jul 12 08:23:06 PM PDT 24 5373425015 ps
T1167 /workspace/coverage/default/2.chip_sw_aes_enc.1446835955 Jul 12 08:07:23 PM PDT 24 Jul 12 08:11:41 PM PDT 24 3231032168 ps
T34 /workspace/coverage/default/0.chip_sw_usbdev_stream.3537184913 Jul 12 07:49:26 PM PDT 24 Jul 12 09:01:43 PM PDT 24 18211072312 ps
T1168 /workspace/coverage/default/36.chip_sw_all_escalation_resets.3601622992 Jul 12 08:20:00 PM PDT 24 Jul 12 08:32:34 PM PDT 24 4956048216 ps
T1169 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.126082688 Jul 12 07:47:59 PM PDT 24 Jul 12 07:58:09 PM PDT 24 4389534250 ps
T1170 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3226994866 Jul 12 07:59:35 PM PDT 24 Jul 12 08:07:03 PM PDT 24 3650896684 ps
T43 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.677375733 Jul 12 07:47:36 PM PDT 24 Jul 12 07:51:51 PM PDT 24 3138418640 ps
T157 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2615813702 Jul 12 07:58:17 PM PDT 24 Jul 12 08:20:58 PM PDT 24 11978072368 ps
T1171 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2625086927 Jul 12 07:56:22 PM PDT 24 Jul 12 08:00:16 PM PDT 24 2933546002 ps
T1172 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.830972893 Jul 12 08:05:54 PM PDT 24 Jul 12 09:07:42 PM PDT 24 14422097246 ps
T1173 /workspace/coverage/default/2.chip_sival_flash_info_access.4277275548 Jul 12 08:03:50 PM PDT 24 Jul 12 08:10:08 PM PDT 24 3183098344 ps
T1174 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.172192270 Jul 12 08:09:51 PM PDT 24 Jul 12 08:35:24 PM PDT 24 8065995206 ps
T1175 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3454592210 Jul 12 07:48:38 PM PDT 24 Jul 12 07:53:53 PM PDT 24 2975645532 ps
T739 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1373366235 Jul 12 08:22:10 PM PDT 24 Jul 12 08:31:13 PM PDT 24 3886666616 ps
T1176 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.311067899 Jul 12 08:17:31 PM PDT 24 Jul 12 08:28:45 PM PDT 24 4300436856 ps
T1177 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.835350599 Jul 12 07:48:53 PM PDT 24 Jul 12 08:06:59 PM PDT 24 9310532600 ps
T1178 /workspace/coverage/default/75.chip_sw_all_escalation_resets.4285594118 Jul 12 08:23:58 PM PDT 24 Jul 12 08:36:40 PM PDT 24 6655200882 ps
T256 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.32960734 Jul 12 07:55:44 PM PDT 24 Jul 12 08:06:34 PM PDT 24 5079672336 ps
T1179 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2389154534 Jul 12 08:15:53 PM PDT 24 Jul 12 08:47:53 PM PDT 24 8889595624 ps
T1180 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.577967707 Jul 12 07:57:04 PM PDT 24 Jul 12 08:03:43 PM PDT 24 7106622690 ps
T230 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1026241942 Jul 12 07:49:21 PM PDT 24 Jul 12 08:19:04 PM PDT 24 7534212488 ps
T1181 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3845689381 Jul 12 07:50:16 PM PDT 24 Jul 12 07:59:25 PM PDT 24 4835388315 ps
T1182 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3473545242 Jul 12 07:47:15 PM PDT 24 Jul 12 07:51:54 PM PDT 24 2633692852 ps
T1183 /workspace/coverage/default/22.chip_sw_all_escalation_resets.100395513 Jul 12 08:19:33 PM PDT 24 Jul 12 08:29:37 PM PDT 24 4732400216 ps
T1184 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.746022156 Jul 12 07:58:11 PM PDT 24 Jul 12 08:31:09 PM PDT 24 7989891636 ps
T755 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.110618457 Jul 12 08:23:23 PM PDT 24 Jul 12 08:30:12 PM PDT 24 3484195772 ps
T1185 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2965727549 Jul 12 08:12:20 PM PDT 24 Jul 12 09:15:06 PM PDT 24 24789250247 ps
T1186 /workspace/coverage/default/3.chip_tap_straps_prod.565255203 Jul 12 08:13:42 PM PDT 24 Jul 12 08:33:35 PM PDT 24 12832334663 ps
T639 /workspace/coverage/default/0.rom_raw_unlock.4284101994 Jul 12 07:53:03 PM PDT 24 Jul 12 07:57:42 PM PDT 24 6032910825 ps
T1187 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3962559885 Jul 12 07:49:03 PM PDT 24 Jul 12 07:58:34 PM PDT 24 5301059940 ps
T689 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.4174256890 Jul 12 08:21:42 PM PDT 24 Jul 12 08:27:48 PM PDT 24 3848885410 ps
T1188 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.695919168 Jul 12 08:20:16 PM PDT 24 Jul 12 08:26:48 PM PDT 24 4178812872 ps
T1189 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3271891680 Jul 12 08:14:21 PM PDT 24 Jul 12 08:39:42 PM PDT 24 7894331290 ps
T740 /workspace/coverage/default/92.chip_sw_all_escalation_resets.1144786354 Jul 12 08:24:21 PM PDT 24 Jul 12 08:37:27 PM PDT 24 5938616512 ps
T1190 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2751996576 Jul 12 07:48:37 PM PDT 24 Jul 12 07:58:50 PM PDT 24 5841447150 ps
T357 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.91204931 Jul 12 08:23:56 PM PDT 24 Jul 12 08:29:31 PM PDT 24 3630869712 ps
T1191 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1768777207 Jul 12 07:47:17 PM PDT 24 Jul 12 08:18:40 PM PDT 24 7779335702 ps
T1192 /workspace/coverage/default/10.chip_sw_all_escalation_resets.186342973 Jul 12 08:17:33 PM PDT 24 Jul 12 08:29:32 PM PDT 24 6314483496 ps
T1193 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2248642318 Jul 12 08:13:31 PM PDT 24 Jul 12 08:17:59 PM PDT 24 3412418392 ps
T1194 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2240094482 Jul 12 07:55:49 PM PDT 24 Jul 12 08:02:18 PM PDT 24 3964593628 ps
T1195 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1710967863 Jul 12 07:50:20 PM PDT 24 Jul 12 09:27:55 PM PDT 24 48939257120 ps
T1196 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.909309671 Jul 12 07:59:43 PM PDT 24 Jul 12 08:10:38 PM PDT 24 6339616255 ps
T391 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.494276005 Jul 12 08:00:49 PM PDT 24 Jul 12 08:07:10 PM PDT 24 7055913280 ps
T257 /workspace/coverage/default/64.chip_sw_all_escalation_resets.2457236426 Jul 12 08:21:28 PM PDT 24 Jul 12 08:31:07 PM PDT 24 6403788158 ps
T164 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2320622452 Jul 12 07:47:46 PM PDT 24 Jul 12 07:51:52 PM PDT 24 2922163104 ps
T66 /workspace/coverage/default/2.chip_tap_straps_testunlock0.3533677348 Jul 12 08:10:07 PM PDT 24 Jul 12 08:17:54 PM PDT 24 4505925859 ps
T1197 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1285297900 Jul 12 07:55:03 PM PDT 24 Jul 12 08:39:37 PM PDT 24 26772795175 ps
T1198 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.503975533 Jul 12 07:54:43 PM PDT 24 Jul 12 08:10:23 PM PDT 24 6925672193 ps
T1199 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3031697803 Jul 12 07:48:42 PM PDT 24 Jul 12 08:32:25 PM PDT 24 11105313434 ps
T1200 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.222269520 Jul 12 07:56:46 PM PDT 24 Jul 12 08:52:52 PM PDT 24 14763287020 ps
T1201 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.289976999 Jul 12 08:04:14 PM PDT 24 Jul 12 08:08:09 PM PDT 24 2735938840 ps
T1202 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1281834472 Jul 12 08:17:24 PM PDT 24 Jul 12 09:02:35 PM PDT 24 10948597752 ps
T396 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3419627420 Jul 12 07:51:57 PM PDT 24 Jul 12 08:00:28 PM PDT 24 4508215352 ps
T1203 /workspace/coverage/default/2.chip_sw_power_idle_load.479881665 Jul 12 08:13:17 PM PDT 24 Jul 12 08:23:37 PM PDT 24 4853685500 ps
T1204 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.4033552199 Jul 12 08:17:11 PM PDT 24 Jul 12 08:26:31 PM PDT 24 4581208840 ps
T1205 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.684897662 Jul 12 07:58:17 PM PDT 24 Jul 12 08:55:20 PM PDT 24 11418461944 ps
T746 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2961359681 Jul 12 08:21:25 PM PDT 24 Jul 12 08:27:26 PM PDT 24 3410015296 ps
T1206 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1767998427 Jul 12 07:49:51 PM PDT 24 Jul 12 07:58:36 PM PDT 24 7166956729 ps
T1207 /workspace/coverage/default/0.chip_sw_csrng_kat_test.3197027302 Jul 12 07:49:44 PM PDT 24 Jul 12 07:53:09 PM PDT 24 2613629422 ps
T1208 /workspace/coverage/default/74.chip_sw_all_escalation_resets.2329849928 Jul 12 08:22:08 PM PDT 24 Jul 12 08:32:37 PM PDT 24 5590653312 ps
T186 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.502333636 Jul 12 07:48:10 PM PDT 24 Jul 12 09:22:47 PM PDT 24 43459511289 ps
T1209 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2886334920 Jul 12 08:03:44 PM PDT 24 Jul 12 08:11:54 PM PDT 24 3689731960 ps
T1210 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1251326409 Jul 12 08:12:51 PM PDT 24 Jul 12 08:45:56 PM PDT 24 28578232260 ps
T1211 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1623085230 Jul 12 07:56:33 PM PDT 24 Jul 12 08:11:17 PM PDT 24 6445257728 ps
T128 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.427334183 Jul 12 08:12:42 PM PDT 24 Jul 12 08:21:43 PM PDT 24 5877622504 ps
T1212 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.929905270 Jul 12 07:55:02 PM PDT 24 Jul 12 08:19:22 PM PDT 24 14907953831 ps
T1213 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1250199587 Jul 12 08:16:00 PM PDT 24 Jul 12 08:27:20 PM PDT 24 4419648130 ps
T1214 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1726199019 Jul 12 07:52:58 PM PDT 24 Jul 12 07:56:58 PM PDT 24 3343386797 ps
T314 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3648847390 Jul 12 07:55:23 PM PDT 24 Jul 12 08:26:55 PM PDT 24 12390377100 ps
T1215 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1219802078 Jul 12 08:09:59 PM PDT 24 Jul 12 08:24:59 PM PDT 24 8213303382 ps
T1216 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.4131873053 Jul 12 07:54:52 PM PDT 24 Jul 12 08:03:20 PM PDT 24 8544342932 ps
T1217 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1222861198 Jul 12 07:50:17 PM PDT 24 Jul 12 07:58:49 PM PDT 24 6951069800 ps
T1218 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.848268232 Jul 12 08:03:55 PM PDT 24 Jul 12 08:19:24 PM PDT 24 4689330040 ps
T1219 /workspace/coverage/default/65.chip_sw_all_escalation_resets.19691718 Jul 12 08:23:18 PM PDT 24 Jul 12 08:31:55 PM PDT 24 5175478244 ps
T1220 /workspace/coverage/default/23.chip_sw_all_escalation_resets.880927587 Jul 12 08:18:54 PM PDT 24 Jul 12 08:28:15 PM PDT 24 5567471220 ps
T1221 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.669654266 Jul 12 07:57:32 PM PDT 24 Jul 12 08:06:57 PM PDT 24 5758590440 ps
T649 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3700699210 Jul 12 08:22:53 PM PDT 24 Jul 12 08:30:23 PM PDT 24 3781514636 ps
T1222 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.787819309 Jul 12 07:59:53 PM PDT 24 Jul 12 08:03:36 PM PDT 24 3075699873 ps
T143 /workspace/coverage/default/0.chip_sw_usbdev_dpi.865099196 Jul 12 07:48:20 PM PDT 24 Jul 12 08:37:18 PM PDT 24 12139541002 ps
T1223 /workspace/coverage/default/0.chip_sw_kmac_idle.1806143727 Jul 12 07:49:55 PM PDT 24 Jul 12 07:54:11 PM PDT 24 2676470446 ps
T92 /workspace/coverage/default/4.chip_sw_all_escalation_resets.2138735333 Jul 12 08:14:54 PM PDT 24 Jul 12 08:24:06 PM PDT 24 5383387496 ps
T1224 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3756530933 Jul 12 07:52:59 PM PDT 24 Jul 12 08:36:32 PM PDT 24 11574311352 ps
T1225 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2930500806 Jul 12 07:53:11 PM PDT 24 Jul 12 08:18:12 PM PDT 24 8033159969 ps
T21 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1476683756 Jul 12 07:50:49 PM PDT 24 Jul 12 07:57:30 PM PDT 24 2950294158 ps
T1226 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.3116361282 Jul 12 08:00:46 PM PDT 24 Jul 12 08:19:39 PM PDT 24 6881818970 ps
T1227 /workspace/coverage/default/0.rom_e2e_asm_init_prod.374790958 Jul 12 07:54:34 PM PDT 24 Jul 12 08:57:14 PM PDT 24 16172499580 ps
T1228 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3908735190 Jul 12 07:49:40 PM PDT 24 Jul 12 08:15:31 PM PDT 24 8471914832 ps
T1229 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1817236598 Jul 12 08:07:18 PM PDT 24 Jul 12 09:10:52 PM PDT 24 14801770554 ps
T1230 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.4249301131 Jul 12 07:57:22 PM PDT 24 Jul 12 08:10:07 PM PDT 24 5100697768 ps
T246 /workspace/coverage/default/38.chip_sw_all_escalation_resets.1542833116 Jul 12 08:19:30 PM PDT 24 Jul 12 08:28:17 PM PDT 24 4032968150 ps
T756 /workspace/coverage/default/28.chip_sw_all_escalation_resets.4106774188 Jul 12 08:19:09 PM PDT 24 Jul 12 08:34:03 PM PDT 24 4627890534 ps
T134 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.473929318 Jul 12 07:54:14 PM PDT 24 Jul 12 08:10:35 PM PDT 24 8561764784 ps
T1231 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3953189802 Jul 12 08:11:05 PM PDT 24 Jul 12 08:21:38 PM PDT 24 5514468937 ps
T1232 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1587282705 Jul 12 08:07:16 PM PDT 24 Jul 12 09:27:49 PM PDT 24 49711859403 ps
T1233 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1802303453 Jul 12 07:48:01 PM PDT 24 Jul 12 07:59:15 PM PDT 24 3536635442 ps
T1234 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2974015839 Jul 12 08:13:59 PM PDT 24 Jul 12 08:24:34 PM PDT 24 6631838240 ps
T1235 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2010305987 Jul 12 08:12:34 PM PDT 24 Jul 12 08:19:07 PM PDT 24 3429736504 ps
T324 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1352667884 Jul 12 08:11:06 PM PDT 24 Jul 12 08:19:34 PM PDT 24 3120121716 ps
T710 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2712922121 Jul 12 08:19:15 PM PDT 24 Jul 12 08:26:57 PM PDT 24 3807237632 ps
T190 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3048252915 Jul 12 08:12:25 PM PDT 24 Jul 12 08:29:43 PM PDT 24 9729814875 ps
T1236 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.347907053 Jul 12 07:48:20 PM PDT 24 Jul 12 08:01:14 PM PDT 24 3966830680 ps
T1237 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3489543619 Jul 12 08:16:41 PM PDT 24 Jul 12 08:25:28 PM PDT 24 3471578236 ps
T1238 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.626818428 Jul 12 08:08:46 PM PDT 24 Jul 12 08:31:05 PM PDT 24 8375258116 ps
T642 /workspace/coverage/default/2.chip_sw_pattgen_ios.4225426296 Jul 12 08:04:06 PM PDT 24 Jul 12 08:09:06 PM PDT 24 2963272152 ps
T1239 /workspace/coverage/default/45.chip_sw_all_escalation_resets.843775646 Jul 12 08:20:25 PM PDT 24 Jul 12 08:31:16 PM PDT 24 4928867240 ps
T1240 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1699122518 Jul 12 07:48:02 PM PDT 24 Jul 12 08:05:51 PM PDT 24 6132465572 ps
T206 /workspace/coverage/default/0.chip_jtag_mem_access.2924772853 Jul 12 07:41:37 PM PDT 24 Jul 12 08:04:55 PM PDT 24 13792144360 ps
T1241 /workspace/coverage/default/1.rom_e2e_asm_init_dev.4273151622 Jul 12 08:05:51 PM PDT 24 Jul 12 09:21:17 PM PDT 24 15214143166 ps
T354 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3193546957 Jul 12 08:00:31 PM PDT 24 Jul 12 08:06:42 PM PDT 24 6324785242 ps
T1242 /workspace/coverage/default/2.chip_sw_plic_sw_irq.2329832404 Jul 12 08:15:07 PM PDT 24 Jul 12 08:20:33 PM PDT 24 2820743296 ps
T1243 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.607007615 Jul 12 08:12:06 PM PDT 24 Jul 12 08:32:28 PM PDT 24 7418147809 ps
T315 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2722904861 Jul 12 08:05:55 PM PDT 24 Jul 12 08:37:26 PM PDT 24 11631567288 ps
T1244 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1500000360 Jul 12 07:49:13 PM PDT 24 Jul 12 07:56:05 PM PDT 24 3800374866 ps
T191 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1759212841 Jul 12 07:58:40 PM PDT 24 Jul 12 08:14:14 PM PDT 24 9808980600 ps
T1245 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3428959645 Jul 12 08:12:55 PM PDT 24 Jul 12 08:19:07 PM PDT 24 5895805296 ps
T1246 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2001763136 Jul 12 08:01:50 PM PDT 24 Jul 12 08:16:46 PM PDT 24 7627778291 ps
T1247 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1024824148 Jul 12 08:18:38 PM PDT 24 Jul 12 08:26:44 PM PDT 24 3923140600 ps
T1248 /workspace/coverage/default/59.chip_sw_all_escalation_resets.2880185742 Jul 12 08:20:52 PM PDT 24 Jul 12 08:29:44 PM PDT 24 4833704152 ps
T1249 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2242554495 Jul 12 07:51:10 PM PDT 24 Jul 12 07:58:03 PM PDT 24 3980304750 ps
T1250 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.4238504593 Jul 12 07:56:53 PM PDT 24 Jul 12 08:36:17 PM PDT 24 12378003795 ps
T1251 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2036689605 Jul 12 08:16:45 PM PDT 24 Jul 12 09:53:14 PM PDT 24 27374256800 ps
T1252 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3359044661 Jul 12 08:08:40 PM PDT 24 Jul 12 09:23:05 PM PDT 24 23520112520 ps
T305 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3342976189 Jul 12 08:18:52 PM PDT 24 Jul 12 08:26:29 PM PDT 24 3340034660 ps
T1253 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3784629915 Jul 12 07:48:49 PM PDT 24 Jul 12 07:57:07 PM PDT 24 4896634326 ps
T690 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.4017401635 Jul 12 08:21:50 PM PDT 24 Jul 12 08:27:52 PM PDT 24 3298740820 ps
T1254 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.893522656 Jul 12 08:15:03 PM PDT 24 Jul 12 08:19:21 PM PDT 24 3160120500 ps
T1255 /workspace/coverage/default/4.chip_tap_straps_testunlock0.3978166084 Jul 12 08:15:20 PM PDT 24 Jul 12 08:24:17 PM PDT 24 6244045279 ps
T610 /workspace/coverage/default/1.chip_sw_edn_boot_mode.3278666173 Jul 12 08:03:32 PM PDT 24 Jul 12 08:12:53 PM PDT 24 3298493598 ps
T1256 /workspace/coverage/default/55.chip_sw_all_escalation_resets.287483318 Jul 12 08:21:52 PM PDT 24 Jul 12 08:30:08 PM PDT 24 4153421246 ps
T1257 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.44123815 Jul 12 07:56:38 PM PDT 24 Jul 12 09:12:38 PM PDT 24 14191947422 ps
T1258 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.2313663134 Jul 12 07:50:49 PM PDT 24 Jul 12 08:04:40 PM PDT 24 7478110190 ps
T48 /workspace/coverage/default/1.chip_sw_spi_device_tpm.60982573 Jul 12 07:54:10 PM PDT 24 Jul 12 07:59:04 PM PDT 24 3476384233 ps
T232 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1102673430 Jul 12 08:09:08 PM PDT 24 Jul 12 09:20:02 PM PDT 24 14286354226 ps
T1259 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2897925754 Jul 12 07:51:10 PM PDT 24 Jul 12 08:28:08 PM PDT 24 8014154560 ps
T1260 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1067868490 Jul 12 08:13:54 PM PDT 24 Jul 12 08:21:43 PM PDT 24 5096441784 ps
T1261 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.48480772 Jul 12 08:08:50 PM PDT 24 Jul 12 08:13:14 PM PDT 24 2425849584 ps
T1262 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.63727424 Jul 12 07:50:37 PM PDT 24 Jul 12 07:56:34 PM PDT 24 3074441098 ps
T1263 /workspace/coverage/default/1.chip_sw_aes_masking_off.989476008 Jul 12 07:57:27 PM PDT 24 Jul 12 08:01:38 PM PDT 24 2889235213 ps
T1264 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.593769375 Jul 12 08:02:27 PM PDT 24 Jul 12 08:23:09 PM PDT 24 9540004472 ps
T1265 /workspace/coverage/default/1.chip_sw_aon_timer_irq.3866504122 Jul 12 07:57:11 PM PDT 24 Jul 12 08:03:45 PM PDT 24 3431765220 ps
T129 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.913634285 Jul 12 07:50:52 PM PDT 24 Jul 12 07:57:22 PM PDT 24 4771894222 ps
T1266 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.613528219 Jul 12 08:09:46 PM PDT 24 Jul 12 08:45:01 PM PDT 24 9492629674 ps
T1267 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.2724020294 Jul 12 07:55:07 PM PDT 24 Jul 12 11:19:58 PM PDT 24 64917306448 ps
T1268 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1671842295 Jul 12 07:59:09 PM PDT 24 Jul 12 08:09:40 PM PDT 24 7837442120 ps
T1269 /workspace/coverage/default/2.chip_sw_kmac_idle.1377158996 Jul 12 08:09:17 PM PDT 24 Jul 12 08:15:09 PM PDT 24 3072960752 ps
T688 /workspace/coverage/default/68.chip_sw_all_escalation_resets.1318719051 Jul 12 08:22:06 PM PDT 24 Jul 12 08:30:56 PM PDT 24 5543323276 ps
T1270 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1325388151 Jul 12 07:55:15 PM PDT 24 Jul 12 08:12:43 PM PDT 24 8963350057 ps
T1271 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.750391972 Jul 12 07:47:14 PM PDT 24 Jul 12 08:13:55 PM PDT 24 7739954414 ps
T1272 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2901270744 Jul 12 07:54:58 PM PDT 24 Jul 12 07:59:29 PM PDT 24 2387434192 ps
T643 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3449280877 Jul 12 07:51:21 PM PDT 24 Jul 12 08:24:47 PM PDT 24 10925278148 ps
T1273 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3758498754 Jul 12 08:25:42 PM PDT 24 Jul 12 08:32:09 PM PDT 24 3355272918 ps
T1274 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2166223783 Jul 12 07:51:39 PM PDT 24 Jul 12 07:57:50 PM PDT 24 4458268710 ps
T1275 /workspace/coverage/default/4.chip_tap_straps_rma.3368160707 Jul 12 08:15:16 PM PDT 24 Jul 12 08:19:06 PM PDT 24 2916358872 ps
T1276 /workspace/coverage/default/0.chip_sw_uart_smoketest.51256210 Jul 12 07:52:05 PM PDT 24 Jul 12 07:56:25 PM PDT 24 3162182748 ps
T1277 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2586973687 Jul 12 07:53:16 PM PDT 24 Jul 12 08:39:22 PM PDT 24 28546794660 ps
T719 /workspace/coverage/default/47.chip_sw_all_escalation_resets.3147528244 Jul 12 08:20:31 PM PDT 24 Jul 12 08:31:37 PM PDT 24 4662630232 ps
T1278 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.979600430 Jul 12 07:50:16 PM PDT 24 Jul 12 08:02:49 PM PDT 24 5084011080 ps
T1279 /workspace/coverage/default/1.chip_sw_hmac_enc.2136233912 Jul 12 07:57:24 PM PDT 24 Jul 12 08:02:09 PM PDT 24 2869823820 ps
T725 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.42877510 Jul 12 08:22:41 PM PDT 24 Jul 12 08:30:00 PM PDT 24 3379584602 ps
T1280 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2544188349 Jul 12 07:59:39 PM PDT 24 Jul 12 09:29:38 PM PDT 24 17907285160 ps
T1281 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3732769110 Jul 12 08:06:10 PM PDT 24 Jul 12 09:06:46 PM PDT 24 15157009531 ps
T1282 /workspace/coverage/default/58.chip_sw_all_escalation_resets.71827994 Jul 12 08:21:31 PM PDT 24 Jul 12 08:30:29 PM PDT 24 5556736700 ps
T1283 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2307258800 Jul 12 08:05:27 PM PDT 24 Jul 12 08:31:03 PM PDT 24 9588518264 ps
T1284 /workspace/coverage/default/0.chip_sw_aes_entropy.1878260505 Jul 12 07:51:22 PM PDT 24 Jul 12 07:56:41 PM PDT 24 3301308664 ps
T1285 /workspace/coverage/default/1.chip_sw_power_sleep_load.3038730504 Jul 12 08:02:01 PM PDT 24 Jul 12 08:13:15 PM PDT 24 10545052808 ps
T1286 /workspace/coverage/default/1.chip_sw_edn_kat.2275231969 Jul 12 07:59:10 PM PDT 24 Jul 12 08:13:20 PM PDT 24 3151886042 ps
T1287 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.420934662 Jul 12 08:17:56 PM PDT 24 Jul 12 08:25:36 PM PDT 24 6403621340 ps
T1288 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3766753423 Jul 12 08:10:12 PM PDT 24 Jul 12 08:20:01 PM PDT 24 4033403272 ps
T203 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.1943638893 Jul 12 07:54:21 PM PDT 24 Jul 12 08:10:09 PM PDT 24 8120342477 ps
T1289 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2110179495 Jul 12 07:47:57 PM PDT 24 Jul 12 08:12:54 PM PDT 24 8735388640 ps
T1290 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1883079684 Jul 12 08:19:10 PM PDT 24 Jul 12 09:24:52 PM PDT 24 15005685864 ps
T1291 /workspace/coverage/default/1.chip_sw_hmac_oneshot.3158124047 Jul 12 08:03:02 PM PDT 24 Jul 12 08:07:54 PM PDT 24 2630338040 ps
T696 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1369963475 Jul 12 08:22:09 PM PDT 24 Jul 12 08:27:31 PM PDT 24 4241533830 ps
T1292 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2570079062 Jul 12 07:47:18 PM PDT 24 Jul 12 07:58:14 PM PDT 24 3464102740 ps
T1293 /workspace/coverage/default/26.chip_sw_all_escalation_resets.3038551334 Jul 12 08:18:48 PM PDT 24 Jul 12 08:29:50 PM PDT 24 4580285236 ps
T1294 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1783036529 Jul 12 08:13:13 PM PDT 24 Jul 12 08:16:55 PM PDT 24 2816660294 ps
T1295 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3558221054 Jul 12 08:00:47 PM PDT 24 Jul 12 08:10:59 PM PDT 24 6282463984 ps
T1296 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3879329788 Jul 12 08:04:12 PM PDT 24 Jul 12 08:21:41 PM PDT 24 5518933404 ps
T1297 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2880084062 Jul 12 08:19:59 PM PDT 24 Jul 12 08:26:55 PM PDT 24 3885580984 ps
T1298 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1472364281 Jul 12 07:55:51 PM PDT 24 Jul 12 11:18:32 PM PDT 24 256158880476 ps
T1299 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3274675474 Jul 12 07:49:12 PM PDT 24 Jul 12 08:20:55 PM PDT 24 16978972149 ps
T1300 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1726396721 Jul 12 07:53:46 PM PDT 24 Jul 12 07:58:18 PM PDT 24 2778864230 ps
T1301 /workspace/coverage/default/44.chip_sw_all_escalation_resets.4282454551 Jul 12 08:20:19 PM PDT 24 Jul 12 08:30:02 PM PDT 24 5002695672 ps
T1302 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.476326614 Jul 12 08:00:54 PM PDT 24 Jul 12 08:07:30 PM PDT 24 4558720458 ps
T1303 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2817977089 Jul 12 07:56:33 PM PDT 24 Jul 12 08:08:00 PM PDT 24 8037318744 ps
T297 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.537534659 Jul 12 07:48:42 PM PDT 24 Jul 12 07:52:26 PM PDT 24 3133868650 ps
T215 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.742398492 Jul 12 08:03:38 PM PDT 24 Jul 12 08:07:56 PM PDT 24 3043611148 ps
T1304 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2718879305 Jul 12 08:16:15 PM PDT 24 Jul 12 08:44:40 PM PDT 24 8315266424 ps
T1305 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3703207641 Jul 12 08:09:34 PM PDT 24 Jul 12 08:15:48 PM PDT 24 2832092843 ps
T1306 /workspace/coverage/default/2.chip_sw_aon_timer_irq.3298653866 Jul 12 08:08:25 PM PDT 24 Jul 12 08:17:28 PM PDT 24 3936234440 ps
T1307 /workspace/coverage/default/1.chip_sw_kmac_idle.1543638272 Jul 12 07:58:51 PM PDT 24 Jul 12 08:04:24 PM PDT 24 2730091344 ps
T1308 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1613091764 Jul 12 08:18:36 PM PDT 24 Jul 12 08:36:19 PM PDT 24 9922356964 ps
T1309 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2895800937 Jul 12 07:50:25 PM PDT 24 Jul 12 08:11:24 PM PDT 24 11292376376 ps
T392 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1089163297 Jul 12 07:50:08 PM PDT 24 Jul 12 07:57:03 PM PDT 24 7250127292 ps
T652 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3771414271 Jul 12 08:21:02 PM PDT 24 Jul 12 08:27:53 PM PDT 24 3996046600 ps
T747 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3778770845 Jul 12 08:19:33 PM PDT 24 Jul 12 08:28:45 PM PDT 24 3177563036 ps
T1310 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.411347928 Jul 12 08:03:05 PM PDT 24 Jul 12 08:13:38 PM PDT 24 3891130280 ps
T687 /workspace/coverage/default/30.chip_sw_all_escalation_resets.3305558160 Jul 12 08:18:45 PM PDT 24 Jul 12 08:27:59 PM PDT 24 4860162640 ps
T1311 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.445566092 Jul 12 08:08:42 PM PDT 24 Jul 12 08:27:43 PM PDT 24 5714375056 ps
T49 /workspace/coverage/default/2.chip_sw_spi_device_tpm.1908503108 Jul 12 08:05:54 PM PDT 24 Jul 12 08:14:21 PM PDT 24 3551720969 ps
T1312 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.452108901 Jul 12 08:20:09 PM PDT 24 Jul 12 08:29:21 PM PDT 24 4423409600 ps
T1313 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3421998447 Jul 12 08:06:12 PM PDT 24 Jul 12 08:36:27 PM PDT 24 9984512066 ps
T744 /workspace/coverage/default/1.chip_sw_all_escalation_resets.2749153695 Jul 12 07:52:17 PM PDT 24 Jul 12 08:04:25 PM PDT 24 4389921824 ps
T1314 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.910886711 Jul 12 07:54:35 PM PDT 24 Jul 12 08:05:51 PM PDT 24 5280068104 ps
T1315 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.855657804 Jul 12 07:55:05 PM PDT 24 Jul 12 08:57:16 PM PDT 24 13681397522 ps
T313 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3951074203 Jul 12 07:47:56 PM PDT 24 Jul 12 08:20:14 PM PDT 24 13348739072 ps
T501 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.932197332 Jul 12 07:49:30 PM PDT 24 Jul 12 08:03:22 PM PDT 24 4905254314 ps
T1316 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1854963726 Jul 12 08:20:50 PM PDT 24 Jul 12 08:26:39 PM PDT 24 4337355528 ps
T1317 /workspace/coverage/default/1.chip_tap_straps_testunlock0.4094026312 Jul 12 07:59:46 PM PDT 24 Jul 12 08:01:53 PM PDT 24 2011475980 ps
T1318 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.520437642 Jul 12 07:48:22 PM PDT 24 Jul 12 07:53:14 PM PDT 24 3592898583 ps
T758 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.807709232 Jul 12 08:18:23 PM PDT 24 Jul 12 08:25:16 PM PDT 24 4400490196 ps
T637 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1463960074 Jul 12 07:57:42 PM PDT 24 Jul 12 08:13:25 PM PDT 24 5189503646 ps
T1319 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1507633576 Jul 12 07:52:56 PM PDT 24 Jul 12 08:03:27 PM PDT 24 4659828600 ps
T1320 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2823979855 Jul 12 07:47:40 PM PDT 24 Jul 12 07:57:24 PM PDT 24 4071980064 ps
T1321 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3458264116 Jul 12 07:47:07 PM PDT 24 Jul 12 08:01:59 PM PDT 24 4736309240 ps
T1322 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.373540720 Jul 12 08:15:29 PM PDT 24 Jul 12 08:33:07 PM PDT 24 7427050474 ps
T711 /workspace/coverage/default/19.chip_sw_all_escalation_resets.2343317002 Jul 12 08:17:01 PM PDT 24 Jul 12 08:32:23 PM PDT 24 4463022500 ps
T1323 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2284645986 Jul 12 07:55:36 PM PDT 24 Jul 12 08:16:46 PM PDT 24 8268057336 ps
T1324 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1058542922 Jul 12 08:16:53 PM PDT 24 Jul 12 08:26:31 PM PDT 24 4352661050 ps
T258 /workspace/coverage/default/86.chip_sw_all_escalation_resets.3355189084 Jul 12 08:23:09 PM PDT 24 Jul 12 08:32:49 PM PDT 24 6219432500 ps
T1325 /workspace/coverage/default/0.rom_e2e_shutdown_output.2223479922 Jul 12 07:55:27 PM PDT 24 Jul 12 08:51:50 PM PDT 24 23284017513 ps
T1326 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2485684156 Jul 12 08:12:08 PM PDT 24 Jul 12 08:15:02 PM PDT 24 2762753033 ps
T1327 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1811869528 Jul 12 08:10:08 PM PDT 24 Jul 12 08:14:31 PM PDT 24 2660540454 ps
T1328 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2164811658 Jul 12 08:11:20 PM PDT 24 Jul 12 08:31:55 PM PDT 24 5324925830 ps
T1329 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.245129758 Jul 12 08:16:51 PM PDT 24 Jul 12 08:19:53 PM PDT 24 2758787528 ps
T1330 /workspace/coverage/default/0.chip_sw_edn_sw_mode.1672566507 Jul 12 07:51:25 PM PDT 24 Jul 12 08:20:52 PM PDT 24 7506596280 ps
T1331 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1692550534 Jul 12 08:09:01 PM PDT 24 Jul 12 08:32:17 PM PDT 24 11159047670 ps
T1332 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1678839459 Jul 12 08:00:41 PM PDT 24 Jul 12 08:20:12 PM PDT 24 7542365257 ps
T67 /workspace/coverage/default/1.chip_tap_straps_rma.3985236777 Jul 12 08:00:41 PM PDT 24 Jul 12 08:06:02 PM PDT 24 3831201857 ps
T1333 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1655379220 Jul 12 07:53:11 PM PDT 24 Jul 12 08:00:03 PM PDT 24 5342147441 ps
T677 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3967765152 Jul 12 08:16:53 PM PDT 24 Jul 12 08:23:39 PM PDT 24 3783101546 ps
T247 /workspace/coverage/default/24.chip_sw_all_escalation_resets.3087147173 Jul 12 08:17:50 PM PDT 24 Jul 12 08:28:17 PM PDT 24 4108959880 ps
T347 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4054149555 Jul 12 07:58:45 PM PDT 24 Jul 12 08:10:25 PM PDT 24 19256114344 ps
T704 /workspace/coverage/default/16.chip_sw_all_escalation_resets.3815220837 Jul 12 08:17:53 PM PDT 24 Jul 12 08:28:09 PM PDT 24 4602704890 ps
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