| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.09 | 95.49 | 93.92 | 95.38 | 94.65 | 97.53 | 99.58 |
| T2763 | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.2349157260 | Jul 13 08:29:19 PM PDT 24 | Jul 13 08:30:38 PM PDT 24 | 4261090297 ps | ||
| T2764 | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.2683398199 | Jul 13 08:36:53 PM PDT 24 | Jul 13 08:38:47 PM PDT 24 | 9869689622 ps | ||
| T2765 | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.1250925408 | Jul 13 08:31:36 PM PDT 24 | Jul 13 08:33:15 PM PDT 24 | 162715317 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.837067688 | Jul 13 08:26:39 PM PDT 24 | Jul 13 08:39:22 PM PDT 24 | 64568468514 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.1857358115 | Jul 13 08:33:59 PM PDT 24 | Jul 13 09:12:59 PM PDT 24 | 123446051434 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/52.xbar_smoke.3132272680 | Jul 13 08:28:43 PM PDT 24 | Jul 13 08:28:50 PM PDT 24 | 50436450 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/22.xbar_smoke.1515368720 | Jul 13 08:22:52 PM PDT 24 | Jul 13 08:23:01 PM PDT 24 | 170230876 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1901037636 | Jul 13 08:21:32 PM PDT 24 | Jul 13 08:32:41 PM PDT 24 | 34144364701 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/42.xbar_same_source.3820566815 | Jul 13 08:27:06 PM PDT 24 | Jul 13 08:28:02 PM PDT 24 | 1805892493 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.371430721 | Jul 13 08:31:17 PM PDT 24 | Jul 13 08:41:23 PM PDT 24 | 13605141131 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/24.xbar_stress_all.2590212099 | Jul 13 08:23:20 PM PDT 24 | Jul 13 08:24:09 PM PDT 24 | 985155674 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.958953080 | Jul 13 08:33:24 PM PDT 24 | Jul 13 08:40:12 PM PDT 24 | 21759116848 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.3340304313 | Jul 13 08:14:18 PM PDT 24 | Jul 13 08:15:02 PM PDT 24 | 3730224119 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.605039077 | Jul 13 08:19:23 PM PDT 24 | Jul 13 08:21:21 PM PDT 24 | 5974412963 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/11.xbar_error_random.695704003 | Jul 13 08:19:29 PM PDT 24 | Jul 13 08:20:29 PM PDT 24 | 603457443 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.307694611 | Jul 13 08:31:22 PM PDT 24 | Jul 13 08:31:29 PM PDT 24 | 53655897 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.737246576 | Jul 13 08:30:23 PM PDT 24 | Jul 13 08:33:50 PM PDT 24 | 1581420503 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.1263770483 | Jul 13 08:36:18 PM PDT 24 | Jul 13 08:39:16 PM PDT 24 | 427558157 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/74.xbar_random.2244185656 | Jul 13 08:32:27 PM PDT 24 | Jul 13 08:33:56 PM PDT 24 | 2019102789 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.1023897857 | Jul 13 08:36:58 PM PDT 24 | Jul 13 09:03:58 PM PDT 24 | 93476854816 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.2567141933 | Jul 13 08:34:56 PM PDT 24 | Jul 13 08:35:33 PM PDT 24 | 305106523 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/11.chip_tl_errors.4050339323 | Jul 13 08:19:14 PM PDT 24 | Jul 13 08:23:26 PM PDT 24 | 3944945740 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.876525972 | Jul 13 08:21:14 PM PDT 24 | Jul 13 08:24:16 PM PDT 24 | 4279333531 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.26536401 | Jul 13 08:31:58 PM PDT 24 | Jul 13 08:33:36 PM PDT 24 | 5168348997 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.525432598 | Jul 13 08:27:01 PM PDT 24 | Jul 13 08:43:59 PM PDT 24 | 53259604243 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2389732531 | Jul 13 08:26:38 PM PDT 24 | Jul 13 08:35:20 PM PDT 24 | 27705063303 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/97.xbar_smoke.4070963625 | Jul 13 08:36:29 PM PDT 24 | Jul 13 08:36:37 PM PDT 24 | 57202111 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/35.xbar_error_random.3410658583 | Jul 13 08:25:32 PM PDT 24 | Jul 13 08:26:08 PM PDT 24 | 837801280 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.3841484808 | Jul 13 08:30:34 PM PDT 24 | Jul 13 09:13:06 PM PDT 24 | 138494261966 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/10.xbar_stress_all.1163520730 | Jul 13 08:19:06 PM PDT 24 | Jul 13 08:22:10 PM PDT 24 | 2084762451 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.979170793 | Jul 13 08:23:38 PM PDT 24 | Jul 13 08:24:45 PM PDT 24 | 3689859004 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.2344185068 | Jul 13 08:36:43 PM PDT 24 | Jul 13 08:40:07 PM PDT 24 | 6104035442 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.1422060702 | Jul 13 08:20:47 PM PDT 24 | Jul 13 08:21:01 PM PDT 24 | 239906731 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/96.xbar_smoke.4232423654 | Jul 13 08:36:34 PM PDT 24 | Jul 13 08:36:44 PM PDT 24 | 213489109 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.134880665 | Jul 13 08:23:32 PM PDT 24 | Jul 13 08:24:07 PM PDT 24 | 357046211 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.3459849694 | Jul 13 08:24:00 PM PDT 24 | Jul 13 08:24:07 PM PDT 24 | 21828174 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.3785552592 | Jul 13 08:21:59 PM PDT 24 | Jul 13 08:22:08 PM PDT 24 | 56095355 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/73.xbar_same_source.1769662394 | Jul 13 08:32:21 PM PDT 24 | Jul 13 08:32:57 PM PDT 24 | 1036481085 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/19.xbar_same_source.895093147 | Jul 13 08:22:16 PM PDT 24 | Jul 13 08:23:33 PM PDT 24 | 2188597905 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.2138740000 | Jul 13 08:15:59 PM PDT 24 | Jul 13 08:16:37 PM PDT 24 | 820514884 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.3012396153 | Jul 13 08:20:27 PM PDT 24 | Jul 13 08:21:16 PM PDT 24 | 508746269 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.60999287 | Jul 13 08:21:51 PM PDT 24 | Jul 13 08:22:04 PM PDT 24 | 90679752 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.227784031 | Jul 13 08:20:12 PM PDT 24 | Jul 13 08:33:38 PM PDT 24 | 44035946941 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.1900452308 | Jul 13 08:35:32 PM PDT 24 | Jul 13 08:38:48 PM PDT 24 | 535722110 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.1029685211 | Jul 13 08:31:31 PM PDT 24 | Jul 13 08:32:10 PM PDT 24 | 898965489 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/30.xbar_smoke.185108300 | Jul 13 08:24:31 PM PDT 24 | Jul 13 08:24:41 PM PDT 24 | 192083779 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/5.xbar_error_random.1513239150 | Jul 13 08:16:30 PM PDT 24 | Jul 13 08:17:12 PM PDT 24 | 1011893810 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.2080100521 | Jul 13 08:35:22 PM PDT 24 | Jul 13 08:40:13 PM PDT 24 | 27139708923 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.876455283 | Jul 13 08:28:34 PM PDT 24 | Jul 13 08:30:14 PM PDT 24 | 8432661504 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.906572264 | Jul 13 08:20:14 PM PDT 24 | Jul 13 08:22:04 PM PDT 24 | 5627647754 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/13.xbar_random.2253738008 | Jul 13 08:20:11 PM PDT 24 | Jul 13 08:20:53 PM PDT 24 | 485948454 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.1539454011 | Jul 13 08:29:29 PM PDT 24 | Jul 13 08:46:56 PM PDT 24 | 56566021292 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/25.xbar_smoke.1414121513 | Jul 13 08:23:29 PM PDT 24 | Jul 13 08:23:39 PM PDT 24 | 214304057 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/47.xbar_stress_all.2734161976 | Jul 13 08:27:56 PM PDT 24 | Jul 13 08:32:45 PM PDT 24 | 3723138657 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.596403916 | Jul 13 08:23:55 PM PDT 24 | Jul 13 08:24:27 PM PDT 24 | 312861018 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.694489592 | Jul 13 08:22:41 PM PDT 24 | Jul 13 08:23:14 PM PDT 24 | 400291341 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.3907083947 | Jul 13 08:31:33 PM PDT 24 | Jul 13 08:37:47 PM PDT 24 | 3035365154 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.3817641422 | Jul 13 08:26:37 PM PDT 24 | Jul 13 08:28:14 PM PDT 24 | 1358930298 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/33.xbar_error_random.1162398568 | Jul 13 08:25:03 PM PDT 24 | Jul 13 08:25:16 PM PDT 24 | 296414966 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2727006132 | Jul 13 08:19:49 PM PDT 24 | Jul 13 08:20:38 PM PDT 24 | 4025691138 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3559483358 | Jul 13 08:19:41 PM PDT 24 | Jul 13 08:19:48 PM PDT 24 | 46289411 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.4034451630 | Jul 13 08:21:50 PM PDT 24 | Jul 13 08:38:15 PM PDT 24 | 50350860400 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.3279854507 | Jul 13 08:36:33 PM PDT 24 | Jul 13 08:36:42 PM PDT 24 | 102032657 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.1866527127 | Jul 13 08:35:03 PM PDT 24 | Jul 13 08:35:09 PM PDT 24 | 22710903 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.112202014 | Jul 13 08:27:12 PM PDT 24 | Jul 13 08:29:53 PM PDT 24 | 449076315 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.3783539033 | Jul 13 08:34:14 PM PDT 24 | Jul 13 08:53:42 PM PDT 24 | 98897272172 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.2133088782 | Jul 13 08:31:23 PM PDT 24 | Jul 13 08:33:46 PM PDT 24 | 7554707293 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/3.xbar_same_source.746254514 | Jul 13 08:14:53 PM PDT 24 | Jul 13 08:16:19 PM PDT 24 | 2365619930 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.1850056498 | Jul 13 08:23:48 PM PDT 24 | Jul 13 08:49:59 PM PDT 24 | 82221142025 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/0.xbar_same_source.2642751442 | Jul 13 08:12:11 PM PDT 24 | Jul 13 08:12:48 PM PDT 24 | 1121719253 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.2198826764 | Jul 13 08:28:46 PM PDT 24 | Jul 13 08:42:49 PM PDT 24 | 74652663240 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/92.xbar_random.254642172 | Jul 13 08:35:29 PM PDT 24 | Jul 13 08:35:55 PM PDT 24 | 596934853 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/86.xbar_stress_all.3309060661 | Jul 13 08:34:39 PM PDT 24 | Jul 13 08:38:10 PM PDT 24 | 5163223626 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.325480277 | Jul 13 08:30:12 PM PDT 24 | Jul 13 08:31:08 PM PDT 24 | 525114609 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/15.xbar_random.39932336 | Jul 13 08:20:47 PM PDT 24 | Jul 13 08:20:56 PM PDT 24 | 110522915 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.2036797527 | Jul 13 08:25:32 PM PDT 24 | Jul 13 08:25:49 PM PDT 24 | 149340321 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.482542204 | Jul 13 08:25:59 PM PDT 24 | Jul 13 08:28:52 PM PDT 24 | 14401444437 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/42.xbar_random.958468866 | Jul 13 08:27:02 PM PDT 24 | Jul 13 08:27:49 PM PDT 24 | 490851221 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.4114845910 | Jul 13 08:25:28 PM PDT 24 | Jul 13 08:26:02 PM PDT 24 | 257193645 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/64.xbar_same_source.902044815 | Jul 13 08:30:51 PM PDT 24 | Jul 13 08:31:37 PM PDT 24 | 1403363238 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/23.xbar_smoke.3475856711 | Jul 13 08:23:05 PM PDT 24 | Jul 13 08:23:17 PM PDT 24 | 246360460 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.720503757 | Jul 13 08:21:05 PM PDT 24 | Jul 13 08:24:24 PM PDT 24 | 17040055374 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/21.xbar_stress_all.4217081903 | Jul 13 08:22:54 PM PDT 24 | Jul 13 08:28:10 PM PDT 24 | 8305649442 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3809452308 | Jul 13 08:21:50 PM PDT 24 | Jul 13 08:23:11 PM PDT 24 | 4216949438 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.1487624093 | Jul 13 08:35:42 PM PDT 24 | Jul 13 08:39:22 PM PDT 24 | 383976933 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/39.xbar_stress_all.169765607 | Jul 13 08:26:18 PM PDT 24 | Jul 13 08:31:10 PM PDT 24 | 3320847006 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.1979643163 | Jul 13 08:36:42 PM PDT 24 | Jul 13 08:36:49 PM PDT 24 | 44774370 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/18.chip_tl_errors.743831780 | Jul 13 08:21:42 PM PDT 24 | Jul 13 08:31:14 PM PDT 24 | 5506260511 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.2289031987 | Jul 13 08:22:27 PM PDT 24 | Jul 13 08:22:35 PM PDT 24 | 56470123 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/4.xbar_same_source.1039547003 | Jul 13 08:16:08 PM PDT 24 | Jul 13 08:17:22 PM PDT 24 | 1639507831 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/16.xbar_random.3238322489 | Jul 13 08:20:55 PM PDT 24 | Jul 13 08:22:24 PM PDT 24 | 1873664383 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/99.xbar_stress_all.2468740193 | Jul 13 08:36:59 PM PDT 24 | Jul 13 08:37:03 PM PDT 24 | 5747218 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.794178550 | Jul 13 08:27:42 PM PDT 24 | Jul 13 08:28:05 PM PDT 24 | 121256783 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.2185377831 | Jul 13 08:26:48 PM PDT 24 | Jul 13 08:27:06 PM PDT 24 | 40813592 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.1124496893 | Jul 13 08:24:04 PM PDT 24 | Jul 13 08:24:23 PM PDT 24 | 411179642 ps | ||
| T139 | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1159085345 | Jul 13 08:13:45 PM PDT 24 | Jul 13 08:20:53 PM PDT 24 | 6593261432 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3903644785 | Jul 13 08:23:49 PM PDT 24 | Jul 13 08:24:53 PM PDT 24 | 208863080 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.2100796371 | Jul 13 08:36:21 PM PDT 24 | Jul 13 08:37:09 PM PDT 24 | 1071910426 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.1119958706 | Jul 13 08:25:25 PM PDT 24 | Jul 13 08:27:42 PM PDT 24 | 2735918536 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.3548270109 | Jul 13 08:29:52 PM PDT 24 | Jul 13 08:31:41 PM PDT 24 | 9301007540 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.543405958 | Jul 13 08:29:05 PM PDT 24 | Jul 13 08:33:50 PM PDT 24 | 15295487326 ps | ||
| T715 | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.1755411772 | Jul 13 08:28:46 PM PDT 24 | Jul 13 08:31:43 PM PDT 24 | 2558258812 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.3177363304 | Jul 13 08:31:23 PM PDT 24 | Jul 13 08:32:15 PM PDT 24 | 527123817 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.1829632386 | Jul 13 08:28:06 PM PDT 24 | Jul 13 08:29:56 PM PDT 24 | 9606710458 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/60.xbar_random.2984265540 | Jul 13 08:30:03 PM PDT 24 | Jul 13 08:31:46 PM PDT 24 | 2345240402 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/46.xbar_error_random.2867004896 | Jul 13 08:27:49 PM PDT 24 | Jul 13 08:27:59 PM PDT 24 | 68194206 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.3401511678 | Jul 13 08:17:35 PM PDT 24 | Jul 13 08:18:00 PM PDT 24 | 228544359 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.767193000 | Jul 13 08:17:41 PM PDT 24 | Jul 13 08:55:55 PM PDT 24 | 136771988371 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.817225644 | Jul 13 08:29:26 PM PDT 24 | Jul 13 08:39:25 PM PDT 24 | 11018092122 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/77.xbar_same_source.3940643861 | Jul 13 08:33:03 PM PDT 24 | Jul 13 08:34:19 PM PDT 24 | 2324607336 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.3350713579 | Jul 13 08:17:34 PM PDT 24 | Jul 13 08:30:47 PM PDT 24 | 69465837477 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/4.xbar_stress_all.2338165565 | Jul 13 08:15:56 PM PDT 24 | Jul 13 08:20:33 PM PDT 24 | 2720166381 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/40.xbar_random.3936330396 | Jul 13 08:26:27 PM PDT 24 | Jul 13 08:27:26 PM PDT 24 | 591354587 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.3957287991 | Jul 13 08:21:07 PM PDT 24 | Jul 13 08:41:32 PM PDT 24 | 69633850793 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.1569932936 | Jul 13 08:29:54 PM PDT 24 | Jul 13 08:57:15 PM PDT 24 | 89711980874 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.3297121011 | Jul 13 08:21:44 PM PDT 24 | Jul 13 08:26:35 PM PDT 24 | 7625979485 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/9.xbar_stress_all.185554045 | Jul 13 08:18:37 PM PDT 24 | Jul 13 08:19:06 PM PDT 24 | 209908094 ps | ||
| T2878 | /workspace/coverage/cover_reg_top/38.xbar_stress_all.3823130327 | Jul 13 08:26:08 PM PDT 24 | Jul 13 08:27:39 PM PDT 24 | 1033780190 ps | ||
| T2879 | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.2134031427 | Jul 13 08:28:06 PM PDT 24 | Jul 13 08:37:22 PM PDT 24 | 5345609499 ps | ||
| T2880 | /workspace/coverage/cover_reg_top/18.chip_csr_rw.3608900387 | Jul 13 08:22:03 PM PDT 24 | Jul 13 08:26:58 PM PDT 24 | 3948071768 ps | ||
| T2881 | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.3871238997 | Jul 13 08:35:11 PM PDT 24 | Jul 13 08:37:48 PM PDT 24 | 322833972 ps | ||
| T2882 | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.3986533856 | Jul 13 08:34:12 PM PDT 24 | Jul 13 08:34:24 PM PDT 24 | 176691853 ps | ||
| T2883 | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.976329810 | Jul 13 08:32:57 PM PDT 24 | Jul 13 08:42:09 PM PDT 24 | 29710790221 ps | ||
| T2884 | /workspace/coverage/cover_reg_top/94.xbar_random.3900616569 | Jul 13 08:36:00 PM PDT 24 | Jul 13 08:36:36 PM PDT 24 | 319748949 ps | ||
| T2885 | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.3301821950 | Jul 13 08:28:33 PM PDT 24 | Jul 13 08:30:31 PM PDT 24 | 6334122528 ps | ||
| T2886 | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.4249850326 | Jul 13 08:21:05 PM PDT 24 | Jul 13 08:35:55 PM PDT 24 | 50291186210 ps | ||
| T2887 | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.1503380791 | Jul 13 08:31:46 PM PDT 24 | Jul 13 08:33:40 PM PDT 24 | 10096371250 ps | ||
| T2888 | /workspace/coverage/cover_reg_top/38.xbar_same_source.4290514577 | Jul 13 08:26:01 PM PDT 24 | Jul 13 08:26:29 PM PDT 24 | 310437848 ps | ||
| T2889 | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.612425204 | Jul 13 08:30:32 PM PDT 24 | Jul 13 08:31:05 PM PDT 24 | 289708559 ps | ||
| T2890 | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.229935284 | Jul 13 08:13:13 PM PDT 24 | Jul 13 08:16:46 PM PDT 24 | 17887776819 ps | ||
| T2891 | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.768213106 | Jul 13 08:12:49 PM PDT 24 | Jul 13 09:05:42 PM PDT 24 | 30783820702 ps | ||
| T2892 | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.1406477962 | Jul 13 08:31:23 PM PDT 24 | Jul 13 08:44:52 PM PDT 24 | 66276419148 ps | ||
| T2893 | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.1790151506 | Jul 13 08:32:53 PM PDT 24 | Jul 13 08:49:38 PM PDT 24 | 55016728877 ps | ||
| T2894 | /workspace/coverage/cover_reg_top/10.xbar_error_random.3946850054 | Jul 13 08:18:56 PM PDT 24 | Jul 13 08:19:08 PM PDT 24 | 182707686 ps | ||
| T2895 | /workspace/coverage/cover_reg_top/42.xbar_smoke.1497535038 | Jul 13 08:26:47 PM PDT 24 | Jul 13 08:26:56 PM PDT 24 | 153736553 ps | ||
| T2896 | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.3860229241 | Jul 13 08:16:18 PM PDT 24 | Jul 13 08:17:20 PM PDT 24 | 5639005112 ps | ||
| T2897 | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3412618089 | Jul 13 08:20:39 PM PDT 24 | Jul 13 08:21:01 PM PDT 24 | 152279332 ps | ||
| T2898 | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.1436866684 | Jul 13 08:35:00 PM PDT 24 | Jul 13 08:44:21 PM PDT 24 | 4589269987 ps | ||
| T2899 | /workspace/coverage/cover_reg_top/65.xbar_error_random.345022143 | Jul 13 08:31:00 PM PDT 24 | Jul 13 08:31:24 PM PDT 24 | 538858590 ps | ||
| T2900 | /workspace/coverage/cover_reg_top/87.xbar_stress_all.1657855690 | Jul 13 08:34:50 PM PDT 24 | Jul 13 08:43:32 PM PDT 24 | 11635800368 ps | ||
| T2901 | /workspace/coverage/cover_reg_top/8.chip_tl_errors.1380947583 | Jul 13 08:18:01 PM PDT 24 | Jul 13 08:21:57 PM PDT 24 | 3531803184 ps | ||
| T2902 | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.2884050328 | Jul 13 08:32:10 PM PDT 24 | Jul 13 08:33:23 PM PDT 24 | 6481090973 ps | ||
| T2903 | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.1948883481 | Jul 13 08:28:05 PM PDT 24 | Jul 13 08:37:37 PM PDT 24 | 49875525939 ps | ||
| T2904 | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.1863216318 | Jul 13 08:30:06 PM PDT 24 | Jul 13 08:30:12 PM PDT 24 | 39778611 ps | ||
| T2905 | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.1308759795 | Jul 13 08:26:20 PM PDT 24 | Jul 13 08:27:15 PM PDT 24 | 926315868 ps | ||
| T2906 | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.2581446564 | Jul 13 08:29:45 PM PDT 24 | Jul 13 08:30:14 PM PDT 24 | 197306364 ps | ||
| T2907 | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.85772342 | Jul 13 08:25:34 PM PDT 24 | Jul 13 08:29:39 PM PDT 24 | 2945083497 ps | ||
| T2908 | /workspace/coverage/cover_reg_top/80.xbar_same_source.589642466 | Jul 13 08:33:40 PM PDT 24 | Jul 13 08:33:48 PM PDT 24 | 166915985 ps | ||
| T2909 | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.2937372333 | Jul 13 08:33:10 PM PDT 24 | Jul 13 08:35:54 PM PDT 24 | 3434612777 ps | ||
| T2910 | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.4089147873 | Jul 13 08:27:42 PM PDT 24 | Jul 13 08:27:49 PM PDT 24 | 42718218 ps | ||
| T2911 | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.1962286103 | Jul 13 08:35:02 PM PDT 24 | Jul 13 08:35:23 PM PDT 24 | 454201597 ps | ||
| T38 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.4158191559 | Jul 13 08:11:25 PM PDT 24 | Jul 13 08:16:47 PM PDT 24 | 4246910800 ps | ||
| T39 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3395312030 | Jul 13 08:11:21 PM PDT 24 | Jul 13 08:16:14 PM PDT 24 | 5244618860 ps | ||
| T40 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1850617548 | Jul 13 08:11:10 PM PDT 24 | Jul 13 08:17:09 PM PDT 24 | 4592205556 ps | ||
| T45 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.580650830 | Jul 13 08:10:56 PM PDT 24 | Jul 13 08:16:11 PM PDT 24 | 5303598720 ps | ||
| T184 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1687046331 | Jul 13 08:11:09 PM PDT 24 | Jul 13 08:15:56 PM PDT 24 | 4716582165 ps | ||
| T185 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.66330357 | Jul 13 08:11:01 PM PDT 24 | Jul 13 08:14:58 PM PDT 24 | 5601232876 ps | ||
| T186 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1345741436 | Jul 13 08:11:08 PM PDT 24 | Jul 13 08:18:00 PM PDT 24 | 5083824413 ps | ||
| T187 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1955547992 | Jul 13 08:11:08 PM PDT 24 | Jul 13 08:16:41 PM PDT 24 | 6037456004 ps | ||
| T191 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1878469081 | Jul 13 08:11:03 PM PDT 24 | Jul 13 08:15:47 PM PDT 24 | 5065631710 ps | ||
| T188 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.4206061303 | Jul 13 08:11:26 PM PDT 24 | Jul 13 08:17:43 PM PDT 24 | 4796493426 ps |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.1204826853 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 2819106900 ps |
| CPU time | 298 seconds |
| Started | Jul 13 07:46:35 PM PDT 24 |
| Finished | Jul 13 07:51:34 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-65377842-05ac-4719-975f-58d3c8fb22c3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204826853 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.1204826853 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.1789608580 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 8162033672 ps |
| CPU time | 484.46 seconds |
| Started | Jul 13 08:15:20 PM PDT 24 |
| Finished | Jul 13 08:23:25 PM PDT 24 |
| Peak memory | 663068 kb |
| Host | smart-8b31570e-ca55-4494-8cf1-f5799b7b5796 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789608580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.1789608580 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.3452658194 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 5638485522 ps |
| CPU time | 1413.47 seconds |
| Started | Jul 13 08:04:07 PM PDT 24 |
| Finished | Jul 13 08:27:42 PM PDT 24 |
| Peak memory | 609540 kb |
| Host | smart-60e8f118-18ba-42cd-ae68-652dbf73ae7d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452658194 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.3452658194 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.997757332 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 79771801552 ps |
| CPU time | 1452.35 seconds |
| Started | Jul 13 08:28:08 PM PDT 24 |
| Finished | Jul 13 08:52:21 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-60e73716-0648-4729-a9ff-704985a76aa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997757332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_d evice_slow_rsp.997757332 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.2269683903 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 31394293938 ps |
| CPU time | 3679.1 seconds |
| Started | Jul 13 08:13:54 PM PDT 24 |
| Finished | Jul 13 09:15:14 PM PDT 24 |
| Peak memory | 592812 kb |
| Host | smart-13ba0170-8b33-4369-a4aa-b3adf79fee34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269683903 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.2269683903 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.3096145274 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 109279607232 ps |
| CPU time | 2167.14 seconds |
| Started | Jul 13 08:15:56 PM PDT 24 |
| Finished | Jul 13 08:52:03 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-9c5538da-17f6-4584-971c-3e9e76a5d6db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096145274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d evice_slow_rsp.3096145274 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.4158191559 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4246910800 ps |
| CPU time | 321.69 seconds |
| Started | Jul 13 08:11:25 PM PDT 24 |
| Finished | Jul 13 08:16:47 PM PDT 24 |
| Peak memory | 656660 kb |
| Host | smart-3562e0c1-954f-47d8-98ba-30104aa166bf |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158191559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.4158191559 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.1481357610 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 129980299216 ps |
| CPU time | 2501.37 seconds |
| Started | Jul 13 08:24:41 PM PDT 24 |
| Finished | Jul 13 09:06:23 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-5205b030-8594-4489-b194-3813467b3e8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481357610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_ device_slow_rsp.1481357610 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.4103579147 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 5289671972 ps |
| CPU time | 663.45 seconds |
| Started | Jul 13 07:46:54 PM PDT 24 |
| Finished | Jul 13 07:57:59 PM PDT 24 |
| Peak memory | 608880 kb |
| Host | smart-05ed6f85-d064-4afd-a33f-c3ffee40a7fa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103579147 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.4103579147 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2619815914 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 98630666901 ps |
| CPU time | 1791.79 seconds |
| Started | Jul 13 08:34:49 PM PDT 24 |
| Finished | Jul 13 09:04:41 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-194e8df0-0679-4cc1-ba7d-d0689dba7565 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619815914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.2619815914 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.rom_raw_unlock.632099093 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 4430981237 ps |
| CPU time | 269.46 seconds |
| Started | Jul 13 07:57:20 PM PDT 24 |
| Finished | Jul 13 08:01:50 PM PDT 24 |
| Peak memory | 623216 kb |
| Host | smart-55f0bdb9-7235-4cc5-8fcc-cc403d44afa8 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=632099093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.632099093 |
| Directory | /workspace/1.rom_raw_unlock/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.3357497251 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 4369076709 ps |
| CPU time | 186.16 seconds |
| Started | Jul 13 08:35:52 PM PDT 24 |
| Finished | Jul 13 08:38:59 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-3397af45-5463-42cc-b732-33e975c5556a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357497251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.3357497251 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1343873024 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 7161685800 ps |
| CPU time | 560.17 seconds |
| Started | Jul 13 07:45:30 PM PDT 24 |
| Finished | Jul 13 07:54:53 PM PDT 24 |
| Peak memory | 610176 kb |
| Host | smart-d8ea1dd4-cb44-4382-a89d-070f3db63048 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1343873024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.1343873024 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3326123729 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 11658456568 ps |
| CPU time | 2591.53 seconds |
| Started | Jul 13 08:04:17 PM PDT 24 |
| Finished | Jul 13 08:47:30 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-115b36d8-d359-43d4-8304-63af2cf0713b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33261 23729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.3326123729 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2361202164 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3215781013 ps |
| CPU time | 323.35 seconds |
| Started | Jul 13 07:59:27 PM PDT 24 |
| Finished | Jul 13 08:04:51 PM PDT 24 |
| Peak memory | 608496 kb |
| Host | smart-9a38440c-c51e-4438-90d1-4359bafdca7b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361 202164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.2361202164 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3492300966 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 20067807500 ps |
| CPU time | 1681.64 seconds |
| Started | Jul 13 07:45:44 PM PDT 24 |
| Finished | Jul 13 08:13:46 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-e2bf1033-24da-4925-a950-fa9bd2942ded |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3492300966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3492300966 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1127979403 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 131260127357 ps |
| CPU time | 2458.23 seconds |
| Started | Jul 13 08:12:04 PM PDT 24 |
| Finished | Jul 13 08:53:03 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-ee328b79-f0d4-409a-842b-bab9622ae33f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127979403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.1127979403 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.1770427788 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 131809996089 ps |
| CPU time | 2444.25 seconds |
| Started | Jul 13 08:20:47 PM PDT 24 |
| Finished | Jul 13 09:01:32 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-04a5ea08-8f41-45d2-b4ae-b77dcd141666 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770427788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_ device_slow_rsp.1770427788 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.529333765 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 3658276828 ps |
| CPU time | 337.02 seconds |
| Started | Jul 13 07:46:05 PM PDT 24 |
| Finished | Jul 13 07:51:44 PM PDT 24 |
| Peak memory | 608708 kb |
| Host | smart-337db98d-46c4-47f3-a96e-1e3d25054c41 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=529333765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.529333765 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.3434438188 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 4154318662 ps |
| CPU time | 728.51 seconds |
| Started | Jul 13 07:52:30 PM PDT 24 |
| Finished | Jul 13 08:04:39 PM PDT 24 |
| Peak memory | 608988 kb |
| Host | smart-a59e0cb7-ed70-449e-899a-5d681a496683 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434438188 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.3434438188 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2329782901 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 15184996920 ps |
| CPU time | 4039.46 seconds |
| Started | Jul 13 08:02:00 PM PDT 24 |
| Finished | Jul 13 09:09:20 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-3004e094-3e75-4e04-a293-a5f30770cc5a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329782901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.2329782901 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.633472212 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 2604018392 ps |
| CPU time | 287.95 seconds |
| Started | Jul 13 08:07:49 PM PDT 24 |
| Finished | Jul 13 08:12:37 PM PDT 24 |
| Peak memory | 609480 kb |
| Host | smart-b44478d4-588a-4f1e-89ee-230c367ea486 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633472212 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_gpio_smoketest.633472212 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.265786606 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 49538182975 ps |
| CPU time | 5791.83 seconds |
| Started | Jul 13 08:00:09 PM PDT 24 |
| Finished | Jul 13 09:36:43 PM PDT 24 |
| Peak memory | 619868 kb |
| Host | smart-c910d94b-469d-406e-a4d7-44251dc6ae3e |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265786606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_lc_walkthrough_dev.265786606 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.628859659 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 4161341146 ps |
| CPU time | 707.69 seconds |
| Started | Jul 13 08:20:15 PM PDT 24 |
| Finished | Jul 13 08:32:03 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-277dcde1-8b92-4963-a6ba-fefd290e6471 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628859659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_ with_rand_reset.628859659 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.1426618264 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 13837846374 ps |
| CPU time | 1474.63 seconds |
| Started | Jul 13 07:56:59 PM PDT 24 |
| Finished | Jul 13 08:21:34 PM PDT 24 |
| Peak memory | 607308 kb |
| Host | smart-e894b44c-3d5d-4759-a319-bf3e41c8d229 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426618264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.1426618264 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3417236066 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 6043236494 ps |
| CPU time | 1054.54 seconds |
| Started | Jul 13 07:50:49 PM PDT 24 |
| Finished | Jul 13 08:08:28 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-dd583c18-bba3-46b9-a1c0-7e81e54f7d2b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3417236066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.3417236066 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.770734676 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 4227940632 ps |
| CPU time | 317.65 seconds |
| Started | Jul 13 08:22:29 PM PDT 24 |
| Finished | Jul 13 08:27:47 PM PDT 24 |
| Peak memory | 600132 kb |
| Host | smart-8ec42598-c786-4b35-a361-094b339caf86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770734676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.770734676 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.1813669809 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 6378619288 ps |
| CPU time | 678.62 seconds |
| Started | Jul 13 07:46:15 PM PDT 24 |
| Finished | Jul 13 07:57:35 PM PDT 24 |
| Peak memory | 624308 kb |
| Host | smart-9ec3e115-d0be-4154-be6d-a555503cfe2f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813669809 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.1813669809 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.4200611559 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 12895080405 ps |
| CPU time | 683.74 seconds |
| Started | Jul 13 08:27:11 PM PDT 24 |
| Finished | Jul 13 08:38:35 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-53481b10-c0a3-490f-9c8b-bc1520abe76c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200611559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al l_with_reset_error.4200611559 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.344163414 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 4150087386 ps |
| CPU time | 611.25 seconds |
| Started | Jul 13 07:51:40 PM PDT 24 |
| Finished | Jul 13 08:01:51 PM PDT 24 |
| Peak memory | 609236 kb |
| Host | smart-92f46b73-f0b0-430d-930e-b167f41c2510 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344163414 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_10.344163414 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.1039632494 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 5597164620 ps |
| CPU time | 665.23 seconds |
| Started | Jul 13 08:15:04 PM PDT 24 |
| Finished | Jul 13 08:26:10 PM PDT 24 |
| Peak memory | 649468 kb |
| Host | smart-894e75bc-684d-436c-9890-f405c4ed658b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1039632494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.1039632494 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.1345952374 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 28758553196 ps |
| CPU time | 3639.4 seconds |
| Started | Jul 13 08:09:21 PM PDT 24 |
| Finished | Jul 13 09:10:01 PM PDT 24 |
| Peak memory | 611164 kb |
| Host | smart-8aa6202b-feb0-413f-8d93-040aabf2139e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345952374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.1345952374 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.965562946 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3346922831 ps |
| CPU time | 297.57 seconds |
| Started | Jul 13 07:44:00 PM PDT 24 |
| Finished | Jul 13 07:49:00 PM PDT 24 |
| Peak memory | 609492 kb |
| Host | smart-32b5af00-4bb6-4ef4-9589-c969aba3c218 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9655 62946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.965562946 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.2454176741 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 81841975140 ps |
| CPU time | 988.07 seconds |
| Started | Jul 13 08:22:21 PM PDT 24 |
| Finished | Jul 13 08:38:50 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-a1320855-58a5-4b33-a154-20e304e3b7e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454176741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2454176741 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.581603759 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 43773325500 ps |
| CPU time | 5264.82 seconds |
| Started | Jul 13 07:59:32 PM PDT 24 |
| Finished | Jul 13 09:27:18 PM PDT 24 |
| Peak memory | 621200 kb |
| Host | smart-ff23e1e5-f56f-41d1-84f3-af95e018b278 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=581603759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.581603759 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2163049362 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 21507512358 ps |
| CPU time | 1594.74 seconds |
| Started | Jul 13 08:01:56 PM PDT 24 |
| Finished | Jul 13 08:28:32 PM PDT 24 |
| Peak memory | 613040 kb |
| Host | smart-ec14dda2-1718-4348-b94e-48e9a9fc5811 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21630493 62 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.2163049362 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1878507992 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 4218008600 ps |
| CPU time | 450.77 seconds |
| Started | Jul 13 08:09:41 PM PDT 24 |
| Finished | Jul 13 08:17:12 PM PDT 24 |
| Peak memory | 647924 kb |
| Host | smart-be93d944-2a08-4bba-b88e-3efe7bb16a30 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878507992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1878507992 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4059253746 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 5378037940 ps |
| CPU time | 484.8 seconds |
| Started | Jul 13 07:56:06 PM PDT 24 |
| Finished | Jul 13 08:04:12 PM PDT 24 |
| Peak memory | 608228 kb |
| Host | smart-b89d228b-cdf4-4344-9955-6334b0dc0c50 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40592537 46 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4059253746 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.235145194 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 11388530568 ps |
| CPU time | 1185.46 seconds |
| Started | Jul 13 07:48:40 PM PDT 24 |
| Finished | Jul 13 08:08:27 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-801ff7e1-8d17-40da-a28b-763af6867acb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235145194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.235145194 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.1513236107 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 5135406760 ps |
| CPU time | 631.73 seconds |
| Started | Jul 13 08:11:31 PM PDT 24 |
| Finished | Jul 13 08:22:03 PM PDT 24 |
| Peak memory | 603912 kb |
| Host | smart-7ae3626c-f1cd-417f-a2e7-6ea293548517 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513236107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.1513236107 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.2425917447 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 4797005420 ps |
| CPU time | 779.59 seconds |
| Started | Jul 13 08:14:50 PM PDT 24 |
| Finished | Jul 13 08:27:50 PM PDT 24 |
| Peak memory | 616432 kb |
| Host | smart-96038011-4889-4084-9c23-5304fe868a88 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2425917447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.2425917447 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2595782020 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3156018817 ps |
| CPU time | 347.5 seconds |
| Started | Jul 13 07:45:36 PM PDT 24 |
| Finished | Jul 13 07:51:24 PM PDT 24 |
| Peak memory | 608332 kb |
| Host | smart-ca1d64d6-b4f3-407b-9034-e50bc824d8af |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595 782020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.2595782020 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.87339413 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3615804672 ps |
| CPU time | 389.79 seconds |
| Started | Jul 13 07:43:54 PM PDT 24 |
| Finished | Jul 13 07:50:25 PM PDT 24 |
| Peak memory | 609600 kb |
| Host | smart-9902c5c3-feb5-4150-bd2d-e4e08068c38d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87339413 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.87339413 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.3846041710 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 4795053172 ps |
| CPU time | 1175.12 seconds |
| Started | Jul 13 08:03:23 PM PDT 24 |
| Finished | Jul 13 08:23:00 PM PDT 24 |
| Peak memory | 608692 kb |
| Host | smart-37e8ec72-a00d-4304-afc0-91edf9d62d72 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846041710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.3846041710 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2127159088 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 45504369200 ps |
| CPU time | 5098 seconds |
| Started | Jul 13 08:01:59 PM PDT 24 |
| Finished | Jul 13 09:26:58 PM PDT 24 |
| Peak memory | 618340 kb |
| Host | smart-f1511b44-61ae-45eb-a28a-c6be045bc203 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127159088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.2127159088 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.1659073907 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 5170744512 ps |
| CPU time | 844.18 seconds |
| Started | Jul 13 07:59:07 PM PDT 24 |
| Finished | Jul 13 08:13:12 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-4563bc48-9a7c-4ec5-bdc1-6d1e5a01096b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1659073907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.1659073907 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.2670928930 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 55302088044 ps |
| CPU time | 995.84 seconds |
| Started | Jul 13 08:33:57 PM PDT 24 |
| Finished | Jul 13 08:50:34 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-aedd3acb-76d4-4ab9-9640-66cc91efaaf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670928930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.2670928930 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.3948156981 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 4897080720 ps |
| CPU time | 683.92 seconds |
| Started | Jul 13 08:23:20 PM PDT 24 |
| Finished | Jul 13 08:34:45 PM PDT 24 |
| Peak memory | 598812 kb |
| Host | smart-181bf3b9-af6e-4817-ba9d-b4827c469b2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948156981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.3948156981 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.66330357 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 5601232876 ps |
| CPU time | 236.23 seconds |
| Started | Jul 13 08:11:01 PM PDT 24 |
| Finished | Jul 13 08:14:58 PM PDT 24 |
| Peak memory | 656684 kb |
| Host | smart-ff496130-359e-4b6c-baff-bcf7d1d8d7c5 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66330357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/nu ll -cm_name 2.chip_padctrl_attributes.66330357 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.871028877 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 5027561480 ps |
| CPU time | 677.34 seconds |
| Started | Jul 13 07:45:34 PM PDT 24 |
| Finished | Jul 13 07:56:53 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-eaa75266-3e9c-406d-99f2-fbe29e67dfc7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871028877 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_rstmgr_cpu_info.871028877 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.2829369095 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 5406530064 ps |
| CPU time | 618.17 seconds |
| Started | Jul 13 08:16:29 PM PDT 24 |
| Finished | Jul 13 08:26:48 PM PDT 24 |
| Peak memory | 649720 kb |
| Host | smart-7287e7c4-0ce9-4e8c-a477-850ae030c3ad |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2829369095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.2829369095 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.1298606215 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 5599185980 ps |
| CPU time | 718.45 seconds |
| Started | Jul 13 08:11:20 PM PDT 24 |
| Finished | Jul 13 08:23:19 PM PDT 24 |
| Peak memory | 649492 kb |
| Host | smart-39a5c21f-e6d6-4235-a4a3-8bb826f67c7e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1298606215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.1298606215 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.3557546567 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 5143206696 ps |
| CPU time | 625.39 seconds |
| Started | Jul 13 08:11:22 PM PDT 24 |
| Finished | Jul 13 08:21:49 PM PDT 24 |
| Peak memory | 650180 kb |
| Host | smart-88846a9f-7ff8-44b3-acb9-e8f74ace072a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3557546567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.3557546567 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.3482467725 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 4141359283 ps |
| CPU time | 471.66 seconds |
| Started | Jul 13 08:32:47 PM PDT 24 |
| Finished | Jul 13 08:40:39 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-b4273027-4ca7-445a-9186-07238af255ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482467725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_rand_reset.3482467725 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.534282254 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 5835627878 ps |
| CPU time | 714.35 seconds |
| Started | Jul 13 08:02:48 PM PDT 24 |
| Finished | Jul 13 08:14:43 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-78593ebe-171d-4546-a504-12ab9429d82d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534282254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.534282254 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2581961129 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 5546873000 ps |
| CPU time | 532.04 seconds |
| Started | Jul 13 07:44:26 PM PDT 24 |
| Finished | Jul 13 07:53:21 PM PDT 24 |
| Peak memory | 611032 kb |
| Host | smart-4cf6c71a-7eb1-4bce-b6b0-108cf33be7d8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581961129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.2581961129 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.2123147212 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 6124889132 ps |
| CPU time | 1264.74 seconds |
| Started | Jul 13 07:46:45 PM PDT 24 |
| Finished | Jul 13 08:07:51 PM PDT 24 |
| Peak memory | 609540 kb |
| Host | smart-e189c2dc-1f32-4263-a9ba-7b4da01226a7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123147212 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.2123147212 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.3148956510 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 29846476863 ps |
| CPU time | 4141.93 seconds |
| Started | Jul 13 08:17:28 PM PDT 24 |
| Finished | Jul 13 09:26:31 PM PDT 24 |
| Peak memory | 593784 kb |
| Host | smart-e7e7a603-3a80-49cd-b38a-668dc7673527 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148956510 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.3148956510 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3146402605 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 7422595696 ps |
| CPU time | 1403 seconds |
| Started | Jul 13 08:03:58 PM PDT 24 |
| Finished | Jul 13 08:27:22 PM PDT 24 |
| Peak memory | 608684 kb |
| Host | smart-f9e69c53-4584-429c-9d3f-455b1315e762 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31464026 05 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.3146402605 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1419799343 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 2839488280 ps |
| CPU time | 251.62 seconds |
| Started | Jul 13 08:05:40 PM PDT 24 |
| Finished | Jul 13 08:09:53 PM PDT 24 |
| Peak memory | 608384 kb |
| Host | smart-f210c9fd-b65d-4cd3-972e-448f77a55d82 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419799343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.1419799343 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_testunlock0.1655876688 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 3724895383 ps |
| CPU time | 286.28 seconds |
| Started | Jul 13 07:46:05 PM PDT 24 |
| Finished | Jul 13 07:50:54 PM PDT 24 |
| Peak memory | 620324 kb |
| Host | smart-0d57014b-15a4-437c-a7d5-3032c23834d0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1655876688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.1655876688 |
| Directory | /workspace/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1754109387 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3186663714 ps |
| CPU time | 273.61 seconds |
| Started | Jul 13 07:50:58 PM PDT 24 |
| Finished | Jul 13 07:55:38 PM PDT 24 |
| Peak memory | 608340 kb |
| Host | smart-b286e6d1-1415-454e-bf62-f8ea25c0aab8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754109387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.1754109387 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.4212810183 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 3637247010 ps |
| CPU time | 434.84 seconds |
| Started | Jul 13 08:17:08 PM PDT 24 |
| Finished | Jul 13 08:24:24 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-e62cd963-b5b8-4393-b079-3a83c04feb66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212810183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_rand_reset.4212810183 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.186239702 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5136409736 ps |
| CPU time | 452.49 seconds |
| Started | Jul 13 07:49:32 PM PDT 24 |
| Finished | Jul 13 07:57:05 PM PDT 24 |
| Peak memory | 609152 kb |
| Host | smart-f3692360-676d-4820-827e-092f63253cbf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18 6239702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.186239702 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3197304176 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3132285181 ps |
| CPU time | 143.77 seconds |
| Started | Jul 13 07:44:57 PM PDT 24 |
| Finished | Jul 13 07:47:23 PM PDT 24 |
| Peak memory | 619436 kb |
| Host | smart-a3ddb177-81b5-464e-8e88-3c71a159bd5d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31973041 76 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.3197304176 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2429962256 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 79160876496 ps |
| CPU time | 14038 seconds |
| Started | Jul 13 07:45:50 PM PDT 24 |
| Finished | Jul 13 11:39:50 PM PDT 24 |
| Peak memory | 634572 kb |
| Host | smart-d35db5d6-8fda-46de-825a-605898680496 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2429962256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.2429962256 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1341100383 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 4154990514 ps |
| CPU time | 635.87 seconds |
| Started | Jul 13 08:09:22 PM PDT 24 |
| Finished | Jul 13 08:19:58 PM PDT 24 |
| Peak memory | 618172 kb |
| Host | smart-83dca230-b703-4a59-803f-0a8a7b0cddcd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1341100383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.1341100383 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.4046180807 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 6509286680 ps |
| CPU time | 525.38 seconds |
| Started | Jul 13 08:19:59 PM PDT 24 |
| Finished | Jul 13 08:28:45 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-2a58e564-93c5-4abd-8deb-3c4fb3750a1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046180807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.4046180807 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2169428171 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 31767359430 ps |
| CPU time | 7324.33 seconds |
| Started | Jul 13 07:44:10 PM PDT 24 |
| Finished | Jul 13 09:46:16 PM PDT 24 |
| Peak memory | 609620 kb |
| Host | smart-ce05efc4-7d1f-46a2-9c3d-1baa290182d9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2169428171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.2169428171 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.499946431 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 43342946628 ps |
| CPU time | 5871.57 seconds |
| Started | Jul 13 07:43:55 PM PDT 24 |
| Finished | Jul 13 09:21:48 PM PDT 24 |
| Peak memory | 620116 kb |
| Host | smart-a2c0d038-68f6-4856-ac08-f5ea3f0f84a9 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=499946431 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.499946431 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.2052883821 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 5860659488 ps |
| CPU time | 1294.37 seconds |
| Started | Jul 13 07:52:21 PM PDT 24 |
| Finished | Jul 13 08:13:56 PM PDT 24 |
| Peak memory | 609544 kb |
| Host | smart-67868f22-ce0b-4191-b23f-9606eb1ce0c1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052883821 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.2052883821 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.2861685084 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 14921200498 ps |
| CPU time | 833.85 seconds |
| Started | Jul 13 08:28:07 PM PDT 24 |
| Finished | Jul 13 08:42:02 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-f065a41c-860e-4af0-aa7a-9c424ede182c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861685084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.2861685084 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.343663046 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 3613451952 ps |
| CPU time | 269.96 seconds |
| Started | Jul 13 08:21:13 PM PDT 24 |
| Finished | Jul 13 08:25:43 PM PDT 24 |
| Peak memory | 598732 kb |
| Host | smart-4c233df4-641d-4cf3-87c1-c684e21cb958 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343663046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.343663046 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.4107319299 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 4859838114 ps |
| CPU time | 805.8 seconds |
| Started | Jul 13 07:48:10 PM PDT 24 |
| Finished | Jul 13 08:01:37 PM PDT 24 |
| Peak memory | 609532 kb |
| Host | smart-6c50268a-7744-4656-bde4-c4a427b41bbf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107319299 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.4107319299 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.546286925 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3123134940 ps |
| CPU time | 280.65 seconds |
| Started | Jul 13 07:59:17 PM PDT 24 |
| Finished | Jul 13 08:03:59 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-586f7498-8f4c-45f7-b884-e060e11a8036 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546286925 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.546286925 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3338172580 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3710502406 ps |
| CPU time | 327.1 seconds |
| Started | Jul 13 07:46:19 PM PDT 24 |
| Finished | Jul 13 07:51:47 PM PDT 24 |
| Peak memory | 619140 kb |
| Host | smart-8c6e342b-c82f-4d1c-b40d-896f2c4a1cd7 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 338172580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.3338172580 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.18732122 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 4269579720 ps |
| CPU time | 424.13 seconds |
| Started | Jul 13 07:44:46 PM PDT 24 |
| Finished | Jul 13 07:51:52 PM PDT 24 |
| Peak memory | 608432 kb |
| Host | smart-aa32f4fd-8f76-4f80-8ffc-71d5f622af7f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18732122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.18732122 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1717660216 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 7605793560 ps |
| CPU time | 918.13 seconds |
| Started | Jul 13 07:51:10 PM PDT 24 |
| Finished | Jul 13 08:06:29 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-4bb15f00-87f1-42a6-813c-885b1debed79 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17176602 16 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.1717660216 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2991476086 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2281937114 ps |
| CPU time | 338.49 seconds |
| Started | Jul 13 08:33:47 PM PDT 24 |
| Finished | Jul 13 08:39:26 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-6b42e3a0-bfb0-4133-811e-f95d5eb88364 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991476086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.2991476086 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3603818284 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 824140778 ps |
| CPU time | 330.55 seconds |
| Started | Jul 13 08:25:14 PM PDT 24 |
| Finished | Jul 13 08:30:44 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-1a3e6156-d8f5-4c12-9f25-53a1e6fdca81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603818284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.3603818284 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3063944752 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 2562417450 ps |
| CPU time | 130.61 seconds |
| Started | Jul 13 07:49:41 PM PDT 24 |
| Finished | Jul 13 07:51:53 PM PDT 24 |
| Peak memory | 620120 kb |
| Host | smart-de8d9a12-6050-41b7-880a-3715d8d37da8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063944752 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.3063944752 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.137062492 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4681386432 ps |
| CPU time | 606.56 seconds |
| Started | Jul 13 08:16:03 PM PDT 24 |
| Finished | Jul 13 08:26:10 PM PDT 24 |
| Peak memory | 649672 kb |
| Host | smart-05c5868b-a7d9-48e7-b597-5f0b85ee899e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 137062492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.137062492 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3622840927 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 44369062485 ps |
| CPU time | 5416.17 seconds |
| Started | Jul 13 07:45:32 PM PDT 24 |
| Finished | Jul 13 09:15:50 PM PDT 24 |
| Peak memory | 620032 kb |
| Host | smart-e9dc653b-5677-410b-aa8e-38c43a539462 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3622840927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.3622840927 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.275695356 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 20869395134 ps |
| CPU time | 3306.29 seconds |
| Started | Jul 13 07:58:23 PM PDT 24 |
| Finished | Jul 13 08:53:30 PM PDT 24 |
| Peak memory | 610216 kb |
| Host | smart-680b82b0-9532-414e-a32a-6250bc3551ef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275695356 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.275695356 |
| Directory | /workspace/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.3720224847 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 11916337952 ps |
| CPU time | 1423.43 seconds |
| Started | Jul 13 07:45:52 PM PDT 24 |
| Finished | Jul 13 08:09:37 PM PDT 24 |
| Peak memory | 603252 kb |
| Host | smart-a364d1e9-3c8f-4211-a61c-ec322aec290f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720224847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.3720224847 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.2158814101 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 3651260017 ps |
| CPU time | 350.82 seconds |
| Started | Jul 13 08:20:25 PM PDT 24 |
| Finished | Jul 13 08:26:17 PM PDT 24 |
| Peak memory | 603868 kb |
| Host | smart-963dd0ea-207b-4ec5-9576-86657df8d247 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158814101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.2158814101 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.1312937655 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 3246738687 ps |
| CPU time | 405.84 seconds |
| Started | Jul 13 08:16:11 PM PDT 24 |
| Finished | Jul 13 08:22:57 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-ea11b4eb-7c4f-48d1-bf8a-b68554242b62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312937655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.1312937655 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1091957750 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 50032410628 ps |
| CPU time | 6029.84 seconds |
| Started | Jul 13 07:47:05 PM PDT 24 |
| Finished | Jul 13 09:27:37 PM PDT 24 |
| Peak memory | 619876 kb |
| Host | smart-703fc53b-c5b6-42d9-ab5c-1de20a0828f1 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091957750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_dev.1091957750 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2661212454 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 13646873958 ps |
| CPU time | 3191.99 seconds |
| Started | Jul 13 07:47:02 PM PDT 24 |
| Finished | Jul 13 08:40:15 PM PDT 24 |
| Peak memory | 622416 kb |
| Host | smart-15ffbc34-d282-4f44-89fe-be9478099e66 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661212454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.2661212454 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.1840486184 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 4339784172 ps |
| CPU time | 749.01 seconds |
| Started | Jul 13 08:03:50 PM PDT 24 |
| Finished | Jul 13 08:16:20 PM PDT 24 |
| Peak memory | 609540 kb |
| Host | smart-081f658b-431b-4297-8284-987152730d49 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840486184 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.1840486184 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.4114405733 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3767727333 ps |
| CPU time | 599.77 seconds |
| Started | Jul 13 07:43:54 PM PDT 24 |
| Finished | Jul 13 07:53:55 PM PDT 24 |
| Peak memory | 609492 kb |
| Host | smart-2c8cb78a-5d68-4c25-ab79-da91b930e640 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=4114405733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.4114405733 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.3085309331 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 3584274168 ps |
| CPU time | 350.06 seconds |
| Started | Jul 13 08:22:52 PM PDT 24 |
| Finished | Jul 13 08:28:43 PM PDT 24 |
| Peak memory | 603836 kb |
| Host | smart-4badda7c-651d-4b51-9426-5ea64ea1cdcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085309331 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.3085309331 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.1540064702 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 1236857498 ps |
| CPU time | 59.42 seconds |
| Started | Jul 13 08:23:49 PM PDT 24 |
| Finished | Jul 13 08:24:49 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-858fd986-c779-4073-811d-022edaa4e852 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540064702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .1540064702 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2127927839 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 4047145292 ps |
| CPU time | 636.93 seconds |
| Started | Jul 13 07:43:38 PM PDT 24 |
| Finished | Jul 13 07:54:18 PM PDT 24 |
| Peak memory | 612076 kb |
| Host | smart-13bba8ba-aebe-4724-b0df-d2e95799ad32 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127927839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2127927839 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.3300703016 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 8006880684 ps |
| CPU time | 528.65 seconds |
| Started | Jul 13 08:16:09 PM PDT 24 |
| Finished | Jul 13 08:24:58 PM PDT 24 |
| Peak memory | 665268 kb |
| Host | smart-1f3f44f1-4a51-4dba-9f36-6f6b1a8b6bc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300703016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r eset.3300703016 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1303866440 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 4049316116 ps |
| CPU time | 774.5 seconds |
| Started | Jul 13 07:47:30 PM PDT 24 |
| Finished | Jul 13 08:00:26 PM PDT 24 |
| Peak memory | 621932 kb |
| Host | smart-dac5ecdb-a8ae-47e2-8fd2-5dca2a29528c |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303866440 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.1303866440 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.1649492833 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 10293174599 ps |
| CPU time | 1993.24 seconds |
| Started | Jul 13 07:45:17 PM PDT 24 |
| Finished | Jul 13 08:18:32 PM PDT 24 |
| Peak memory | 623584 kb |
| Host | smart-6ff59a26-b985-43eb-9765-03ef1fbf06b4 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16494 92833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.1649492833 |
| Directory | /workspace/0.rom_e2e_jtag_debug_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.383160322 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 4275713862 ps |
| CPU time | 754.61 seconds |
| Started | Jul 13 07:45:21 PM PDT 24 |
| Finished | Jul 13 07:57:57 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-5ecdb26f-10d3-44b5-aca0-c1a956a03bd5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383160322 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.383160322 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.605907268 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 8255971871 ps |
| CPU time | 371.03 seconds |
| Started | Jul 13 08:25:31 PM PDT 24 |
| Finished | Jul 13 08:31:43 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-4f28ecd3-ba67-4fec-b2df-14695d5c0a92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605907268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.605907268 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.3806673033 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 3797026218 ps |
| CPU time | 576.15 seconds |
| Started | Jul 13 07:47:38 PM PDT 24 |
| Finished | Jul 13 07:57:14 PM PDT 24 |
| Peak memory | 609228 kb |
| Host | smart-bf7d19b8-962c-43d9-98fd-3f7e7c60795e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806673033 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.3806673033 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.3511963824 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 578343407 ps |
| CPU time | 235.72 seconds |
| Started | Jul 13 08:21:44 PM PDT 24 |
| Finished | Jul 13 08:25:40 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-8bc78157-cb44-4990-abab-52b71449d8c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511963824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_rand_reset.3511963824 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.3382265978 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 13702133139 ps |
| CPU time | 681.26 seconds |
| Started | Jul 13 08:22:57 PM PDT 24 |
| Finished | Jul 13 08:34:19 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-fc8e19f5-6f29-4141-9c0a-678a1da51f21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382265978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al l_with_reset_error.3382265978 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.85539986 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4045626298 ps |
| CPU time | 509.47 seconds |
| Started | Jul 13 07:59:32 PM PDT 24 |
| Finished | Jul 13 08:08:02 PM PDT 24 |
| Peak memory | 609532 kb |
| Host | smart-63d3858a-dffa-4225-84e2-47c7f35c9b11 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85539986 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_gpio.85539986 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3294420919 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3756767420 ps |
| CPU time | 376.89 seconds |
| Started | Jul 13 08:16:31 PM PDT 24 |
| Finished | Jul 13 08:22:49 PM PDT 24 |
| Peak memory | 648260 kb |
| Host | smart-bd3d18be-dd20-4a77-aee6-4e19fe79b7b3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294420919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3294420919 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.1665435493 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 3063507833 ps |
| CPU time | 170.67 seconds |
| Started | Jul 13 08:14:44 PM PDT 24 |
| Finished | Jul 13 08:17:35 PM PDT 24 |
| Peak memory | 598792 kb |
| Host | smart-5105257c-81f7-4564-b6d5-24ea43227a7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665435493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.1665435493 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3005418755 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 3231700270 ps |
| CPU time | 452.73 seconds |
| Started | Jul 13 07:42:54 PM PDT 24 |
| Finished | Jul 13 07:50:27 PM PDT 24 |
| Peak memory | 608696 kb |
| Host | smart-47336046-b71d-4140-a8ca-7f96fea63ffe |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300541 8755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.3005418755 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.956164797 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 2996227424 ps |
| CPU time | 281.55 seconds |
| Started | Jul 13 08:23:47 PM PDT 24 |
| Finished | Jul 13 08:28:29 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-6f5df9bf-d4c3-42ed-b6b2-b5d3feccf9e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956164797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.956164797 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.1607045739 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 75673263938 ps |
| CPU time | 1485.55 seconds |
| Started | Jul 13 08:27:46 PM PDT 24 |
| Finished | Jul 13 08:52:32 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-c975291d-69d4-4ab6-b935-12c6c71e6f49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607045739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_ device_slow_rsp.1607045739 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.4123881670 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 3096910093 ps |
| CPU time | 270.66 seconds |
| Started | Jul 13 07:59:27 PM PDT 24 |
| Finished | Jul 13 08:03:59 PM PDT 24 |
| Peak memory | 621964 kb |
| Host | smart-296a173b-e329-4fac-ba3e-8d2cbe019338 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123881670 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.4123881670 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.1269338157 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 4484143192 ps |
| CPU time | 471.28 seconds |
| Started | Jul 13 08:20:36 PM PDT 24 |
| Finished | Jul 13 08:28:28 PM PDT 24 |
| Peak memory | 603876 kb |
| Host | smart-84fd098b-1e87-4356-84c6-71c039244945 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269338157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.1269338157 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.2827688856 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 5883221100 ps |
| CPU time | 846.67 seconds |
| Started | Jul 13 07:58:43 PM PDT 24 |
| Finished | Jul 13 08:12:51 PM PDT 24 |
| Peak memory | 649760 kb |
| Host | smart-ccf9c897-a552-488f-96e8-826d7692b1ba |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2827688856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.2827688856 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.1976865113 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1795814309 ps |
| CPU time | 95.74 seconds |
| Started | Jul 13 08:21:15 PM PDT 24 |
| Finished | Jul 13 08:22:51 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-11971c81-6fdb-423a-8f8a-399392fa551a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976865113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1976865113 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.2633584413 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 16281277851 ps |
| CPU time | 752.51 seconds |
| Started | Jul 13 08:36:43 PM PDT 24 |
| Finished | Jul 13 08:49:16 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-2781d276-f392-47e3-ab3a-05248199b37f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633584413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.2633584413 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.448062678 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3968297238 ps |
| CPU time | 487.61 seconds |
| Started | Jul 13 07:47:04 PM PDT 24 |
| Finished | Jul 13 07:55:13 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-751b907f-7e05-43e9-9f78-9ddf00b02cc1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448062678 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.chip_sw_gpio.448062678 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1988520761 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 11077052520 ps |
| CPU time | 1864.12 seconds |
| Started | Jul 13 07:48:31 PM PDT 24 |
| Finished | Jul 13 08:19:37 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-7f9e3ac9-a74c-4e42-866e-9c4a5365d43f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1988520761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.1988520761 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.393893866 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5569013676 ps |
| CPU time | 598.93 seconds |
| Started | Jul 13 08:16:53 PM PDT 24 |
| Finished | Jul 13 08:26:53 PM PDT 24 |
| Peak memory | 649696 kb |
| Host | smart-d513c5d7-d448-4820-886e-a9a44017d215 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 393893866 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.393893866 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3408629303 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4837549000 ps |
| CPU time | 691.62 seconds |
| Started | Jul 13 07:59:35 PM PDT 24 |
| Finished | Jul 13 08:11:07 PM PDT 24 |
| Peak memory | 608700 kb |
| Host | smart-7db0475a-41c8-4300-a6be-2232b5140695 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408629303 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.3408629303 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.719286317 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 2887651578 ps |
| CPU time | 282.95 seconds |
| Started | Jul 13 07:51:26 PM PDT 24 |
| Finished | Jul 13 07:56:10 PM PDT 24 |
| Peak memory | 609720 kb |
| Host | smart-c8d71253-470f-4001-a1ec-38cd6911b360 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7192863 17 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.719286317 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2931317068 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 6254504102 ps |
| CPU time | 1053.13 seconds |
| Started | Jul 13 07:46:31 PM PDT 24 |
| Finished | Jul 13 08:04:05 PM PDT 24 |
| Peak memory | 610192 kb |
| Host | smart-63503c95-405b-4a25-b1a9-31f4988bd7f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931317068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.2931317068 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1469550439 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 11195556423 ps |
| CPU time | 624.02 seconds |
| Started | Jul 13 08:12:31 PM PDT 24 |
| Finished | Jul 13 08:22:55 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-a670734b-30bb-4d7a-9825-ae2684074977 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469550439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.1469550439 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.403318209 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 3838355900 ps |
| CPU time | 330.76 seconds |
| Started | Jul 13 07:49:36 PM PDT 24 |
| Finished | Jul 13 07:55:09 PM PDT 24 |
| Peak memory | 647960 kb |
| Host | smart-299c69bc-22df-4864-a8a0-14471068be2f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403318209 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _alert_handler_lpg_sleep_mode_alerts.403318209 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.4173992124 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 5063833330 ps |
| CPU time | 600.6 seconds |
| Started | Jul 13 07:46:32 PM PDT 24 |
| Finished | Jul 13 07:56:33 PM PDT 24 |
| Peak memory | 649536 kb |
| Host | smart-b6d5137d-b86c-4c7d-994c-16f34e045988 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4173992124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.4173992124 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.975249460 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 3900517802 ps |
| CPU time | 423.44 seconds |
| Started | Jul 13 08:09:21 PM PDT 24 |
| Finished | Jul 13 08:16:25 PM PDT 24 |
| Peak memory | 648160 kb |
| Host | smart-d3536deb-ac68-47b6-a9be-64696328c4e8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975249460 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_s w_alert_handler_lpg_sleep_mode_alerts.975249460 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.627233927 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 5879349362 ps |
| CPU time | 671.23 seconds |
| Started | Jul 13 08:09:38 PM PDT 24 |
| Finished | Jul 13 08:20:50 PM PDT 24 |
| Peak memory | 649976 kb |
| Host | smart-67b51305-2d5c-4b9f-85ed-990e442a6c35 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 627233927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.627233927 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.2797430264 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 5314938270 ps |
| CPU time | 840.83 seconds |
| Started | Jul 13 08:09:42 PM PDT 24 |
| Finished | Jul 13 08:23:44 PM PDT 24 |
| Peak memory | 649368 kb |
| Host | smart-fd9f8f0d-0359-46c3-820f-3ba0242de42a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2797430264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.2797430264 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1787487068 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 4013312652 ps |
| CPU time | 491.28 seconds |
| Started | Jul 13 08:11:43 PM PDT 24 |
| Finished | Jul 13 08:19:55 PM PDT 24 |
| Peak memory | 648304 kb |
| Host | smart-21d0b541-6483-484a-bf65-c9b150b4cc7d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787487068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1787487068 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.2497549672 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 5011126740 ps |
| CPU time | 756.3 seconds |
| Started | Jul 13 08:10:01 PM PDT 24 |
| Finished | Jul 13 08:22:38 PM PDT 24 |
| Peak memory | 649524 kb |
| Host | smart-fdf42f18-1b1c-4761-8ec2-7af0b2030ae7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2497549672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.2497549672 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2524999047 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 4186192784 ps |
| CPU time | 401.63 seconds |
| Started | Jul 13 08:10:53 PM PDT 24 |
| Finished | Jul 13 08:17:35 PM PDT 24 |
| Peak memory | 648232 kb |
| Host | smart-f97c08da-eaa0-4dad-8e7d-1c6149aa6085 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524999047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2524999047 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.33343177 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 5027554280 ps |
| CPU time | 684.62 seconds |
| Started | Jul 13 08:10:27 PM PDT 24 |
| Finished | Jul 13 08:21:53 PM PDT 24 |
| Peak memory | 649280 kb |
| Host | smart-f8e4aaa4-fc1f-49ac-910c-f7d9dbe7bdff |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 33343177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.33343177 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.253750724 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 5458608520 ps |
| CPU time | 714.19 seconds |
| Started | Jul 13 08:10:35 PM PDT 24 |
| Finished | Jul 13 08:22:30 PM PDT 24 |
| Peak memory | 649832 kb |
| Host | smart-9607daed-8c88-41c3-a0ec-5015db73d1eb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 253750724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.253750724 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.860552502 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 4163842100 ps |
| CPU time | 471.71 seconds |
| Started | Jul 13 08:11:22 PM PDT 24 |
| Finished | Jul 13 08:19:15 PM PDT 24 |
| Peak memory | 648248 kb |
| Host | smart-fb383cea-d38f-415a-b055-3cedb38dfa1b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860552502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_s w_alert_handler_lpg_sleep_mode_alerts.860552502 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.1760671203 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 5138470100 ps |
| CPU time | 730.63 seconds |
| Started | Jul 13 08:11:04 PM PDT 24 |
| Finished | Jul 13 08:23:15 PM PDT 24 |
| Peak memory | 649476 kb |
| Host | smart-70037576-3801-462d-a447-beec25916773 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1760671203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.1760671203 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.787086809 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 3621187880 ps |
| CPU time | 503.57 seconds |
| Started | Jul 13 08:11:23 PM PDT 24 |
| Finished | Jul 13 08:19:47 PM PDT 24 |
| Peak memory | 648172 kb |
| Host | smart-db1fbf23-fe00-4fa3-ab6e-a39fe3101292 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787086809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_s w_alert_handler_lpg_sleep_mode_alerts.787086809 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.2954117999 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 5453676000 ps |
| CPU time | 489.23 seconds |
| Started | Jul 13 08:10:54 PM PDT 24 |
| Finished | Jul 13 08:19:04 PM PDT 24 |
| Peak memory | 649560 kb |
| Host | smart-63d1a7c8-64cf-43f8-a6ff-fa238bf75314 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2954117999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.2954117999 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1919596757 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 3949759246 ps |
| CPU time | 380.84 seconds |
| Started | Jul 13 08:11:04 PM PDT 24 |
| Finished | Jul 13 08:17:26 PM PDT 24 |
| Peak memory | 648188 kb |
| Host | smart-328e42bc-3be2-487e-8861-24190545ceb8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919596757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1919596757 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.1676801260 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 5522310830 ps |
| CPU time | 734.92 seconds |
| Started | Jul 13 08:11:01 PM PDT 24 |
| Finished | Jul 13 08:23:16 PM PDT 24 |
| Peak memory | 649608 kb |
| Host | smart-e7ed9001-6c68-4562-b714-ba950a38e038 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1676801260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.1676801260 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2130602499 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 3891503354 ps |
| CPU time | 453.67 seconds |
| Started | Jul 13 08:12:54 PM PDT 24 |
| Finished | Jul 13 08:20:28 PM PDT 24 |
| Peak memory | 648208 kb |
| Host | smart-a9867ac6-bac5-4777-926f-66282aef84fe |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130602499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2130602499 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.2750069756 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 5422685996 ps |
| CPU time | 643.24 seconds |
| Started | Jul 13 08:11:59 PM PDT 24 |
| Finished | Jul 13 08:22:43 PM PDT 24 |
| Peak memory | 649412 kb |
| Host | smart-21339e3b-89d0-4e53-a0bc-6cc1e9b666ba |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2750069756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.2750069756 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3257123212 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 3460931824 ps |
| CPU time | 371.26 seconds |
| Started | Jul 13 08:13:06 PM PDT 24 |
| Finished | Jul 13 08:19:18 PM PDT 24 |
| Peak memory | 648172 kb |
| Host | smart-f8e7d84d-da27-4b66-9359-704d3c5765d1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257123212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3257123212 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2932549599 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 3763081368 ps |
| CPU time | 420.37 seconds |
| Started | Jul 13 08:12:26 PM PDT 24 |
| Finished | Jul 13 08:19:27 PM PDT 24 |
| Peak memory | 648120 kb |
| Host | smart-cd13a1b6-0c0e-4c77-9cbe-79eaa406cd05 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932549599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2932549599 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.414129969 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 3765041672 ps |
| CPU time | 475.46 seconds |
| Started | Jul 13 08:12:38 PM PDT 24 |
| Finished | Jul 13 08:20:34 PM PDT 24 |
| Peak memory | 648004 kb |
| Host | smart-e8a49fd1-18bc-4e03-b272-306655d1f047 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414129969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_s w_alert_handler_lpg_sleep_mode_alerts.414129969 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.3693784832 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 5679312608 ps |
| CPU time | 638.88 seconds |
| Started | Jul 13 08:12:31 PM PDT 24 |
| Finished | Jul 13 08:23:10 PM PDT 24 |
| Peak memory | 649592 kb |
| Host | smart-4b6e3cb3-78bf-4002-ba2f-3fc4b5478edf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3693784832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.3693784832 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1030856622 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 3874042480 ps |
| CPU time | 357.92 seconds |
| Started | Jul 13 08:15:31 PM PDT 24 |
| Finished | Jul 13 08:21:30 PM PDT 24 |
| Peak memory | 647956 kb |
| Host | smart-c930a97f-c78b-45fb-bf4d-6826218df468 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030856622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1030856622 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.3766573817 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 5244303670 ps |
| CPU time | 935.32 seconds |
| Started | Jul 13 08:11:59 PM PDT 24 |
| Finished | Jul 13 08:27:35 PM PDT 24 |
| Peak memory | 649520 kb |
| Host | smart-077e1873-98d0-4160-87b6-7ab56dafa413 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3766573817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.3766573817 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3034224039 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 4273292500 ps |
| CPU time | 437.96 seconds |
| Started | Jul 13 08:13:22 PM PDT 24 |
| Finished | Jul 13 08:20:41 PM PDT 24 |
| Peak memory | 648180 kb |
| Host | smart-6d732dd9-e2e9-4e5a-b8b8-6d8bdca9b449 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034224039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3034224039 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1465348732 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 3297074388 ps |
| CPU time | 420.71 seconds |
| Started | Jul 13 08:15:25 PM PDT 24 |
| Finished | Jul 13 08:22:27 PM PDT 24 |
| Peak memory | 647984 kb |
| Host | smart-b98310bf-23da-49b5-8dea-fbd7f0e7ad69 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465348732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1465348732 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.556699836 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 5582377250 ps |
| CPU time | 642.3 seconds |
| Started | Jul 13 08:11:12 PM PDT 24 |
| Finished | Jul 13 08:21:54 PM PDT 24 |
| Peak memory | 649636 kb |
| Host | smart-9bfe55d2-3742-4bdf-94b6-cd0737079194 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 556699836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.556699836 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.29515062 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 4050360880 ps |
| CPU time | 474.79 seconds |
| Started | Jul 13 08:13:33 PM PDT 24 |
| Finished | Jul 13 08:21:28 PM PDT 24 |
| Peak memory | 648276 kb |
| Host | smart-0adefdd0-5951-4a69-b0df-74b6f0fd14c9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29515062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw _alert_handler_lpg_sleep_mode_alerts.29515062 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.620243985 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 3817430956 ps |
| CPU time | 384.86 seconds |
| Started | Jul 13 08:12:44 PM PDT 24 |
| Finished | Jul 13 08:19:10 PM PDT 24 |
| Peak memory | 648436 kb |
| Host | smart-1b240beb-be34-42d3-b001-8090f725c57c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620243985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_s w_alert_handler_lpg_sleep_mode_alerts.620243985 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.4286293789 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 4501360880 ps |
| CPU time | 530.13 seconds |
| Started | Jul 13 08:12:42 PM PDT 24 |
| Finished | Jul 13 08:21:32 PM PDT 24 |
| Peak memory | 649720 kb |
| Host | smart-035af4cb-5e68-46f4-afa7-17544be9b977 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4286293789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.4286293789 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.475671706 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 5593694910 ps |
| CPU time | 576.36 seconds |
| Started | Jul 13 08:14:55 PM PDT 24 |
| Finished | Jul 13 08:24:33 PM PDT 24 |
| Peak memory | 649416 kb |
| Host | smart-7bef50e4-9202-4b4c-bc8b-527bd656ee3d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 475671706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.475671706 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.3138095383 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 5937033900 ps |
| CPU time | 711.72 seconds |
| Started | Jul 13 08:13:32 PM PDT 24 |
| Finished | Jul 13 08:25:24 PM PDT 24 |
| Peak memory | 649432 kb |
| Host | smart-012bc549-221a-4dc8-85e7-573096c9b0f3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3138095383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.3138095383 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2913812703 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 3732796600 ps |
| CPU time | 377.39 seconds |
| Started | Jul 13 08:14:15 PM PDT 24 |
| Finished | Jul 13 08:20:33 PM PDT 24 |
| Peak memory | 648328 kb |
| Host | smart-779cafde-0cc4-4641-a8a0-82f90b6d0ee5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913812703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2913812703 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.121593652 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 4441261270 ps |
| CPU time | 458.62 seconds |
| Started | Jul 13 08:12:58 PM PDT 24 |
| Finished | Jul 13 08:20:37 PM PDT 24 |
| Peak memory | 648204 kb |
| Host | smart-07d6c847-7fe1-4867-8af7-a8f8ff5b4030 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121593652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_s w_alert_handler_lpg_sleep_mode_alerts.121593652 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.2228357264 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 4650425680 ps |
| CPU time | 548.97 seconds |
| Started | Jul 13 08:12:03 PM PDT 24 |
| Finished | Jul 13 08:21:12 PM PDT 24 |
| Peak memory | 649784 kb |
| Host | smart-e0ad24f8-0901-4fc8-b767-0de1e68fd64d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2228357264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.2228357264 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.1578417130 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 5273075624 ps |
| CPU time | 511.72 seconds |
| Started | Jul 13 08:12:25 PM PDT 24 |
| Finished | Jul 13 08:20:57 PM PDT 24 |
| Peak memory | 649744 kb |
| Host | smart-d19c1664-2a86-4956-809d-0faadff959d8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1578417130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.1578417130 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3197700780 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 3373907864 ps |
| CPU time | 493.82 seconds |
| Started | Jul 13 08:10:08 PM PDT 24 |
| Finished | Jul 13 08:18:22 PM PDT 24 |
| Peak memory | 648176 kb |
| Host | smart-96524231-7584-4f09-94f6-c51eada90193 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197700780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.3197700780 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.3982892820 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 4470430640 ps |
| CPU time | 523.52 seconds |
| Started | Jul 13 08:08:41 PM PDT 24 |
| Finished | Jul 13 08:17:25 PM PDT 24 |
| Peak memory | 649936 kb |
| Host | smart-7b2583a3-192b-499d-87e0-56ff3a26872e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3982892820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.3982892820 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.568449795 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 5162005648 ps |
| CPU time | 891.49 seconds |
| Started | Jul 13 08:14:52 PM PDT 24 |
| Finished | Jul 13 08:29:44 PM PDT 24 |
| Peak memory | 649868 kb |
| Host | smart-344cffbd-b1d6-4abf-93df-0b6b3da43c96 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 568449795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.568449795 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.932457671 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 5753463728 ps |
| CPU time | 551.44 seconds |
| Started | Jul 13 08:13:47 PM PDT 24 |
| Finished | Jul 13 08:23:00 PM PDT 24 |
| Peak memory | 649632 kb |
| Host | smart-6476c69f-f888-4a84-b00a-78d7469f042a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 932457671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.932457671 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3290563773 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 3993087626 ps |
| CPU time | 370.6 seconds |
| Started | Jul 13 08:13:39 PM PDT 24 |
| Finished | Jul 13 08:19:50 PM PDT 24 |
| Peak memory | 648084 kb |
| Host | smart-40508d5a-a75a-4276-85ae-f8c2ae2ec477 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290563773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3290563773 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.122413838 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 5708158632 ps |
| CPU time | 576.3 seconds |
| Started | Jul 13 08:13:54 PM PDT 24 |
| Finished | Jul 13 08:23:31 PM PDT 24 |
| Peak memory | 649592 kb |
| Host | smart-b081f8f8-747b-4f58-ac1d-08657dfb67bf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 122413838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.122413838 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2908977403 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 4231046362 ps |
| CPU time | 487.1 seconds |
| Started | Jul 13 08:18:26 PM PDT 24 |
| Finished | Jul 13 08:26:34 PM PDT 24 |
| Peak memory | 647940 kb |
| Host | smart-9fb78e4b-d0a6-4aec-b531-054f82bd7b64 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908977403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2908977403 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.3714514425 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 5582285788 ps |
| CPU time | 769.42 seconds |
| Started | Jul 13 08:08:44 PM PDT 24 |
| Finished | Jul 13 08:21:34 PM PDT 24 |
| Peak memory | 649528 kb |
| Host | smart-19d02d21-1479-4704-93d0-4ad44cfd7840 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3714514425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.3714514425 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1425160024 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 3034827002 ps |
| CPU time | 322.33 seconds |
| Started | Jul 13 08:13:52 PM PDT 24 |
| Finished | Jul 13 08:19:15 PM PDT 24 |
| Peak memory | 647960 kb |
| Host | smart-3bd429cf-07d7-43c1-a8f4-5aabfbb06879 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425160024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1425160024 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.4014399984 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 6030824060 ps |
| CPU time | 700.63 seconds |
| Started | Jul 13 08:14:15 PM PDT 24 |
| Finished | Jul 13 08:25:56 PM PDT 24 |
| Peak memory | 649184 kb |
| Host | smart-70f6416d-253a-441e-b2b7-75aa946c8435 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4014399984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.4014399984 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2073494689 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 4005842424 ps |
| CPU time | 447.43 seconds |
| Started | Jul 13 08:14:48 PM PDT 24 |
| Finished | Jul 13 08:22:17 PM PDT 24 |
| Peak memory | 647988 kb |
| Host | smart-470c80d1-daad-44c7-bf3b-bed4d743b4f1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073494689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2073494689 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3752903342 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 3331657664 ps |
| CPU time | 455.16 seconds |
| Started | Jul 13 08:15:18 PM PDT 24 |
| Finished | Jul 13 08:22:54 PM PDT 24 |
| Peak memory | 648056 kb |
| Host | smart-2ab8e60e-70d5-4815-ae7d-1099d9cc5077 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752903342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3752903342 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1465420537 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 4405592144 ps |
| CPU time | 452.21 seconds |
| Started | Jul 13 08:16:13 PM PDT 24 |
| Finished | Jul 13 08:23:46 PM PDT 24 |
| Peak memory | 648588 kb |
| Host | smart-00117e37-d97c-4641-9ed1-4e1f31a81fa1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465420537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1465420537 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.415394121 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 3878437376 ps |
| CPU time | 380.55 seconds |
| Started | Jul 13 08:15:21 PM PDT 24 |
| Finished | Jul 13 08:21:42 PM PDT 24 |
| Peak memory | 648756 kb |
| Host | smart-6548d503-8438-4a90-a050-689ec6d02ec0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415394121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_s w_alert_handler_lpg_sleep_mode_alerts.415394121 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.2938217923 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 5784824056 ps |
| CPU time | 661.51 seconds |
| Started | Jul 13 08:15:07 PM PDT 24 |
| Finished | Jul 13 08:26:09 PM PDT 24 |
| Peak memory | 649520 kb |
| Host | smart-a1eaf24e-ad76-4437-b07b-cf792c534c9c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2938217923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.2938217923 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.2913607104 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 4931070888 ps |
| CPU time | 785.83 seconds |
| Started | Jul 13 08:15:24 PM PDT 24 |
| Finished | Jul 13 08:28:31 PM PDT 24 |
| Peak memory | 649516 kb |
| Host | smart-981a56ac-3f20-4c83-9b76-ec43d7708107 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2913607104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.2913607104 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3099355595 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 4145782416 ps |
| CPU time | 402.48 seconds |
| Started | Jul 13 08:14:57 PM PDT 24 |
| Finished | Jul 13 08:21:40 PM PDT 24 |
| Peak memory | 648112 kb |
| Host | smart-c4670e1d-8cd4-40e3-99ce-e3e21c034c27 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099355595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3099355595 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1339848820 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 3589148660 ps |
| CPU time | 432.65 seconds |
| Started | Jul 13 08:15:25 PM PDT 24 |
| Finished | Jul 13 08:22:38 PM PDT 24 |
| Peak memory | 647848 kb |
| Host | smart-a1498503-35a5-4760-9c54-7fe7a09ecaf3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339848820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1339848820 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2848624276 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 3892846248 ps |
| CPU time | 370.1 seconds |
| Started | Jul 13 08:17:12 PM PDT 24 |
| Finished | Jul 13 08:23:23 PM PDT 24 |
| Peak memory | 648128 kb |
| Host | smart-4a4400a1-5bdc-406a-9744-d467337033bf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848624276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2848624276 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3830437640 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 3930140600 ps |
| CPU time | 502.7 seconds |
| Started | Jul 13 08:10:03 PM PDT 24 |
| Finished | Jul 13 08:18:26 PM PDT 24 |
| Peak memory | 648116 kb |
| Host | smart-9255c10a-6896-40a8-8c62-cd9a18b91e95 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830437640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.3830437640 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.4171097978 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 4136312672 ps |
| CPU time | 475.85 seconds |
| Started | Jul 13 08:17:01 PM PDT 24 |
| Finished | Jul 13 08:24:57 PM PDT 24 |
| Peak memory | 647928 kb |
| Host | smart-6b1cd25d-9fef-4996-9254-2cc22137da9c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171097978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4171097978 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.2686280047 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 4918347840 ps |
| CPU time | 492.48 seconds |
| Started | Jul 13 08:15:33 PM PDT 24 |
| Finished | Jul 13 08:23:46 PM PDT 24 |
| Peak memory | 649476 kb |
| Host | smart-57ffe58c-43e8-4d09-a0a7-2c4d59ee3d2f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2686280047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.2686280047 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2896787769 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 4113835576 ps |
| CPU time | 506.01 seconds |
| Started | Jul 13 08:19:23 PM PDT 24 |
| Finished | Jul 13 08:27:50 PM PDT 24 |
| Peak memory | 648272 kb |
| Host | smart-426ffd15-8d57-48a6-8296-e21633b0eb87 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896787769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2896787769 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.412004303 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 3503596400 ps |
| CPU time | 382 seconds |
| Started | Jul 13 08:18:04 PM PDT 24 |
| Finished | Jul 13 08:24:26 PM PDT 24 |
| Peak memory | 648216 kb |
| Host | smart-b27cf882-ad34-4ebb-9826-7e49882c3ef7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412004303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_s w_alert_handler_lpg_sleep_mode_alerts.412004303 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.2349421571 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 5100035548 ps |
| CPU time | 733.82 seconds |
| Started | Jul 13 08:17:13 PM PDT 24 |
| Finished | Jul 13 08:29:28 PM PDT 24 |
| Peak memory | 649292 kb |
| Host | smart-723665b8-6122-4bff-a6da-58601925c5bd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2349421571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.2349421571 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.4280217113 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 5510675860 ps |
| CPU time | 532.58 seconds |
| Started | Jul 13 08:18:29 PM PDT 24 |
| Finished | Jul 13 08:27:22 PM PDT 24 |
| Peak memory | 649544 kb |
| Host | smart-a01727b8-7362-43d6-81bd-f2b0187035f7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4280217113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.4280217113 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.2029929238 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 3963383412 ps |
| CPU time | 549.86 seconds |
| Started | Jul 13 08:18:02 PM PDT 24 |
| Finished | Jul 13 08:27:13 PM PDT 24 |
| Peak memory | 649048 kb |
| Host | smart-fc6fa406-eb42-491d-9c1c-811c4c7ca002 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2029929238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.2029929238 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.856652404 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4955356440 ps |
| CPU time | 534.77 seconds |
| Started | Jul 13 07:44:24 PM PDT 24 |
| Finished | Jul 13 07:53:20 PM PDT 24 |
| Peak memory | 609860 kb |
| Host | smart-d4f2e730-70bd-4ae5-8e3f-f6e834a35a40 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856652404 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.856652404 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3829346401 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 4073582524 ps |
| CPU time | 703.42 seconds |
| Started | Jul 13 07:44:37 PM PDT 24 |
| Finished | Jul 13 07:56:21 PM PDT 24 |
| Peak memory | 609236 kb |
| Host | smart-12f0a35b-3c65-4526-947d-a32f991b2f59 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829346401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.3829346401 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.203514528 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 3497956362 ps |
| CPU time | 355.47 seconds |
| Started | Jul 13 07:44:27 PM PDT 24 |
| Finished | Jul 13 07:50:25 PM PDT 24 |
| Peak memory | 609120 kb |
| Host | smart-25634fd9-22ca-40dd-887c-65e7d94342ee |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203514528 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.203514528 |
| Directory | /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3116951332 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 7166336700 ps |
| CPU time | 574.09 seconds |
| Started | Jul 13 07:43:56 PM PDT 24 |
| Finished | Jul 13 07:53:31 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-36e2ba7b-8c35-4a08-abb6-ce686c129f53 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3116951332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3116951332 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.1728904183 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 6559968184 ps |
| CPU time | 706.61 seconds |
| Started | Jul 13 08:13:57 PM PDT 24 |
| Finished | Jul 13 08:25:44 PM PDT 24 |
| Peak memory | 598228 kb |
| Host | smart-9d35a5bf-038c-4cbd-a8b0-bb9f568e58b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728904183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.1728904183 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.2923109374 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 4787356120 ps |
| CPU time | 692.89 seconds |
| Started | Jul 13 08:12:44 PM PDT 24 |
| Finished | Jul 13 08:24:18 PM PDT 24 |
| Peak memory | 609924 kb |
| Host | smart-574a7632-d7d7-4c7b-99fa-8878733fe9e3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2923109374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.2923109374 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3119068056 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 4914064984 ps |
| CPU time | 754.27 seconds |
| Started | Jul 13 07:44:41 PM PDT 24 |
| Finished | Jul 13 07:57:17 PM PDT 24 |
| Peak memory | 608612 kb |
| Host | smart-b49531b2-30fe-44e2-999b-fe40d1f07d59 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119068056 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.3119068056 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3673851339 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 6021579136 ps |
| CPU time | 1152.81 seconds |
| Started | Jul 13 07:46:05 PM PDT 24 |
| Finished | Jul 13 08:05:20 PM PDT 24 |
| Peak memory | 608596 kb |
| Host | smart-e9705e80-8b62-43b5-b947-442c0cda4509 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673851339 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.3673851339 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.2385295742 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 3199959400 ps |
| CPU time | 287.95 seconds |
| Started | Jul 13 07:46:02 PM PDT 24 |
| Finished | Jul 13 07:50:53 PM PDT 24 |
| Peak memory | 609224 kb |
| Host | smart-830c32b7-994c-4db2-b2e7-9d40faa06c03 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385295742 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_hmac_enc_idle.2385295742 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1997075732 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2921698591 ps |
| CPU time | 135.45 seconds |
| Started | Jul 13 07:48:15 PM PDT 24 |
| Finished | Jul 13 07:50:31 PM PDT 24 |
| Peak memory | 614388 kb |
| Host | smart-c6e55666-8b8b-4fb1-9a8f-3cce54919ba9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1997075732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.1997075732 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1992431561 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 4480339774 ps |
| CPU time | 577.3 seconds |
| Started | Jul 13 07:49:01 PM PDT 24 |
| Finished | Jul 13 07:58:39 PM PDT 24 |
| Peak memory | 623112 kb |
| Host | smart-e9313af2-6cab-4b87-a313-93d99dc48201 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992431561 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.1992431561 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.527541208 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 6884875288 ps |
| CPU time | 806.08 seconds |
| Started | Jul 13 08:06:41 PM PDT 24 |
| Finished | Jul 13 08:20:07 PM PDT 24 |
| Peak memory | 620380 kb |
| Host | smart-3c55bf63-4736-4867-8529-7b6a1f4fc0bb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=527541208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.527541208 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.3699648509 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 3815901108 ps |
| CPU time | 258.87 seconds |
| Started | Jul 13 08:24:03 PM PDT 24 |
| Finished | Jul 13 08:28:23 PM PDT 24 |
| Peak memory | 603756 kb |
| Host | smart-2bfabe66-fa91-4941-8aef-68d7e2ce0240 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699648509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.3699648509 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.1755411772 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 2558258812 ps |
| CPU time | 176.7 seconds |
| Started | Jul 13 08:28:46 PM PDT 24 |
| Finished | Jul 13 08:31:43 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-3d7cf6fe-0969-4dab-b082-4afeb56b29aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755411772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.1755411772 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2904332279 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 6841667920 ps |
| CPU time | 1526.67 seconds |
| Started | Jul 13 07:50:31 PM PDT 24 |
| Finished | Jul 13 08:16:01 PM PDT 24 |
| Peak memory | 608924 kb |
| Host | smart-24f96976-5936-4d50-80ad-a08a98f79954 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2904332279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.2904332279 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.21867500 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3139072488 ps |
| CPU time | 270.43 seconds |
| Started | Jul 13 07:48:20 PM PDT 24 |
| Finished | Jul 13 07:52:51 PM PDT 24 |
| Peak memory | 608688 kb |
| Host | smart-998c55ad-63a6-44dc-a2df-469cada0faea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21867500 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.21867500 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3539928633 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 4370069243 ps |
| CPU time | 554.49 seconds |
| Started | Jul 13 07:48:21 PM PDT 24 |
| Finished | Jul 13 07:57:38 PM PDT 24 |
| Peak memory | 622992 kb |
| Host | smart-325be91f-9ea5-4e18-8ffa-2629409355c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539928633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3539928633 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1261645982 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 3472949160 ps |
| CPU time | 338.45 seconds |
| Started | Jul 13 08:04:13 PM PDT 24 |
| Finished | Jul 13 08:09:52 PM PDT 24 |
| Peak memory | 608032 kb |
| Host | smart-ccebff22-831a-4450-b64d-08021fb0236e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261645982 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.1261645982 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.841019061 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 11355497043 ps |
| CPU time | 459.69 seconds |
| Started | Jul 13 08:11:15 PM PDT 24 |
| Finished | Jul 13 08:18:55 PM PDT 24 |
| Peak memory | 591428 kb |
| Host | smart-ddfa1643-f013-4351-a074-b4e92f019f00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841019061 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.chip_rv_dm_lc_disabled.841019061 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.924159500 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 17932307240 ps |
| CPU time | 572.93 seconds |
| Started | Jul 13 07:44:08 PM PDT 24 |
| Finished | Jul 13 07:53:43 PM PDT 24 |
| Peak memory | 618292 kb |
| Host | smart-7ca88c60-e183-43dc-9e24-936f5f979618 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=924159500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.924159500 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2878088433 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 5056791948 ps |
| CPU time | 666.9 seconds |
| Started | Jul 13 07:44:23 PM PDT 24 |
| Finished | Jul 13 07:55:31 PM PDT 24 |
| Peak memory | 624500 kb |
| Host | smart-9762f9da-343e-4d20-be50-6358ac410f10 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878088433 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.2878088433 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.113514950 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 2531753472 ps |
| CPU time | 321.98 seconds |
| Started | Jul 13 07:45:55 PM PDT 24 |
| Finished | Jul 13 07:51:19 PM PDT 24 |
| Peak memory | 610600 kb |
| Host | smart-d05c41ab-a6f9-4b25-ba3f-643e482d7d38 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113514950 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.113514950 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.2406711919 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 2551889550 ps |
| CPU time | 276.14 seconds |
| Started | Jul 13 07:46:20 PM PDT 24 |
| Finished | Jul 13 07:50:57 PM PDT 24 |
| Peak memory | 610556 kb |
| Host | smart-9b76ab65-6f2f-4394-95f1-2964bf123f6f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406711919 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.2406711919 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2724921164 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 35979421436 ps |
| CPU time | 7831.48 seconds |
| Started | Jul 13 07:44:34 PM PDT 24 |
| Finished | Jul 13 09:55:09 PM PDT 24 |
| Peak memory | 609952 kb |
| Host | smart-497ef559-8660-44c8-8610-495e95526d53 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724921164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.2724921164 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3340284640 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 5313573500 ps |
| CPU time | 551.01 seconds |
| Started | Jul 13 07:43:43 PM PDT 24 |
| Finished | Jul 13 07:52:55 PM PDT 24 |
| Peak memory | 608996 kb |
| Host | smart-418f1541-58d6-4b1e-b2f9-6e3e7d9fb7a4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33 40284640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.3340284640 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1902657514 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 12672028752 ps |
| CPU time | 2876.69 seconds |
| Started | Jul 13 07:43:28 PM PDT 24 |
| Finished | Jul 13 08:31:27 PM PDT 24 |
| Peak memory | 617200 kb |
| Host | smart-2674a484-d6f5-40fa-bba5-497631d60425 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902 657514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.1902657514 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.955282956 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 5196633560 ps |
| CPU time | 651.07 seconds |
| Started | Jul 13 07:46:57 PM PDT 24 |
| Finished | Jul 13 07:57:49 PM PDT 24 |
| Peak memory | 610272 kb |
| Host | smart-2b6853d0-7d2f-4f65-8ddc-85de23d8ac36 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=955282956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.955282956 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2743389129 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 3208895290 ps |
| CPU time | 483.29 seconds |
| Started | Jul 13 07:46:21 PM PDT 24 |
| Finished | Jul 13 07:54:25 PM PDT 24 |
| Peak memory | 615468 kb |
| Host | smart-cf9d1f67-55f6-441a-8ed4-b8d99e881380 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2743389129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.2743389129 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.4002651952 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 7806802215 ps |
| CPU time | 360.64 seconds |
| Started | Jul 13 08:13:37 PM PDT 24 |
| Finished | Jul 13 08:19:38 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-344aa832-c394-40a6-b7a3-db3c0b00c0f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002651952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.4002651952 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1125188492 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 14327798266 ps |
| CPU time | 774.16 seconds |
| Started | Jul 13 08:13:43 PM PDT 24 |
| Finished | Jul 13 08:26:38 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-a7ac3e73-44bd-4b9c-b167-05e2ad4c67c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125188492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all _with_reset_error.1125188492 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.759919448 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 1276189892 ps |
| CPU time | 62.21 seconds |
| Started | Jul 13 08:19:30 PM PDT 24 |
| Finished | Jul 13 08:20:33 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-82a788b6-9749-4913-aed6-9bcef2bf3426 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759919448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr .759919448 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.2720254029 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 2713317984 ps |
| CPU time | 141.47 seconds |
| Started | Jul 13 08:19:41 PM PDT 24 |
| Finished | Jul 13 08:22:03 PM PDT 24 |
| Peak memory | 598696 kb |
| Host | smart-8629c4b3-c573-4a23-bb6a-55001f8a2b4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720254029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.2720254029 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.3974216899 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 3891774000 ps |
| CPU time | 291.26 seconds |
| Started | Jul 13 08:23:29 PM PDT 24 |
| Finished | Jul 13 08:28:21 PM PDT 24 |
| Peak memory | 598980 kb |
| Host | smart-66b3840e-88e9-4e56-873c-8cbfa51cb533 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974216899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.3974216899 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.3322690260 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 6474508881 ps |
| CPU time | 761.18 seconds |
| Started | Jul 13 08:25:23 PM PDT 24 |
| Finished | Jul 13 08:38:04 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-b478d55c-6448-4d62-932e-19e92ed12c43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322690260 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.3322690260 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.15787985 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 1886244090 ps |
| CPU time | 70.6 seconds |
| Started | Jul 13 08:26:34 PM PDT 24 |
| Finished | Jul 13 08:27:45 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-8c07c2c7-7636-4538-aa4b-1628ec6a8dee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15787985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.15787985 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.2383716947 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 3238579388 ps |
| CPU time | 129.87 seconds |
| Started | Jul 13 08:29:16 PM PDT 24 |
| Finished | Jul 13 08:31:26 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-4b84cd58-084a-48de-881e-86ccd3ed42ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383716947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.2383716947 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.47249860 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 4957667541 ps |
| CPU time | 452.52 seconds |
| Started | Jul 13 08:29:34 PM PDT 24 |
| Finished | Jul 13 08:37:07 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-f0542c2a-cd18-4637-a7cb-5f0e0eb915e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47249860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_ with_reset_error.47249860 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.3507973279 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 288236534 ps |
| CPU time | 27.68 seconds |
| Started | Jul 13 08:33:39 PM PDT 24 |
| Finished | Jul 13 08:34:07 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-1e213ffb-4d13-4b68-adb8-6d6f7dc4bc2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507973279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.3507973279 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.1839702571 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 2388121266 ps |
| CPU time | 249.85 seconds |
| Started | Jul 13 08:35:00 PM PDT 24 |
| Finished | Jul 13 08:39:11 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-42d32336-0999-4c41-a15b-7bca18839501 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839702571 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.1839702571 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.1917381928 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4507476508 ps |
| CPU time | 494.6 seconds |
| Started | Jul 13 07:49:27 PM PDT 24 |
| Finished | Jul 13 07:57:44 PM PDT 24 |
| Peak memory | 609552 kb |
| Host | smart-a9e64c9e-363d-40dc-820b-6e1ff0fc9bc3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917381928 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.1917381928 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3255250526 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 11831524270 ps |
| CPU time | 1705.36 seconds |
| Started | Jul 13 07:48:36 PM PDT 24 |
| Finished | Jul 13 08:17:02 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-54b806a1-4544-4980-8895-13e50dba08ca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3255250526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.3255250526 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2236695727 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 5185264832 ps |
| CPU time | 965.18 seconds |
| Started | Jul 13 07:47:03 PM PDT 24 |
| Finished | Jul 13 08:03:10 PM PDT 24 |
| Peak memory | 608692 kb |
| Host | smart-bbf24e35-6f9e-4cf7-9065-aa1e0e9a9051 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22366 95727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.2236695727 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.2736917862 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 3785849098 ps |
| CPU time | 616.57 seconds |
| Started | Jul 13 08:04:16 PM PDT 24 |
| Finished | Jul 13 08:14:33 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-0c883c91-c9c9-4406-8647-18a08f7779dc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736917862 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.2736917862 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_rma.3133739854 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 2687115420 ps |
| CPU time | 165.42 seconds |
| Started | Jul 13 07:43:38 PM PDT 24 |
| Finished | Jul 13 07:46:26 PM PDT 24 |
| Peak memory | 620224 kb |
| Host | smart-37308313-6a2c-428d-9294-fe576b132cc3 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133739854 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.3133739854 |
| Directory | /workspace/0.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.1843840872 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 3479406344 ps |
| CPU time | 601.75 seconds |
| Started | Jul 13 07:46:13 PM PDT 24 |
| Finished | Jul 13 07:56:16 PM PDT 24 |
| Peak memory | 608828 kb |
| Host | smart-1626f91e-aa9d-49d3-9509-7c349dd3455c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843840872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.1843840872 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2335808755 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 9002417474 ps |
| CPU time | 2289.68 seconds |
| Started | Jul 13 07:46:57 PM PDT 24 |
| Finished | Jul 13 08:25:08 PM PDT 24 |
| Peak memory | 610480 kb |
| Host | smart-80caedd9-3517-491a-ac5b-e118d6658d71 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233580 8755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.2335808755 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2653791381 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 13452698328 ps |
| CPU time | 4189.64 seconds |
| Started | Jul 13 07:47:49 PM PDT 24 |
| Finished | Jul 13 08:57:39 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-901d83c6-1468-4730-bc3a-cf3b777e83b5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26537 91381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.2653791381 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3632728161 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 17196515896 ps |
| CPU time | 3715.23 seconds |
| Started | Jul 13 07:51:21 PM PDT 24 |
| Finished | Jul 13 08:53:18 PM PDT 24 |
| Peak memory | 609852 kb |
| Host | smart-f717a0ea-d9e6-4ee3-8d25-0ffa9cf2f705 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3632728161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.3632728161 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1240741964 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 2913256932 ps |
| CPU time | 122.19 seconds |
| Started | Jul 13 07:51:07 PM PDT 24 |
| Finished | Jul 13 07:53:11 PM PDT 24 |
| Peak memory | 620340 kb |
| Host | smart-19411fd7-72e5-45c7-9c0b-62996549cea3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240741964 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.1240741964 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1185687662 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2417756360 ps |
| CPU time | 265.15 seconds |
| Started | Jul 13 08:06:28 PM PDT 24 |
| Finished | Jul 13 08:10:54 PM PDT 24 |
| Peak memory | 616412 kb |
| Host | smart-567718e7-f1ae-4a3c-bc50-aa4dd074e2d1 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185687662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.1185687662 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1007243111 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 26820199346 ps |
| CPU time | 5666.99 seconds |
| Started | Jul 13 08:09:32 PM PDT 24 |
| Finished | Jul 13 09:44:00 PM PDT 24 |
| Peak memory | 610004 kb |
| Host | smart-878d4210-c3a2-440c-8fa9-8284b6b561cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007243111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.1007243111 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1863325065 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 24587922332 ps |
| CPU time | 6413.16 seconds |
| Started | Jul 13 07:49:09 PM PDT 24 |
| Finished | Jul 13 09:36:04 PM PDT 24 |
| Peak memory | 608892 kb |
| Host | smart-40d1fb82-71fe-4ece-9dfb-39efbf1b445a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1863325065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1863325065 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.684802373 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 54975214152 ps |
| CPU time | 9245.97 seconds |
| Started | Jul 13 08:11:11 PM PDT 24 |
| Finished | Jul 13 10:45:18 PM PDT 24 |
| Peak memory | 633848 kb |
| Host | smart-b8a8880c-f435-48be-b408-b596d2632d65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684802373 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 0.chip_csr_aliasing.684802373 |
| Directory | /workspace/0.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.599322574 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 5520721536 ps |
| CPU time | 599.92 seconds |
| Started | Jul 13 08:11:07 PM PDT 24 |
| Finished | Jul 13 08:21:08 PM PDT 24 |
| Peak memory | 592936 kb |
| Host | smart-8b038d18-bcd2-4bda-a123-0592f15c8516 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599322574 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.599322574 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2843279020 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 4468312507 ps |
| CPU time | 278.29 seconds |
| Started | Jul 13 08:12:39 PM PDT 24 |
| Finished | Jul 13 08:17:18 PM PDT 24 |
| Peak memory | 662708 kb |
| Host | smart-cd336537-58a7-429f-a532-7fa4a40e9063 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843279020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.2843279020 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.709276572 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 5450978728 ps |
| CPU time | 591.41 seconds |
| Started | Jul 13 08:12:36 PM PDT 24 |
| Finished | Jul 13 08:22:28 PM PDT 24 |
| Peak memory | 598764 kb |
| Host | smart-6aae60fc-58e2-4ce2-bb29-56507e0ee8af |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709276572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.709276572 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3823639445 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 7598088448 ps |
| CPU time | 470.16 seconds |
| Started | Jul 13 08:11:26 PM PDT 24 |
| Finished | Jul 13 08:19:17 PM PDT 24 |
| Peak memory | 589996 kb |
| Host | smart-0b402850-3bdf-457e-b88a-f934113170f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823639445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.3823639445 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.942143868 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 31699462283 ps |
| CPU time | 3844.98 seconds |
| Started | Jul 13 08:11:13 PM PDT 24 |
| Finished | Jul 13 09:15:20 PM PDT 24 |
| Peak memory | 593504 kb |
| Host | smart-083ec8da-41da-4eb8-a0a8-709647afbbb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942143868 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.chip_same_csr_outstanding.942143868 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.4191341637 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 1718031123 ps |
| CPU time | 87.2 seconds |
| Started | Jul 13 08:12:04 PM PDT 24 |
| Finished | Jul 13 08:13:32 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-5530027a-c218-4639-8dbc-e2a6405e2036 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191341637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 4191341637 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2476227607 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 202882943 ps |
| CPU time | 27.86 seconds |
| Started | Jul 13 08:12:19 PM PDT 24 |
| Finished | Jul 13 08:12:47 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-fa0dd21c-1e22-4b3b-a96c-f13881cdfdf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476227607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .2476227607 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.4097008251 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 502515715 ps |
| CPU time | 48.7 seconds |
| Started | Jul 13 08:12:19 PM PDT 24 |
| Finished | Jul 13 08:13:09 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-2d206d07-c854-4ce0-a320-1c3390a2567f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097008251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.4097008251 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.3008496685 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 78553072 ps |
| CPU time | 10.79 seconds |
| Started | Jul 13 08:11:28 PM PDT 24 |
| Finished | Jul 13 08:11:40 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-38200c83-4ece-4b45-9f1c-c93b20ca4dd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008496685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.3008496685 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2946140715 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 15675492627 ps |
| CPU time | 199.22 seconds |
| Started | Jul 13 08:12:19 PM PDT 24 |
| Finished | Jul 13 08:15:38 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-f138a5bf-b8d9-4b07-8ced-10d35073288d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946140715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2946140715 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.134616263 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 61920726334 ps |
| CPU time | 1108.99 seconds |
| Started | Jul 13 08:12:15 PM PDT 24 |
| Finished | Jul 13 08:30:44 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-370ef323-9fa8-4a73-9426-c722bb4dd770 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134616263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.134616263 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.81917098 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 535556612 ps |
| CPU time | 50.64 seconds |
| Started | Jul 13 08:11:54 PM PDT 24 |
| Finished | Jul 13 08:12:45 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-120264a9-b218-4d38-9fad-9b6926cd4eac |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81917098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays .81917098 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.2642751442 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 1121719253 ps |
| CPU time | 36.77 seconds |
| Started | Jul 13 08:12:11 PM PDT 24 |
| Finished | Jul 13 08:12:48 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-1c442af7-11f2-43b7-94e8-4aa6ff59a8aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642751442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2642751442 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.3184737923 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 48229704 ps |
| CPU time | 7.42 seconds |
| Started | Jul 13 08:11:28 PM PDT 24 |
| Finished | Jul 13 08:11:36 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-3ea74418-5e8b-46b6-80fa-216ad424f227 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184737923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3184737923 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.4008420197 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 8548309333 ps |
| CPU time | 101.94 seconds |
| Started | Jul 13 08:11:31 PM PDT 24 |
| Finished | Jul 13 08:13:14 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-7cb8e4a4-e2b7-479f-a471-bb97b1b5f671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008420197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.4008420197 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2412661825 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 5731542983 ps |
| CPU time | 102.75 seconds |
| Started | Jul 13 08:11:29 PM PDT 24 |
| Finished | Jul 13 08:13:13 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-b5dd5e1a-cf76-4d51-b926-473a9ad8da18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412661825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2412661825 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3280468349 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 50524035 ps |
| CPU time | 7.13 seconds |
| Started | Jul 13 08:11:26 PM PDT 24 |
| Finished | Jul 13 08:11:34 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-b968c52b-85e8-4ab6-8d02-d8fb6cd1d24c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280468349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .3280468349 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.755979690 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 4974161257 ps |
| CPU time | 242.97 seconds |
| Started | Jul 13 08:12:50 PM PDT 24 |
| Finished | Jul 13 08:16:53 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-efd55418-1bef-4262-b06e-fa33667d4163 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755979690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.755979690 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2901788672 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 3835665119 ps |
| CPU time | 137.7 seconds |
| Started | Jul 13 08:12:20 PM PDT 24 |
| Finished | Jul 13 08:14:38 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-29d9c7cf-3cbf-44c6-a63b-d4c4f3193202 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901788672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.2901788672 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3312301209 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 2360905416 ps |
| CPU time | 289.07 seconds |
| Started | Jul 13 08:12:20 PM PDT 24 |
| Finished | Jul 13 08:17:09 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-2e01708a-957c-4d3b-a772-1c8570fa94f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312301209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_rand_reset.3312301209 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1346609012 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 36215467 ps |
| CPU time | 8.42 seconds |
| Started | Jul 13 08:12:14 PM PDT 24 |
| Finished | Jul 13 08:12:22 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-9d8e07e5-b820-481f-8937-7a71347eef83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346609012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1346609012 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2233926968 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 30961154014 ps |
| CPU time | 5012.58 seconds |
| Started | Jul 13 08:12:59 PM PDT 24 |
| Finished | Jul 13 09:36:32 PM PDT 24 |
| Peak memory | 593912 kb |
| Host | smart-7404d16d-9211-4a4b-8f08-b8a218e1eb4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233926968 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.chip_csr_aliasing.2233926968 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2348349953 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 8388548528 ps |
| CPU time | 1102.44 seconds |
| Started | Jul 13 08:12:42 PM PDT 24 |
| Finished | Jul 13 08:31:05 PM PDT 24 |
| Peak memory | 590564 kb |
| Host | smart-f4f4f1ad-5d0c-4f38-b6a7-12afed47598a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348349953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.2348349953 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1159085345 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 6593261432 ps |
| CPU time | 427.2 seconds |
| Started | Jul 13 08:13:45 PM PDT 24 |
| Finished | Jul 13 08:20:53 PM PDT 24 |
| Peak memory | 661684 kb |
| Host | smart-9ec1d93b-4bfc-4eb6-898c-13b778d2013d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159085345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r eset.1159085345 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.313969449 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 15024234126 ps |
| CPU time | 561.8 seconds |
| Started | Jul 13 08:12:55 PM PDT 24 |
| Finished | Jul 13 08:22:17 PM PDT 24 |
| Peak memory | 590084 kb |
| Host | smart-076b17b5-0864-4ebd-a41c-b5c9ccb2a106 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313969449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 .chip_prim_tl_access.313969449 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2611394277 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 8390946394 ps |
| CPU time | 439.98 seconds |
| Started | Jul 13 08:12:59 PM PDT 24 |
| Finished | Jul 13 08:20:20 PM PDT 24 |
| Peak memory | 591448 kb |
| Host | smart-7c769992-4676-4c16-bab8-c9620d7f6f77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611394277 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.2611394277 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.768213106 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 30783820702 ps |
| CPU time | 3172.35 seconds |
| Started | Jul 13 08:12:49 PM PDT 24 |
| Finished | Jul 13 09:05:42 PM PDT 24 |
| Peak memory | 593180 kb |
| Host | smart-0d1e426b-48ca-4b90-a6ad-c258521d904e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768213106 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 1.chip_same_csr_outstanding.768213106 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.1456423398 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 3163935648 ps |
| CPU time | 188.59 seconds |
| Started | Jul 13 08:12:50 PM PDT 24 |
| Finished | Jul 13 08:15:59 PM PDT 24 |
| Peak memory | 603792 kb |
| Host | smart-899c2007-1c3c-4b26-9f5a-335f64730efb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456423398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.1456423398 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.1671104082 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 1473914649 ps |
| CPU time | 75.5 seconds |
| Started | Jul 13 08:13:24 PM PDT 24 |
| Finished | Jul 13 08:14:41 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-7614c6a6-189c-4fef-8846-5bb49a0bc4a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671104082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device. 1671104082 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2393284137 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 24172936399 ps |
| CPU time | 473.18 seconds |
| Started | Jul 13 08:13:13 PM PDT 24 |
| Finished | Jul 13 08:21:07 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-c6110ffb-0ccf-4565-a07a-ef428ea6f084 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393284137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.2393284137 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.522697846 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 75842258 ps |
| CPU time | 6.97 seconds |
| Started | Jul 13 08:13:35 PM PDT 24 |
| Finished | Jul 13 08:13:42 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-e1ac5f74-3faa-48dd-94f5-28f53723c894 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522697846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr. 522697846 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.1343031347 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 2454586266 ps |
| CPU time | 107.24 seconds |
| Started | Jul 13 08:13:25 PM PDT 24 |
| Finished | Jul 13 08:15:13 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-088bb55d-09e2-4135-b5c0-06c29017329b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343031347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1343031347 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.3653151383 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 2403719320 ps |
| CPU time | 97.69 seconds |
| Started | Jul 13 08:12:59 PM PDT 24 |
| Finished | Jul 13 08:14:37 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-c27f8264-67bb-48a0-ad24-fc7664e1d862 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653151383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.3653151383 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.229935284 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 17887776819 ps |
| CPU time | 212.31 seconds |
| Started | Jul 13 08:13:13 PM PDT 24 |
| Finished | Jul 13 08:16:46 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-e461112f-8bd4-47cc-892c-fd5d186a531a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229935284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.229935284 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.298674148 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 16894167121 ps |
| CPU time | 315.3 seconds |
| Started | Jul 13 08:13:11 PM PDT 24 |
| Finished | Jul 13 08:18:26 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-51be9265-21a6-429d-9417-2cc45f079e49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298674148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.298674148 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.115452841 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 304201657 ps |
| CPU time | 31.53 seconds |
| Started | Jul 13 08:12:58 PM PDT 24 |
| Finished | Jul 13 08:13:30 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-7d091853-0c61-4196-a409-8edc24abef76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115452841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delay s.115452841 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.381384612 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 2614459742 ps |
| CPU time | 100.8 seconds |
| Started | Jul 13 08:13:26 PM PDT 24 |
| Finished | Jul 13 08:15:08 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-cff04739-f1c3-4cdf-8a59-36ed2ec272a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381384612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.381384612 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.2933192012 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 58402956 ps |
| CPU time | 7.86 seconds |
| Started | Jul 13 08:12:54 PM PDT 24 |
| Finished | Jul 13 08:13:02 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-bb303d43-7b11-48f1-bf15-18c1abaaf2a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933192012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2933192012 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.4114004620 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 8507421103 ps |
| CPU time | 100.94 seconds |
| Started | Jul 13 08:12:49 PM PDT 24 |
| Finished | Jul 13 08:14:30 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-a4c93187-1978-4942-95be-468af5d4abd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114004620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.4114004620 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3813645079 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 5576553571 ps |
| CPU time | 103.37 seconds |
| Started | Jul 13 08:12:55 PM PDT 24 |
| Finished | Jul 13 08:14:39 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-f539de66-42e3-4cb1-8f47-4415f22ba625 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813645079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3813645079 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1395694952 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 44192944 ps |
| CPU time | 7.03 seconds |
| Started | Jul 13 08:12:48 PM PDT 24 |
| Finished | Jul 13 08:12:56 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-a4c2169c-80cf-4621-9abc-6cdc44b0ceb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395694952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays .1395694952 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1529400314 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 10358568064 ps |
| CPU time | 453.57 seconds |
| Started | Jul 13 08:13:53 PM PDT 24 |
| Finished | Jul 13 08:21:27 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-a01029b3-c619-40ae-ba8c-9fe6fbc83d6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529400314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1529400314 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2615395244 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 429849552 ps |
| CPU time | 234.62 seconds |
| Started | Jul 13 08:13:37 PM PDT 24 |
| Finished | Jul 13 08:17:32 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-6f0c80ff-62a7-4337-93b3-f0d660aeb805 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615395244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.2615395244 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.160029848 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 35485528 ps |
| CPU time | 8.16 seconds |
| Started | Jul 13 08:13:37 PM PDT 24 |
| Finished | Jul 13 08:13:45 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-7bb4516a-e95a-42fe-9bcd-9aabe709e852 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160029848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.160029848 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.1314750794 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 5473567428 ps |
| CPU time | 720.51 seconds |
| Started | Jul 13 08:19:12 PM PDT 24 |
| Finished | Jul 13 08:31:13 PM PDT 24 |
| Peak memory | 598968 kb |
| Host | smart-491a633a-ab7f-4d32-beb3-1ecaa511a14f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314750794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.1314750794 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1252825761 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 31664017861 ps |
| CPU time | 3800.33 seconds |
| Started | Jul 13 08:18:46 PM PDT 24 |
| Finished | Jul 13 09:22:07 PM PDT 24 |
| Peak memory | 593620 kb |
| Host | smart-cff62e98-e14a-45f0-9eee-c53c6b7af449 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252825761 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.1252825761 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.1927285254 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 3997351960 ps |
| CPU time | 271.01 seconds |
| Started | Jul 13 08:18:45 PM PDT 24 |
| Finished | Jul 13 08:23:17 PM PDT 24 |
| Peak memory | 598628 kb |
| Host | smart-f9099df0-3609-4b1a-bc77-d5cc21b5f353 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927285254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.1927285254 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.1204758557 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 579951736 ps |
| CPU time | 25.67 seconds |
| Started | Jul 13 08:18:54 PM PDT 24 |
| Finished | Jul 13 08:19:20 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-d72f4a90-efea-431f-96bc-510969c2e3e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204758557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .1204758557 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.4048848284 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 112144265660 ps |
| CPU time | 2252.54 seconds |
| Started | Jul 13 08:18:52 PM PDT 24 |
| Finished | Jul 13 08:56:26 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-9af10c8f-d53d-4a43-830b-92482c4d80c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048848284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.4048848284 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1294029010 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 139558504 ps |
| CPU time | 10.23 seconds |
| Started | Jul 13 08:19:01 PM PDT 24 |
| Finished | Jul 13 08:19:12 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-e1c8d338-2000-4e8e-836d-e5e0ec1da636 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294029010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add r.1294029010 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.3946850054 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 182707686 ps |
| CPU time | 10.62 seconds |
| Started | Jul 13 08:18:56 PM PDT 24 |
| Finished | Jul 13 08:19:08 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-ccc5fb55-1d43-45da-bde1-46d0dff75bed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946850054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3946850054 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.3161752335 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 340106014 ps |
| CPU time | 16.8 seconds |
| Started | Jul 13 08:18:53 PM PDT 24 |
| Finished | Jul 13 08:19:11 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-3b1c172f-f781-4974-86d9-0872c523c4f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161752335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.3161752335 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1793118417 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 77737695777 ps |
| CPU time | 933.76 seconds |
| Started | Jul 13 08:18:58 PM PDT 24 |
| Finished | Jul 13 08:34:32 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-c3b65879-0935-4da2-af03-e07823d096e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793118417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1793118417 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.250673013 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 67197724238 ps |
| CPU time | 1262.01 seconds |
| Started | Jul 13 08:18:53 PM PDT 24 |
| Finished | Jul 13 08:39:55 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-fdeb0df2-dda1-4b1d-ae98-733720519656 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250673013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.250673013 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1035919348 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 467729930 ps |
| CPU time | 38.46 seconds |
| Started | Jul 13 08:18:53 PM PDT 24 |
| Finished | Jul 13 08:19:32 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-1d090abf-cddd-4926-9fde-cf3a5139091e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035919348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_del ays.1035919348 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.2918723492 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 1570000820 ps |
| CPU time | 55.42 seconds |
| Started | Jul 13 08:18:53 PM PDT 24 |
| Finished | Jul 13 08:19:49 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-8a460968-867c-478a-b5da-c1b238b228ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918723492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2918723492 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.2122200214 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 135423667 ps |
| CPU time | 8.67 seconds |
| Started | Jul 13 08:18:43 PM PDT 24 |
| Finished | Jul 13 08:18:52 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-d7949af0-287e-4730-b28f-2918787392d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122200214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2122200214 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.341204867 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 5652823804 ps |
| CPU time | 66.29 seconds |
| Started | Jul 13 08:18:52 PM PDT 24 |
| Finished | Jul 13 08:19:59 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-5ed1a500-90e2-41a6-961e-008713f8d6c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341204867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.341204867 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1861522682 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 5967567453 ps |
| CPU time | 108.7 seconds |
| Started | Jul 13 08:18:53 PM PDT 24 |
| Finished | Jul 13 08:20:42 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-956d8892-04a0-4dd6-a869-e131a6d37304 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861522682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.1861522682 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3523827423 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 57990259 ps |
| CPU time | 8.12 seconds |
| Started | Jul 13 08:18:43 PM PDT 24 |
| Finished | Jul 13 08:18:52 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-d34b92bb-a5dd-420c-a6b9-36e00ef0311a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523827423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.3523827423 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.1163520730 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 2084762451 ps |
| CPU time | 183.28 seconds |
| Started | Jul 13 08:19:06 PM PDT 24 |
| Finished | Jul 13 08:22:10 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-6f233185-3e8c-459b-9817-1a72f8be73f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163520730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1163520730 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.433680999 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 8271077046 ps |
| CPU time | 331.39 seconds |
| Started | Jul 13 08:19:06 PM PDT 24 |
| Finished | Jul 13 08:24:38 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-4675b9ac-9904-4c6a-a4b5-e8f816af5416 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433680999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.433680999 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1157746152 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 330668900 ps |
| CPU time | 110.49 seconds |
| Started | Jul 13 08:19:02 PM PDT 24 |
| Finished | Jul 13 08:20:53 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-e22bfbaa-a3e8-47a9-ba1f-f84d1ae80ec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157746152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_rand_reset.1157746152 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.207173862 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 796248680 ps |
| CPU time | 221.69 seconds |
| Started | Jul 13 08:19:01 PM PDT 24 |
| Finished | Jul 13 08:22:43 PM PDT 24 |
| Peak memory | 575188 kb |
| Host | smart-85f9e5ea-f67c-4fa6-87c0-8f5aa80ee73e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207173862 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_reset_error.207173862 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1394640432 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 1082448318 ps |
| CPU time | 49.66 seconds |
| Started | Jul 13 08:19:01 PM PDT 24 |
| Finished | Jul 13 08:19:51 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-cfbcc91a-3cea-4ad8-a44c-9a3e65250efb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394640432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1394640432 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.3233701832 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 6002635720 ps |
| CPU time | 653.81 seconds |
| Started | Jul 13 08:19:30 PM PDT 24 |
| Finished | Jul 13 08:30:25 PM PDT 24 |
| Peak memory | 597088 kb |
| Host | smart-b6819e21-f6ba-4187-ac0e-238ddc06aac0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233701832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.3233701832 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2418322808 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 15848383416 ps |
| CPU time | 1906.31 seconds |
| Started | Jul 13 08:19:11 PM PDT 24 |
| Finished | Jul 13 08:50:58 PM PDT 24 |
| Peak memory | 592804 kb |
| Host | smart-b5a7287a-f979-4c9c-b000-bcdd1a85a392 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418322808 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.2418322808 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.4050339323 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 3944945740 ps |
| CPU time | 252.45 seconds |
| Started | Jul 13 08:19:14 PM PDT 24 |
| Finished | Jul 13 08:23:26 PM PDT 24 |
| Peak memory | 598656 kb |
| Host | smart-d06725df-f210-4e5a-9ce0-4f324f10a01a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050339323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.4050339323 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.2139561193 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1692179893 ps |
| CPU time | 91.71 seconds |
| Started | Jul 13 08:19:30 PM PDT 24 |
| Finished | Jul 13 08:21:02 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-0f9a24ca-8836-4d73-96ef-04430d4a42c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139561193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device .2139561193 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3330227686 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 5334686629 ps |
| CPU time | 106.71 seconds |
| Started | Jul 13 08:19:31 PM PDT 24 |
| Finished | Jul 13 08:21:19 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-5af0668d-f643-427e-807d-025a717acdfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330227686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.3330227686 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.695704003 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 603457443 ps |
| CPU time | 59.06 seconds |
| Started | Jul 13 08:19:29 PM PDT 24 |
| Finished | Jul 13 08:20:29 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-4bd115d0-6b91-471b-88ce-6699f5dc9a37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695704003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.695704003 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.1300993358 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 1262379307 ps |
| CPU time | 50.87 seconds |
| Started | Jul 13 08:19:22 PM PDT 24 |
| Finished | Jul 13 08:20:13 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-eae41996-e9a6-4d4f-bd9b-0b73e720fb3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300993358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.1300993358 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1756063539 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 11992149448 ps |
| CPU time | 141.25 seconds |
| Started | Jul 13 08:19:30 PM PDT 24 |
| Finished | Jul 13 08:21:53 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-d7b4cc6f-ff46-4235-a357-0240a0bbcb38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756063539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1756063539 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.4223808312 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 54000540503 ps |
| CPU time | 1051.4 seconds |
| Started | Jul 13 08:19:30 PM PDT 24 |
| Finished | Jul 13 08:37:03 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-c8b23612-47a7-4153-92e0-f1ac5086585d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223808312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.4223808312 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.317674540 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 161069389 ps |
| CPU time | 18.89 seconds |
| Started | Jul 13 08:19:23 PM PDT 24 |
| Finished | Jul 13 08:19:42 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-3e4e2780-46c1-4bdf-b2b8-1aa8101f2934 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317674540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_dela ys.317674540 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.3817204129 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 1952205548 ps |
| CPU time | 60.9 seconds |
| Started | Jul 13 08:19:29 PM PDT 24 |
| Finished | Jul 13 08:20:31 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-851173ce-0843-48be-853c-b96e32a24c93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817204129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3817204129 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.3473599495 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 46744597 ps |
| CPU time | 6.3 seconds |
| Started | Jul 13 08:19:21 PM PDT 24 |
| Finished | Jul 13 08:19:27 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-cb986483-164b-40c9-a620-578422189b62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473599495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3473599495 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.953986074 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 7031782270 ps |
| CPU time | 84.02 seconds |
| Started | Jul 13 08:19:20 PM PDT 24 |
| Finished | Jul 13 08:20:44 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-26b50ed8-cc82-417e-9ca3-c064cbb86ca5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953986074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.953986074 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.605039077 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 5974412963 ps |
| CPU time | 117.84 seconds |
| Started | Jul 13 08:19:23 PM PDT 24 |
| Finished | Jul 13 08:21:21 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-9eea1c5f-4bd1-46e3-b2be-17ce9a75b569 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605039077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.605039077 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2196124793 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 45476254 ps |
| CPU time | 7.19 seconds |
| Started | Jul 13 08:19:21 PM PDT 24 |
| Finished | Jul 13 08:19:28 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-03394a1c-9229-4e26-8a6f-85be5234675b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196124793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.2196124793 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.1888597777 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 11116570625 ps |
| CPU time | 446.2 seconds |
| Started | Jul 13 08:19:29 PM PDT 24 |
| Finished | Jul 13 08:26:56 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-0a767b73-af63-4b1b-9900-f5a0ebd00156 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888597777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1888597777 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2832709763 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 3623668060 ps |
| CPU time | 306.26 seconds |
| Started | Jul 13 08:19:30 PM PDT 24 |
| Finished | Jul 13 08:24:37 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-f9d8ffb3-5cc0-46be-8dd7-ce1a747d5fa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832709763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2832709763 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2326447145 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 3050645111 ps |
| CPU time | 198.19 seconds |
| Started | Jul 13 08:19:30 PM PDT 24 |
| Finished | Jul 13 08:22:50 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-e97b2c62-a66b-48a9-8494-ec257176a83e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326447145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.2326447145 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1755592763 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 1923435835 ps |
| CPU time | 297.03 seconds |
| Started | Jul 13 08:19:29 PM PDT 24 |
| Finished | Jul 13 08:24:27 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-d901afd5-ac3f-41b0-8d0f-1a7006a886ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755592763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.1755592763 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1961699486 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 1182992195 ps |
| CPU time | 45.63 seconds |
| Started | Jul 13 08:19:30 PM PDT 24 |
| Finished | Jul 13 08:20:17 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-1f5336bc-31dc-4a0a-9132-bcf382a620f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961699486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1961699486 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.732388682 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 4386030832 ps |
| CPU time | 397.05 seconds |
| Started | Jul 13 08:19:58 PM PDT 24 |
| Finished | Jul 13 08:26:36 PM PDT 24 |
| Peak memory | 597616 kb |
| Host | smart-7d8f87e8-88ee-4fcb-83f9-89e18284639d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732388682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.732388682 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.979457004 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 29516967794 ps |
| CPU time | 3000.88 seconds |
| Started | Jul 13 08:19:39 PM PDT 24 |
| Finished | Jul 13 09:09:41 PM PDT 24 |
| Peak memory | 593548 kb |
| Host | smart-6927edb5-b299-4813-959e-82d29ddcf76a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979457004 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 12.chip_same_csr_outstanding.979457004 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.103545278 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 2971709205 ps |
| CPU time | 125.71 seconds |
| Started | Jul 13 08:19:50 PM PDT 24 |
| Finished | Jul 13 08:21:56 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-9967a6d2-73c4-4342-a2b9-d0e5e127a49f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103545278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device. 103545278 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.87343164 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 80657619351 ps |
| CPU time | 1447.96 seconds |
| Started | Jul 13 08:19:50 PM PDT 24 |
| Finished | Jul 13 08:43:59 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-b1924e4e-909b-4692-a570-5219c527d637 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87343164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_de vice_slow_rsp.87343164 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3999251768 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 844446618 ps |
| CPU time | 36.39 seconds |
| Started | Jul 13 08:19:57 PM PDT 24 |
| Finished | Jul 13 08:20:34 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-0799521e-d91a-46dc-a3e8-978397bcd61c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999251768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.3999251768 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.1902731557 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 438889666 ps |
| CPU time | 41.81 seconds |
| Started | Jul 13 08:19:56 PM PDT 24 |
| Finished | Jul 13 08:20:38 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-9bc6071e-fa56-4afe-aeae-5d39bd9bd127 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902731557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1902731557 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.815147573 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 1462057392 ps |
| CPU time | 45.93 seconds |
| Started | Jul 13 08:19:49 PM PDT 24 |
| Finished | Jul 13 08:20:35 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-6034a70b-549a-4598-bdbd-69b3e5f4212d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815147573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.815147573 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2727006132 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 4025691138 ps |
| CPU time | 48.92 seconds |
| Started | Jul 13 08:19:49 PM PDT 24 |
| Finished | Jul 13 08:20:38 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-ee61cd75-66a7-47b4-b39f-37b126d144d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727006132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2727006132 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2782797712 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 24907349805 ps |
| CPU time | 462.28 seconds |
| Started | Jul 13 08:19:51 PM PDT 24 |
| Finished | Jul 13 08:27:33 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-8f18628b-348b-4a3d-9e8b-56acb17491b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782797712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2782797712 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3855189149 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 417666620 ps |
| CPU time | 39.07 seconds |
| Started | Jul 13 08:19:50 PM PDT 24 |
| Finished | Jul 13 08:20:30 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-8e50f323-b7f0-44d4-8b0a-aca3a21d6e3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855189149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del ays.3855189149 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.3106449990 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 564916900 ps |
| CPU time | 45.9 seconds |
| Started | Jul 13 08:19:58 PM PDT 24 |
| Finished | Jul 13 08:20:44 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-99ea2643-f9e8-4762-9965-3783df3518f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106449990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3106449990 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.2380655353 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 42665888 ps |
| CPU time | 6.67 seconds |
| Started | Jul 13 08:19:39 PM PDT 24 |
| Finished | Jul 13 08:19:46 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-283bf077-ab24-48bb-943d-7391f9adaf5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380655353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2380655353 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1988785644 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 6897011273 ps |
| CPU time | 81.53 seconds |
| Started | Jul 13 08:19:40 PM PDT 24 |
| Finished | Jul 13 08:21:02 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-938425e4-4dd6-4961-8a0b-f411dd0308aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988785644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1988785644 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3593825760 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 4513489666 ps |
| CPU time | 80.67 seconds |
| Started | Jul 13 08:19:38 PM PDT 24 |
| Finished | Jul 13 08:21:00 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-33c2e2be-d02b-44a0-ae9f-1d44d0628028 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593825760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3593825760 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3559483358 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 46289411 ps |
| CPU time | 6.79 seconds |
| Started | Jul 13 08:19:41 PM PDT 24 |
| Finished | Jul 13 08:19:48 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-c31ac759-f1e1-4f3e-9a8e-6b0cef08545c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559483358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay s.3559483358 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.529167368 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1506738037 ps |
| CPU time | 172.27 seconds |
| Started | Jul 13 08:19:57 PM PDT 24 |
| Finished | Jul 13 08:22:50 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-a8f6fd40-8f20-408e-a901-3d287db78808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529167368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.529167368 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3201700190 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 901251394 ps |
| CPU time | 83.14 seconds |
| Started | Jul 13 08:19:58 PM PDT 24 |
| Finished | Jul 13 08:21:22 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-e6ab8755-38b8-478d-a3d6-28eaf23520bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201700190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3201700190 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1055903283 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 2470740267 ps |
| CPU time | 118.41 seconds |
| Started | Jul 13 08:19:57 PM PDT 24 |
| Finished | Jul 13 08:21:56 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-4aab2338-9080-40d6-9309-9c6982cfc838 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055903283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.1055903283 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2270585259 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 1014337732 ps |
| CPU time | 54.47 seconds |
| Started | Jul 13 08:19:57 PM PDT 24 |
| Finished | Jul 13 08:20:52 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-9feae209-3025-4d49-b08f-07a2d3dbc5fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270585259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2270585259 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.3311169406 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 4230633906 ps |
| CPU time | 330.39 seconds |
| Started | Jul 13 08:20:28 PM PDT 24 |
| Finished | Jul 13 08:25:58 PM PDT 24 |
| Peak memory | 597128 kb |
| Host | smart-568e154c-a5cf-422f-b3dd-26436735baa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311169406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.3311169406 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.4150212791 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 14933546449 ps |
| CPU time | 1736.92 seconds |
| Started | Jul 13 08:20:12 PM PDT 24 |
| Finished | Jul 13 08:49:09 PM PDT 24 |
| Peak memory | 593140 kb |
| Host | smart-61418a4a-6469-4036-88e9-7e11708227bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150212791 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.4150212791 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.3886662869 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 4721140865 ps |
| CPU time | 452.41 seconds |
| Started | Jul 13 08:20:13 PM PDT 24 |
| Finished | Jul 13 08:27:46 PM PDT 24 |
| Peak memory | 604156 kb |
| Host | smart-31e85e03-1db1-486b-8e97-2e20cec3eb65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886662869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.3886662869 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.3174496100 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 2591414166 ps |
| CPU time | 110.6 seconds |
| Started | Jul 13 08:20:14 PM PDT 24 |
| Finished | Jul 13 08:22:05 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-27c2d849-d223-4b24-babf-7bcfb33a5dcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174496100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device .3174496100 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1426363090 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 66693551695 ps |
| CPU time | 1117.43 seconds |
| Started | Jul 13 08:20:14 PM PDT 24 |
| Finished | Jul 13 08:38:52 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-2c11152e-f221-4624-9966-7905c26b66b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426363090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_ device_slow_rsp.1426363090 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2791003222 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 318861017 ps |
| CPU time | 37.57 seconds |
| Started | Jul 13 08:20:15 PM PDT 24 |
| Finished | Jul 13 08:20:53 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-789b6d02-d017-43a4-ad00-a21ccfe4d3cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791003222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.2791003222 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.717073527 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 2210955120 ps |
| CPU time | 82.83 seconds |
| Started | Jul 13 08:20:15 PM PDT 24 |
| Finished | Jul 13 08:21:38 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-c446ee63-44c0-4d25-aad3-2d109494ae38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717073527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.717073527 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.2253738008 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 485948454 ps |
| CPU time | 41.54 seconds |
| Started | Jul 13 08:20:11 PM PDT 24 |
| Finished | Jul 13 08:20:53 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-766468df-f400-4bc3-8dce-9215e64516d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253738008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.2253738008 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2110870842 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 52085648617 ps |
| CPU time | 582.7 seconds |
| Started | Jul 13 08:20:14 PM PDT 24 |
| Finished | Jul 13 08:29:57 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-ff7dbacf-0ffd-421c-aa4c-300a9ea34035 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110870842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2110870842 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.227784031 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 44035946941 ps |
| CPU time | 805.72 seconds |
| Started | Jul 13 08:20:12 PM PDT 24 |
| Finished | Jul 13 08:33:38 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-caa66527-c1c1-42f8-a14e-bcb78654cec0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227784031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.227784031 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3283863352 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 450252937 ps |
| CPU time | 47.77 seconds |
| Started | Jul 13 08:20:13 PM PDT 24 |
| Finished | Jul 13 08:21:01 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-ad43b5ba-2336-4c33-be23-2072e21dde8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283863352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.3283863352 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.2116812184 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 688845287 ps |
| CPU time | 30.05 seconds |
| Started | Jul 13 08:20:16 PM PDT 24 |
| Finished | Jul 13 08:20:47 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-e955f9db-efd0-4950-ad38-f436d9969768 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116812184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2116812184 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.2103262823 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 211681110 ps |
| CPU time | 9.81 seconds |
| Started | Jul 13 08:20:12 PM PDT 24 |
| Finished | Jul 13 08:20:22 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-d7282525-ce5b-4043-a9d1-fafb84cdf18f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103262823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2103262823 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2668671178 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 7850025718 ps |
| CPU time | 92.47 seconds |
| Started | Jul 13 08:20:11 PM PDT 24 |
| Finished | Jul 13 08:21:43 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-309bc2dc-99b7-4131-a067-6b9303d6a32c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668671178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2668671178 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.906572264 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 5627647754 ps |
| CPU time | 109.76 seconds |
| Started | Jul 13 08:20:14 PM PDT 24 |
| Finished | Jul 13 08:22:04 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-6fd1c9f7-4e35-41e5-bb90-0810695791b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906572264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.906572264 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3822212320 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 47637004 ps |
| CPU time | 6.86 seconds |
| Started | Jul 13 08:20:12 PM PDT 24 |
| Finished | Jul 13 08:20:19 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-0671d1d4-0899-4e88-84fb-12b4d5c51531 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822212320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay s.3822212320 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.3826193060 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 16246153305 ps |
| CPU time | 675.42 seconds |
| Started | Jul 13 08:20:18 PM PDT 24 |
| Finished | Jul 13 08:31:34 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-6eb6492a-dc7b-4b23-8dac-58bf6ca65f69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826193060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3826193060 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.1042228711 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 5468883480 ps |
| CPU time | 216.34 seconds |
| Started | Jul 13 08:20:16 PM PDT 24 |
| Finished | Jul 13 08:23:53 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-acb32289-31aa-443a-bfd3-d93c3e5dc1d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042228711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1042228711 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.536535704 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 773890456 ps |
| CPU time | 244.97 seconds |
| Started | Jul 13 08:20:16 PM PDT 24 |
| Finished | Jul 13 08:24:21 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-4c89f41d-4aca-4c18-abce-28e3b8b50336 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536535704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_reset_error.536535704 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1758742817 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 283000925 ps |
| CPU time | 35.72 seconds |
| Started | Jul 13 08:20:17 PM PDT 24 |
| Finished | Jul 13 08:20:53 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-54a3ad58-d04a-46a2-8758-87d7157506c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758742817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1758742817 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.1972146807 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 5762080200 ps |
| CPU time | 580.49 seconds |
| Started | Jul 13 08:20:40 PM PDT 24 |
| Finished | Jul 13 08:30:21 PM PDT 24 |
| Peak memory | 598860 kb |
| Host | smart-40f7383b-84e9-4296-a708-968f8aef30fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972146807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.1972146807 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.591236208 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 31314861772 ps |
| CPU time | 3852.27 seconds |
| Started | Jul 13 08:20:25 PM PDT 24 |
| Finished | Jul 13 09:24:38 PM PDT 24 |
| Peak memory | 593304 kb |
| Host | smart-79144279-febd-4e64-8cd9-7d8ad9759ca9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591236208 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 14.chip_same_csr_outstanding.591236208 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.668028230 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 2051896092 ps |
| CPU time | 100.33 seconds |
| Started | Jul 13 08:20:25 PM PDT 24 |
| Finished | Jul 13 08:22:06 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-69497009-1022-4b2f-b8f4-b04bd07ca8ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668028230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device. 668028230 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.211159466 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 69045690564 ps |
| CPU time | 1361.28 seconds |
| Started | Jul 13 08:20:40 PM PDT 24 |
| Finished | Jul 13 08:43:21 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-f7de90cf-1fc3-4c63-8fe4-7c6d1147df9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211159466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_d evice_slow_rsp.211159466 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3412618089 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 152279332 ps |
| CPU time | 21.52 seconds |
| Started | Jul 13 08:20:39 PM PDT 24 |
| Finished | Jul 13 08:21:01 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-2b72cb1f-408c-49ba-9969-f76243705466 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412618089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add r.3412618089 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.465685147 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 825233019 ps |
| CPU time | 32.65 seconds |
| Started | Jul 13 08:20:37 PM PDT 24 |
| Finished | Jul 13 08:21:11 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-2afd26f3-67c5-4c60-b1e9-728406606672 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465685147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.465685147 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.3206947387 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 1594223579 ps |
| CPU time | 64.02 seconds |
| Started | Jul 13 08:20:25 PM PDT 24 |
| Finished | Jul 13 08:21:30 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-8928450c-881f-44f9-bbe8-d81205b181db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206947387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.3206947387 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.3008102941 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 97969688374 ps |
| CPU time | 1145.83 seconds |
| Started | Jul 13 08:20:25 PM PDT 24 |
| Finished | Jul 13 08:39:32 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-971ea8ab-79d5-43ab-b97d-f8adfe6f14ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008102941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3008102941 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1038386759 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 61162142256 ps |
| CPU time | 1176.3 seconds |
| Started | Jul 13 08:20:26 PM PDT 24 |
| Finished | Jul 13 08:40:03 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-961cd704-3026-4d7f-a90a-907c97f82168 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038386759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1038386759 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.3012396153 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 508746269 ps |
| CPU time | 48.53 seconds |
| Started | Jul 13 08:20:27 PM PDT 24 |
| Finished | Jul 13 08:21:16 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-8fd76bb6-7d56-48fa-9a6b-91af2f1f64e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012396153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del ays.3012396153 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.1314552008 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 1442283348 ps |
| CPU time | 52.16 seconds |
| Started | Jul 13 08:20:37 PM PDT 24 |
| Finished | Jul 13 08:21:30 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-35a10389-2a3f-41c7-a0f9-82075ee3e677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314552008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1314552008 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.1541720194 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 40003053 ps |
| CPU time | 6.92 seconds |
| Started | Jul 13 08:20:27 PM PDT 24 |
| Finished | Jul 13 08:20:35 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-4cdb6c00-5d18-4320-929e-05aa7452879e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541720194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1541720194 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.2991133104 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 8752222090 ps |
| CPU time | 109.62 seconds |
| Started | Jul 13 08:20:25 PM PDT 24 |
| Finished | Jul 13 08:22:15 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-ebc85236-3250-4ca3-a5fe-2ca8cb79f414 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991133104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2991133104 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1184337641 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 5239290050 ps |
| CPU time | 98.97 seconds |
| Started | Jul 13 08:20:28 PM PDT 24 |
| Finished | Jul 13 08:22:07 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-a4fc7fe5-b846-41c4-8dbb-ddeb896579d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184337641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1184337641 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.1691743735 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 35347349 ps |
| CPU time | 5.98 seconds |
| Started | Jul 13 08:20:25 PM PDT 24 |
| Finished | Jul 13 08:20:32 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-319ae2af-af50-4191-9323-8998c3cb6003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691743735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.1691743735 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.2576374392 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 15776335178 ps |
| CPU time | 668.26 seconds |
| Started | Jul 13 08:20:38 PM PDT 24 |
| Finished | Jul 13 08:31:47 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-4197dc39-81ee-431e-810e-5a8150eecefd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576374392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2576374392 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.1302598212 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 13048391769 ps |
| CPU time | 575.57 seconds |
| Started | Jul 13 08:20:40 PM PDT 24 |
| Finished | Jul 13 08:30:16 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-9cf8d61a-0c2e-4cca-b056-9a98c383781f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302598212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1302598212 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.4008893740 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 500039031 ps |
| CPU time | 205.24 seconds |
| Started | Jul 13 08:20:37 PM PDT 24 |
| Finished | Jul 13 08:24:03 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-2de9a93d-543f-4ae8-9e1f-4b1a83cceb35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008893740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.4008893740 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3472685573 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 5358068105 ps |
| CPU time | 301.16 seconds |
| Started | Jul 13 08:20:37 PM PDT 24 |
| Finished | Jul 13 08:25:39 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-f976ac24-60ed-4a5d-8462-109e8e5369ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472685573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.3472685573 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.2994348003 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 53284951 ps |
| CPU time | 9.12 seconds |
| Started | Jul 13 08:20:38 PM PDT 24 |
| Finished | Jul 13 08:20:48 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-ea85aff1-1ab2-4a1a-a3f2-03eebd380c03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994348003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2994348003 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.1117164225 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 3390267972 ps |
| CPU time | 331.75 seconds |
| Started | Jul 13 08:20:55 PM PDT 24 |
| Finished | Jul 13 08:26:27 PM PDT 24 |
| Peak memory | 598680 kb |
| Host | smart-e39acd62-4fd2-4c1c-9ab4-5a231eed9447 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117164225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.1117164225 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.2276430797 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 27079763704 ps |
| CPU time | 3089.4 seconds |
| Started | Jul 13 08:20:38 PM PDT 24 |
| Finished | Jul 13 09:12:08 PM PDT 24 |
| Peak memory | 593620 kb |
| Host | smart-29550570-b051-46d3-8d87-58e3d4a0dd92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276430797 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.2276430797 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.3233673622 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 301309766 ps |
| CPU time | 14.59 seconds |
| Started | Jul 13 08:20:51 PM PDT 24 |
| Finished | Jul 13 08:21:06 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-0b662cbf-8eda-4921-befe-ad6f28cf5434 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233673622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device .3233673622 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.1422060702 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 239906731 ps |
| CPU time | 14.08 seconds |
| Started | Jul 13 08:20:47 PM PDT 24 |
| Finished | Jul 13 08:21:01 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-0ab0266d-6172-4e74-9518-87f561712122 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422060702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.1422060702 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.3004691553 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 124226282 ps |
| CPU time | 13.86 seconds |
| Started | Jul 13 08:20:50 PM PDT 24 |
| Finished | Jul 13 08:21:04 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-ee07f2df-084c-4cb3-8c93-3fb4dcb68846 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004691553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3004691553 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.39932336 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 110522915 ps |
| CPU time | 8.14 seconds |
| Started | Jul 13 08:20:47 PM PDT 24 |
| Finished | Jul 13 08:20:56 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-905b9c77-e277-4e08-ab6f-7421c5ade506 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39932336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.39932336 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.1208409241 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 56502762436 ps |
| CPU time | 645.1 seconds |
| Started | Jul 13 08:20:48 PM PDT 24 |
| Finished | Jul 13 08:31:33 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-4baf693c-c4d2-491c-aff2-8b26d71a3435 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208409241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1208409241 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.4169867825 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 52530467279 ps |
| CPU time | 894.87 seconds |
| Started | Jul 13 08:20:48 PM PDT 24 |
| Finished | Jul 13 08:35:43 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-69f22939-750c-4d87-82c8-88b77144111a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169867825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.4169867825 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.1470599795 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 59979467 ps |
| CPU time | 8.07 seconds |
| Started | Jul 13 08:20:48 PM PDT 24 |
| Finished | Jul 13 08:20:56 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-acd31db7-b291-4f17-bd19-79af9c1533ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470599795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del ays.1470599795 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.3711561826 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 394902265 ps |
| CPU time | 17.49 seconds |
| Started | Jul 13 08:20:51 PM PDT 24 |
| Finished | Jul 13 08:21:09 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-f817eebf-17a8-49b1-8180-545d0d71d912 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711561826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3711561826 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.1629386847 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 207022442 ps |
| CPU time | 10.64 seconds |
| Started | Jul 13 08:20:39 PM PDT 24 |
| Finished | Jul 13 08:20:50 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-f68ec7bb-91b2-4847-a3dc-554f9df9afe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629386847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1629386847 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.1417044145 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 9123184743 ps |
| CPU time | 110.48 seconds |
| Started | Jul 13 08:20:46 PM PDT 24 |
| Finished | Jul 13 08:22:37 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-b5834970-8a2c-4e6d-a2ed-48505508f08c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417044145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1417044145 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3278311254 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 4553367629 ps |
| CPU time | 84.3 seconds |
| Started | Jul 13 08:20:46 PM PDT 24 |
| Finished | Jul 13 08:22:11 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-f76e0c6a-2578-4698-9a59-60cf1440c22d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278311254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3278311254 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.3419453078 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 45654475 ps |
| CPU time | 6.79 seconds |
| Started | Jul 13 08:20:36 PM PDT 24 |
| Finished | Jul 13 08:20:43 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-31752c64-3e6e-4f14-be41-b3ebf97fd4b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419453078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay s.3419453078 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.266270933 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 1021343006 ps |
| CPU time | 114.88 seconds |
| Started | Jul 13 08:20:51 PM PDT 24 |
| Finished | Jul 13 08:22:47 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-5fb7e0eb-41f4-45a2-89e3-feaf2654a781 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266270933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.266270933 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.2124526870 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 11945968385 ps |
| CPU time | 416.72 seconds |
| Started | Jul 13 08:20:59 PM PDT 24 |
| Finished | Jul 13 08:27:56 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-3956b1be-4ccf-425d-a9b0-c403de78388d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124526870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2124526870 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3421870329 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 238717260 ps |
| CPU time | 100.2 seconds |
| Started | Jul 13 08:20:56 PM PDT 24 |
| Finished | Jul 13 08:22:36 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-6415b4e6-1806-4822-9d63-da86f2c58d21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421870329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_rand_reset.3421870329 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3186558336 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 121062471 ps |
| CPU time | 28.18 seconds |
| Started | Jul 13 08:20:56 PM PDT 24 |
| Finished | Jul 13 08:21:25 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-7f903c5c-d9d0-455f-a3ab-8f070d186d35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186558336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al l_with_reset_error.3186558336 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.1132896277 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 1049280338 ps |
| CPU time | 52.13 seconds |
| Started | Jul 13 08:20:47 PM PDT 24 |
| Finished | Jul 13 08:21:40 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-f63975f7-c976-4d09-8d57-cf68c67d8f7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132896277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1132896277 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.3825761911 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 5886869800 ps |
| CPU time | 599.92 seconds |
| Started | Jul 13 08:21:14 PM PDT 24 |
| Finished | Jul 13 08:31:15 PM PDT 24 |
| Peak memory | 598852 kb |
| Host | smart-06d9dd8c-1b73-42d0-b53a-5d5a20a415e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825761911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.3825761911 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.879662830 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 29145423180 ps |
| CPU time | 4034.54 seconds |
| Started | Jul 13 08:20:57 PM PDT 24 |
| Finished | Jul 13 09:28:12 PM PDT 24 |
| Peak memory | 592976 kb |
| Host | smart-be1b91c0-f955-44d1-b2f5-e1b2a5448c74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879662830 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 16.chip_same_csr_outstanding.879662830 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.2966493506 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 3561924005 ps |
| CPU time | 187.75 seconds |
| Started | Jul 13 08:20:55 PM PDT 24 |
| Finished | Jul 13 08:24:03 PM PDT 24 |
| Peak memory | 598792 kb |
| Host | smart-d7611b2e-ab02-463a-8b46-ea8a3e4fd42e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966493506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.2966493506 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.1980890361 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 16402229 ps |
| CPU time | 6.48 seconds |
| Started | Jul 13 08:21:06 PM PDT 24 |
| Finished | Jul 13 08:21:13 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-e75b3372-e758-48de-8214-fc6bad53991a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980890361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device .1980890361 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.3957287991 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 69633850793 ps |
| CPU time | 1224.93 seconds |
| Started | Jul 13 08:21:07 PM PDT 24 |
| Finished | Jul 13 08:41:32 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-879c6bf5-1b56-4333-a8cb-2296d3a1bb59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957287991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.3957287991 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.3220647324 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 1142913128 ps |
| CPU time | 39.14 seconds |
| Started | Jul 13 08:21:06 PM PDT 24 |
| Finished | Jul 13 08:21:46 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-f4d6931d-c0be-4322-a368-dad1aa267f1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220647324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add r.3220647324 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.1375572596 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 578842428 ps |
| CPU time | 57.21 seconds |
| Started | Jul 13 08:21:07 PM PDT 24 |
| Finished | Jul 13 08:22:04 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-c0a87de4-a14b-475e-beed-1c98dd609076 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375572596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1375572596 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.3238322489 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 1873664383 ps |
| CPU time | 89.4 seconds |
| Started | Jul 13 08:20:55 PM PDT 24 |
| Finished | Jul 13 08:22:24 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-718a2c6d-1fee-42cd-97c7-7e9baaada246 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238322489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.3238322489 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.720503757 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 17040055374 ps |
| CPU time | 197.81 seconds |
| Started | Jul 13 08:21:05 PM PDT 24 |
| Finished | Jul 13 08:24:24 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-be54ec42-15e9-429b-b429-0e3acf132dc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720503757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.720503757 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.4249850326 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 50291186210 ps |
| CPU time | 889.09 seconds |
| Started | Jul 13 08:21:05 PM PDT 24 |
| Finished | Jul 13 08:35:55 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-97114363-25f6-4524-8832-cc77ef7740fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249850326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.4249850326 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.3264399044 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 51800526 ps |
| CPU time | 9.45 seconds |
| Started | Jul 13 08:20:57 PM PDT 24 |
| Finished | Jul 13 08:21:07 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-7349f7a3-ac41-4de6-80f5-ecf479e731a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264399044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.3264399044 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.602452747 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 415254679 ps |
| CPU time | 38.46 seconds |
| Started | Jul 13 08:21:05 PM PDT 24 |
| Finished | Jul 13 08:21:44 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-a9f9730c-cdd2-45f8-953d-f07be78bce04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602452747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.602452747 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.3849591372 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 50391172 ps |
| CPU time | 7.16 seconds |
| Started | Jul 13 08:20:58 PM PDT 24 |
| Finished | Jul 13 08:21:06 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-a50049e2-2dd2-4569-a575-98066f2de3c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849591372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3849591372 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.2938657481 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 8478228806 ps |
| CPU time | 94.91 seconds |
| Started | Jul 13 08:20:56 PM PDT 24 |
| Finished | Jul 13 08:22:32 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-9825a41b-173f-4ce7-a38d-40ba907790eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938657481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2938657481 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.720425367 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 6757620045 ps |
| CPU time | 124.75 seconds |
| Started | Jul 13 08:20:56 PM PDT 24 |
| Finished | Jul 13 08:23:01 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-e61188b0-5ba0-4984-b1a5-28a4ba42adda |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720425367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.720425367 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.3421911514 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 45050332 ps |
| CPU time | 6.51 seconds |
| Started | Jul 13 08:20:56 PM PDT 24 |
| Finished | Jul 13 08:21:03 PM PDT 24 |
| Peak memory | 574012 kb |
| Host | smart-b3d710ed-5a8b-46be-bc45-83eda3110245 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421911514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay s.3421911514 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.876525972 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 4279333531 ps |
| CPU time | 181.43 seconds |
| Started | Jul 13 08:21:14 PM PDT 24 |
| Finished | Jul 13 08:24:16 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-e25ab597-9238-42f0-ae43-dde8dc0bcf47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876525972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.876525972 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.1091502595 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 22888203 ps |
| CPU time | 29.59 seconds |
| Started | Jul 13 08:21:12 PM PDT 24 |
| Finished | Jul 13 08:21:42 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-de506131-368f-43b2-8553-36ef7380d1f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091502595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_rand_reset.1091502595 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.2018358439 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 9025826201 ps |
| CPU time | 544.54 seconds |
| Started | Jul 13 08:21:14 PM PDT 24 |
| Finished | Jul 13 08:30:19 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-cdb67431-8046-4840-8c9c-be4d974d47f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018358439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.2018358439 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.640464370 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 1223786932 ps |
| CPU time | 57.54 seconds |
| Started | Jul 13 08:21:07 PM PDT 24 |
| Finished | Jul 13 08:22:05 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-660bc422-6aa0-4e4c-83d8-bea797257e99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640464370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.640464370 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.3435237688 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 4706308005 ps |
| CPU time | 366.63 seconds |
| Started | Jul 13 08:21:41 PM PDT 24 |
| Finished | Jul 13 08:27:48 PM PDT 24 |
| Peak memory | 597316 kb |
| Host | smart-f6d2b55d-f43b-4b41-a44d-7087cd59e6c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435237688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.3435237688 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.2264103399 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 26909436538 ps |
| CPU time | 3401.42 seconds |
| Started | Jul 13 08:21:20 PM PDT 24 |
| Finished | Jul 13 09:18:02 PM PDT 24 |
| Peak memory | 593544 kb |
| Host | smart-348fb644-361e-4254-8d3b-fd83f1975d0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264103399 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.2264103399 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.2533171340 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 1268369103 ps |
| CPU time | 60.68 seconds |
| Started | Jul 13 08:21:32 PM PDT 24 |
| Finished | Jul 13 08:22:33 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-e9419742-716d-4b9b-bb34-01250e6835f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533171340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .2533171340 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1901037636 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 34144364701 ps |
| CPU time | 668.3 seconds |
| Started | Jul 13 08:21:32 PM PDT 24 |
| Finished | Jul 13 08:32:41 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-c8b978d7-bf1a-4517-954c-957985b7dc19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901037636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_ device_slow_rsp.1901037636 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.3447163100 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 1005517746 ps |
| CPU time | 42.77 seconds |
| Started | Jul 13 08:21:43 PM PDT 24 |
| Finished | Jul 13 08:22:27 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-6695660c-34a1-49b1-afe1-52fa24a9a3b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447163100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.3447163100 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.3359882812 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 485249119 ps |
| CPU time | 45.66 seconds |
| Started | Jul 13 08:21:43 PM PDT 24 |
| Finished | Jul 13 08:22:29 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-6ba7b6c8-1c6e-4819-81ab-21e7f3ed3182 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359882812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3359882812 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.2617269337 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 538937892 ps |
| CPU time | 48.51 seconds |
| Started | Jul 13 08:21:24 PM PDT 24 |
| Finished | Jul 13 08:22:13 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-67031afc-d5e9-4c99-9683-573eb0fdbd60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617269337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.2617269337 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.1505286554 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 25807374509 ps |
| CPU time | 300.78 seconds |
| Started | Jul 13 08:21:32 PM PDT 24 |
| Finished | Jul 13 08:26:33 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-09862860-2422-4238-bd5f-710207510581 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505286554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.1505286554 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.1625248 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 45784829988 ps |
| CPU time | 815.09 seconds |
| Started | Jul 13 08:21:33 PM PDT 24 |
| Finished | Jul 13 08:35:10 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-bb7702d7-1020-4979-af98-5588175959e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.1625248 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.3187859907 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 178531260 ps |
| CPU time | 20.26 seconds |
| Started | Jul 13 08:21:32 PM PDT 24 |
| Finished | Jul 13 08:21:53 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-30572bd1-79fe-4171-a8f9-920316727604 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187859907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del ays.3187859907 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.3306502726 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 386117464 ps |
| CPU time | 13.09 seconds |
| Started | Jul 13 08:21:34 PM PDT 24 |
| Finished | Jul 13 08:21:47 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-1a0d5073-2034-415c-aa50-2aa065be7182 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306502726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3306502726 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.2445308247 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 48476425 ps |
| CPU time | 7.38 seconds |
| Started | Jul 13 08:21:19 PM PDT 24 |
| Finished | Jul 13 08:21:27 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-464f2b43-69a7-4cea-869a-2f84cae214a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445308247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2445308247 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.1676784982 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 5357507379 ps |
| CPU time | 60.07 seconds |
| Started | Jul 13 08:21:23 PM PDT 24 |
| Finished | Jul 13 08:22:24 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-8fd8252e-0ce8-4c0f-9655-2cd06a48fb7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676784982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1676784982 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.2153090342 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 5379125130 ps |
| CPU time | 105.24 seconds |
| Started | Jul 13 08:21:23 PM PDT 24 |
| Finished | Jul 13 08:23:09 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-67243706-045e-4510-81db-8fc90e81a2ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153090342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2153090342 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.2475721063 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 45253882 ps |
| CPU time | 5.86 seconds |
| Started | Jul 13 08:21:23 PM PDT 24 |
| Finished | Jul 13 08:21:30 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-01a4a7e9-8110-4957-b0bd-5c92ae902835 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475721063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.2475721063 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.1121010321 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 4498209904 ps |
| CPU time | 392.1 seconds |
| Started | Jul 13 08:21:43 PM PDT 24 |
| Finished | Jul 13 08:28:16 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-8d15dfe4-fff5-48e1-b2cd-e94ee3b24900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121010321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1121010321 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.3297121011 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 7625979485 ps |
| CPU time | 290.1 seconds |
| Started | Jul 13 08:21:44 PM PDT 24 |
| Finished | Jul 13 08:26:35 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-967c1755-ec92-4312-8515-58c0dd6c3af5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297121011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3297121011 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.534254269 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 14237225353 ps |
| CPU time | 704.09 seconds |
| Started | Jul 13 08:21:42 PM PDT 24 |
| Finished | Jul 13 08:33:27 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-8585edb3-dea1-4d6f-bc90-0f92fb73c8ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534254269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_reset_error.534254269 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.3045948405 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 374930590 ps |
| CPU time | 21.02 seconds |
| Started | Jul 13 08:21:42 PM PDT 24 |
| Finished | Jul 13 08:22:03 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-56a6c487-213b-4af3-ae5c-864f3852eb70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045948405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3045948405 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.3608900387 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 3948071768 ps |
| CPU time | 293.89 seconds |
| Started | Jul 13 08:22:03 PM PDT 24 |
| Finished | Jul 13 08:26:58 PM PDT 24 |
| Peak memory | 597352 kb |
| Host | smart-12a15606-03c7-4221-a805-5c758feb1f46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608900387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.3608900387 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1583841024 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 15429359712 ps |
| CPU time | 2261.57 seconds |
| Started | Jul 13 08:21:45 PM PDT 24 |
| Finished | Jul 13 08:59:27 PM PDT 24 |
| Peak memory | 593396 kb |
| Host | smart-5ef993bf-4018-4fb8-8910-2f89226f8228 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583841024 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.1583841024 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.743831780 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 5506260511 ps |
| CPU time | 571.93 seconds |
| Started | Jul 13 08:21:42 PM PDT 24 |
| Finished | Jul 13 08:31:14 PM PDT 24 |
| Peak memory | 603932 kb |
| Host | smart-ab7c468e-a4e2-4d7a-9ae4-07434d8a647f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743831780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.743831780 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.2198402137 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 1227513116 ps |
| CPU time | 52.76 seconds |
| Started | Jul 13 08:21:50 PM PDT 24 |
| Finished | Jul 13 08:22:44 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-23947f8f-ec52-4e1c-b8e3-a737dc952f4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198402137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .2198402137 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.4034451630 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 50350860400 ps |
| CPU time | 983.94 seconds |
| Started | Jul 13 08:21:50 PM PDT 24 |
| Finished | Jul 13 08:38:15 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-c5d8eafa-3e21-44b8-9f37-bf8c382587e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034451630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.4034451630 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2289384919 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 104879897 ps |
| CPU time | 15 seconds |
| Started | Jul 13 08:21:52 PM PDT 24 |
| Finished | Jul 13 08:22:08 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-67a44368-3182-4e38-925e-a594e0ad33c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289384919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add r.2289384919 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.548640656 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 1236999085 ps |
| CPU time | 44.46 seconds |
| Started | Jul 13 08:21:50 PM PDT 24 |
| Finished | Jul 13 08:22:35 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-2e49fc39-8904-43bf-a153-e303fecd83a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548640656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.548640656 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.1969885690 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 723308796 ps |
| CPU time | 28 seconds |
| Started | Jul 13 08:21:52 PM PDT 24 |
| Finished | Jul 13 08:22:21 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-c6401c0d-bfe9-4ee4-95a9-5849b53cf12d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969885690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.1969885690 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.2033890294 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 10872977119 ps |
| CPU time | 127.71 seconds |
| Started | Jul 13 08:21:50 PM PDT 24 |
| Finished | Jul 13 08:23:58 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-d29e64b5-64a3-4cd2-ba6c-7d23be70afb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033890294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2033890294 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.885675925 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 8364395002 ps |
| CPU time | 150.31 seconds |
| Started | Jul 13 08:21:50 PM PDT 24 |
| Finished | Jul 13 08:24:21 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-b2eeeee5-e986-4343-8889-3b6df5b89147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885675925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.885675925 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.1315325901 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 460142797 ps |
| CPU time | 44.3 seconds |
| Started | Jul 13 08:21:51 PM PDT 24 |
| Finished | Jul 13 08:22:36 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-5ebd1433-a8ce-4807-9ca9-e2af39e45613 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315325901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.1315325901 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.2740000296 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 106978966 ps |
| CPU time | 10.73 seconds |
| Started | Jul 13 08:21:52 PM PDT 24 |
| Finished | Jul 13 08:22:04 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-e605e44c-52a8-4454-bfd6-cd08588a33bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740000296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2740000296 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.1789800648 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 191205522 ps |
| CPU time | 9.33 seconds |
| Started | Jul 13 08:21:42 PM PDT 24 |
| Finished | Jul 13 08:21:52 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-30bccc6a-2574-4124-b303-3a170d679366 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789800648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1789800648 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.1298048001 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 8780465584 ps |
| CPU time | 107.67 seconds |
| Started | Jul 13 08:21:43 PM PDT 24 |
| Finished | Jul 13 08:23:31 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-84c40986-1a7b-4141-abbc-7f1c12032614 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298048001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1298048001 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3809452308 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 4216949438 ps |
| CPU time | 80.21 seconds |
| Started | Jul 13 08:21:50 PM PDT 24 |
| Finished | Jul 13 08:23:11 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-77440815-7f86-440d-9451-35a8bbd63a3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809452308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3809452308 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1230383950 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 45093309 ps |
| CPU time | 7.18 seconds |
| Started | Jul 13 08:21:42 PM PDT 24 |
| Finished | Jul 13 08:21:50 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-1c26b3f0-c62d-4d17-b5c9-ec98d5e5b854 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230383950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay s.1230383950 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.2407566604 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 2848939511 ps |
| CPU time | 258.92 seconds |
| Started | Jul 13 08:21:51 PM PDT 24 |
| Finished | Jul 13 08:26:10 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-9179554f-be8b-4559-841a-39eeaa0fce5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407566604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2407566604 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.3730871199 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 848089822 ps |
| CPU time | 36.42 seconds |
| Started | Jul 13 08:22:01 PM PDT 24 |
| Finished | Jul 13 08:22:38 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-dc8d7791-0f69-4c81-9fb4-a67f676ac68f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730871199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3730871199 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1947617661 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 147275739 ps |
| CPU time | 36.43 seconds |
| Started | Jul 13 08:21:53 PM PDT 24 |
| Finished | Jul 13 08:22:30 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-dc38be7e-edf9-43cf-b800-6136713192e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947617661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.1947617661 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.3800602263 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 183458784 ps |
| CPU time | 63.56 seconds |
| Started | Jul 13 08:22:03 PM PDT 24 |
| Finished | Jul 13 08:23:07 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-48b7309a-c7cf-4f14-8da7-d3df1cdbdd62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800602263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.3800602263 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.60999287 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 90679752 ps |
| CPU time | 12.31 seconds |
| Started | Jul 13 08:21:51 PM PDT 24 |
| Finished | Jul 13 08:22:04 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-b07422b2-94cd-4a63-b12c-caac67c5e9a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60999287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.60999287 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.534239193 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 4015509358 ps |
| CPU time | 326.94 seconds |
| Started | Jul 13 08:22:11 PM PDT 24 |
| Finished | Jul 13 08:27:38 PM PDT 24 |
| Peak memory | 598320 kb |
| Host | smart-c8b096be-da2f-448f-8d0f-355ef3a85a0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534239193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.534239193 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.2130731336 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 15038766021 ps |
| CPU time | 2125.19 seconds |
| Started | Jul 13 08:22:00 PM PDT 24 |
| Finished | Jul 13 08:57:26 PM PDT 24 |
| Peak memory | 593296 kb |
| Host | smart-37ebf8ad-4aac-4387-8976-13e05d7727ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130731336 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.2130731336 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.3863430686 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 4727370000 ps |
| CPU time | 384.55 seconds |
| Started | Jul 13 08:22:01 PM PDT 24 |
| Finished | Jul 13 08:28:26 PM PDT 24 |
| Peak memory | 603848 kb |
| Host | smart-56f35d04-ea58-4872-a899-da4f8a13ed80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863430686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.3863430686 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.4091910927 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 515648337 ps |
| CPU time | 60.86 seconds |
| Started | Jul 13 08:22:09 PM PDT 24 |
| Finished | Jul 13 08:23:10 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-084fdbb5-3a7e-4fcb-8920-b5260e0cd2e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091910927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device .4091910927 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.202594352 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 48177199078 ps |
| CPU time | 902.03 seconds |
| Started | Jul 13 08:22:10 PM PDT 24 |
| Finished | Jul 13 08:37:12 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-029fbd14-3538-470f-8a95-9a5d519ba9f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202594352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_d evice_slow_rsp.202594352 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.1579726466 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 41987717 ps |
| CPU time | 8.41 seconds |
| Started | Jul 13 08:22:10 PM PDT 24 |
| Finished | Jul 13 08:22:18 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-25fd5a3b-1aa0-4a23-8836-f5c325e8d29f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579726466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add r.1579726466 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.88437014 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 224850118 ps |
| CPU time | 11.41 seconds |
| Started | Jul 13 08:22:16 PM PDT 24 |
| Finished | Jul 13 08:22:28 PM PDT 24 |
| Peak memory | 575204 kb |
| Host | smart-c8e8361b-683a-4ca9-8d8a-0bfd17146c47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88437014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.88437014 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.1572258386 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 571920399 ps |
| CPU time | 24.45 seconds |
| Started | Jul 13 08:21:59 PM PDT 24 |
| Finished | Jul 13 08:22:24 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-42e70eba-fd9b-495b-a7a6-89456f9e5392 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572258386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.1572258386 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.1685226730 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 102754201380 ps |
| CPU time | 1212.38 seconds |
| Started | Jul 13 08:22:12 PM PDT 24 |
| Finished | Jul 13 08:42:25 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-1cab9752-568d-4cc7-a6c3-bf9829254e0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685226730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1685226730 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.2360746702 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 39570759707 ps |
| CPU time | 746.28 seconds |
| Started | Jul 13 08:22:08 PM PDT 24 |
| Finished | Jul 13 08:34:35 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-9cad65be-6604-49bd-b89a-2373441996f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360746702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2360746702 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.3785552592 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 56095355 ps |
| CPU time | 8.33 seconds |
| Started | Jul 13 08:21:59 PM PDT 24 |
| Finished | Jul 13 08:22:08 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-cd72b5ac-db0f-4fac-8f15-2d4c8ac5e12d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785552592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del ays.3785552592 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.895093147 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 2188597905 ps |
| CPU time | 76.7 seconds |
| Started | Jul 13 08:22:16 PM PDT 24 |
| Finished | Jul 13 08:23:33 PM PDT 24 |
| Peak memory | 575204 kb |
| Host | smart-e50dfc35-f1f3-473a-a8cb-8fc95f0eb261 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895093147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.895093147 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.2668786202 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 191851409 ps |
| CPU time | 10.28 seconds |
| Started | Jul 13 08:22:04 PM PDT 24 |
| Finished | Jul 13 08:22:15 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-30088f4f-b04b-49f7-b58e-3979435ff1f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668786202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2668786202 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.743058383 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 5228314880 ps |
| CPU time | 60.2 seconds |
| Started | Jul 13 08:21:59 PM PDT 24 |
| Finished | Jul 13 08:22:59 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-3f357f04-14d1-491f-a387-586120c7fb2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743058383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.743058383 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2543823431 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 4939331993 ps |
| CPU time | 95.4 seconds |
| Started | Jul 13 08:21:59 PM PDT 24 |
| Finished | Jul 13 08:23:35 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-111e559b-c2c4-4ec9-9a0a-d8ce87a862c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543823431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2543823431 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.4047454297 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 41759435 ps |
| CPU time | 6.85 seconds |
| Started | Jul 13 08:21:58 PM PDT 24 |
| Finished | Jul 13 08:22:05 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-f3a348bc-47c9-47a5-963e-575aa55fe167 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047454297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.4047454297 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.1088853904 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 10188361460 ps |
| CPU time | 373.89 seconds |
| Started | Jul 13 08:22:08 PM PDT 24 |
| Finished | Jul 13 08:28:22 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-4e51e054-e242-4aff-bbeb-0bb7b6d8c49b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088853904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1088853904 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.3387738651 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 16439124490 ps |
| CPU time | 638.22 seconds |
| Started | Jul 13 08:22:13 PM PDT 24 |
| Finished | Jul 13 08:32:51 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-00209f9a-58ae-4f4e-922f-58adf271c63e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387738651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3387738651 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.428816799 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 138132182 ps |
| CPU time | 39.04 seconds |
| Started | Jul 13 08:22:11 PM PDT 24 |
| Finished | Jul 13 08:22:51 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-0776e413-8a3a-4766-ba67-fa878c58e1ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428816799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_ with_rand_reset.428816799 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.2543118471 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 1453666777 ps |
| CPU time | 262.58 seconds |
| Started | Jul 13 08:22:08 PM PDT 24 |
| Finished | Jul 13 08:26:31 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-58a644c3-2697-40e0-a5bb-b66927121ff5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543118471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.2543118471 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.1335942457 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 363316687 ps |
| CPU time | 21.46 seconds |
| Started | Jul 13 08:22:16 PM PDT 24 |
| Finished | Jul 13 08:22:37 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-43ed62e3-087b-439b-afcd-62e259e692bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335942457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.1335942457 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.2546729652 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 33441999426 ps |
| CPU time | 5027.96 seconds |
| Started | Jul 13 08:14:07 PM PDT 24 |
| Finished | Jul 13 09:37:55 PM PDT 24 |
| Peak memory | 593832 kb |
| Host | smart-8528f90d-3060-4c70-ba03-0b1367fcf89e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546729652 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.chip_csr_aliasing.2546729652 |
| Directory | /workspace/2.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.1166389373 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 61105286696 ps |
| CPU time | 5991.08 seconds |
| Started | Jul 13 08:13:55 PM PDT 24 |
| Finished | Jul 13 09:53:47 PM PDT 24 |
| Peak memory | 592536 kb |
| Host | smart-d00e4223-02ef-48dc-9371-f449233dbdc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166389373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.1166389373 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.2765764879 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 5475369856 ps |
| CPU time | 277.92 seconds |
| Started | Jul 13 08:14:51 PM PDT 24 |
| Finished | Jul 13 08:19:30 PM PDT 24 |
| Peak memory | 663912 kb |
| Host | smart-1c720b94-cf7c-4317-bd9e-01349ef98114 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765764879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.2765764879 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.3182386192 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 5463082764 ps |
| CPU time | 711.32 seconds |
| Started | Jul 13 08:14:35 PM PDT 24 |
| Finished | Jul 13 08:26:27 PM PDT 24 |
| Peak memory | 598528 kb |
| Host | smart-abee8986-9988-4b8a-9b0e-a9c439711e3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182386192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.3182386192 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.3488135388 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 7107220040 ps |
| CPU time | 357.23 seconds |
| Started | Jul 13 08:14:05 PM PDT 24 |
| Finished | Jul 13 08:20:02 PM PDT 24 |
| Peak memory | 589924 kb |
| Host | smart-8cbfb622-803f-4c63-b366-29c0873e685d |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488135388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.3488135388 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.2712840708 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 10495126580 ps |
| CPU time | 426.96 seconds |
| Started | Jul 13 08:13:52 PM PDT 24 |
| Finished | Jul 13 08:20:59 PM PDT 24 |
| Peak memory | 590396 kb |
| Host | smart-cab2e7f9-7597-44a7-9b23-a3eb54c0a4ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712840708 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.2712840708 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.3091880786 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 3437749792 ps |
| CPU time | 275.69 seconds |
| Started | Jul 13 08:13:55 PM PDT 24 |
| Finished | Jul 13 08:18:31 PM PDT 24 |
| Peak memory | 603856 kb |
| Host | smart-0fbdf3dc-81b3-43e6-92ff-a9c1530ede72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091880786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.3091880786 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.127121770 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 1752787008 ps |
| CPU time | 74.79 seconds |
| Started | Jul 13 08:14:15 PM PDT 24 |
| Finished | Jul 13 08:15:31 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-4bd3017a-649f-4c82-b3e2-76c4dda5eef5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127121770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.127121770 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.4117285568 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 85995221458 ps |
| CPU time | 1713.85 seconds |
| Started | Jul 13 08:14:18 PM PDT 24 |
| Finished | Jul 13 08:42:52 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-fd59c5b9-60ec-448d-9fae-4edad422e6b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117285568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.4117285568 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.3222060902 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 967637720 ps |
| CPU time | 47.55 seconds |
| Started | Jul 13 08:14:31 PM PDT 24 |
| Finished | Jul 13 08:15:19 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-d24d8487-1efa-47b2-9db9-a28bad701fe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222060902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .3222060902 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.3771902485 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 1819097791 ps |
| CPU time | 70.63 seconds |
| Started | Jul 13 08:14:25 PM PDT 24 |
| Finished | Jul 13 08:15:36 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-0173d970-96aa-4d51-af17-d06d6d5c473f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771902485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3771902485 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.447273111 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 1301616813 ps |
| CPU time | 47.02 seconds |
| Started | Jul 13 08:14:08 PM PDT 24 |
| Finished | Jul 13 08:14:55 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-2e089c3e-a544-4fc4-b093-232780aca61e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447273111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.447273111 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.3340304313 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 3730224119 ps |
| CPU time | 43.16 seconds |
| Started | Jul 13 08:14:18 PM PDT 24 |
| Finished | Jul 13 08:15:02 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-9b4f371d-8379-4543-a7f8-efbb0fc8a42d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340304313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3340304313 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.4040139650 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 69787953626 ps |
| CPU time | 1285.76 seconds |
| Started | Jul 13 08:14:18 PM PDT 24 |
| Finished | Jul 13 08:35:44 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-d0d9cdb7-1852-4fbb-b106-cd90addb004b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040139650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.4040139650 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.3909144953 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 186510845 ps |
| CPU time | 20.4 seconds |
| Started | Jul 13 08:14:19 PM PDT 24 |
| Finished | Jul 13 08:14:40 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-c19b27a2-fea1-4287-8073-a054daf16821 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909144953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.3909144953 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.1571134902 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 189065798 ps |
| CPU time | 20.87 seconds |
| Started | Jul 13 08:14:31 PM PDT 24 |
| Finished | Jul 13 08:14:52 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-5f1015a3-970e-47da-8e28-bb6f9ac8b4e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571134902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1571134902 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.1883427624 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 186726019 ps |
| CPU time | 9.91 seconds |
| Started | Jul 13 08:14:10 PM PDT 24 |
| Finished | Jul 13 08:14:20 PM PDT 24 |
| Peak memory | 573996 kb |
| Host | smart-aafc6ce2-3ff4-413c-9159-a1aae0f45912 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883427624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1883427624 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.3145415064 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 10412160027 ps |
| CPU time | 128.55 seconds |
| Started | Jul 13 08:14:07 PM PDT 24 |
| Finished | Jul 13 08:16:16 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-cbf8b03d-d645-45c0-afe0-eb4f1660d6f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145415064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3145415064 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.4287973528 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 3564804868 ps |
| CPU time | 62.09 seconds |
| Started | Jul 13 08:14:06 PM PDT 24 |
| Finished | Jul 13 08:15:09 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-a0464f74-bf54-4d59-b0c0-09175a4a4bcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287973528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.4287973528 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.2218200192 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 44296630 ps |
| CPU time | 7.13 seconds |
| Started | Jul 13 08:14:17 PM PDT 24 |
| Finished | Jul 13 08:14:25 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-2fad1dcd-2e28-4415-972a-8a00d4e7dcf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218200192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .2218200192 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.2053744352 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 2731068093 ps |
| CPU time | 300.73 seconds |
| Started | Jul 13 08:14:51 PM PDT 24 |
| Finished | Jul 13 08:19:52 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-226ff3d2-b695-49e2-9bdc-4bf84ca6e4c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053744352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2053744352 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.2663409147 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 10986125524 ps |
| CPU time | 534.33 seconds |
| Started | Jul 13 08:14:31 PM PDT 24 |
| Finished | Jul 13 08:23:25 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-841feed3-50e6-4c5f-b59e-92be17da2b31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663409147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.2663409147 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.3829974384 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 192282602 ps |
| CPU time | 136.4 seconds |
| Started | Jul 13 08:14:32 PM PDT 24 |
| Finished | Jul 13 08:16:48 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-ec839b8d-a8c7-4538-9c20-eb0ca6d30eeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829974384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_rand_reset.3829974384 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.234812250 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 777436784 ps |
| CPU time | 190.22 seconds |
| Started | Jul 13 08:14:31 PM PDT 24 |
| Finished | Jul 13 08:17:41 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-35fbcd4d-8967-4093-82f5-e1149dd23a9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234812250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_reset_error.234812250 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.598870503 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 230431951 ps |
| CPU time | 30.38 seconds |
| Started | Jul 13 08:14:26 PM PDT 24 |
| Finished | Jul 13 08:14:57 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-09c1905d-edc7-4531-8205-2da1809ccf31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598870503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.598870503 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.3061633903 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 3014169076 ps |
| CPU time | 149.81 seconds |
| Started | Jul 13 08:22:08 PM PDT 24 |
| Finished | Jul 13 08:24:38 PM PDT 24 |
| Peak memory | 598760 kb |
| Host | smart-d533699d-4a69-4524-bf47-15d609707e9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061633903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.3061633903 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.162490775 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 3495621482 ps |
| CPU time | 154.92 seconds |
| Started | Jul 13 08:22:17 PM PDT 24 |
| Finished | Jul 13 08:24:52 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-7530bd6b-62ce-4d96-bcbf-4cd729ec4e47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162490775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device. 162490775 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.4026295119 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 41847287537 ps |
| CPU time | 768.55 seconds |
| Started | Jul 13 08:22:18 PM PDT 24 |
| Finished | Jul 13 08:35:07 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-44c4ec64-42cd-4964-ac5f-496b96bcf07c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026295119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_ device_slow_rsp.4026295119 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.2016503336 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 244078080 ps |
| CPU time | 31.46 seconds |
| Started | Jul 13 08:22:17 PM PDT 24 |
| Finished | Jul 13 08:22:49 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-063c9071-9398-4edc-8503-a42acb690cd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016503336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.2016503336 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.2137795488 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 1726514514 ps |
| CPU time | 62.52 seconds |
| Started | Jul 13 08:22:18 PM PDT 24 |
| Finished | Jul 13 08:23:21 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-6287acbb-537f-45ee-8d91-e342689129f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137795488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.2137795488 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.1794871272 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 221647848 ps |
| CPU time | 26.19 seconds |
| Started | Jul 13 08:22:17 PM PDT 24 |
| Finished | Jul 13 08:22:44 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-3618c789-29cc-48c5-b1bc-8c0d1f8dbc73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794871272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.1794871272 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.3114420450 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 35796219643 ps |
| CPU time | 636.98 seconds |
| Started | Jul 13 08:22:19 PM PDT 24 |
| Finished | Jul 13 08:32:56 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-8eb96fc5-b6fb-4924-b7b3-779aea6422b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114420450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3114420450 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.1370272455 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 330046761 ps |
| CPU time | 34.37 seconds |
| Started | Jul 13 08:22:21 PM PDT 24 |
| Finished | Jul 13 08:22:56 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-256b31a8-e17e-4cd5-b275-08751f0e5666 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370272455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.1370272455 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.3866967790 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 647755274 ps |
| CPU time | 24.92 seconds |
| Started | Jul 13 08:22:18 PM PDT 24 |
| Finished | Jul 13 08:22:43 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-f3301a51-6d7f-4e33-9278-a9682698346d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866967790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3866967790 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.415869112 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 56338839 ps |
| CPU time | 7.63 seconds |
| Started | Jul 13 08:22:09 PM PDT 24 |
| Finished | Jul 13 08:22:17 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-24f34215-dde3-4e7c-84a2-b0fc6829ef95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415869112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.415869112 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.908936220 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 8628772267 ps |
| CPU time | 99.18 seconds |
| Started | Jul 13 08:22:18 PM PDT 24 |
| Finished | Jul 13 08:23:58 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-75966f81-f80f-42c6-8370-509b1d74fc75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908936220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.908936220 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.3332772025 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 5520129625 ps |
| CPU time | 102.07 seconds |
| Started | Jul 13 08:22:18 PM PDT 24 |
| Finished | Jul 13 08:24:01 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-ccce0180-3bfd-4277-af66-05da042b93fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332772025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.3332772025 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.3861735538 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 48228002 ps |
| CPU time | 6.06 seconds |
| Started | Jul 13 08:22:18 PM PDT 24 |
| Finished | Jul 13 08:22:25 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-296cf5dc-659f-48a4-a713-d778fe00bafc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861735538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.3861735538 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.4291697511 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 5973576173 ps |
| CPU time | 293.28 seconds |
| Started | Jul 13 08:22:28 PM PDT 24 |
| Finished | Jul 13 08:27:22 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-fd920db6-7be8-41df-8809-5e4f134cdd63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291697511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.4291697511 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.1673896056 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 11120081713 ps |
| CPU time | 432.68 seconds |
| Started | Jul 13 08:22:28 PM PDT 24 |
| Finished | Jul 13 08:29:41 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-2c2894e3-a2d8-4e27-b9a8-ffb73e090f09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673896056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1673896056 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.487740313 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 264582051 ps |
| CPU time | 112.51 seconds |
| Started | Jul 13 08:22:27 PM PDT 24 |
| Finished | Jul 13 08:24:20 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-b6736c73-78a5-4410-84f3-363b0f37b3bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487740313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_ with_rand_reset.487740313 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.470135192 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 636777438 ps |
| CPU time | 210.69 seconds |
| Started | Jul 13 08:22:26 PM PDT 24 |
| Finished | Jul 13 08:25:58 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-9b0f2590-5f25-4fa2-825c-161e2f5e90b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470135192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_reset_error.470135192 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.1314108617 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 655321305 ps |
| CPU time | 33.53 seconds |
| Started | Jul 13 08:22:19 PM PDT 24 |
| Finished | Jul 13 08:22:53 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-e9edd901-caa6-4829-b63d-d5811319775f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314108617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1314108617 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.694489592 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 400291341 ps |
| CPU time | 32.31 seconds |
| Started | Jul 13 08:22:41 PM PDT 24 |
| Finished | Jul 13 08:23:14 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-201a358b-fb73-4dd3-9a14-2939a8d4c31a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694489592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device. 694489592 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.1191350578 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 37148349680 ps |
| CPU time | 662.94 seconds |
| Started | Jul 13 08:22:43 PM PDT 24 |
| Finished | Jul 13 08:33:46 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-f3ee50ab-da6b-42f5-841b-8e7b8c39aca4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191350578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.1191350578 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.1320060237 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 275942513 ps |
| CPU time | 13.74 seconds |
| Started | Jul 13 08:22:53 PM PDT 24 |
| Finished | Jul 13 08:23:07 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-aa675832-49ee-48d8-a560-ccbf2f41186e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320060237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.1320060237 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.401442975 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 2195921144 ps |
| CPU time | 72.32 seconds |
| Started | Jul 13 08:22:44 PM PDT 24 |
| Finished | Jul 13 08:23:57 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-88529404-c97f-4342-943e-cb392821daa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401442975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.401442975 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.2927326196 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 1548913961 ps |
| CPU time | 58.27 seconds |
| Started | Jul 13 08:22:42 PM PDT 24 |
| Finished | Jul 13 08:23:41 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-69c87d16-0400-4e6d-98bf-3f3756e33652 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927326196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.2927326196 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.1582625000 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 77615201296 ps |
| CPU time | 866.03 seconds |
| Started | Jul 13 08:22:42 PM PDT 24 |
| Finished | Jul 13 08:37:08 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-51786b07-f0d0-4809-b7fd-22abb1f25d5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582625000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1582625000 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.3985069888 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 66757755466 ps |
| CPU time | 1223.17 seconds |
| Started | Jul 13 08:22:41 PM PDT 24 |
| Finished | Jul 13 08:43:05 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-59bfe097-04d5-4bed-8e8e-d0cfe16d7373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985069888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3985069888 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.2509933202 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 469176919 ps |
| CPU time | 50.81 seconds |
| Started | Jul 13 08:22:43 PM PDT 24 |
| Finished | Jul 13 08:23:35 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-08bc70a6-11af-4d27-a1a4-943f222eaf9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509933202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del ays.2509933202 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.271794516 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 509985004 ps |
| CPU time | 45.28 seconds |
| Started | Jul 13 08:22:41 PM PDT 24 |
| Finished | Jul 13 08:23:27 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-b024ff5a-89ed-461d-b789-4526186bf55e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271794516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.271794516 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.2991348455 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 46601492 ps |
| CPU time | 7.27 seconds |
| Started | Jul 13 08:22:29 PM PDT 24 |
| Finished | Jul 13 08:22:37 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-b5dc26b2-a4fd-438e-abd8-c38a73d4ddc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991348455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2991348455 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.3023210062 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 6932913725 ps |
| CPU time | 80.56 seconds |
| Started | Jul 13 08:22:42 PM PDT 24 |
| Finished | Jul 13 08:24:03 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-b3f3e800-c2cc-4a46-9d92-7fa31a604b35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023210062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3023210062 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.3587989410 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 5330584843 ps |
| CPU time | 102.31 seconds |
| Started | Jul 13 08:22:43 PM PDT 24 |
| Finished | Jul 13 08:24:26 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-0756182d-07bc-4d43-bab5-a3ca347e477a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587989410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3587989410 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.2289031987 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 56470123 ps |
| CPU time | 7.7 seconds |
| Started | Jul 13 08:22:27 PM PDT 24 |
| Finished | Jul 13 08:22:35 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-552e379a-ac49-4a04-8273-4e727212800a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289031987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.2289031987 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.4217081903 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 8305649442 ps |
| CPU time | 315.65 seconds |
| Started | Jul 13 08:22:54 PM PDT 24 |
| Finished | Jul 13 08:28:10 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-2fa409ff-00d4-480e-9697-4e3e105d314c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217081903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.4217081903 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.3970554765 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 144863678 ps |
| CPU time | 16.44 seconds |
| Started | Jul 13 08:22:53 PM PDT 24 |
| Finished | Jul 13 08:23:10 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-4b359804-f3ed-410d-9547-067b75e14e2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970554765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3970554765 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.3888951707 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 3180473836 ps |
| CPU time | 405.04 seconds |
| Started | Jul 13 08:23:00 PM PDT 24 |
| Finished | Jul 13 08:29:46 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-b4eb2d0c-c739-459a-90c5-77ca5365ae5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888951707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.3888951707 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.2865102608 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 242173434 ps |
| CPU time | 33.34 seconds |
| Started | Jul 13 08:22:40 PM PDT 24 |
| Finished | Jul 13 08:23:14 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-e1ad1901-0a49-47d3-a41e-6280562c1910 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865102608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2865102608 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.1030405387 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 272535243 ps |
| CPU time | 13.74 seconds |
| Started | Jul 13 08:22:52 PM PDT 24 |
| Finished | Jul 13 08:23:06 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-ffb6a8de-164b-4f54-8513-d0473ee2d02e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030405387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device .1030405387 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.37852619 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 34948747368 ps |
| CPU time | 650.49 seconds |
| Started | Jul 13 08:22:54 PM PDT 24 |
| Finished | Jul 13 08:33:45 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-717da3f3-fc04-46e3-aee8-8a2e57fbdef2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37852619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_de vice_slow_rsp.37852619 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.2129985406 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 547770702 ps |
| CPU time | 25.74 seconds |
| Started | Jul 13 08:23:01 PM PDT 24 |
| Finished | Jul 13 08:23:27 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-2ecbf714-163f-4db7-b7ee-934fb1ac389b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129985406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add r.2129985406 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.3613110256 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 145921752 ps |
| CPU time | 14.31 seconds |
| Started | Jul 13 08:22:52 PM PDT 24 |
| Finished | Jul 13 08:23:07 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-25c714d3-97c9-423c-8512-8c002994fe93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613110256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3613110256 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.4255003261 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 510832284 ps |
| CPU time | 47.09 seconds |
| Started | Jul 13 08:22:53 PM PDT 24 |
| Finished | Jul 13 08:23:40 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-a1b78806-a814-4652-840f-9d964de91b13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255003261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.4255003261 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.524545937 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 62185532321 ps |
| CPU time | 766.59 seconds |
| Started | Jul 13 08:22:52 PM PDT 24 |
| Finished | Jul 13 08:35:39 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-44fdc569-ae2b-44c8-a1e7-6ee84c9e7d21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524545937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.524545937 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.1256282104 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 43137740453 ps |
| CPU time | 792.94 seconds |
| Started | Jul 13 08:22:54 PM PDT 24 |
| Finished | Jul 13 08:36:08 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-b909af13-e862-4fb0-8f2d-b35a25d6e00b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256282104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1256282104 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.2382487331 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 470723218 ps |
| CPU time | 45.69 seconds |
| Started | Jul 13 08:22:53 PM PDT 24 |
| Finished | Jul 13 08:23:39 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-eb2caf80-2f51-47e4-bddb-66383b9539ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382487331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.2382487331 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.3115382119 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 75788924 ps |
| CPU time | 8.54 seconds |
| Started | Jul 13 08:22:57 PM PDT 24 |
| Finished | Jul 13 08:23:06 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-d07bbd7c-d01b-421a-a026-b455333467d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115382119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3115382119 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.1515368720 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 170230876 ps |
| CPU time | 8.15 seconds |
| Started | Jul 13 08:22:52 PM PDT 24 |
| Finished | Jul 13 08:23:01 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-58ad91f5-fb03-44e2-806c-6dad06ebcc14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515368720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1515368720 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.2107825781 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 9650181420 ps |
| CPU time | 116.34 seconds |
| Started | Jul 13 08:22:51 PM PDT 24 |
| Finished | Jul 13 08:24:48 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-67274591-3491-478a-80a1-527961127d5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107825781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2107825781 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.734721490 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 5132410184 ps |
| CPU time | 94.1 seconds |
| Started | Jul 13 08:22:51 PM PDT 24 |
| Finished | Jul 13 08:24:26 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-2d0c45df-2b80-459f-8253-9252a4e3aa6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734721490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.734721490 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.4259516085 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 49594485 ps |
| CPU time | 6.64 seconds |
| Started | Jul 13 08:22:52 PM PDT 24 |
| Finished | Jul 13 08:22:59 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-e4da1091-4035-4b3f-9b77-fce0ecc1acd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259516085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.4259516085 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.2453277001 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 3529731118 ps |
| CPU time | 329.69 seconds |
| Started | Jul 13 08:23:00 PM PDT 24 |
| Finished | Jul 13 08:28:30 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-3c1e0f47-23cf-45f1-b5ca-e86eb7a775f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453277001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2453277001 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.1277620654 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 11127318156 ps |
| CPU time | 418.29 seconds |
| Started | Jul 13 08:23:00 PM PDT 24 |
| Finished | Jul 13 08:29:59 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-35b6248d-14c5-44cd-8ee5-f27a4c12ceaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277620654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1277620654 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.1278297619 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 2274698251 ps |
| CPU time | 174.48 seconds |
| Started | Jul 13 08:23:03 PM PDT 24 |
| Finished | Jul 13 08:25:58 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-88b2707b-8879-488e-8bf8-d2c9123c9829 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278297619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.1278297619 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.3696051995 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 2371694519 ps |
| CPU time | 277.84 seconds |
| Started | Jul 13 08:23:03 PM PDT 24 |
| Finished | Jul 13 08:27:41 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-510023c0-a026-4199-ba78-70e2a8c97cdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696051995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.3696051995 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.4191753798 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 173340500 ps |
| CPU time | 21.29 seconds |
| Started | Jul 13 08:23:03 PM PDT 24 |
| Finished | Jul 13 08:23:25 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-0dc33076-6639-4e4b-8cce-40818b2e9192 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191753798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.4191753798 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.2838466282 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 3588200624 ps |
| CPU time | 266.28 seconds |
| Started | Jul 13 08:23:01 PM PDT 24 |
| Finished | Jul 13 08:27:28 PM PDT 24 |
| Peak memory | 599712 kb |
| Host | smart-c171685a-12ee-4687-b280-965857207177 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838466282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.2838466282 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.3491684816 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 12618686 ps |
| CPU time | 6.12 seconds |
| Started | Jul 13 08:23:12 PM PDT 24 |
| Finished | Jul 13 08:23:19 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-bc007d27-7ebb-4c37-9b63-4f393c65c29a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491684816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device .3491684816 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2758005287 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 43507448352 ps |
| CPU time | 786.68 seconds |
| Started | Jul 13 08:23:12 PM PDT 24 |
| Finished | Jul 13 08:36:19 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-7ad7c66f-f719-4e1b-aedc-8bda826f1e3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758005287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_ device_slow_rsp.2758005287 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.475671146 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 1510139790 ps |
| CPU time | 72.13 seconds |
| Started | Jul 13 08:23:19 PM PDT 24 |
| Finished | Jul 13 08:24:32 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-89bb2d97-f6ae-4575-98c8-a06072d55d87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475671146 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr .475671146 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.2930403772 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 356695605 ps |
| CPU time | 32.61 seconds |
| Started | Jul 13 08:23:12 PM PDT 24 |
| Finished | Jul 13 08:23:45 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-579ff946-73e2-469b-9fcc-6ae0c29ab675 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930403772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2930403772 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.2979633317 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 290357636 ps |
| CPU time | 14.62 seconds |
| Started | Jul 13 08:23:00 PM PDT 24 |
| Finished | Jul 13 08:23:15 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-4f736de0-d842-4494-be92-83e95b8f4294 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979633317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.2979633317 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.4135668853 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 101840421073 ps |
| CPU time | 1212.63 seconds |
| Started | Jul 13 08:23:02 PM PDT 24 |
| Finished | Jul 13 08:43:15 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-5faf8a89-5656-464d-bfbc-02db5e559337 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135668853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.4135668853 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.1175099824 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 49785508123 ps |
| CPU time | 935.94 seconds |
| Started | Jul 13 08:23:02 PM PDT 24 |
| Finished | Jul 13 08:38:38 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-86d5dc43-ba61-4f79-aa0f-3fc90a4e4e13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175099824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1175099824 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.1209053299 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 287589221 ps |
| CPU time | 25.53 seconds |
| Started | Jul 13 08:23:02 PM PDT 24 |
| Finished | Jul 13 08:23:28 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-84d0ac98-0521-4b42-8156-a930dcc73bc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209053299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.1209053299 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.1444561280 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 604076504 ps |
| CPU time | 52.43 seconds |
| Started | Jul 13 08:23:13 PM PDT 24 |
| Finished | Jul 13 08:24:06 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-112eade4-2a73-4ffb-8fa7-f708db856124 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444561280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1444561280 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.3475856711 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 246360460 ps |
| CPU time | 11.38 seconds |
| Started | Jul 13 08:23:05 PM PDT 24 |
| Finished | Jul 13 08:23:17 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-1ba87353-baac-4b16-8ca3-9d796e3d5bb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475856711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3475856711 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.1941052081 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 7910365820 ps |
| CPU time | 89.64 seconds |
| Started | Jul 13 08:23:02 PM PDT 24 |
| Finished | Jul 13 08:24:32 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-049159a0-3265-4202-b95f-e4285b884fb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941052081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1941052081 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.2650643017 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 5938113339 ps |
| CPU time | 115.75 seconds |
| Started | Jul 13 08:23:05 PM PDT 24 |
| Finished | Jul 13 08:25:01 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-521306ae-6a75-4558-a5d4-68f61212f46c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650643017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2650643017 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.2921325416 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 41533387 ps |
| CPU time | 6.74 seconds |
| Started | Jul 13 08:23:01 PM PDT 24 |
| Finished | Jul 13 08:23:08 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-62e0aede-d15e-4ed0-97af-938833ddeaac |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921325416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay s.2921325416 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.1806672070 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 2042858710 ps |
| CPU time | 227.86 seconds |
| Started | Jul 13 08:23:23 PM PDT 24 |
| Finished | Jul 13 08:27:11 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-695cc9d4-ebad-42b6-838d-96c70c6c83a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806672070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1806672070 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.3455235496 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 9153696812 ps |
| CPU time | 362.44 seconds |
| Started | Jul 13 08:23:23 PM PDT 24 |
| Finished | Jul 13 08:29:26 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-a8beba6e-c385-4346-8a32-006e1b132d55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455235496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3455235496 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.3999306261 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 4144978498 ps |
| CPU time | 632.21 seconds |
| Started | Jul 13 08:23:21 PM PDT 24 |
| Finished | Jul 13 08:33:53 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-92c5ced6-eb90-4619-849f-1f4a3220db34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999306261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_rand_reset.3999306261 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.1141927495 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 858153093 ps |
| CPU time | 301.72 seconds |
| Started | Jul 13 08:23:20 PM PDT 24 |
| Finished | Jul 13 08:28:23 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-1ea3840f-ccf3-49a6-ba68-a322b414146e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141927495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.1141927495 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.2988685102 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 1239628476 ps |
| CPU time | 53.15 seconds |
| Started | Jul 13 08:23:13 PM PDT 24 |
| Finished | Jul 13 08:24:07 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-a88a0c46-630b-421c-9f05-45c46c1f026f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988685102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2988685102 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.2732858789 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 2672426234 ps |
| CPU time | 144.16 seconds |
| Started | Jul 13 08:23:19 PM PDT 24 |
| Finished | Jul 13 08:25:44 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-f89f7083-c1ab-4ffa-87d0-e2efc6c6ef4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732858789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device .2732858789 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.2801468481 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 130264569074 ps |
| CPU time | 2494.7 seconds |
| Started | Jul 13 08:23:20 PM PDT 24 |
| Finished | Jul 13 09:04:55 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-3b748f3a-abba-41ea-ba4e-6fa84f161be3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801468481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.2801468481 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.1671453141 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 162551474 ps |
| CPU time | 10.34 seconds |
| Started | Jul 13 08:23:22 PM PDT 24 |
| Finished | Jul 13 08:23:32 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-dfb1e7c9-cb13-4cfa-9c72-e3eae9996c76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671453141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.1671453141 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.3881658 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 110958063 ps |
| CPU time | 11.53 seconds |
| Started | Jul 13 08:23:22 PM PDT 24 |
| Finished | Jul 13 08:23:34 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-2c09a16d-f201-4c7e-a751-5183eafd1f04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3881658 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.150401968 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 248498713 ps |
| CPU time | 28.84 seconds |
| Started | Jul 13 08:23:21 PM PDT 24 |
| Finished | Jul 13 08:23:50 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-e47abc24-3d82-4852-ab83-d1b4c14a947f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150401968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.150401968 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.711312851 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 18679050427 ps |
| CPU time | 215.26 seconds |
| Started | Jul 13 08:23:20 PM PDT 24 |
| Finished | Jul 13 08:26:56 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-41b0f59a-6ffa-474c-9214-34a3c4a8504e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711312851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.711312851 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.3874856075 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 59555130082 ps |
| CPU time | 1132.23 seconds |
| Started | Jul 13 08:23:20 PM PDT 24 |
| Finished | Jul 13 08:42:13 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-c57d6d64-8458-4e86-9e78-ef243ff0df06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874856075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3874856075 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.2565521067 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 371066379 ps |
| CPU time | 35.97 seconds |
| Started | Jul 13 08:23:20 PM PDT 24 |
| Finished | Jul 13 08:23:57 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-46271116-e37f-4ec3-8b8c-7cba1c5d63b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565521067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.2565521067 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.4262031462 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 959576348 ps |
| CPU time | 34.49 seconds |
| Started | Jul 13 08:23:20 PM PDT 24 |
| Finished | Jul 13 08:23:54 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-72a6c5cf-7ca9-455e-8e26-ba25a7020377 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262031462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.4262031462 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.2898281590 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 50521633 ps |
| CPU time | 7.03 seconds |
| Started | Jul 13 08:23:21 PM PDT 24 |
| Finished | Jul 13 08:23:29 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-866feed1-4f6d-440c-bed9-ada2d0de62c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898281590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2898281590 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.2592478147 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 9315938747 ps |
| CPU time | 105.9 seconds |
| Started | Jul 13 08:23:22 PM PDT 24 |
| Finished | Jul 13 08:25:09 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-c1845efc-fe42-4a6d-89b8-959525950204 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592478147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2592478147 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.3718532103 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 5631395520 ps |
| CPU time | 98.21 seconds |
| Started | Jul 13 08:23:20 PM PDT 24 |
| Finished | Jul 13 08:24:59 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-77b0e296-ddff-40bd-97e8-36c3cb0c7b37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718532103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3718532103 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.807657330 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 41240285 ps |
| CPU time | 6.2 seconds |
| Started | Jul 13 08:23:18 PM PDT 24 |
| Finished | Jul 13 08:23:25 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-fa224fbf-48fd-45c5-813e-bf9d3dff270e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807657330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays .807657330 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.2590212099 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 985155674 ps |
| CPU time | 47.87 seconds |
| Started | Jul 13 08:23:20 PM PDT 24 |
| Finished | Jul 13 08:24:09 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-d2d2aad1-67a7-46fb-abbf-c29538048303 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590212099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2590212099 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.2851208197 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 12245411789 ps |
| CPU time | 466.25 seconds |
| Started | Jul 13 08:23:23 PM PDT 24 |
| Finished | Jul 13 08:31:10 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-6dd921f6-d08f-4d39-b664-00d0f6b3d38b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851208197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2851208197 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.2964907875 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 366051154 ps |
| CPU time | 123.56 seconds |
| Started | Jul 13 08:23:21 PM PDT 24 |
| Finished | Jul 13 08:25:25 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-5377e589-f61d-4d70-81dd-04461e7c27ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964907875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_rand_reset.2964907875 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.2400329534 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 6745692613 ps |
| CPU time | 401.16 seconds |
| Started | Jul 13 08:23:24 PM PDT 24 |
| Finished | Jul 13 08:30:06 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-239ca660-012d-4e7c-ab5b-3bd8b3ebed50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400329534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al l_with_reset_error.2400329534 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.2625652606 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 452213224 ps |
| CPU time | 23.85 seconds |
| Started | Jul 13 08:23:23 PM PDT 24 |
| Finished | Jul 13 08:23:47 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-d82e815d-6c22-46f5-a04e-ce89e4cac88e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625652606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2625652606 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.154388504 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 369335979 ps |
| CPU time | 46.3 seconds |
| Started | Jul 13 08:23:29 PM PDT 24 |
| Finished | Jul 13 08:24:16 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-570bd231-5fad-482e-87be-fb7f3d2207c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154388504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device. 154388504 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.2495829172 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 55543027184 ps |
| CPU time | 1095.37 seconds |
| Started | Jul 13 08:23:31 PM PDT 24 |
| Finished | Jul 13 08:41:47 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-544c3bed-cda5-438c-acdd-af2512c8b079 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495829172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_ device_slow_rsp.2495829172 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.719319685 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 267460377 ps |
| CPU time | 32.94 seconds |
| Started | Jul 13 08:23:39 PM PDT 24 |
| Finished | Jul 13 08:24:12 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-6a8aec02-0a7d-4c5e-91b7-2244d986417a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719319685 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr .719319685 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.1309988469 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 430623382 ps |
| CPU time | 20.52 seconds |
| Started | Jul 13 08:23:29 PM PDT 24 |
| Finished | Jul 13 08:23:49 PM PDT 24 |
| Peak memory | 575012 kb |
| Host | smart-a6e32564-b767-4422-b123-ee9da01a07dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309988469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1309988469 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.3403332935 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 749254414 ps |
| CPU time | 29.77 seconds |
| Started | Jul 13 08:23:29 PM PDT 24 |
| Finished | Jul 13 08:24:00 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-eb084f2f-3d44-4060-967e-6bc854399b0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403332935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.3403332935 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.119285923 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 25893562699 ps |
| CPU time | 281.68 seconds |
| Started | Jul 13 08:23:31 PM PDT 24 |
| Finished | Jul 13 08:28:14 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-11d0371f-328d-4e56-befa-b88b08e1d13d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119285923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.119285923 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.1307855446 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 47116077478 ps |
| CPU time | 933.7 seconds |
| Started | Jul 13 08:23:28 PM PDT 24 |
| Finished | Jul 13 08:39:03 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-c8854cde-f958-466e-9710-b8536f4d0fec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307855446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1307855446 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.134880665 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 357046211 ps |
| CPU time | 34.38 seconds |
| Started | Jul 13 08:23:32 PM PDT 24 |
| Finished | Jul 13 08:24:07 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-6dcc291f-dcca-4973-87a1-18b36c5c4e7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134880665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_dela ys.134880665 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.1128820668 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 259351215 ps |
| CPU time | 10.76 seconds |
| Started | Jul 13 08:23:28 PM PDT 24 |
| Finished | Jul 13 08:23:39 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-95458984-c945-4b90-b485-407b83ac97a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128820668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1128820668 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.1414121513 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 214304057 ps |
| CPU time | 9.38 seconds |
| Started | Jul 13 08:23:29 PM PDT 24 |
| Finished | Jul 13 08:23:39 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-ba23261d-2d38-426a-9e6e-8a22ff35b6af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414121513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1414121513 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.1276890222 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 9749205767 ps |
| CPU time | 120.4 seconds |
| Started | Jul 13 08:23:32 PM PDT 24 |
| Finished | Jul 13 08:25:33 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-5caa6c58-f4bc-4f34-9059-73d76e8ad435 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276890222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1276890222 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.1697251248 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 5481787176 ps |
| CPU time | 104.91 seconds |
| Started | Jul 13 08:23:32 PM PDT 24 |
| Finished | Jul 13 08:25:17 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-8e2f00b7-a296-407b-8b4b-125bf927eaf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697251248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1697251248 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.3555647594 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 47562404 ps |
| CPU time | 6.48 seconds |
| Started | Jul 13 08:23:29 PM PDT 24 |
| Finished | Jul 13 08:23:36 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-9cfdae1a-4a82-4120-b5fc-e7e1201c36cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555647594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay s.3555647594 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.2493332312 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 4129954997 ps |
| CPU time | 154.24 seconds |
| Started | Jul 13 08:23:38 PM PDT 24 |
| Finished | Jul 13 08:26:12 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-79a6fe84-4e53-4044-85e6-eeb46ef6a02e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493332312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2493332312 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.1622598997 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 693388513 ps |
| CPU time | 56.13 seconds |
| Started | Jul 13 08:23:39 PM PDT 24 |
| Finished | Jul 13 08:24:36 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-ea7f686b-c705-4dac-b6ba-9b548232b571 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622598997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1622598997 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.3661446689 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 103017558 ps |
| CPU time | 25.2 seconds |
| Started | Jul 13 08:23:37 PM PDT 24 |
| Finished | Jul 13 08:24:02 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-09274f0f-4411-4ea6-ba0d-1eed13318dfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661446689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.3661446689 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.3401290283 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 2926822686 ps |
| CPU time | 322.57 seconds |
| Started | Jul 13 08:23:38 PM PDT 24 |
| Finished | Jul 13 08:29:01 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-927e03f4-5f1b-4d57-a882-6ad68ef760ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401290283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.3401290283 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.1475283751 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 1250180860 ps |
| CPU time | 51.36 seconds |
| Started | Jul 13 08:23:39 PM PDT 24 |
| Finished | Jul 13 08:24:31 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-75c7a446-f456-4be4-aead-7582936b9422 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475283751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.1475283751 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.1393527188 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 2991157896 ps |
| CPU time | 163.82 seconds |
| Started | Jul 13 08:23:38 PM PDT 24 |
| Finished | Jul 13 08:26:23 PM PDT 24 |
| Peak memory | 599124 kb |
| Host | smart-994192e3-0555-44cd-913b-eead0ed44a8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393527188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.1393527188 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.1850056498 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 82221142025 ps |
| CPU time | 1571.22 seconds |
| Started | Jul 13 08:23:48 PM PDT 24 |
| Finished | Jul 13 08:49:59 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-f7638fbc-ef53-4156-abbd-746170084d31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850056498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_ device_slow_rsp.1850056498 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.2440861560 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 35332811 ps |
| CPU time | 5.59 seconds |
| Started | Jul 13 08:23:47 PM PDT 24 |
| Finished | Jul 13 08:23:53 PM PDT 24 |
| Peak memory | 573960 kb |
| Host | smart-3f1179f5-3c24-44a9-b4b0-9e691a7d8baf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440861560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.2440861560 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.312942704 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 1552624387 ps |
| CPU time | 57.14 seconds |
| Started | Jul 13 08:23:46 PM PDT 24 |
| Finished | Jul 13 08:24:44 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-e122ca49-2d64-4890-bccf-326314885022 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312942704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.312942704 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.1116574196 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 348151465 ps |
| CPU time | 35.63 seconds |
| Started | Jul 13 08:23:37 PM PDT 24 |
| Finished | Jul 13 08:24:13 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-905b1bf0-55d4-4c84-8b2e-97433c220fec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116574196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.1116574196 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.4182525731 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 52076547093 ps |
| CPU time | 575.79 seconds |
| Started | Jul 13 08:23:37 PM PDT 24 |
| Finished | Jul 13 08:33:13 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-b244f4c8-2da0-4a2b-9c30-f84c5b630368 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182525731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.4182525731 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.636787256 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 36370866972 ps |
| CPU time | 624.44 seconds |
| Started | Jul 13 08:23:48 PM PDT 24 |
| Finished | Jul 13 08:34:12 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-69786fe1-4015-427e-8ea2-ceb0cf927431 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636787256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.636787256 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.500763737 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 617272444 ps |
| CPU time | 60.29 seconds |
| Started | Jul 13 08:23:38 PM PDT 24 |
| Finished | Jul 13 08:24:38 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-ea586989-0101-45be-b980-3aee4c870257 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500763737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_dela ys.500763737 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.1598295654 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 2133979579 ps |
| CPU time | 68.29 seconds |
| Started | Jul 13 08:23:54 PM PDT 24 |
| Finished | Jul 13 08:25:03 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-650005ea-2513-4b41-b55f-86b5ab56e9fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598295654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1598295654 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.4209955653 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 47077091 ps |
| CPU time | 6.99 seconds |
| Started | Jul 13 08:23:36 PM PDT 24 |
| Finished | Jul 13 08:23:43 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-fdec9aff-57aa-468d-806e-e824c3b2ba4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209955653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.4209955653 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.1293989796 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 7948958986 ps |
| CPU time | 98.77 seconds |
| Started | Jul 13 08:23:37 PM PDT 24 |
| Finished | Jul 13 08:25:16 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-0bb90ca5-2c6f-4348-9a4d-aa5f67312e28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293989796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1293989796 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.979170793 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 3689859004 ps |
| CPU time | 66.63 seconds |
| Started | Jul 13 08:23:38 PM PDT 24 |
| Finished | Jul 13 08:24:45 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-2cf05755-ce75-4f76-9338-bdecfbe8c378 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979170793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.979170793 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.168612476 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 55516115 ps |
| CPU time | 8.12 seconds |
| Started | Jul 13 08:23:37 PM PDT 24 |
| Finished | Jul 13 08:23:46 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-bc937354-c209-44fe-b247-30efde38e0fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168612476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays .168612476 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.3017431668 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 517793151 ps |
| CPU time | 48.77 seconds |
| Started | Jul 13 08:23:48 PM PDT 24 |
| Finished | Jul 13 08:24:37 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-58ee4a47-c4e7-4bd5-8d21-51ca21cbbd0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017431668 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3017431668 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.1996326053 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 14862279095 ps |
| CPU time | 746.92 seconds |
| Started | Jul 13 08:23:47 PM PDT 24 |
| Finished | Jul 13 08:36:14 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-634c586b-24a3-489f-868d-271207063211 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996326053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.1996326053 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3903644785 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 208863080 ps |
| CPU time | 64.01 seconds |
| Started | Jul 13 08:23:49 PM PDT 24 |
| Finished | Jul 13 08:24:53 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-3ae3db1a-bdc9-4211-91f8-8a8789c94f44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903644785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al l_with_reset_error.3903644785 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.305494531 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1128083989 ps |
| CPU time | 47.36 seconds |
| Started | Jul 13 08:23:54 PM PDT 24 |
| Finished | Jul 13 08:24:42 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-2b93539e-ee38-4a73-ae71-9baed6913126 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305494531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.305494531 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.2387971850 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 4468357526 ps |
| CPU time | 325.89 seconds |
| Started | Jul 13 08:23:55 PM PDT 24 |
| Finished | Jul 13 08:29:21 PM PDT 24 |
| Peak memory | 598824 kb |
| Host | smart-9c028c97-3145-455e-b185-eaeca4c11e05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387971850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.2387971850 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.704873782 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 306314975 ps |
| CPU time | 29.35 seconds |
| Started | Jul 13 08:23:57 PM PDT 24 |
| Finished | Jul 13 08:24:26 PM PDT 24 |
| Peak memory | 575196 kb |
| Host | smart-f6684891-dc50-49a1-8477-24863c923a88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704873782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device. 704873782 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.1246491593 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 9756253443 ps |
| CPU time | 173.12 seconds |
| Started | Jul 13 08:24:01 PM PDT 24 |
| Finished | Jul 13 08:26:54 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-f3751c24-8eb1-4a68-92f0-d41a3b6543d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246491593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.1246491593 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.1124496893 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 411179642 ps |
| CPU time | 18.83 seconds |
| Started | Jul 13 08:24:04 PM PDT 24 |
| Finished | Jul 13 08:24:23 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-79ac57dd-b127-4068-a06e-621643c910bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124496893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.1124496893 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.3380983728 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 1905089578 ps |
| CPU time | 53.76 seconds |
| Started | Jul 13 08:24:00 PM PDT 24 |
| Finished | Jul 13 08:24:54 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-5a5a30a6-4b0a-46d9-8c12-3f22590d903d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380983728 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3380983728 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.1536281969 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 334477599 ps |
| CPU time | 36.93 seconds |
| Started | Jul 13 08:23:55 PM PDT 24 |
| Finished | Jul 13 08:24:32 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-b92d103f-3bca-4e57-86bc-7982f88727fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536281969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.1536281969 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.2618124478 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 30931549897 ps |
| CPU time | 364.26 seconds |
| Started | Jul 13 08:23:56 PM PDT 24 |
| Finished | Jul 13 08:30:01 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-0317fad3-6693-42f7-a56d-5e628df573d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618124478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2618124478 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.521300870 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 39201305818 ps |
| CPU time | 803.05 seconds |
| Started | Jul 13 08:23:55 PM PDT 24 |
| Finished | Jul 13 08:37:19 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-27b4e238-4187-4b70-9c06-5ab815c500fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521300870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.521300870 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.596403916 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 312861018 ps |
| CPU time | 31.12 seconds |
| Started | Jul 13 08:23:55 PM PDT 24 |
| Finished | Jul 13 08:24:27 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-d8de91f2-461f-4adf-9d1f-82659b20d705 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596403916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_dela ys.596403916 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.2648422877 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 795324809 ps |
| CPU time | 27.62 seconds |
| Started | Jul 13 08:23:56 PM PDT 24 |
| Finished | Jul 13 08:24:24 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-7c057941-1321-49ab-b16b-23cb60f1ae6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648422877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2648422877 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.3000117410 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 55986499 ps |
| CPU time | 7.37 seconds |
| Started | Jul 13 08:23:50 PM PDT 24 |
| Finished | Jul 13 08:23:58 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-2824b95b-17f5-473d-bb41-327e8d5adc9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000117410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3000117410 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.4147983146 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 8861229073 ps |
| CPU time | 105.03 seconds |
| Started | Jul 13 08:23:55 PM PDT 24 |
| Finished | Jul 13 08:25:41 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-b3904823-c274-48ab-8f1d-70f8a81d9e82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147983146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.4147983146 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.2234765199 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 6874099045 ps |
| CPU time | 122.11 seconds |
| Started | Jul 13 08:24:00 PM PDT 24 |
| Finished | Jul 13 08:26:02 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-687fa9c8-50b6-4945-bc89-b4b6d611fcee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234765199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2234765199 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.1233344048 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 47867374 ps |
| CPU time | 6.58 seconds |
| Started | Jul 13 08:23:47 PM PDT 24 |
| Finished | Jul 13 08:23:54 PM PDT 24 |
| Peak memory | 573996 kb |
| Host | smart-62a0f945-34d4-4914-acec-421b5dc884bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233344048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.1233344048 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.4124264165 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 9370266093 ps |
| CPU time | 404.41 seconds |
| Started | Jul 13 08:24:04 PM PDT 24 |
| Finished | Jul 13 08:30:49 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-94b97040-9fb2-4273-b92b-6664fc975d19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124264165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.4124264165 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.3434233939 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 2365147451 ps |
| CPU time | 82.52 seconds |
| Started | Jul 13 08:24:03 PM PDT 24 |
| Finished | Jul 13 08:25:26 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-d00db0df-98e3-463e-9ac7-24ee5f9d135a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434233939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3434233939 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.2336281263 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 1034144514 ps |
| CPU time | 123.36 seconds |
| Started | Jul 13 08:24:04 PM PDT 24 |
| Finished | Jul 13 08:26:08 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-6fc04720-842b-4750-ae64-e4d283409f74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336281263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_rand_reset.2336281263 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3131919226 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 17716890472 ps |
| CPU time | 841.74 seconds |
| Started | Jul 13 08:24:03 PM PDT 24 |
| Finished | Jul 13 08:38:06 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-1597c225-587c-4a8e-8d3e-256d09f4f800 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131919226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.3131919226 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.3459849694 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 21828174 ps |
| CPU time | 6.24 seconds |
| Started | Jul 13 08:24:00 PM PDT 24 |
| Finished | Jul 13 08:24:07 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-b2c0edcd-aeaa-42ea-a4e2-4c2549381b56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459849694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3459849694 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.1547738486 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 2006367302 ps |
| CPU time | 93.45 seconds |
| Started | Jul 13 08:24:15 PM PDT 24 |
| Finished | Jul 13 08:25:49 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-8e89fa6e-ff5c-4e59-be99-d8691d89139b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547738486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device .1547738486 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.1316289227 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 55602476943 ps |
| CPU time | 1062.23 seconds |
| Started | Jul 13 08:24:14 PM PDT 24 |
| Finished | Jul 13 08:41:57 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-6dcad0b4-d625-4d70-974b-6404f3129532 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316289227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.1316289227 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.1644274065 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 24126038 ps |
| CPU time | 5.5 seconds |
| Started | Jul 13 08:24:13 PM PDT 24 |
| Finished | Jul 13 08:24:19 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-dc6fd7fa-1ab9-4b00-95a5-0772ff4e8435 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644274065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add r.1644274065 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.2785550484 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 1876809862 ps |
| CPU time | 77.31 seconds |
| Started | Jul 13 08:24:13 PM PDT 24 |
| Finished | Jul 13 08:25:31 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-c5532ec4-4b95-4677-8772-198b9a77a7cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785550484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2785550484 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.2198994261 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 212621022 ps |
| CPU time | 24.21 seconds |
| Started | Jul 13 08:24:03 PM PDT 24 |
| Finished | Jul 13 08:24:27 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-508fafff-e93d-4917-8a16-fb07fe047a88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198994261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.2198994261 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.392987485 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 11624602013 ps |
| CPU time | 138.36 seconds |
| Started | Jul 13 08:24:03 PM PDT 24 |
| Finished | Jul 13 08:26:22 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-2a563649-e844-49c8-b8cc-1ae94a817529 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392987485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.392987485 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.3504821848 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 11172409161 ps |
| CPU time | 210.27 seconds |
| Started | Jul 13 08:24:03 PM PDT 24 |
| Finished | Jul 13 08:27:33 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-769b3317-11ef-47f1-9a64-87df486da037 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504821848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3504821848 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.3932138286 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 357055519 ps |
| CPU time | 37.32 seconds |
| Started | Jul 13 08:24:06 PM PDT 24 |
| Finished | Jul 13 08:24:43 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-12874a1d-b6b3-4d07-87a3-a9874967387f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932138286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del ays.3932138286 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.1474285854 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 798141924 ps |
| CPU time | 24.39 seconds |
| Started | Jul 13 08:24:14 PM PDT 24 |
| Finished | Jul 13 08:24:39 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-10fce720-5e50-4a28-b6d5-a30b9eb27c8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474285854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1474285854 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.778362697 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 44300066 ps |
| CPU time | 6.71 seconds |
| Started | Jul 13 08:24:03 PM PDT 24 |
| Finished | Jul 13 08:24:11 PM PDT 24 |
| Peak memory | 575176 kb |
| Host | smart-e79e9065-feb5-4956-8c29-d6d672dc2870 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778362697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.778362697 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.3864847309 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 6210849429 ps |
| CPU time | 71.14 seconds |
| Started | Jul 13 08:24:04 PM PDT 24 |
| Finished | Jul 13 08:25:16 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-70c21615-55c7-41a2-abb6-80af0ed15210 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864847309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3864847309 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.4265237936 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 5755610132 ps |
| CPU time | 113.24 seconds |
| Started | Jul 13 08:24:05 PM PDT 24 |
| Finished | Jul 13 08:25:59 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-384e71b8-bb52-49a4-afff-ec3055d5281f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265237936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.4265237936 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.788983513 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 46169891 ps |
| CPU time | 6.42 seconds |
| Started | Jul 13 08:24:05 PM PDT 24 |
| Finished | Jul 13 08:24:12 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-4ca6d1ee-5e88-41fd-965b-3c6da5da54d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788983513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays .788983513 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.2148104718 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 4369804591 ps |
| CPU time | 183.37 seconds |
| Started | Jul 13 08:24:22 PM PDT 24 |
| Finished | Jul 13 08:27:26 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-fe7c7f35-6bd1-4e3e-b2ca-235eb1189cbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148104718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2148104718 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.484809446 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 1965578925 ps |
| CPU time | 154.46 seconds |
| Started | Jul 13 08:24:24 PM PDT 24 |
| Finished | Jul 13 08:27:00 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-1cae6eef-a48c-4563-bb02-362065986af6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484809446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.484809446 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.512759576 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 460031300 ps |
| CPU time | 146.21 seconds |
| Started | Jul 13 08:24:24 PM PDT 24 |
| Finished | Jul 13 08:26:51 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-d6187eca-67c3-49b1-a024-74ec665e2e0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512759576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_ with_rand_reset.512759576 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.1479914929 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 833432577 ps |
| CPU time | 114.87 seconds |
| Started | Jul 13 08:24:24 PM PDT 24 |
| Finished | Jul 13 08:26:20 PM PDT 24 |
| Peak memory | 575176 kb |
| Host | smart-a3a723a5-dd30-49b4-8568-00d78c049680 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479914929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al l_with_reset_error.1479914929 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.1880986699 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 216709774 ps |
| CPU time | 28.71 seconds |
| Started | Jul 13 08:24:14 PM PDT 24 |
| Finished | Jul 13 08:24:43 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-d00261fd-0446-4aa2-8d06-a53948074627 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880986699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1880986699 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.1159015051 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 3298276069 ps |
| CPU time | 146.76 seconds |
| Started | Jul 13 08:24:23 PM PDT 24 |
| Finished | Jul 13 08:26:51 PM PDT 24 |
| Peak memory | 598740 kb |
| Host | smart-9c174963-20e1-4275-8a40-d844bcbe90d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159015051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.1159015051 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.1753989660 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 1035760393 ps |
| CPU time | 52.21 seconds |
| Started | Jul 13 08:24:22 PM PDT 24 |
| Finished | Jul 13 08:25:16 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-74134a2f-ccf8-4272-89a0-69b6a03a4101 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753989660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .1753989660 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.3690022585 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 23943939151 ps |
| CPU time | 443.34 seconds |
| Started | Jul 13 08:24:22 PM PDT 24 |
| Finished | Jul 13 08:31:46 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-c992379c-0813-4435-8778-a8a2c8e4d222 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690022585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_ device_slow_rsp.3690022585 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.4211389750 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 581123746 ps |
| CPU time | 27.23 seconds |
| Started | Jul 13 08:24:21 PM PDT 24 |
| Finished | Jul 13 08:24:48 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-318b7362-f888-4890-8db8-871a2bef2aed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211389750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.4211389750 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.1619097215 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 1005858552 ps |
| CPU time | 36.73 seconds |
| Started | Jul 13 08:24:21 PM PDT 24 |
| Finished | Jul 13 08:24:58 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-bd8fe7da-6fa4-4f5c-ae98-7c91fa5cd9d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619097215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1619097215 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.2253905288 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 74513097 ps |
| CPU time | 10.24 seconds |
| Started | Jul 13 08:24:25 PM PDT 24 |
| Finished | Jul 13 08:24:36 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-e3b4dc23-32a9-43c4-9f48-a1c985f0217b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253905288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.2253905288 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.1151074045 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 49975362330 ps |
| CPU time | 615.16 seconds |
| Started | Jul 13 08:24:24 PM PDT 24 |
| Finished | Jul 13 08:34:40 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-c4670df7-3438-4061-8ea2-3ec4da0fe3a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151074045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1151074045 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.3585666971 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 20071438460 ps |
| CPU time | 371.62 seconds |
| Started | Jul 13 08:24:23 PM PDT 24 |
| Finished | Jul 13 08:30:36 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-d77a5d4f-d5b3-454e-ad1c-93c9bf9281b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585666971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3585666971 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.2715132365 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 209483122 ps |
| CPU time | 22.96 seconds |
| Started | Jul 13 08:24:23 PM PDT 24 |
| Finished | Jul 13 08:24:47 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-fe9c17bf-691a-46b2-b582-cac5bc2563fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715132365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.2715132365 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.1453631584 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 89360601 ps |
| CPU time | 10.55 seconds |
| Started | Jul 13 08:24:22 PM PDT 24 |
| Finished | Jul 13 08:24:33 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-4a4684c9-55d1-4b7c-8c12-0041490ecd73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453631584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1453631584 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.4070811513 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 54549676 ps |
| CPU time | 7.08 seconds |
| Started | Jul 13 08:24:22 PM PDT 24 |
| Finished | Jul 13 08:24:29 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-e136b1bf-cc55-49bf-bd83-f2d408a623bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070811513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.4070811513 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.3789508941 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 8748212037 ps |
| CPU time | 102.92 seconds |
| Started | Jul 13 08:24:22 PM PDT 24 |
| Finished | Jul 13 08:26:05 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-336b344e-b464-4ccf-ba38-de8bfca9f7d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789508941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3789508941 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.2903688443 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 5216112160 ps |
| CPU time | 95.15 seconds |
| Started | Jul 13 08:24:23 PM PDT 24 |
| Finished | Jul 13 08:25:59 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-10783aa1-5b5a-49cf-a929-8ab8d2649b7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903688443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.2903688443 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.2379818978 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 42230820 ps |
| CPU time | 6.42 seconds |
| Started | Jul 13 08:24:24 PM PDT 24 |
| Finished | Jul 13 08:24:31 PM PDT 24 |
| Peak memory | 573848 kb |
| Host | smart-00190b82-c1c3-462e-8c30-b890e4e4be71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379818978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.2379818978 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.1676596929 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 11633136115 ps |
| CPU time | 499.23 seconds |
| Started | Jul 13 08:24:23 PM PDT 24 |
| Finished | Jul 13 08:32:43 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-dd361d19-1cd2-4d8c-9ff5-7e27163c2317 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676596929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1676596929 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.339216327 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 8009820345 ps |
| CPU time | 308.6 seconds |
| Started | Jul 13 08:24:31 PM PDT 24 |
| Finished | Jul 13 08:29:40 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-62ee65c4-528e-44cd-8ba5-df638f767c38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339216327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.339216327 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.3575431975 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 364277627 ps |
| CPU time | 116.08 seconds |
| Started | Jul 13 08:24:24 PM PDT 24 |
| Finished | Jul 13 08:26:21 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-e229a933-9d18-438f-875c-a844fd2ebd00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575431975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.3575431975 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.1158328444 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 6017606002 ps |
| CPU time | 608.54 seconds |
| Started | Jul 13 08:24:31 PM PDT 24 |
| Finished | Jul 13 08:34:40 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-4befde64-4a15-404b-8d3f-319ba5e219ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158328444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.1158328444 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.451828566 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 89585553 ps |
| CPU time | 15.77 seconds |
| Started | Jul 13 08:24:26 PM PDT 24 |
| Finished | Jul 13 08:24:42 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-c62ddbb7-fa14-4a63-ae7f-7e90c51f7fd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451828566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.451828566 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.2732137559 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 60695234402 ps |
| CPU time | 6289.82 seconds |
| Started | Jul 13 08:14:34 PM PDT 24 |
| Finished | Jul 13 09:59:25 PM PDT 24 |
| Peak memory | 593712 kb |
| Host | smart-05f12916-74e5-4340-a60b-9478862b2c20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732137559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.2732137559 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.1804714785 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 4733536574 ps |
| CPU time | 365.69 seconds |
| Started | Jul 13 08:15:23 PM PDT 24 |
| Finished | Jul 13 08:21:29 PM PDT 24 |
| Peak memory | 598352 kb |
| Host | smart-e4376ad4-cf76-4ef8-bd42-58b331f94895 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804714785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.1804714785 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.3712668697 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 29365335998 ps |
| CPU time | 3655.92 seconds |
| Started | Jul 13 08:14:59 PM PDT 24 |
| Finished | Jul 13 09:15:55 PM PDT 24 |
| Peak memory | 593524 kb |
| Host | smart-1f348cdf-2f90-4122-9c1c-0410872f6af9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712668697 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.3712668697 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.3970934572 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 767067507 ps |
| CPU time | 42.81 seconds |
| Started | Jul 13 08:14:53 PM PDT 24 |
| Finished | Jul 13 08:15:36 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-9ffb629d-94be-43e4-9f83-a4d9afae685c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970934572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 3970934572 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3729855520 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 155127730296 ps |
| CPU time | 2849.64 seconds |
| Started | Jul 13 08:14:56 PM PDT 24 |
| Finished | Jul 13 09:02:26 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-4326509a-ed96-43bd-a7b1-2458af977545 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729855520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d evice_slow_rsp.3729855520 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.601586982 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 995393061 ps |
| CPU time | 45.78 seconds |
| Started | Jul 13 08:15:11 PM PDT 24 |
| Finished | Jul 13 08:15:57 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-83774d8c-2cd8-42a6-85c0-aebf1430aaa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601586982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr. 601586982 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.3737730514 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 534983702 ps |
| CPU time | 51.13 seconds |
| Started | Jul 13 08:15:01 PM PDT 24 |
| Finished | Jul 13 08:15:52 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-a49d95d0-b7b2-4997-95e6-7dc4acd5ee17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737730514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3737730514 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.573580528 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 804694018 ps |
| CPU time | 39.35 seconds |
| Started | Jul 13 08:14:55 PM PDT 24 |
| Finished | Jul 13 08:15:35 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-330c99ef-9a8f-453d-a111-569bce90af83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573580528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.573580528 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.2239700647 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 86168341835 ps |
| CPU time | 968.02 seconds |
| Started | Jul 13 08:14:52 PM PDT 24 |
| Finished | Jul 13 08:31:00 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-1a8ac876-b838-4687-8d1e-70296f47bbd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239700647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2239700647 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.1421326641 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 24195793560 ps |
| CPU time | 435.7 seconds |
| Started | Jul 13 08:14:56 PM PDT 24 |
| Finished | Jul 13 08:22:12 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-06d41762-858c-4292-ba40-a8141a3bc58b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421326641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1421326641 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.3640146240 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 95871879 ps |
| CPU time | 13.53 seconds |
| Started | Jul 13 08:14:54 PM PDT 24 |
| Finished | Jul 13 08:15:08 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-1f630e49-192f-48d9-b4fb-d2ad6dce1b5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640146240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela ys.3640146240 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.746254514 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 2365619930 ps |
| CPU time | 86.35 seconds |
| Started | Jul 13 08:14:53 PM PDT 24 |
| Finished | Jul 13 08:16:19 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-3873db81-707e-430d-9d62-0c990af1f7e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746254514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.746254514 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.2112508653 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 194696356 ps |
| CPU time | 11.8 seconds |
| Started | Jul 13 08:14:45 PM PDT 24 |
| Finished | Jul 13 08:14:57 PM PDT 24 |
| Peak memory | 574036 kb |
| Host | smart-3c5cc9b9-efd9-4995-b7a7-129a99d9a43b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112508653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2112508653 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.3100026329 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 10114841389 ps |
| CPU time | 141.56 seconds |
| Started | Jul 13 08:15:16 PM PDT 24 |
| Finished | Jul 13 08:17:38 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-3b104533-5348-4333-b791-bcc82cb1223c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100026329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3100026329 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2383887131 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 5006343095 ps |
| CPU time | 92.7 seconds |
| Started | Jul 13 08:14:55 PM PDT 24 |
| Finished | Jul 13 08:16:28 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-f6d08354-6fb2-4bbe-8b7b-0e0e72156b8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383887131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2383887131 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.1650021160 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 43059583 ps |
| CPU time | 7.18 seconds |
| Started | Jul 13 08:14:43 PM PDT 24 |
| Finished | Jul 13 08:14:51 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-fe4f8451-165e-4db7-80d5-12e0b10a305d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650021160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .1650021160 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.473180827 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 1478112286 ps |
| CPU time | 131.15 seconds |
| Started | Jul 13 08:15:14 PM PDT 24 |
| Finished | Jul 13 08:17:25 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-9445b409-8738-47c9-85e0-aefb1a56307a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473180827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.473180827 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.1284624151 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 4136275575 ps |
| CPU time | 153.35 seconds |
| Started | Jul 13 08:15:10 PM PDT 24 |
| Finished | Jul 13 08:17:43 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-efe97cbd-4b97-4a53-a061-dab22fd4a8e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284624151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1284624151 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.1651307033 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 3337567239 ps |
| CPU time | 552.33 seconds |
| Started | Jul 13 08:15:17 PM PDT 24 |
| Finished | Jul 13 08:24:29 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-d50a5e7c-b62e-4c28-9915-c2e5ff93494a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651307033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.1651307033 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.1903203223 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 81552184 ps |
| CPU time | 17.3 seconds |
| Started | Jul 13 08:15:22 PM PDT 24 |
| Finished | Jul 13 08:15:40 PM PDT 24 |
| Peak memory | 575108 kb |
| Host | smart-240257c2-5b63-4f86-8d2e-84ce7c08554d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903203223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.1903203223 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.1364780900 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 95981992 ps |
| CPU time | 16.27 seconds |
| Started | Jul 13 08:14:59 PM PDT 24 |
| Finished | Jul 13 08:15:15 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-a1ca4455-f6cc-443b-8063-104e3b7ff947 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364780900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1364780900 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.3022372868 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 1192295854 ps |
| CPU time | 104.45 seconds |
| Started | Jul 13 08:24:32 PM PDT 24 |
| Finished | Jul 13 08:26:18 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-403bb126-4f4b-4fbd-91a5-5ef3254c3b03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022372868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device .3022372868 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.445536848 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 34978561797 ps |
| CPU time | 654.15 seconds |
| Started | Jul 13 08:24:31 PM PDT 24 |
| Finished | Jul 13 08:35:27 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-6d5fdd07-ba70-4713-83fd-a28c8d7e4536 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445536848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_d evice_slow_rsp.445536848 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.2222427832 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 198972345 ps |
| CPU time | 10.9 seconds |
| Started | Jul 13 08:24:42 PM PDT 24 |
| Finished | Jul 13 08:24:54 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-bc1a8f28-6654-4a5f-92ed-42a79ba2c909 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222427832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.2222427832 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.4270035980 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 472430813 ps |
| CPU time | 47.11 seconds |
| Started | Jul 13 08:24:31 PM PDT 24 |
| Finished | Jul 13 08:25:19 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-7abf9d93-d2ba-484a-ab73-2664cb75e182 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270035980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.4270035980 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.1842185064 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 369338198 ps |
| CPU time | 17.85 seconds |
| Started | Jul 13 08:24:32 PM PDT 24 |
| Finished | Jul 13 08:24:51 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-fb66fa1b-794c-4e10-919e-97a4e6c629d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842185064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.1842185064 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.2241116729 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 21315945515 ps |
| CPU time | 253.16 seconds |
| Started | Jul 13 08:24:32 PM PDT 24 |
| Finished | Jul 13 08:28:46 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-a08d91b4-abcd-4566-8fb5-8f4c05746de8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241116729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2241116729 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.1657520562 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 40363121585 ps |
| CPU time | 783.86 seconds |
| Started | Jul 13 08:24:31 PM PDT 24 |
| Finished | Jul 13 08:37:36 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-08973bbc-616d-4693-aecf-b938c10a3190 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657520562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1657520562 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.1498249858 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 463652049 ps |
| CPU time | 52.54 seconds |
| Started | Jul 13 08:24:32 PM PDT 24 |
| Finished | Jul 13 08:25:26 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-8dc9c496-e211-47a9-a62c-ec5b8f4985ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498249858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del ays.1498249858 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.2732173246 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 988789370 ps |
| CPU time | 36.3 seconds |
| Started | Jul 13 08:24:32 PM PDT 24 |
| Finished | Jul 13 08:25:09 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-2a4816dc-105f-4c49-a6d4-e7595a5399f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732173246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2732173246 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.185108300 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 192083779 ps |
| CPU time | 9.57 seconds |
| Started | Jul 13 08:24:31 PM PDT 24 |
| Finished | Jul 13 08:24:41 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-ce8862f7-fc45-45ad-a199-29bb40dcc782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185108300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.185108300 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.3771995306 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 4634707113 ps |
| CPU time | 56.26 seconds |
| Started | Jul 13 08:24:30 PM PDT 24 |
| Finished | Jul 13 08:25:27 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-c3a139ca-0036-4a25-b557-adcbf6286cc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771995306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3771995306 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.2176976501 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 4776924972 ps |
| CPU time | 85.45 seconds |
| Started | Jul 13 08:24:32 PM PDT 24 |
| Finished | Jul 13 08:25:58 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-31bf061d-773a-494b-9cdb-d8201850eb22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176976501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2176976501 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.4213606100 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 44644915 ps |
| CPU time | 7.5 seconds |
| Started | Jul 13 08:24:32 PM PDT 24 |
| Finished | Jul 13 08:24:40 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-7567b2dd-1cb2-48d3-8d67-ddd53fe39e70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213606100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.4213606100 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.2068455513 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 3503473551 ps |
| CPU time | 286.58 seconds |
| Started | Jul 13 08:24:42 PM PDT 24 |
| Finished | Jul 13 08:29:29 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-0b5d59a8-b2a4-45a6-af23-3a65a7aeb7ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068455513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2068455513 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.4094328193 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 7679223936 ps |
| CPU time | 298.79 seconds |
| Started | Jul 13 08:24:42 PM PDT 24 |
| Finished | Jul 13 08:29:42 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-399fe803-5a99-4a3b-98b2-0947b1e3d5bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094328193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.4094328193 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.4239108130 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 2476118979 ps |
| CPU time | 388.51 seconds |
| Started | Jul 13 08:24:40 PM PDT 24 |
| Finished | Jul 13 08:31:09 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-e6763e24-4a98-4fc3-b8cf-b5da250de959 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239108130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.4239108130 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1981122245 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 7209169511 ps |
| CPU time | 349.43 seconds |
| Started | Jul 13 08:24:44 PM PDT 24 |
| Finished | Jul 13 08:30:34 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-cc03b2b8-8b26-4f6c-8e2a-d6f5f7b3b491 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981122245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.1981122245 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.1754061279 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 1039001026 ps |
| CPU time | 45.16 seconds |
| Started | Jul 13 08:24:32 PM PDT 24 |
| Finished | Jul 13 08:25:19 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-20f94cec-4042-4ce2-81c1-b8574f396513 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754061279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1754061279 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.2918680089 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 2059484856 ps |
| CPU time | 99.76 seconds |
| Started | Jul 13 08:24:44 PM PDT 24 |
| Finished | Jul 13 08:26:24 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-262ca10d-9e91-4ff0-a485-a034e7c24792 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918680089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .2918680089 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.1252857312 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 181993704 ps |
| CPU time | 21.17 seconds |
| Started | Jul 13 08:24:46 PM PDT 24 |
| Finished | Jul 13 08:25:08 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-f42c39a4-1f07-4111-93dd-f1b3b915e14a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252857312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.1252857312 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.1037536957 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 249124033 ps |
| CPU time | 11.99 seconds |
| Started | Jul 13 08:24:45 PM PDT 24 |
| Finished | Jul 13 08:24:57 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-d410a4ae-af37-4631-b2fb-0c02556f78d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037536957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1037536957 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.4059652637 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 1493863624 ps |
| CPU time | 54.1 seconds |
| Started | Jul 13 08:24:42 PM PDT 24 |
| Finished | Jul 13 08:25:37 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-c60f1b1d-af9d-403a-8354-be89ae50cfb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059652637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.4059652637 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.2875161911 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 53809496576 ps |
| CPU time | 611.46 seconds |
| Started | Jul 13 08:24:44 PM PDT 24 |
| Finished | Jul 13 08:34:56 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-ae9e2ee8-0b18-4b75-beb8-ea6b97f48f36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875161911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2875161911 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.1943246614 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 9894949176 ps |
| CPU time | 185.22 seconds |
| Started | Jul 13 08:24:43 PM PDT 24 |
| Finished | Jul 13 08:27:48 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-d4238b0a-839c-4c58-8ad5-90510ff7014a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943246614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1943246614 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.1753204766 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 597116103 ps |
| CPU time | 60.73 seconds |
| Started | Jul 13 08:24:42 PM PDT 24 |
| Finished | Jul 13 08:25:44 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-d3a95f72-18e0-4d56-9370-2677ad129e62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753204766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del ays.1753204766 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.2018298538 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 510153140 ps |
| CPU time | 18.78 seconds |
| Started | Jul 13 08:24:41 PM PDT 24 |
| Finished | Jul 13 08:25:00 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-31e06def-c9aa-4a9b-90a3-821dfd40de9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018298538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.2018298538 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.3443326083 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 45517962 ps |
| CPU time | 6.63 seconds |
| Started | Jul 13 08:24:44 PM PDT 24 |
| Finished | Jul 13 08:24:51 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-bd09b8f8-ebeb-43e3-9452-dcf9df134b38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443326083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3443326083 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.2625503554 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 5718996000 ps |
| CPU time | 65.91 seconds |
| Started | Jul 13 08:24:43 PM PDT 24 |
| Finished | Jul 13 08:25:49 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-baf62b30-d17b-4960-8199-367b3cceb222 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625503554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2625503554 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.1626666142 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 6325350595 ps |
| CPU time | 121.53 seconds |
| Started | Jul 13 08:24:44 PM PDT 24 |
| Finished | Jul 13 08:26:46 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-fb12a35d-05fc-40d2-89d7-87b34f3ced48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626666142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1626666142 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.2394858459 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 52603300 ps |
| CPU time | 7.3 seconds |
| Started | Jul 13 08:24:44 PM PDT 24 |
| Finished | Jul 13 08:24:52 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-e3a9924c-10bd-469d-b7dd-58274fd7d56a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394858459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay s.2394858459 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.2175485049 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 9551394093 ps |
| CPU time | 431.73 seconds |
| Started | Jul 13 08:24:43 PM PDT 24 |
| Finished | Jul 13 08:31:55 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-2e2625db-f23c-4600-8236-65ec214aa549 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175485049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2175485049 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.1109110965 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 1314250766 ps |
| CPU time | 132.83 seconds |
| Started | Jul 13 08:24:55 PM PDT 24 |
| Finished | Jul 13 08:27:09 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-7465f353-ce42-4d58-aaef-e53839aa3d23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109110965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1109110965 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1732092725 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 385806287 ps |
| CPU time | 140.96 seconds |
| Started | Jul 13 08:24:54 PM PDT 24 |
| Finished | Jul 13 08:27:16 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-b634d184-6fc5-489e-8d8c-1261a24a5237 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732092725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all _with_rand_reset.1732092725 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.2679657480 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 11794381076 ps |
| CPU time | 546.49 seconds |
| Started | Jul 13 08:24:55 PM PDT 24 |
| Finished | Jul 13 08:34:03 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-1525f839-9310-4bdc-99c2-e0db8872bf86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679657480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.2679657480 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.1878728538 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 57526591 ps |
| CPU time | 6.62 seconds |
| Started | Jul 13 08:24:44 PM PDT 24 |
| Finished | Jul 13 08:24:52 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-f234580a-c964-4269-b3a6-9cdcb4a7e205 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878728538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1878728538 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.1775495447 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 825695893 ps |
| CPU time | 45.23 seconds |
| Started | Jul 13 08:24:55 PM PDT 24 |
| Finished | Jul 13 08:25:41 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-d40a4187-d9c2-4299-93ac-88f4ba683261 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775495447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .1775495447 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.2656734558 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 125553210921 ps |
| CPU time | 2406.45 seconds |
| Started | Jul 13 08:24:54 PM PDT 24 |
| Finished | Jul 13 09:05:02 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-f465bd13-30d5-4508-9118-94fe33af4792 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656734558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_ device_slow_rsp.2656734558 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.3799813821 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 1323517926 ps |
| CPU time | 59.02 seconds |
| Started | Jul 13 08:24:53 PM PDT 24 |
| Finished | Jul 13 08:25:53 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-322f6519-fe11-4083-aeab-aa9d985787ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799813821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.3799813821 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.3710439226 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 66958119 ps |
| CPU time | 9.33 seconds |
| Started | Jul 13 08:24:55 PM PDT 24 |
| Finished | Jul 13 08:25:05 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-a204afeb-b163-48e5-9f1d-239f2f458f5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710439226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.3710439226 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.3241812569 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 2763717009 ps |
| CPU time | 108.14 seconds |
| Started | Jul 13 08:24:56 PM PDT 24 |
| Finished | Jul 13 08:26:44 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-f4db9da2-f8d5-40e6-ad1e-6860dbf39b51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241812569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.3241812569 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.2661712613 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 63131555764 ps |
| CPU time | 685.17 seconds |
| Started | Jul 13 08:24:57 PM PDT 24 |
| Finished | Jul 13 08:36:23 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-0307d6e8-c5fe-4ae9-8191-d85a39b08012 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661712613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2661712613 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.2780165255 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 6748015417 ps |
| CPU time | 126.25 seconds |
| Started | Jul 13 08:24:55 PM PDT 24 |
| Finished | Jul 13 08:27:02 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-c570fa5e-e773-436f-b62c-1fa0face123c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780165255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2780165255 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.4101413072 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 127005020 ps |
| CPU time | 14.63 seconds |
| Started | Jul 13 08:24:59 PM PDT 24 |
| Finished | Jul 13 08:25:14 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-d2218152-aefa-45a1-99f5-81598c4f6b85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101413072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del ays.4101413072 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.724483367 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 316314428 ps |
| CPU time | 29.31 seconds |
| Started | Jul 13 08:24:54 PM PDT 24 |
| Finished | Jul 13 08:25:24 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-d18c468c-1767-4751-a184-e1755ffd1614 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724483367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.724483367 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.1767331403 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 184111136 ps |
| CPU time | 9.56 seconds |
| Started | Jul 13 08:24:54 PM PDT 24 |
| Finished | Jul 13 08:25:04 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-cd94b62c-4c47-4cc8-a1e2-6704d840b2d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767331403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1767331403 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.2511436476 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 9217416031 ps |
| CPU time | 102.76 seconds |
| Started | Jul 13 08:24:58 PM PDT 24 |
| Finished | Jul 13 08:26:41 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-e044c6e2-8140-4bd3-bb61-10796108a64c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511436476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2511436476 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.409164147 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 5877848473 ps |
| CPU time | 111.47 seconds |
| Started | Jul 13 08:25:00 PM PDT 24 |
| Finished | Jul 13 08:26:52 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-6ee95e18-261c-4747-8123-80c4f56fa597 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409164147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.409164147 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.669969583 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 43890626 ps |
| CPU time | 6.45 seconds |
| Started | Jul 13 08:24:55 PM PDT 24 |
| Finished | Jul 13 08:25:03 PM PDT 24 |
| Peak memory | 574012 kb |
| Host | smart-32675f80-485d-4c77-b6a6-bb87dca38f4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669969583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays .669969583 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.2280110345 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 7641594125 ps |
| CPU time | 314.58 seconds |
| Started | Jul 13 08:25:04 PM PDT 24 |
| Finished | Jul 13 08:30:19 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-fb6bcfa9-fdc4-45a2-acf7-33b670622ca9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280110345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2280110345 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.2404040527 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 2759426342 ps |
| CPU time | 183.53 seconds |
| Started | Jul 13 08:25:04 PM PDT 24 |
| Finished | Jul 13 08:28:08 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-f15fb00e-839d-4ede-8667-b107da528736 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404040527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2404040527 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.3539669977 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 2348636329 ps |
| CPU time | 442.61 seconds |
| Started | Jul 13 08:25:07 PM PDT 24 |
| Finished | Jul 13 08:32:30 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-2ffec104-1d2d-4cba-9c05-75099646a775 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539669977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_rand_reset.3539669977 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.1094933143 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 528462481 ps |
| CPU time | 132.07 seconds |
| Started | Jul 13 08:25:03 PM PDT 24 |
| Finished | Jul 13 08:27:16 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-838d55df-bbc9-4347-aa14-5bad2473f8d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094933143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.1094933143 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.2950075603 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 247676688 ps |
| CPU time | 13.88 seconds |
| Started | Jul 13 08:24:55 PM PDT 24 |
| Finished | Jul 13 08:25:09 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-22a0edde-cdc1-4abe-b33b-8968ef3baf94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950075603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2950075603 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.3831492279 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 375222220 ps |
| CPU time | 30.85 seconds |
| Started | Jul 13 08:25:04 PM PDT 24 |
| Finished | Jul 13 08:25:35 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-1cff429d-8cb6-48bd-b5b7-a20cd9727777 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831492279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .3831492279 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1898436206 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 120305990879 ps |
| CPU time | 2355.79 seconds |
| Started | Jul 13 08:25:04 PM PDT 24 |
| Finished | Jul 13 09:04:21 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-640a66e4-05ab-4ec7-8180-388b61e348fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898436206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.1898436206 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.2047184551 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 16069780 ps |
| CPU time | 5.44 seconds |
| Started | Jul 13 08:25:15 PM PDT 24 |
| Finished | Jul 13 08:25:21 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-1b39227d-7881-4474-8c2f-6bfe6f4d6073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047184551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.2047184551 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.1162398568 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 296414966 ps |
| CPU time | 13.16 seconds |
| Started | Jul 13 08:25:03 PM PDT 24 |
| Finished | Jul 13 08:25:16 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-2ddb5a93-9219-4a1b-bd15-1999416618eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162398568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1162398568 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.1681542214 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 589582751 ps |
| CPU time | 62.17 seconds |
| Started | Jul 13 08:25:06 PM PDT 24 |
| Finished | Jul 13 08:26:09 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-45f9da3b-208b-41f1-a8e7-04be332353c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681542214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.1681542214 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.1873750916 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 32916083215 ps |
| CPU time | 370.69 seconds |
| Started | Jul 13 08:25:06 PM PDT 24 |
| Finished | Jul 13 08:31:17 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-1a3d53aa-4fdc-479a-b232-984c6d90260c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873750916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.1873750916 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.1207201301 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 12298635960 ps |
| CPU time | 247.56 seconds |
| Started | Jul 13 08:25:07 PM PDT 24 |
| Finished | Jul 13 08:29:15 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-69804e6c-c2e6-41df-9153-33c602bfe8b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207201301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.1207201301 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.1892588882 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 71044327 ps |
| CPU time | 9.84 seconds |
| Started | Jul 13 08:25:03 PM PDT 24 |
| Finished | Jul 13 08:25:13 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-37196355-7f1d-41df-9578-a8a56a81960d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892588882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.1892588882 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.1306761247 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 1405650425 ps |
| CPU time | 47.16 seconds |
| Started | Jul 13 08:25:04 PM PDT 24 |
| Finished | Jul 13 08:25:52 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-906ecf83-39d5-4b82-a404-2508751635fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306761247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1306761247 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.4001910007 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 56680456 ps |
| CPU time | 7.41 seconds |
| Started | Jul 13 08:25:04 PM PDT 24 |
| Finished | Jul 13 08:25:12 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-e5395560-43ae-47c9-a1c3-e72a71518534 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001910007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.4001910007 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.4103518734 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 7473795197 ps |
| CPU time | 90.1 seconds |
| Started | Jul 13 08:25:04 PM PDT 24 |
| Finished | Jul 13 08:26:34 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-4917434a-8c00-40af-9a70-65bbab4f257b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103518734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.4103518734 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.2586249426 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 5439711449 ps |
| CPU time | 104.39 seconds |
| Started | Jul 13 08:25:03 PM PDT 24 |
| Finished | Jul 13 08:26:48 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-226b9359-35b3-47b4-8016-c2808c79102f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586249426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.2586249426 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.3404376142 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 48206859 ps |
| CPU time | 7.16 seconds |
| Started | Jul 13 08:25:04 PM PDT 24 |
| Finished | Jul 13 08:25:12 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-eec6f26a-d3a7-4132-b3f3-6545b8f68c75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404376142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.3404376142 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.336703851 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 1642011817 ps |
| CPU time | 154.07 seconds |
| Started | Jul 13 08:25:14 PM PDT 24 |
| Finished | Jul 13 08:27:49 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-028753bf-8fd0-403d-9fd4-8a9d776fdf09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336703851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.336703851 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.795961646 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 2694463518 ps |
| CPU time | 222.36 seconds |
| Started | Jul 13 08:25:15 PM PDT 24 |
| Finished | Jul 13 08:28:58 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-20e752c8-33e2-459f-b8c5-7f8e606b3340 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795961646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.795961646 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.1671850415 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 8835959356 ps |
| CPU time | 459.37 seconds |
| Started | Jul 13 08:25:17 PM PDT 24 |
| Finished | Jul 13 08:32:57 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-1f3968ce-50e2-4733-b8b5-5e6bb3b35bd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671850415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.1671850415 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.627827930 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 1377171919 ps |
| CPU time | 67.14 seconds |
| Started | Jul 13 08:25:20 PM PDT 24 |
| Finished | Jul 13 08:26:27 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-6826b2fa-d0e1-4605-94e9-a5c746360b9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627827930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.627827930 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.1119958706 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 2735918536 ps |
| CPU time | 136.43 seconds |
| Started | Jul 13 08:25:25 PM PDT 24 |
| Finished | Jul 13 08:27:42 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-d128e0d6-856d-44fe-b1c6-c3b2a5068418 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119958706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .1119958706 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.2475120340 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 97101279959 ps |
| CPU time | 1851.47 seconds |
| Started | Jul 13 08:25:29 PM PDT 24 |
| Finished | Jul 13 08:56:21 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-99c5735e-4996-47b6-b3a2-356f0b54a04b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475120340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_ device_slow_rsp.2475120340 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.4114845910 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 257193645 ps |
| CPU time | 33 seconds |
| Started | Jul 13 08:25:28 PM PDT 24 |
| Finished | Jul 13 08:26:02 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-aa3d476e-fd6e-4568-bc4b-2b0daa0b2c9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114845910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.4114845910 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.264894482 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 1971880309 ps |
| CPU time | 80.24 seconds |
| Started | Jul 13 08:25:24 PM PDT 24 |
| Finished | Jul 13 08:26:45 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-df2da97c-a1ff-4510-9ae9-47320df8add9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264894482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.264894482 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.3191221782 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 619359004 ps |
| CPU time | 27.82 seconds |
| Started | Jul 13 08:25:17 PM PDT 24 |
| Finished | Jul 13 08:25:45 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-a816b2dd-f9d5-46d7-9d8e-56f8919dc7bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191221782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.3191221782 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.4219262437 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 30420038178 ps |
| CPU time | 334.24 seconds |
| Started | Jul 13 08:25:23 PM PDT 24 |
| Finished | Jul 13 08:30:58 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-96caabf3-a92a-4c19-ba72-c69664fa4ed9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219262437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.4219262437 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.4216726202 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 22174930762 ps |
| CPU time | 409.37 seconds |
| Started | Jul 13 08:25:28 PM PDT 24 |
| Finished | Jul 13 08:32:18 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-7bbe2ba5-ee17-494b-9e74-5c0a78947090 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216726202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.4216726202 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.4025921902 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 593663889 ps |
| CPU time | 60.21 seconds |
| Started | Jul 13 08:25:14 PM PDT 24 |
| Finished | Jul 13 08:26:15 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-095ce781-d1f5-4795-ac2a-d29120e51323 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025921902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del ays.4025921902 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.1441092369 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 368967698 ps |
| CPU time | 33.02 seconds |
| Started | Jul 13 08:25:28 PM PDT 24 |
| Finished | Jul 13 08:26:02 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-98d823b7-5019-4645-a520-d5b7f3af118b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441092369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1441092369 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.955160971 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 50184766 ps |
| CPU time | 6.91 seconds |
| Started | Jul 13 08:25:14 PM PDT 24 |
| Finished | Jul 13 08:25:22 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-ec4d69af-6976-4ff4-9699-21da7ea5926e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955160971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.955160971 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.3597763442 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 6884924119 ps |
| CPU time | 80.35 seconds |
| Started | Jul 13 08:25:19 PM PDT 24 |
| Finished | Jul 13 08:26:40 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-1a6df1f5-69bb-4346-a95b-68fc70515019 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597763442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3597763442 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.2206222404 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 5125890592 ps |
| CPU time | 98.64 seconds |
| Started | Jul 13 08:25:19 PM PDT 24 |
| Finished | Jul 13 08:26:58 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-7765287d-b6bb-40a5-8eda-3818dfb3ab40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206222404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2206222404 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.3403332099 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 51630339 ps |
| CPU time | 6.96 seconds |
| Started | Jul 13 08:25:14 PM PDT 24 |
| Finished | Jul 13 08:25:22 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-81d3a0bf-c834-4cb9-a127-6ec624aabeae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403332099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay s.3403332099 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.3013532366 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 9039970475 ps |
| CPU time | 368.27 seconds |
| Started | Jul 13 08:25:24 PM PDT 24 |
| Finished | Jul 13 08:31:33 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-a97d6527-8fae-4075-aeaa-cec25e138161 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013532366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3013532366 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.4183842354 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 1249226835 ps |
| CPU time | 111.93 seconds |
| Started | Jul 13 08:25:24 PM PDT 24 |
| Finished | Jul 13 08:27:17 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-d58f6d57-4995-42e2-ae2c-6911a5e4e362 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183842354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.4183842354 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.3308541758 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 474879173 ps |
| CPU time | 180.21 seconds |
| Started | Jul 13 08:25:22 PM PDT 24 |
| Finished | Jul 13 08:28:22 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-1c0c6d23-2b1e-477d-9d2a-74c4439a599c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308541758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.3308541758 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.782958452 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 780786854 ps |
| CPU time | 38.87 seconds |
| Started | Jul 13 08:25:25 PM PDT 24 |
| Finished | Jul 13 08:26:04 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-ecbaa4dc-bb1a-460e-868d-b9e3ff90f9d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782958452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.782958452 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.2036797527 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 149340321 ps |
| CPU time | 16.14 seconds |
| Started | Jul 13 08:25:32 PM PDT 24 |
| Finished | Jul 13 08:25:49 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-487d5353-bd47-4a0f-91fc-2bf22eb15a90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036797527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .2036797527 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.1024617909 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 142781351355 ps |
| CPU time | 2535.96 seconds |
| Started | Jul 13 08:25:33 PM PDT 24 |
| Finished | Jul 13 09:07:50 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-516d2d37-e7dc-490c-b90b-bc6642a24d5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024617909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_ device_slow_rsp.1024617909 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.2241589491 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 72738732 ps |
| CPU time | 11.09 seconds |
| Started | Jul 13 08:25:30 PM PDT 24 |
| Finished | Jul 13 08:25:41 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-f2f6a13f-c04c-4fd4-b9bc-f69ec9ba1a90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241589491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.2241589491 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.3410658583 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 837801280 ps |
| CPU time | 36.44 seconds |
| Started | Jul 13 08:25:32 PM PDT 24 |
| Finished | Jul 13 08:26:08 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-b8235c00-3304-49fd-8127-9295de845779 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410658583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3410658583 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.2933093478 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 1190667614 ps |
| CPU time | 48.31 seconds |
| Started | Jul 13 08:25:32 PM PDT 24 |
| Finished | Jul 13 08:26:21 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-32595ce9-15ea-45c5-8d81-1a41ce88f9a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933093478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.2933093478 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.369152216 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 51702369254 ps |
| CPU time | 581.33 seconds |
| Started | Jul 13 08:25:32 PM PDT 24 |
| Finished | Jul 13 08:35:14 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-426a864b-b7eb-42dc-b4ba-350a53e59fe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369152216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.369152216 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.2513914764 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 51557379026 ps |
| CPU time | 930.19 seconds |
| Started | Jul 13 08:25:30 PM PDT 24 |
| Finished | Jul 13 08:41:01 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-505f52cc-e6d5-454b-9bc3-481780274749 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513914764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2513914764 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.1545435461 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 163680739 ps |
| CPU time | 16.48 seconds |
| Started | Jul 13 08:25:31 PM PDT 24 |
| Finished | Jul 13 08:25:48 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-9c927eb3-2cb9-4b9a-b2b6-6e45335a1733 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545435461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_del ays.1545435461 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.4274888284 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 464562942 ps |
| CPU time | 35.04 seconds |
| Started | Jul 13 08:25:31 PM PDT 24 |
| Finished | Jul 13 08:26:07 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-0f7103f9-cbb8-41ab-ac8c-f1e6a72afd2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274888284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.4274888284 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.1689291446 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 176062392 ps |
| CPU time | 9.01 seconds |
| Started | Jul 13 08:25:23 PM PDT 24 |
| Finished | Jul 13 08:25:33 PM PDT 24 |
| Peak memory | 574012 kb |
| Host | smart-3d71740d-67a3-487d-877f-6b6bedfd4ca8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689291446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1689291446 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.1208463774 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 7058199244 ps |
| CPU time | 78.52 seconds |
| Started | Jul 13 08:25:24 PM PDT 24 |
| Finished | Jul 13 08:26:43 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-352517dc-7780-4bb8-a442-23d9a0feb19d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208463774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1208463774 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.1062852899 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 5005734720 ps |
| CPU time | 90.96 seconds |
| Started | Jul 13 08:25:34 PM PDT 24 |
| Finished | Jul 13 08:27:05 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-dcb24f35-ddb5-47bc-81b4-a8c14a9da060 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062852899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1062852899 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.859831113 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 40814667 ps |
| CPU time | 6.03 seconds |
| Started | Jul 13 08:25:24 PM PDT 24 |
| Finished | Jul 13 08:25:31 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-0e91784b-e07d-4061-bd33-2cc4c2787c1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859831113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays .859831113 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.929297262 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 9394118942 ps |
| CPU time | 345.32 seconds |
| Started | Jul 13 08:25:33 PM PDT 24 |
| Finished | Jul 13 08:31:19 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-80d28a82-1436-46ff-b08a-e774a6dcff7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929297262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.929297262 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.85772342 |
| Short name | T2907 |
| Test name | |
| Test status | |
| Simulation time | 2945083497 ps |
| CPU time | 244.79 seconds |
| Started | Jul 13 08:25:34 PM PDT 24 |
| Finished | Jul 13 08:29:39 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-b7eda323-211f-4c8e-a1d2-c6a7098ce746 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85772342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_w ith_rand_reset.85772342 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.2811745954 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 195499099 ps |
| CPU time | 67.18 seconds |
| Started | Jul 13 08:25:40 PM PDT 24 |
| Finished | Jul 13 08:26:47 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-10898044-cde0-474d-8140-373aaefa3f3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811745954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.2811745954 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.1795583944 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 464019719 ps |
| CPU time | 27.07 seconds |
| Started | Jul 13 08:25:32 PM PDT 24 |
| Finished | Jul 13 08:26:00 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-74c55d19-32cc-41bd-9beb-afad5a14e616 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795583944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1795583944 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.2874547022 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 1206605757 ps |
| CPU time | 50.82 seconds |
| Started | Jul 13 08:25:48 PM PDT 24 |
| Finished | Jul 13 08:26:40 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-a1d79b75-6ed3-4a7b-a176-44833848cebd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874547022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .2874547022 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.4178141931 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 104111865316 ps |
| CPU time | 1815.64 seconds |
| Started | Jul 13 08:25:43 PM PDT 24 |
| Finished | Jul 13 08:55:59 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-ea123515-7efe-4cdb-87b0-e9a006c23e0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178141931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.4178141931 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3170229098 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 166623819 ps |
| CPU time | 22 seconds |
| Started | Jul 13 08:25:43 PM PDT 24 |
| Finished | Jul 13 08:26:06 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-ed7a277f-f226-4d05-ba7c-66e95267d92d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170229098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.3170229098 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.185032721 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 191684837 ps |
| CPU time | 22.15 seconds |
| Started | Jul 13 08:25:41 PM PDT 24 |
| Finished | Jul 13 08:26:04 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-66bcad4e-61d9-4664-bc63-7eaa9266a99e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185032721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.185032721 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.4249668844 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 351058666 ps |
| CPU time | 33.39 seconds |
| Started | Jul 13 08:25:41 PM PDT 24 |
| Finished | Jul 13 08:26:15 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-6c031237-8aa2-466a-9d84-0d49aa94c24b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249668844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.4249668844 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.132248987 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 7962044110 ps |
| CPU time | 96.2 seconds |
| Started | Jul 13 08:25:49 PM PDT 24 |
| Finished | Jul 13 08:27:26 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-27ebdecc-e58f-4958-96cd-f7681902e78c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132248987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.132248987 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.2823892503 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 29810477747 ps |
| CPU time | 570.78 seconds |
| Started | Jul 13 08:25:49 PM PDT 24 |
| Finished | Jul 13 08:35:20 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-d84f3774-7464-44b2-a854-0b3573c8ba04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823892503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2823892503 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.3971990212 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 243514233 ps |
| CPU time | 23.01 seconds |
| Started | Jul 13 08:25:40 PM PDT 24 |
| Finished | Jul 13 08:26:04 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-28f99a9e-044a-4d3e-80fa-c202598d7909 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971990212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.3971990212 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.3288952514 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 295939699 ps |
| CPU time | 13.19 seconds |
| Started | Jul 13 08:25:43 PM PDT 24 |
| Finished | Jul 13 08:25:56 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-72602352-28ca-4bbd-ace1-2db009625bfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288952514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3288952514 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.109684996 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 175241536 ps |
| CPU time | 9.56 seconds |
| Started | Jul 13 08:25:40 PM PDT 24 |
| Finished | Jul 13 08:25:50 PM PDT 24 |
| Peak memory | 573852 kb |
| Host | smart-cf84b241-0976-4ccb-8b2b-ef6d0acc3b6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109684996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.109684996 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.2315680009 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 10154983357 ps |
| CPU time | 118.81 seconds |
| Started | Jul 13 08:25:42 PM PDT 24 |
| Finished | Jul 13 08:27:41 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-e5b06e78-418d-4681-949c-1492e06a0359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315680009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2315680009 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.1381291963 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 4642389217 ps |
| CPU time | 89.1 seconds |
| Started | Jul 13 08:25:42 PM PDT 24 |
| Finished | Jul 13 08:27:11 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-9c5dabe1-7fe1-44f7-8f3e-5ba89fa82337 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381291963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1381291963 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.3789016884 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 54881605 ps |
| CPU time | 7.12 seconds |
| Started | Jul 13 08:25:42 PM PDT 24 |
| Finished | Jul 13 08:25:50 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-c4ad5dc5-577b-4bee-9a55-aa5c328dd73b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789016884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.3789016884 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.3530429897 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 11887280702 ps |
| CPU time | 463.59 seconds |
| Started | Jul 13 08:25:48 PM PDT 24 |
| Finished | Jul 13 08:33:33 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-b01da636-55e7-4a6c-9a26-0f167dd9b6fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530429897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3530429897 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.1895356400 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 1573119386 ps |
| CPU time | 157.46 seconds |
| Started | Jul 13 08:25:41 PM PDT 24 |
| Finished | Jul 13 08:28:19 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-f8c38d07-d73b-4c0a-bc99-3596ebd2f1e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895356400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1895356400 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.2996385618 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 838612583 ps |
| CPU time | 82.08 seconds |
| Started | Jul 13 08:25:41 PM PDT 24 |
| Finished | Jul 13 08:27:04 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-eeb08674-8b38-44ef-aba1-8bb62ddedcb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996385618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.2996385618 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.748026050 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 1722533840 ps |
| CPU time | 197.38 seconds |
| Started | Jul 13 08:25:44 PM PDT 24 |
| Finished | Jul 13 08:29:02 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-9786d045-c42e-4fb0-b121-c0f5f483773a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748026050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_reset_error.748026050 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.335855538 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 183850186 ps |
| CPU time | 25.35 seconds |
| Started | Jul 13 08:25:43 PM PDT 24 |
| Finished | Jul 13 08:26:09 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-27e0c8b6-f716-4311-bee1-5f52ec5650db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335855538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.335855538 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.3981897272 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 628119397 ps |
| CPU time | 56.17 seconds |
| Started | Jul 13 08:25:50 PM PDT 24 |
| Finished | Jul 13 08:26:47 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-53d09b1a-d3d7-4a04-9a2c-d3387abcc790 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981897272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .3981897272 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.3522000636 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 66488466104 ps |
| CPU time | 1334.24 seconds |
| Started | Jul 13 08:25:50 PM PDT 24 |
| Finished | Jul 13 08:48:05 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-a698443f-5450-40b2-a506-44793d94f1a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522000636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_ device_slow_rsp.3522000636 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.185787996 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 180755215 ps |
| CPU time | 22.87 seconds |
| Started | Jul 13 08:25:50 PM PDT 24 |
| Finished | Jul 13 08:26:13 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-72176d36-c21e-45b4-ba44-7af98e579409 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185787996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr .185787996 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.2836974105 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 1985563939 ps |
| CPU time | 79.61 seconds |
| Started | Jul 13 08:25:50 PM PDT 24 |
| Finished | Jul 13 08:27:10 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-7b95d82a-9e3e-49d6-ba0e-f73ebe575331 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836974105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2836974105 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.2879201291 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 1153466544 ps |
| CPU time | 49.1 seconds |
| Started | Jul 13 08:25:50 PM PDT 24 |
| Finished | Jul 13 08:26:39 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-683df728-b977-4b8d-84fc-3a36197c9ad9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879201291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.2879201291 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.2190480032 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 92100976941 ps |
| CPU time | 1090.96 seconds |
| Started | Jul 13 08:25:50 PM PDT 24 |
| Finished | Jul 13 08:44:02 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-0990a68b-5927-4a82-999f-657ef639c8e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190480032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2190480032 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.21603069 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 14251826929 ps |
| CPU time | 259.35 seconds |
| Started | Jul 13 08:25:50 PM PDT 24 |
| Finished | Jul 13 08:30:10 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-0dda0905-33a7-427d-8f4f-8a5030e7d72e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21603069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.21603069 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.1776363155 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 80737704 ps |
| CPU time | 9.77 seconds |
| Started | Jul 13 08:25:51 PM PDT 24 |
| Finished | Jul 13 08:26:01 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-0ec508cd-cadd-4271-aef8-482f9dc6e9f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776363155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.1776363155 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.2913147731 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 429531448 ps |
| CPU time | 34.08 seconds |
| Started | Jul 13 08:25:49 PM PDT 24 |
| Finished | Jul 13 08:26:24 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-935da00c-64f0-4712-a1f6-f5ba47863223 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913147731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2913147731 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.252237806 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 53656542 ps |
| CPU time | 6.72 seconds |
| Started | Jul 13 08:25:52 PM PDT 24 |
| Finished | Jul 13 08:25:59 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-0af9aa56-594b-4061-b4ed-09bcbc530681 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252237806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.252237806 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.336913049 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 9128518295 ps |
| CPU time | 105.71 seconds |
| Started | Jul 13 08:25:51 PM PDT 24 |
| Finished | Jul 13 08:27:37 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-36847a5e-7309-4fad-9b2d-a31182efd95e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336913049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.336913049 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.3288079232 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 5128158023 ps |
| CPU time | 98.31 seconds |
| Started | Jul 13 08:25:51 PM PDT 24 |
| Finished | Jul 13 08:27:30 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-3ab0ceeb-ce1a-4a51-8257-fdd3bbd78e94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288079232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3288079232 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.1773047426 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 49710130 ps |
| CPU time | 6.67 seconds |
| Started | Jul 13 08:25:49 PM PDT 24 |
| Finished | Jul 13 08:25:56 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-c4573c98-2076-4445-9554-23ebca02bb85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773047426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay s.1773047426 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.2142267782 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 1622940493 ps |
| CPU time | 54.96 seconds |
| Started | Jul 13 08:26:04 PM PDT 24 |
| Finished | Jul 13 08:26:59 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-10b7eeb6-644c-4091-a732-d39f330b5d41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142267782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2142267782 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.2207767802 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 9214380813 ps |
| CPU time | 334.25 seconds |
| Started | Jul 13 08:26:04 PM PDT 24 |
| Finished | Jul 13 08:31:38 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-93f9d56e-78b2-42b2-b019-f0c075a5134a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207767802 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2207767802 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.3229203684 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 4009968263 ps |
| CPU time | 544.71 seconds |
| Started | Jul 13 08:26:00 PM PDT 24 |
| Finished | Jul 13 08:35:05 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-bf0cf43b-eafb-4328-9827-9a300513939a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229203684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.3229203684 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.1356625901 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 8081869294 ps |
| CPU time | 866.05 seconds |
| Started | Jul 13 08:26:03 PM PDT 24 |
| Finished | Jul 13 08:40:30 PM PDT 24 |
| Peak memory | 582544 kb |
| Host | smart-36eb7823-e6d6-4651-a135-083676314fef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356625901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.1356625901 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.1884819711 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 228775756 ps |
| CPU time | 26.2 seconds |
| Started | Jul 13 08:25:51 PM PDT 24 |
| Finished | Jul 13 08:26:18 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-8c59e1f6-8d5d-410b-8398-3a1f70638d94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884819711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1884819711 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.999537667 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 1210958212 ps |
| CPU time | 92.86 seconds |
| Started | Jul 13 08:26:01 PM PDT 24 |
| Finished | Jul 13 08:27:35 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-7822202d-b0f7-4efc-8f9c-27e19a702fd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999537667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device. 999537667 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2716875852 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 100469208420 ps |
| CPU time | 1784.86 seconds |
| Started | Jul 13 08:26:01 PM PDT 24 |
| Finished | Jul 13 08:55:47 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-8e7f544f-6be0-4fd5-9ace-f8ca936f5d9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716875852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_ device_slow_rsp.2716875852 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.2723756212 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 159474378 ps |
| CPU time | 21.12 seconds |
| Started | Jul 13 08:26:20 PM PDT 24 |
| Finished | Jul 13 08:26:42 PM PDT 24 |
| Peak memory | 575208 kb |
| Host | smart-77da79ed-5920-439b-a6b2-812eb75369b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723756212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.2723756212 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.2706061678 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 453078320 ps |
| CPU time | 19.42 seconds |
| Started | Jul 13 08:26:00 PM PDT 24 |
| Finished | Jul 13 08:26:19 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-499c6edd-96ee-499f-b9e8-7984275a4afc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706061678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2706061678 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.3753097276 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 1831670692 ps |
| CPU time | 69.7 seconds |
| Started | Jul 13 08:26:03 PM PDT 24 |
| Finished | Jul 13 08:27:13 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-e8bf44d6-e0fd-4386-be17-3c897da752ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753097276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.3753097276 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.482542204 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 14401444437 ps |
| CPU time | 172.12 seconds |
| Started | Jul 13 08:25:59 PM PDT 24 |
| Finished | Jul 13 08:28:52 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-33ec0b9e-7739-4349-a7eb-2ef5b6c36e3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482542204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.482542204 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.3806626963 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 10263874851 ps |
| CPU time | 182.83 seconds |
| Started | Jul 13 08:26:03 PM PDT 24 |
| Finished | Jul 13 08:29:06 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-7ba3ff2a-d534-40b9-ac51-8d705cf63b22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806626963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3806626963 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.4245210298 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 435492668 ps |
| CPU time | 39.95 seconds |
| Started | Jul 13 08:26:03 PM PDT 24 |
| Finished | Jul 13 08:26:43 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-04888c55-7721-46d6-b397-b13d10a0c60e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245210298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del ays.4245210298 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.4290514577 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 310437848 ps |
| CPU time | 27.72 seconds |
| Started | Jul 13 08:26:01 PM PDT 24 |
| Finished | Jul 13 08:26:29 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-157027a6-6c94-4366-8ceb-b4fc87de217d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290514577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.4290514577 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.1480434288 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 178862217 ps |
| CPU time | 9.21 seconds |
| Started | Jul 13 08:26:02 PM PDT 24 |
| Finished | Jul 13 08:26:12 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-c68c13e7-a4bf-44e1-a0f6-7b52fedc0981 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480434288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1480434288 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.1673810575 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 7524936066 ps |
| CPU time | 85.44 seconds |
| Started | Jul 13 08:26:01 PM PDT 24 |
| Finished | Jul 13 08:27:27 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-e50d8d55-bb09-4c15-ac3f-b90f7b31140d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673810575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.1673810575 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.1403950642 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 4726802397 ps |
| CPU time | 90.72 seconds |
| Started | Jul 13 08:26:01 PM PDT 24 |
| Finished | Jul 13 08:27:32 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-ced636d1-4eb9-41cd-b82b-b10c01c8a41b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403950642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1403950642 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.3915965552 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 45025055 ps |
| CPU time | 6.97 seconds |
| Started | Jul 13 08:26:01 PM PDT 24 |
| Finished | Jul 13 08:26:08 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-ed9c97fa-8615-4ddc-bee8-44d8b7177c4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915965552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.3915965552 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.3823130327 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 1033780190 ps |
| CPU time | 90.52 seconds |
| Started | Jul 13 08:26:08 PM PDT 24 |
| Finished | Jul 13 08:27:39 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-c5a0fb0e-f3ab-457a-b703-c0c724181977 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823130327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3823130327 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.1179829333 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 964707504 ps |
| CPU time | 36.57 seconds |
| Started | Jul 13 08:26:20 PM PDT 24 |
| Finished | Jul 13 08:26:57 PM PDT 24 |
| Peak memory | 575136 kb |
| Host | smart-8a02b4b6-f564-4c59-b564-cdad87432521 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179829333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1179829333 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.486755623 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 2450233008 ps |
| CPU time | 267.99 seconds |
| Started | Jul 13 08:26:08 PM PDT 24 |
| Finished | Jul 13 08:30:37 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-0c48aa12-a4ae-48e8-a785-bfb80be2edf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486755623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_ with_rand_reset.486755623 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2349331273 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 4787363870 ps |
| CPU time | 199.32 seconds |
| Started | Jul 13 08:26:09 PM PDT 24 |
| Finished | Jul 13 08:29:28 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-66f7c45b-0d9b-4682-a110-405f731d0b17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349331273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.2349331273 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.1308759795 |
| Short name | T2905 |
| Test name | |
| Test status | |
| Simulation time | 926315868 ps |
| CPU time | 54 seconds |
| Started | Jul 13 08:26:20 PM PDT 24 |
| Finished | Jul 13 08:27:15 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-6b5aa6de-237d-4739-a238-5685c10f444d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308759795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1308759795 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.744718261 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 3461512167 ps |
| CPU time | 149.8 seconds |
| Started | Jul 13 08:26:20 PM PDT 24 |
| Finished | Jul 13 08:28:51 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-47fbfc6e-a00b-473c-9f60-d8ca264d2710 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744718261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device. 744718261 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.871567842 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 73296944722 ps |
| CPU time | 1417.17 seconds |
| Started | Jul 13 08:26:18 PM PDT 24 |
| Finished | Jul 13 08:49:55 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-d7e6c369-4ea7-4111-a6cf-4e34255047c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871567842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_d evice_slow_rsp.871567842 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.705071891 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 94578936 ps |
| CPU time | 14.69 seconds |
| Started | Jul 13 08:26:19 PM PDT 24 |
| Finished | Jul 13 08:26:34 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-e12b161c-3429-4faa-9345-aff328816399 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705071891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr .705071891 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.3067250093 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 1752917538 ps |
| CPU time | 69.49 seconds |
| Started | Jul 13 08:26:18 PM PDT 24 |
| Finished | Jul 13 08:27:28 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-34b4bf68-dbad-4e49-a0c9-9144c53bc931 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067250093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3067250093 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.2837529705 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 1260173412 ps |
| CPU time | 43.04 seconds |
| Started | Jul 13 08:26:09 PM PDT 24 |
| Finished | Jul 13 08:26:52 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-8d24972e-1a7e-4d3c-8c1c-1e3627a25db4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837529705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.2837529705 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.1442272102 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 109282723698 ps |
| CPU time | 1217.63 seconds |
| Started | Jul 13 08:26:10 PM PDT 24 |
| Finished | Jul 13 08:46:28 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-d899fcf7-786e-45f7-8ebb-d5f636c95540 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442272102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1442272102 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.469690372 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 29379472244 ps |
| CPU time | 577.84 seconds |
| Started | Jul 13 08:26:18 PM PDT 24 |
| Finished | Jul 13 08:35:56 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-9e0a2728-beb3-4e05-a503-3b0f370812b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469690372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.469690372 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.903769862 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 40532633 ps |
| CPU time | 7.3 seconds |
| Started | Jul 13 08:26:20 PM PDT 24 |
| Finished | Jul 13 08:26:28 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-a7cad209-17b3-4b2b-8584-780b5ee96908 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903769862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_dela ys.903769862 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.1713975328 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 1997473169 ps |
| CPU time | 64.09 seconds |
| Started | Jul 13 08:26:19 PM PDT 24 |
| Finished | Jul 13 08:27:24 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-8c7c4357-b058-496e-8508-c261dda4116a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713975328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1713975328 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.523957859 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 44488193 ps |
| CPU time | 6.65 seconds |
| Started | Jul 13 08:26:08 PM PDT 24 |
| Finished | Jul 13 08:26:15 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-f30d228a-71db-47b1-808e-9a38b191fa80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523957859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.523957859 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.3587563850 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 6556589435 ps |
| CPU time | 79.41 seconds |
| Started | Jul 13 08:26:09 PM PDT 24 |
| Finished | Jul 13 08:27:29 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-aa471612-e580-4d3b-b7b9-5adf14eedcda |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587563850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3587563850 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1869959704 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 4965115299 ps |
| CPU time | 87.64 seconds |
| Started | Jul 13 08:26:11 PM PDT 24 |
| Finished | Jul 13 08:27:39 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-5e7542ae-1930-4092-b9cb-d1253de270f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869959704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1869959704 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.3033882818 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 41378632 ps |
| CPU time | 6.63 seconds |
| Started | Jul 13 08:26:20 PM PDT 24 |
| Finished | Jul 13 08:26:27 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-bbc50a4e-7637-4233-866b-d578fd8601a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033882818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.3033882818 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.169765607 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 3320847006 ps |
| CPU time | 290.84 seconds |
| Started | Jul 13 08:26:18 PM PDT 24 |
| Finished | Jul 13 08:31:10 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-cbdb90b4-d1e8-48cf-8814-0cab671ca5e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169765607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.169765607 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.2803465776 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 2565584359 ps |
| CPU time | 211.95 seconds |
| Started | Jul 13 08:26:18 PM PDT 24 |
| Finished | Jul 13 08:29:51 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-69b17d9f-da7d-4d6a-b605-bb7013f1d1bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803465776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2803465776 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.537415209 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 228585369 ps |
| CPU time | 93.1 seconds |
| Started | Jul 13 08:26:17 PM PDT 24 |
| Finished | Jul 13 08:27:51 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-e71b835b-b972-4573-9ffd-a3b6dbeda410 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537415209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_ with_rand_reset.537415209 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.3788361597 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 218291653 ps |
| CPU time | 75.56 seconds |
| Started | Jul 13 08:26:18 PM PDT 24 |
| Finished | Jul 13 08:27:34 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-dab60c34-79f1-47b0-9e9a-02c8d8811f0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788361597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.3788361597 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.2218983875 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 561421945 ps |
| CPU time | 27.09 seconds |
| Started | Jul 13 08:26:20 PM PDT 24 |
| Finished | Jul 13 08:26:48 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-78dec530-2c40-4c38-9c8a-ab08320abc21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218983875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2218983875 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.419478408 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 60577151542 ps |
| CPU time | 9645.84 seconds |
| Started | Jul 13 08:15:41 PM PDT 24 |
| Finished | Jul 13 10:56:28 PM PDT 24 |
| Peak memory | 632928 kb |
| Host | smart-cfac6efd-aad6-4c31-b3c2-be3304ffa06f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419478408 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 4.chip_csr_aliasing.419478408 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.4228028162 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 10932979279 ps |
| CPU time | 1431.24 seconds |
| Started | Jul 13 08:15:42 PM PDT 24 |
| Finished | Jul 13 08:39:34 PM PDT 24 |
| Peak memory | 592912 kb |
| Host | smart-fbf8f42a-793c-4e28-b7f1-34a02f5e68aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228028162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.4228028162 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.2554491765 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 3939412646 ps |
| CPU time | 329.6 seconds |
| Started | Jul 13 08:16:09 PM PDT 24 |
| Finished | Jul 13 08:21:39 PM PDT 24 |
| Peak memory | 599212 kb |
| Host | smart-13fbaf75-e7c5-497c-bf1f-d83c694d2f12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554491765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.2554491765 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.1334615836 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 28850507742 ps |
| CPU time | 4201.66 seconds |
| Started | Jul 13 08:15:42 PM PDT 24 |
| Finished | Jul 13 09:25:44 PM PDT 24 |
| Peak memory | 593232 kb |
| Host | smart-0b35b61d-1d8e-4d50-9ecf-2da096759e38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334615836 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.1334615836 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.2659955850 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 3207312188 ps |
| CPU time | 171.22 seconds |
| Started | Jul 13 08:15:47 PM PDT 24 |
| Finished | Jul 13 08:18:39 PM PDT 24 |
| Peak memory | 599672 kb |
| Host | smart-0555a3cd-ee84-4899-abbb-a11dfcd6747d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659955850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.2659955850 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.736047164 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 810399007 ps |
| CPU time | 68.15 seconds |
| Started | Jul 13 08:15:54 PM PDT 24 |
| Finished | Jul 13 08:17:03 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-1bafe1c8-ee96-4a63-bae3-e144c3354124 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736047164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.736047164 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.2138740000 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 820514884 ps |
| CPU time | 37.14 seconds |
| Started | Jul 13 08:15:59 PM PDT 24 |
| Finished | Jul 13 08:16:37 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-724320ef-fd68-49d0-be93-f2636916637c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138740000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .2138740000 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.3238638195 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 385469011 ps |
| CPU time | 17.8 seconds |
| Started | Jul 13 08:15:56 PM PDT 24 |
| Finished | Jul 13 08:16:14 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-01b9862a-74a0-4fbd-abea-97812a9653dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238638195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3238638195 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.2068624983 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 885264285 ps |
| CPU time | 39.35 seconds |
| Started | Jul 13 08:15:59 PM PDT 24 |
| Finished | Jul 13 08:16:39 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-a39d0c84-5efb-4611-b27a-982c57b74ca3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068624983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.2068624983 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.2284119493 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 49511786526 ps |
| CPU time | 544.73 seconds |
| Started | Jul 13 08:15:55 PM PDT 24 |
| Finished | Jul 13 08:25:00 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-6a0cccc7-1ddc-4eb4-a820-c66230dc216c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284119493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2284119493 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.689282637 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 64662662406 ps |
| CPU time | 1196.23 seconds |
| Started | Jul 13 08:15:55 PM PDT 24 |
| Finished | Jul 13 08:35:52 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-b546e4bc-347f-4b60-91ff-46ab8cffa93b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689282637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.689282637 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.3090793771 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 284283831 ps |
| CPU time | 29.09 seconds |
| Started | Jul 13 08:15:55 PM PDT 24 |
| Finished | Jul 13 08:16:25 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-b306c89e-0382-458a-9cc3-ba76e2ac859b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090793771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela ys.3090793771 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.1039547003 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 1639507831 ps |
| CPU time | 73.63 seconds |
| Started | Jul 13 08:16:08 PM PDT 24 |
| Finished | Jul 13 08:17:22 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-fce93306-cefe-4496-9dd3-72b92d0923ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039547003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1039547003 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.1169189398 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 54925136 ps |
| CPU time | 7.4 seconds |
| Started | Jul 13 08:15:47 PM PDT 24 |
| Finished | Jul 13 08:15:55 PM PDT 24 |
| Peak memory | 573996 kb |
| Host | smart-356693a8-96b1-4161-bb27-a262e9acd276 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169189398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1169189398 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.2442853655 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 6982508667 ps |
| CPU time | 81.8 seconds |
| Started | Jul 13 08:15:51 PM PDT 24 |
| Finished | Jul 13 08:17:14 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-70b7142a-d0c5-45e1-86c3-b89c8ee51a46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442853655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2442853655 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.631094164 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 5641012690 ps |
| CPU time | 109.39 seconds |
| Started | Jul 13 08:15:47 PM PDT 24 |
| Finished | Jul 13 08:17:37 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-75514813-d3fc-413b-825a-6b02fc0f2229 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631094164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.631094164 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.548780280 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 50607538 ps |
| CPU time | 7.36 seconds |
| Started | Jul 13 08:15:46 PM PDT 24 |
| Finished | Jul 13 08:15:54 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-bb64f772-a6b0-45f1-9382-51be47ce91aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548780280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays. 548780280 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.2338165565 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 2720166381 ps |
| CPU time | 276.97 seconds |
| Started | Jul 13 08:15:56 PM PDT 24 |
| Finished | Jul 13 08:20:33 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-539a151a-41c5-47f7-a408-75c41b51303c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338165565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2338165565 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.699659308 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 4484474920 ps |
| CPU time | 138.73 seconds |
| Started | Jul 13 08:16:08 PM PDT 24 |
| Finished | Jul 13 08:18:28 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-d313e21a-2068-4c41-8573-9522ad3dbcdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699659308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.699659308 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2984947407 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 6439322219 ps |
| CPU time | 723.46 seconds |
| Started | Jul 13 08:15:56 PM PDT 24 |
| Finished | Jul 13 08:28:00 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-79ca2483-e7e2-4f9f-b4eb-e4bda07bb5cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984947407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.2984947407 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.2904414400 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 752089590 ps |
| CPU time | 39 seconds |
| Started | Jul 13 08:15:59 PM PDT 24 |
| Finished | Jul 13 08:16:38 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-1cd3e4dd-9d6c-480d-9629-d952c78c590b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904414400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2904414400 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.4217758771 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 860971503 ps |
| CPU time | 43.95 seconds |
| Started | Jul 13 08:26:28 PM PDT 24 |
| Finished | Jul 13 08:27:13 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-210491d5-b384-4d19-bc14-6c89f6ea2076 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217758771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device .4217758771 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.1513282730 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 78959540243 ps |
| CPU time | 1445.44 seconds |
| Started | Jul 13 08:26:28 PM PDT 24 |
| Finished | Jul 13 08:50:34 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-25e15846-b7b2-4f6d-97c1-5c931940ec46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513282730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_ device_slow_rsp.1513282730 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.724045773 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 1122342546 ps |
| CPU time | 50.52 seconds |
| Started | Jul 13 08:26:28 PM PDT 24 |
| Finished | Jul 13 08:27:19 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-27357800-28be-4f3f-a35e-68b6f411bc12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724045773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr .724045773 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.3936330396 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 591354587 ps |
| CPU time | 58.6 seconds |
| Started | Jul 13 08:26:27 PM PDT 24 |
| Finished | Jul 13 08:27:26 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-87488a8d-a447-4b5a-a831-97f513858970 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936330396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.3936330396 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.4166668331 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 55289788436 ps |
| CPU time | 639.99 seconds |
| Started | Jul 13 08:26:28 PM PDT 24 |
| Finished | Jul 13 08:37:08 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-2e17399d-bcf2-4e87-82f2-193bb6db15cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166668331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.4166668331 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.3072551115 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 33881235222 ps |
| CPU time | 563.99 seconds |
| Started | Jul 13 08:26:29 PM PDT 24 |
| Finished | Jul 13 08:35:53 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-61b41123-cddd-415a-a139-5d4837fd023e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072551115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3072551115 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.1515584894 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 563379162 ps |
| CPU time | 59.32 seconds |
| Started | Jul 13 08:26:28 PM PDT 24 |
| Finished | Jul 13 08:27:28 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-14cd3282-3133-4eb2-a7e7-1e735fae7ad8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515584894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.1515584894 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.775222462 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 2429396034 ps |
| CPU time | 84.42 seconds |
| Started | Jul 13 08:26:29 PM PDT 24 |
| Finished | Jul 13 08:27:54 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-b07ff4b9-6105-4242-948f-b5a48880a8f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775222462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.775222462 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.1566791591 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 46502531 ps |
| CPU time | 6.71 seconds |
| Started | Jul 13 08:26:17 PM PDT 24 |
| Finished | Jul 13 08:26:24 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-89a80798-98fa-439a-a972-a74a273828d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566791591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1566791591 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.2390470246 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 9527751192 ps |
| CPU time | 116.32 seconds |
| Started | Jul 13 08:26:35 PM PDT 24 |
| Finished | Jul 13 08:28:32 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-4375520d-13f1-42e5-9591-5fa4bae6e749 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390470246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2390470246 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.2640306295 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 4087343741 ps |
| CPU time | 71.6 seconds |
| Started | Jul 13 08:26:27 PM PDT 24 |
| Finished | Jul 13 08:27:39 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-fe7bb172-cac4-4cfe-88ac-d02e4df3e7c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640306295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2640306295 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.1583054042 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 52412404 ps |
| CPU time | 7.34 seconds |
| Started | Jul 13 08:26:28 PM PDT 24 |
| Finished | Jul 13 08:26:36 PM PDT 24 |
| Peak memory | 573916 kb |
| Host | smart-d4de9b5a-e4b0-4f59-8016-1d2ff9c695b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583054042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.1583054042 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.3456491486 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 5947459068 ps |
| CPU time | 231.37 seconds |
| Started | Jul 13 08:26:27 PM PDT 24 |
| Finished | Jul 13 08:30:19 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-db17b504-3804-49e2-96dc-abb621632780 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456491486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3456491486 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.3817641422 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 1358930298 ps |
| CPU time | 96.97 seconds |
| Started | Jul 13 08:26:37 PM PDT 24 |
| Finished | Jul 13 08:28:14 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-8aa01cfd-abb6-4559-a6a7-cea6024ac4b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817641422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3817641422 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.1420552821 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 3729104395 ps |
| CPU time | 469.92 seconds |
| Started | Jul 13 08:26:38 PM PDT 24 |
| Finished | Jul 13 08:34:29 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-aed3ac83-5033-4607-8073-dc42b69cea92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420552821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_rand_reset.1420552821 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.85896263 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 543484264 ps |
| CPU time | 206.51 seconds |
| Started | Jul 13 08:26:39 PM PDT 24 |
| Finished | Jul 13 08:30:07 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-6f4f3725-2f0f-4cdf-be7c-4e5a5b852834 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85896263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_ with_reset_error.85896263 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.2692037027 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 424125650 ps |
| CPU time | 23.39 seconds |
| Started | Jul 13 08:26:30 PM PDT 24 |
| Finished | Jul 13 08:26:53 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-fab5ef67-5835-4b95-bd51-d80f751a4cbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692037027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2692037027 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.746327672 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 827577119 ps |
| CPU time | 79.44 seconds |
| Started | Jul 13 08:26:37 PM PDT 24 |
| Finished | Jul 13 08:27:57 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-2642ae48-2399-495c-af49-435cd0977057 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746327672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device. 746327672 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2389732531 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 27705063303 ps |
| CPU time | 521.61 seconds |
| Started | Jul 13 08:26:38 PM PDT 24 |
| Finished | Jul 13 08:35:20 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-bae75897-518e-420a-b97f-ff615be34287 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389732531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.2389732531 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.3819889391 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 448006240 ps |
| CPU time | 21.33 seconds |
| Started | Jul 13 08:26:50 PM PDT 24 |
| Finished | Jul 13 08:27:12 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-12af7514-8c0a-4c08-90b0-4a4500a27a4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819889391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add r.3819889391 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.3009666000 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 2566161415 ps |
| CPU time | 93.54 seconds |
| Started | Jul 13 08:26:50 PM PDT 24 |
| Finished | Jul 13 08:28:23 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-415f04e7-8847-4b7e-8759-d2e853337224 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009666000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3009666000 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.720058734 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 356410025 ps |
| CPU time | 17.89 seconds |
| Started | Jul 13 08:26:39 PM PDT 24 |
| Finished | Jul 13 08:26:58 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-90a507bb-14af-4224-bdf2-6ab84a52bb05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720058734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.720058734 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.837067688 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 64568468514 ps |
| CPU time | 761.69 seconds |
| Started | Jul 13 08:26:39 PM PDT 24 |
| Finished | Jul 13 08:39:22 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-06a43aea-8144-4c44-abee-7432e1c523c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837067688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.837067688 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.245475456 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 63188621703 ps |
| CPU time | 1132.96 seconds |
| Started | Jul 13 08:26:40 PM PDT 24 |
| Finished | Jul 13 08:45:34 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-b4d72702-b3d1-4656-83e9-a3033a1b793a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245475456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.245475456 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.1696976557 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 582399624 ps |
| CPU time | 59.31 seconds |
| Started | Jul 13 08:26:41 PM PDT 24 |
| Finished | Jul 13 08:27:40 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-298fed63-4a34-416c-978f-119108814c7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696976557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.1696976557 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.337418422 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 453774404 ps |
| CPU time | 17.12 seconds |
| Started | Jul 13 08:26:39 PM PDT 24 |
| Finished | Jul 13 08:26:57 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-ae047d05-a523-4509-a261-54e4d088857a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337418422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.337418422 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.1942801798 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 187008717 ps |
| CPU time | 9.27 seconds |
| Started | Jul 13 08:26:41 PM PDT 24 |
| Finished | Jul 13 08:26:50 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-7ffe28ca-26e7-4163-9ee7-6bfbbe7edf73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942801798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1942801798 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.2094191655 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 3977925892 ps |
| CPU time | 48.68 seconds |
| Started | Jul 13 08:26:39 PM PDT 24 |
| Finished | Jul 13 08:27:29 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-7c86f629-2fb8-480c-a6e9-e95c6cfed793 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094191655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2094191655 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.3052092065 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 4685881153 ps |
| CPU time | 87.82 seconds |
| Started | Jul 13 08:26:39 PM PDT 24 |
| Finished | Jul 13 08:28:08 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-de164cec-f0ae-446f-ab23-d4bcfd00b997 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052092065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3052092065 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.3861776699 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 49932830 ps |
| CPU time | 5.81 seconds |
| Started | Jul 13 08:26:38 PM PDT 24 |
| Finished | Jul 13 08:26:45 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-1376a37e-0327-4b50-863b-0659d78dc1f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861776699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.3861776699 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.3532126117 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 4490862320 ps |
| CPU time | 176.43 seconds |
| Started | Jul 13 08:26:48 PM PDT 24 |
| Finished | Jul 13 08:29:45 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-f33f445c-2d7e-4b0d-bdf6-0568f65dd40b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532126117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3532126117 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.3186851767 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 257542579 ps |
| CPU time | 9.67 seconds |
| Started | Jul 13 08:26:46 PM PDT 24 |
| Finished | Jul 13 08:26:56 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-69cbfd5b-b5a5-4038-a0d0-69e0bff4d4b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186851767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3186851767 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3494237544 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 171119775 ps |
| CPU time | 81.57 seconds |
| Started | Jul 13 08:26:46 PM PDT 24 |
| Finished | Jul 13 08:28:08 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-bca87915-efeb-46bc-a52e-13d690645acb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494237544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.3494237544 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.2185377831 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 40813592 ps |
| CPU time | 17.49 seconds |
| Started | Jul 13 08:26:48 PM PDT 24 |
| Finished | Jul 13 08:27:06 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-c625e3fa-b44f-4444-bedf-81bf19b0b3a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185377831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.2185377831 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.160104239 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 428374131 ps |
| CPU time | 21.01 seconds |
| Started | Jul 13 08:26:50 PM PDT 24 |
| Finished | Jul 13 08:27:12 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-d0ce91c3-4d63-450f-bd08-fa13d8fc0547 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160104239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.160104239 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.2668641455 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 776165148 ps |
| CPU time | 33.78 seconds |
| Started | Jul 13 08:27:00 PM PDT 24 |
| Finished | Jul 13 08:27:35 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-fcfaed52-68b4-4db5-af8e-a6abe979d3a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668641455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device .2668641455 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.525432598 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 53259604243 ps |
| CPU time | 1017.81 seconds |
| Started | Jul 13 08:27:01 PM PDT 24 |
| Finished | Jul 13 08:43:59 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-e9ac84c2-0372-4595-87a3-5e8b4845f689 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525432598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_d evice_slow_rsp.525432598 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.1404879674 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 218685178 ps |
| CPU time | 25.4 seconds |
| Started | Jul 13 08:27:01 PM PDT 24 |
| Finished | Jul 13 08:27:27 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-bceb80ad-3a12-4b8c-85fd-a6f8b9c8867f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404879674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add r.1404879674 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.822831321 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 301608684 ps |
| CPU time | 27.9 seconds |
| Started | Jul 13 08:27:05 PM PDT 24 |
| Finished | Jul 13 08:27:33 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-9291cf6d-4332-41be-a944-9563736354a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822831321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.822831321 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.958468866 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 490851221 ps |
| CPU time | 46.36 seconds |
| Started | Jul 13 08:27:02 PM PDT 24 |
| Finished | Jul 13 08:27:49 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-170e7ddd-8870-4d74-91d4-76fbd0f4c680 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958468866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.958468866 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.2279071359 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 56650989281 ps |
| CPU time | 694.44 seconds |
| Started | Jul 13 08:27:03 PM PDT 24 |
| Finished | Jul 13 08:38:37 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-a5b04078-0ad5-45ca-8e92-5668747f197b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279071359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2279071359 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.4281031175 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 30240642754 ps |
| CPU time | 561.57 seconds |
| Started | Jul 13 08:27:06 PM PDT 24 |
| Finished | Jul 13 08:36:29 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-aec84f72-3f3f-4895-aa02-f571fd4a3186 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281031175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.4281031175 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.2695548302 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 556262918 ps |
| CPU time | 54.48 seconds |
| Started | Jul 13 08:27:00 PM PDT 24 |
| Finished | Jul 13 08:27:55 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-42b120b1-8931-4911-901f-2953d632e43c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695548302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del ays.2695548302 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.3820566815 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 1805892493 ps |
| CPU time | 55.23 seconds |
| Started | Jul 13 08:27:06 PM PDT 24 |
| Finished | Jul 13 08:28:02 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-a09226fb-cab2-4cf9-9d79-4e9b300d0a20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820566815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3820566815 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.1497535038 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 153736553 ps |
| CPU time | 8.6 seconds |
| Started | Jul 13 08:26:47 PM PDT 24 |
| Finished | Jul 13 08:26:56 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-bc624603-20a9-42cb-8f2b-5680ab58f12b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497535038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1497535038 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.980091002 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 7950632520 ps |
| CPU time | 88.06 seconds |
| Started | Jul 13 08:27:02 PM PDT 24 |
| Finished | Jul 13 08:28:31 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-487d2c80-859f-4aa1-abe9-d89cbbfe6030 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980091002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.980091002 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.3921555540 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 4526973980 ps |
| CPU time | 84.14 seconds |
| Started | Jul 13 08:27:07 PM PDT 24 |
| Finished | Jul 13 08:28:31 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-351a8b8b-c5d1-4f92-800f-22b0a9e1def5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921555540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3921555540 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.3044889334 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 44645558 ps |
| CPU time | 6.82 seconds |
| Started | Jul 13 08:27:02 PM PDT 24 |
| Finished | Jul 13 08:27:10 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-a370841e-fabf-47ec-9496-3f36a96ce933 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044889334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay s.3044889334 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.3551710581 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 15394512894 ps |
| CPU time | 594.3 seconds |
| Started | Jul 13 08:27:10 PM PDT 24 |
| Finished | Jul 13 08:37:05 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-8f5b9222-7b54-4f40-bd7a-6895e96dfbca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551710581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3551710581 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.3480779752 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 954651146 ps |
| CPU time | 27.04 seconds |
| Started | Jul 13 08:27:10 PM PDT 24 |
| Finished | Jul 13 08:27:37 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-40e6330a-0ecf-4f2a-a6d5-8f6442d77aad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480779752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3480779752 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.112202014 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 449076315 ps |
| CPU time | 160 seconds |
| Started | Jul 13 08:27:12 PM PDT 24 |
| Finished | Jul 13 08:29:53 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-dc489485-d8bd-43b4-997e-3fb96d2696b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112202014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_ with_rand_reset.112202014 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.3824283135 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 38394167 ps |
| CPU time | 8.16 seconds |
| Started | Jul 13 08:27:02 PM PDT 24 |
| Finished | Jul 13 08:27:10 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-62bccfdb-950c-49da-a42e-85bd3c1e258d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824283135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3824283135 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.1882985891 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 4448041395 ps |
| CPU time | 202.63 seconds |
| Started | Jul 13 08:27:10 PM PDT 24 |
| Finished | Jul 13 08:30:33 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-c17d27e5-442f-4c0d-82c4-3ad5c0e12d22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882985891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device .1882985891 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.3323442509 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 2854563588 ps |
| CPU time | 59.97 seconds |
| Started | Jul 13 08:27:10 PM PDT 24 |
| Finished | Jul 13 08:28:11 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-cae66885-3f46-4185-81f7-a6def12b3c74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323442509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_ device_slow_rsp.3323442509 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.1261515358 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 156282283 ps |
| CPU time | 9.51 seconds |
| Started | Jul 13 08:27:14 PM PDT 24 |
| Finished | Jul 13 08:27:24 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-16cf944a-0751-435f-b428-ecd5b32afbec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261515358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.1261515358 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.1371608291 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 1522248733 ps |
| CPU time | 59.67 seconds |
| Started | Jul 13 08:27:12 PM PDT 24 |
| Finished | Jul 13 08:28:12 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-e9d11846-c6b7-417f-9e0c-09e538d6eb04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371608291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1371608291 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.462007169 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 597373549 ps |
| CPU time | 24.5 seconds |
| Started | Jul 13 08:27:09 PM PDT 24 |
| Finished | Jul 13 08:27:34 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-cee0351c-c851-4115-b4fb-db4bf8d604e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462007169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.462007169 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.3103227144 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 75849752743 ps |
| CPU time | 840.28 seconds |
| Started | Jul 13 08:27:14 PM PDT 24 |
| Finished | Jul 13 08:41:15 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-69221c21-9310-4a1b-9e7b-207282d81846 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103227144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3103227144 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.1006750704 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 19304992070 ps |
| CPU time | 370.87 seconds |
| Started | Jul 13 08:27:12 PM PDT 24 |
| Finished | Jul 13 08:33:24 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-bcb0043e-9212-419f-b001-1892cf17ad80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006750704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1006750704 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.1370259711 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 533193530 ps |
| CPU time | 43.06 seconds |
| Started | Jul 13 08:27:11 PM PDT 24 |
| Finished | Jul 13 08:27:54 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-8fbcf5b1-eb62-4c74-bb08-31672b31cc15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370259711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.1370259711 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.664349399 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 419870610 ps |
| CPU time | 36.27 seconds |
| Started | Jul 13 08:27:12 PM PDT 24 |
| Finished | Jul 13 08:27:49 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-a4397f01-7a25-4824-ad86-0914511810ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664349399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.664349399 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.3168722948 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 56122505 ps |
| CPU time | 7.35 seconds |
| Started | Jul 13 08:27:14 PM PDT 24 |
| Finished | Jul 13 08:27:22 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-17eda6ab-600a-493c-bb8c-86d86479e4d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168722948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3168722948 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.2612812927 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 7695599752 ps |
| CPU time | 86.76 seconds |
| Started | Jul 13 08:27:12 PM PDT 24 |
| Finished | Jul 13 08:28:39 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-198d1cbc-3b03-4d7f-aaf4-be42bdc33174 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612812927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2612812927 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.3698219088 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 5512838813 ps |
| CPU time | 103.82 seconds |
| Started | Jul 13 08:27:14 PM PDT 24 |
| Finished | Jul 13 08:28:59 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-db9a3381-0a44-403d-a71f-df6be27b0c45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698219088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3698219088 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.2341784765 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 40063428 ps |
| CPU time | 6.57 seconds |
| Started | Jul 13 08:27:14 PM PDT 24 |
| Finished | Jul 13 08:27:22 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-7fc981fb-6971-4e8f-a31f-c88cfdbd03da |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341784765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.2341784765 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.590235253 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 3709888301 ps |
| CPU time | 287.82 seconds |
| Started | Jul 13 08:27:14 PM PDT 24 |
| Finished | Jul 13 08:32:03 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-704bd6fc-91b2-4a88-a18b-05cabd3caf34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590235253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.590235253 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.838774721 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 4761836777 ps |
| CPU time | 168.91 seconds |
| Started | Jul 13 08:27:13 PM PDT 24 |
| Finished | Jul 13 08:30:02 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-952238c8-ab68-4f96-92f0-facc97167f70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838774721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.838774721 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.3349273554 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 2495569251 ps |
| CPU time | 196.3 seconds |
| Started | Jul 13 08:27:13 PM PDT 24 |
| Finished | Jul 13 08:30:30 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-f5fa1172-2224-409a-9093-57338fe67313 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349273554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.3349273554 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.291893540 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 195441076 ps |
| CPU time | 49.61 seconds |
| Started | Jul 13 08:27:10 PM PDT 24 |
| Finished | Jul 13 08:28:00 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-89499b34-4652-4117-ba34-4f9a4ba23cec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291893540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_reset_error.291893540 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.361120052 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 221962000 ps |
| CPU time | 25.2 seconds |
| Started | Jul 13 08:27:11 PM PDT 24 |
| Finished | Jul 13 08:27:37 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-5564680e-8f38-4c35-8a76-6f97ce8a85d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361120052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.361120052 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.3302991015 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 391822678 ps |
| CPU time | 18.28 seconds |
| Started | Jul 13 08:27:19 PM PDT 24 |
| Finished | Jul 13 08:27:38 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-0132ad51-219b-4a33-825a-2b170b70dc3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302991015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .3302991015 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.748014851 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 71986513296 ps |
| CPU time | 1328.77 seconds |
| Started | Jul 13 08:27:19 PM PDT 24 |
| Finished | Jul 13 08:49:29 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-1b230a1e-940a-40be-86d2-039c5e816268 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748014851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_d evice_slow_rsp.748014851 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.2979002365 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 223750534 ps |
| CPU time | 28.86 seconds |
| Started | Jul 13 08:27:20 PM PDT 24 |
| Finished | Jul 13 08:27:49 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-4054b0da-8ca7-4f28-adff-740d9fc0550b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979002365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add r.2979002365 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.3428964831 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 790295713 ps |
| CPU time | 29.52 seconds |
| Started | Jul 13 08:27:22 PM PDT 24 |
| Finished | Jul 13 08:27:52 PM PDT 24 |
| Peak memory | 575164 kb |
| Host | smart-c296654d-088f-4608-8723-5041bc873293 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428964831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3428964831 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.907837721 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 537317019 ps |
| CPU time | 52.86 seconds |
| Started | Jul 13 08:27:18 PM PDT 24 |
| Finished | Jul 13 08:28:12 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-31b3a3bd-9682-4f8a-987a-f201bcbf2624 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907837721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.907837721 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.2893435212 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 93503293764 ps |
| CPU time | 1084.55 seconds |
| Started | Jul 13 08:27:20 PM PDT 24 |
| Finished | Jul 13 08:45:25 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-85e4537a-a5e3-4d8c-8d35-902fb7c404f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893435212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2893435212 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.3677241219 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 34959283734 ps |
| CPU time | 648.83 seconds |
| Started | Jul 13 08:27:22 PM PDT 24 |
| Finished | Jul 13 08:38:11 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-42588613-bb19-471a-bcad-e232c5dee258 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677241219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3677241219 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.1572778009 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 196912850 ps |
| CPU time | 18.85 seconds |
| Started | Jul 13 08:27:20 PM PDT 24 |
| Finished | Jul 13 08:27:39 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-8627b659-dad1-4163-bc48-09f26494dbc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572778009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.1572778009 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.93076086 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 450761039 ps |
| CPU time | 37.85 seconds |
| Started | Jul 13 08:27:22 PM PDT 24 |
| Finished | Jul 13 08:28:01 PM PDT 24 |
| Peak memory | 575172 kb |
| Host | smart-26db1b42-eaa9-4a3a-9643-93d1767d41c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93076086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.93076086 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.865875361 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 46557191 ps |
| CPU time | 6.75 seconds |
| Started | Jul 13 08:27:23 PM PDT 24 |
| Finished | Jul 13 08:27:30 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-f6ba103f-bc30-4015-ac45-a203d34d0244 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865875361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.865875361 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.3133752258 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 8664035181 ps |
| CPU time | 105.44 seconds |
| Started | Jul 13 08:27:18 PM PDT 24 |
| Finished | Jul 13 08:29:04 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-aa0ea4ea-1df3-4d91-8101-78711e1871ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133752258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3133752258 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.2541103329 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 5452674032 ps |
| CPU time | 92.17 seconds |
| Started | Jul 13 08:27:21 PM PDT 24 |
| Finished | Jul 13 08:28:53 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-7745695c-dd95-4401-ab61-f8acd5a0527a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541103329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2541103329 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.4112017560 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 50400871 ps |
| CPU time | 7.4 seconds |
| Started | Jul 13 08:27:20 PM PDT 24 |
| Finished | Jul 13 08:27:28 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-7d61f36f-3cda-4adc-b01c-fac168a87b0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112017560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay s.4112017560 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.715170458 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 2793282861 ps |
| CPU time | 145.8 seconds |
| Started | Jul 13 08:27:19 PM PDT 24 |
| Finished | Jul 13 08:29:46 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-c9542b1a-2793-4031-9f6a-63a0e7a916c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715170458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.715170458 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.1930103671 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 2674337162 ps |
| CPU time | 228.17 seconds |
| Started | Jul 13 08:27:19 PM PDT 24 |
| Finished | Jul 13 08:31:08 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-f5fd98d3-2bf8-4c7e-bf9b-fd07ee9fa3cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930103671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1930103671 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.125310333 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 8482336547 ps |
| CPU time | 431.22 seconds |
| Started | Jul 13 08:27:23 PM PDT 24 |
| Finished | Jul 13 08:34:35 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-7a1e448b-3ccb-4a75-b973-dbcdd0c3de74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125310333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_ with_rand_reset.125310333 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.2853596966 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 892136752 ps |
| CPU time | 159.33 seconds |
| Started | Jul 13 08:27:22 PM PDT 24 |
| Finished | Jul 13 08:30:02 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-7c77d5ac-8347-415a-a4fd-f65e7f532f28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853596966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.2853596966 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.2609618766 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 51980835 ps |
| CPU time | 9.84 seconds |
| Started | Jul 13 08:27:23 PM PDT 24 |
| Finished | Jul 13 08:27:33 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-185458a2-7278-49d4-b47f-f77f51ad2464 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609618766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2609618766 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.746124505 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 938392652 ps |
| CPU time | 90.1 seconds |
| Started | Jul 13 08:27:30 PM PDT 24 |
| Finished | Jul 13 08:29:00 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-4cf029dc-960b-43e6-85b6-c98197531aa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746124505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device. 746124505 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.2054540516 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 31560144842 ps |
| CPU time | 604.99 seconds |
| Started | Jul 13 08:27:29 PM PDT 24 |
| Finished | Jul 13 08:37:34 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-6741b4f3-b863-40c8-9be3-b720e39e9974 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054540516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.2054540516 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.2864133141 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 802512436 ps |
| CPU time | 36.7 seconds |
| Started | Jul 13 08:27:41 PM PDT 24 |
| Finished | Jul 13 08:28:17 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-a38fe16f-9b2b-4e41-971a-9df9e0dffb03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864133141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add r.2864133141 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.3556745330 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 2118904261 ps |
| CPU time | 94.3 seconds |
| Started | Jul 13 08:27:29 PM PDT 24 |
| Finished | Jul 13 08:29:03 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-9c34b29a-6f06-4632-9987-0226e428c2bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556745330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3556745330 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.3459072995 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 44258443 ps |
| CPU time | 7.45 seconds |
| Started | Jul 13 08:27:28 PM PDT 24 |
| Finished | Jul 13 08:27:36 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-ffd4db79-0a52-47ef-9b25-a809606dd720 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459072995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.3459072995 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.1703735059 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 90381671966 ps |
| CPU time | 1104.88 seconds |
| Started | Jul 13 08:27:28 PM PDT 24 |
| Finished | Jul 13 08:45:53 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-d7894675-b28d-4a28-8aba-6705e63335f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703735059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.1703735059 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.1431515451 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 43300603546 ps |
| CPU time | 747.67 seconds |
| Started | Jul 13 08:27:26 PM PDT 24 |
| Finished | Jul 13 08:39:55 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-2339ce09-2cf3-47f6-91b9-42f0d2e4403c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431515451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1431515451 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.322518173 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 574805010 ps |
| CPU time | 53.02 seconds |
| Started | Jul 13 08:27:28 PM PDT 24 |
| Finished | Jul 13 08:28:21 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-c24b324e-5764-4477-9cf1-ce46db525119 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322518173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_dela ys.322518173 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.4263219988 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 561749071 ps |
| CPU time | 20.19 seconds |
| Started | Jul 13 08:27:30 PM PDT 24 |
| Finished | Jul 13 08:27:51 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-dc858a84-0257-4228-b64f-dff4ba1210f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263219988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.4263219988 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.515712906 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 37469534 ps |
| CPU time | 6.14 seconds |
| Started | Jul 13 08:27:29 PM PDT 24 |
| Finished | Jul 13 08:27:36 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-f39010f6-8d93-4060-b2cf-fb379413c904 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515712906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.515712906 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.760747347 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 7971910048 ps |
| CPU time | 89.43 seconds |
| Started | Jul 13 08:27:29 PM PDT 24 |
| Finished | Jul 13 08:28:59 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-726eeeda-f1b5-404d-836c-b6019fd00b78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760747347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.760747347 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.3321374773 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 5953637249 ps |
| CPU time | 112.25 seconds |
| Started | Jul 13 08:27:27 PM PDT 24 |
| Finished | Jul 13 08:29:19 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-911141d6-7689-4789-8e78-b6e41b5797e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321374773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.3321374773 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.3086405691 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 52311793 ps |
| CPU time | 7.33 seconds |
| Started | Jul 13 08:27:28 PM PDT 24 |
| Finished | Jul 13 08:27:36 PM PDT 24 |
| Peak memory | 573996 kb |
| Host | smart-75a7657b-5220-4fce-8748-520a2df397ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086405691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay s.3086405691 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.850341637 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 3353452647 ps |
| CPU time | 366.36 seconds |
| Started | Jul 13 08:27:38 PM PDT 24 |
| Finished | Jul 13 08:33:45 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-6cd7a0ad-1b44-490d-b771-185c3336aadd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850341637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.850341637 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.699079208 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 490299172 ps |
| CPU time | 42.83 seconds |
| Started | Jul 13 08:27:40 PM PDT 24 |
| Finished | Jul 13 08:28:23 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-3f18d04a-f0f5-474e-a1de-a2cd0d83dd48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699079208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.699079208 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.2730449919 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 1691785806 ps |
| CPU time | 237.77 seconds |
| Started | Jul 13 08:27:38 PM PDT 24 |
| Finished | Jul 13 08:31:36 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-db7cebe6-8426-4faf-b20f-8b97940b2852 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730449919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.2730449919 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.794178550 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 121256783 ps |
| CPU time | 22.58 seconds |
| Started | Jul 13 08:27:42 PM PDT 24 |
| Finished | Jul 13 08:28:05 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-19c512eb-301b-450d-884c-3382af6132ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794178550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_reset_error.794178550 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.1179973977 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 64032165 ps |
| CPU time | 6.44 seconds |
| Started | Jul 13 08:27:41 PM PDT 24 |
| Finished | Jul 13 08:27:48 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-80f8491d-787c-4db3-8e52-8dfa514da1e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179973977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1179973977 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.3700138130 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 1364002562 ps |
| CPU time | 67.28 seconds |
| Started | Jul 13 08:27:37 PM PDT 24 |
| Finished | Jul 13 08:28:45 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-6025d468-e1f2-4c38-b6b5-9bbf39445041 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700138130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device .3700138130 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.2352089110 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 148091527 ps |
| CPU time | 19.64 seconds |
| Started | Jul 13 08:27:48 PM PDT 24 |
| Finished | Jul 13 08:28:08 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-8156a956-2849-4499-8be3-0be598f65ce1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352089110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add r.2352089110 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.2867004896 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 68194206 ps |
| CPU time | 9.18 seconds |
| Started | Jul 13 08:27:49 PM PDT 24 |
| Finished | Jul 13 08:27:59 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-e9064e19-8998-46b8-881b-8b1ff891db36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867004896 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2867004896 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.1843183764 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 1887316376 ps |
| CPU time | 88.98 seconds |
| Started | Jul 13 08:27:37 PM PDT 24 |
| Finished | Jul 13 08:29:07 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-05ca932f-fb34-4d5d-8f6c-280d98524aaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843183764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.1843183764 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.1992067085 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 18511592194 ps |
| CPU time | 209.19 seconds |
| Started | Jul 13 08:27:39 PM PDT 24 |
| Finished | Jul 13 08:31:09 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-36341850-6428-4e6a-9d3d-e87419f39de9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992067085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1992067085 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.1012907076 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 17633684791 ps |
| CPU time | 330.6 seconds |
| Started | Jul 13 08:27:38 PM PDT 24 |
| Finished | Jul 13 08:33:09 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-e3a24a4e-9275-4cf6-86af-ce6d21d5ca12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012907076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1012907076 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.2825312180 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 229670870 ps |
| CPU time | 24.3 seconds |
| Started | Jul 13 08:27:38 PM PDT 24 |
| Finished | Jul 13 08:28:03 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-af8af402-e3b2-4fac-8ad4-9a9ec94602b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825312180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del ays.2825312180 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.3114850713 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 2297408275 ps |
| CPU time | 77.66 seconds |
| Started | Jul 13 08:27:46 PM PDT 24 |
| Finished | Jul 13 08:29:04 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-4c449258-30f8-42d4-bff3-e3c5dbc506f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114850713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3114850713 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.4170994652 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 201475912 ps |
| CPU time | 9.41 seconds |
| Started | Jul 13 08:27:38 PM PDT 24 |
| Finished | Jul 13 08:27:47 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-f96417c6-3d5e-4d93-8520-bb3decd2d910 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170994652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.4170994652 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.747496163 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 9366623429 ps |
| CPU time | 114.35 seconds |
| Started | Jul 13 08:27:38 PM PDT 24 |
| Finished | Jul 13 08:29:33 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-ffd6c8bc-5c93-4941-a3f4-019ab349852a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747496163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.747496163 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.3274354874 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 4976737972 ps |
| CPU time | 94.22 seconds |
| Started | Jul 13 08:27:43 PM PDT 24 |
| Finished | Jul 13 08:29:18 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-c71fc2d2-113f-4c4c-aaf0-5f6fae68b90d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274354874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3274354874 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.4089147873 |
| Short name | T2910 |
| Test name | |
| Test status | |
| Simulation time | 42718218 ps |
| CPU time | 6.49 seconds |
| Started | Jul 13 08:27:42 PM PDT 24 |
| Finished | Jul 13 08:27:49 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-18f9301c-fc5b-4b1a-a05b-556663fab3e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089147873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.4089147873 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.651376653 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 12213686377 ps |
| CPU time | 479.33 seconds |
| Started | Jul 13 08:27:50 PM PDT 24 |
| Finished | Jul 13 08:35:50 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-ba28b35a-27e2-47ce-946f-34371c286319 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651376653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.651376653 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.620717941 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 1953743576 ps |
| CPU time | 193.79 seconds |
| Started | Jul 13 08:27:48 PM PDT 24 |
| Finished | Jul 13 08:31:03 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-5cf70881-ffad-44a7-8bba-5868cbcb54e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620717941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.620717941 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.3469499475 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 305941704 ps |
| CPU time | 225.98 seconds |
| Started | Jul 13 08:27:48 PM PDT 24 |
| Finished | Jul 13 08:31:35 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-9e2f5c75-974f-4d5c-8c90-ec66fe575e9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469499475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.3469499475 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.1174878816 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 5672684416 ps |
| CPU time | 292.25 seconds |
| Started | Jul 13 08:27:50 PM PDT 24 |
| Finished | Jul 13 08:32:42 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-53d48afd-b158-4963-a08c-2ad23ee93776 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174878816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.1174878816 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.3154085272 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 25930711 ps |
| CPU time | 6.47 seconds |
| Started | Jul 13 08:27:47 PM PDT 24 |
| Finished | Jul 13 08:27:53 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-7af9f227-e5fb-46c0-88ac-f484cfe47858 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154085272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.3154085272 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.1349054649 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 684573625 ps |
| CPU time | 68.27 seconds |
| Started | Jul 13 08:27:56 PM PDT 24 |
| Finished | Jul 13 08:29:05 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-6a5baa3c-aff9-4fae-be8b-7c208bd28287 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349054649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device .1349054649 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.2046311984 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 8740559527 ps |
| CPU time | 167.28 seconds |
| Started | Jul 13 08:27:56 PM PDT 24 |
| Finished | Jul 13 08:30:44 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-a9b67d2e-f3bb-496e-8a10-bcab9646b306 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046311984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.2046311984 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.634501820 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 513241971 ps |
| CPU time | 25.1 seconds |
| Started | Jul 13 08:27:56 PM PDT 24 |
| Finished | Jul 13 08:28:21 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-4cc3aa3e-f688-4b8d-b2b8-71b03b2fe6b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634501820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr .634501820 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.3556840085 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 633345715 ps |
| CPU time | 26.97 seconds |
| Started | Jul 13 08:27:57 PM PDT 24 |
| Finished | Jul 13 08:28:24 PM PDT 24 |
| Peak memory | 574984 kb |
| Host | smart-23454a02-e835-4ad6-a4c1-b49ed65ac45b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556840085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3556840085 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.818197315 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 2357271308 ps |
| CPU time | 96.04 seconds |
| Started | Jul 13 08:27:47 PM PDT 24 |
| Finished | Jul 13 08:29:24 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-3fa13230-1dff-47f5-a747-c7f270567f72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818197315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.818197315 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.350038014 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 105620357425 ps |
| CPU time | 1215.82 seconds |
| Started | Jul 13 08:27:47 PM PDT 24 |
| Finished | Jul 13 08:48:03 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-24556b8d-1e9d-4f43-91e5-d14a6a647656 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350038014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.350038014 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.3241932759 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 37092309115 ps |
| CPU time | 707.08 seconds |
| Started | Jul 13 08:27:56 PM PDT 24 |
| Finished | Jul 13 08:39:44 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-f862ed04-5fa1-45ad-86aa-9185369722bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241932759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3241932759 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.3913761588 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 401946098 ps |
| CPU time | 37.48 seconds |
| Started | Jul 13 08:27:47 PM PDT 24 |
| Finished | Jul 13 08:28:25 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-05b6fdc0-3b93-4820-92a6-a0f5256ee927 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913761588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del ays.3913761588 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.2130212714 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 127709039 ps |
| CPU time | 13.42 seconds |
| Started | Jul 13 08:27:55 PM PDT 24 |
| Finished | Jul 13 08:28:09 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-9d65cac5-a6ca-4327-a241-06fced1ff7c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130212714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2130212714 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.4290311413 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 203729624 ps |
| CPU time | 9.45 seconds |
| Started | Jul 13 08:27:47 PM PDT 24 |
| Finished | Jul 13 08:27:57 PM PDT 24 |
| Peak memory | 574012 kb |
| Host | smart-e0aa8573-c876-4341-8071-c61786337ebc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290311413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.4290311413 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.3328827132 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 8026718357 ps |
| CPU time | 94.69 seconds |
| Started | Jul 13 08:27:48 PM PDT 24 |
| Finished | Jul 13 08:29:23 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-0869f88f-b0f1-4e48-a194-910462724e58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328827132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3328827132 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1345109926 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 4881993421 ps |
| CPU time | 87.38 seconds |
| Started | Jul 13 08:27:49 PM PDT 24 |
| Finished | Jul 13 08:29:17 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-ced81b74-e19b-4bad-a32f-cbc94ae19902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345109926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1345109926 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.3917591574 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 51220515 ps |
| CPU time | 6.96 seconds |
| Started | Jul 13 08:27:48 PM PDT 24 |
| Finished | Jul 13 08:27:56 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-6057807b-d1c6-4b10-bd0b-53aa84200ce5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917591574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay s.3917591574 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.2734161976 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 3723138657 ps |
| CPU time | 289.21 seconds |
| Started | Jul 13 08:27:56 PM PDT 24 |
| Finished | Jul 13 08:32:45 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-3e1e03cf-85cb-4133-8e31-49f6e80b1a80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734161976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2734161976 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.2126179854 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 6403550255 ps |
| CPU time | 244.99 seconds |
| Started | Jul 13 08:27:56 PM PDT 24 |
| Finished | Jul 13 08:32:01 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-9873a554-0f40-440a-bcdd-eec111470d38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126179854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2126179854 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.1628030316 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 2759314235 ps |
| CPU time | 336.11 seconds |
| Started | Jul 13 08:27:57 PM PDT 24 |
| Finished | Jul 13 08:33:34 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-d2314cf7-91e0-416f-a0c8-7fbf946fe338 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628030316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.1628030316 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.3998845151 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 132502501 ps |
| CPU time | 72 seconds |
| Started | Jul 13 08:27:57 PM PDT 24 |
| Finished | Jul 13 08:29:09 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-617042a0-ec15-4217-8ea1-43c29ee96bf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998845151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.3998845151 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.669143220 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 121499901 ps |
| CPU time | 16.11 seconds |
| Started | Jul 13 08:27:54 PM PDT 24 |
| Finished | Jul 13 08:28:11 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-f7e25376-7b5a-48e7-8f74-3d020c012730 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669143220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.669143220 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.1862036702 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 1206324693 ps |
| CPU time | 48.45 seconds |
| Started | Jul 13 08:28:10 PM PDT 24 |
| Finished | Jul 13 08:28:59 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-81ac762e-b9f4-4b0b-9e00-75aced809b8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862036702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .1862036702 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.2615041357 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 248671468 ps |
| CPU time | 12.16 seconds |
| Started | Jul 13 08:28:05 PM PDT 24 |
| Finished | Jul 13 08:28:17 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-e498f65c-77a0-449c-b5d9-4aaced31c08f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615041357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.2615041357 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.2778145313 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 2444603527 ps |
| CPU time | 86.49 seconds |
| Started | Jul 13 08:28:09 PM PDT 24 |
| Finished | Jul 13 08:29:36 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-b6472d8a-4d43-43ac-9c8e-46a73289e6af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778145313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2778145313 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.2921447368 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 1176480358 ps |
| CPU time | 47.64 seconds |
| Started | Jul 13 08:28:07 PM PDT 24 |
| Finished | Jul 13 08:28:56 PM PDT 24 |
| Peak memory | 575164 kb |
| Host | smart-8b827c09-177d-4432-85ed-92b195c841b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921447368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.2921447368 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.1948883481 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 49875525939 ps |
| CPU time | 571.07 seconds |
| Started | Jul 13 08:28:05 PM PDT 24 |
| Finished | Jul 13 08:37:37 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-5ffbeefa-68c6-4611-a02d-23cf47f2f89d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948883481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1948883481 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.419978193 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 37138767217 ps |
| CPU time | 705.95 seconds |
| Started | Jul 13 08:28:10 PM PDT 24 |
| Finished | Jul 13 08:39:57 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-ceb7e679-5476-43e0-a264-d6aab9ed036b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419978193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.419978193 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.3719929709 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 335396886 ps |
| CPU time | 32.92 seconds |
| Started | Jul 13 08:28:07 PM PDT 24 |
| Finished | Jul 13 08:28:40 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-fda89b45-f1d4-41a4-ad4c-05272f2f5d39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719929709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.3719929709 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.1575220946 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 1278453736 ps |
| CPU time | 35.09 seconds |
| Started | Jul 13 08:28:06 PM PDT 24 |
| Finished | Jul 13 08:28:42 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-99ffb778-76b6-4175-97a1-26fc35dff88a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575220946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1575220946 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.2039715271 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 135920511 ps |
| CPU time | 8.43 seconds |
| Started | Jul 13 08:27:55 PM PDT 24 |
| Finished | Jul 13 08:28:04 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-c6d7c036-5d15-46f2-a579-e51c48943964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039715271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2039715271 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.483781803 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 9215582482 ps |
| CPU time | 103.06 seconds |
| Started | Jul 13 08:27:56 PM PDT 24 |
| Finished | Jul 13 08:29:40 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-8d474a2d-da3d-4d54-b8c9-5ece3717bdd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483781803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.483781803 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.1608886722 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 5747321056 ps |
| CPU time | 107.16 seconds |
| Started | Jul 13 08:28:06 PM PDT 24 |
| Finished | Jul 13 08:29:54 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-78b1a4de-111e-42e0-9be6-c154fb7c30c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608886722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1608886722 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.3351941441 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 45146233 ps |
| CPU time | 6.36 seconds |
| Started | Jul 13 08:27:56 PM PDT 24 |
| Finished | Jul 13 08:28:03 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-bfd88115-7e68-4e11-a763-c2ba484c29d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351941441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delay s.3351941441 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.166680661 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 217638524 ps |
| CPU time | 10.4 seconds |
| Started | Jul 13 08:28:10 PM PDT 24 |
| Finished | Jul 13 08:28:21 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-cab452af-b7c6-4b63-92ab-fe5b04a04aa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166680661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.166680661 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.490715177 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 604506710 ps |
| CPU time | 55.31 seconds |
| Started | Jul 13 08:28:11 PM PDT 24 |
| Finished | Jul 13 08:29:06 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-77b3bbc1-a44c-4b08-a2fc-8ecfc9a8ec60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490715177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.490715177 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.2134031427 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 5345609499 ps |
| CPU time | 555.07 seconds |
| Started | Jul 13 08:28:06 PM PDT 24 |
| Finished | Jul 13 08:37:22 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-6e3877f2-0b83-4af1-bd10-77410e2d22e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134031427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al l_with_reset_error.2134031427 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.2560531937 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 656740916 ps |
| CPU time | 33.89 seconds |
| Started | Jul 13 08:28:06 PM PDT 24 |
| Finished | Jul 13 08:28:41 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-33d865bc-66c1-4ceb-9662-e8a0c5d9e713 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560531937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2560531937 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.567949099 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 310859432 ps |
| CPU time | 25.62 seconds |
| Started | Jul 13 08:28:14 PM PDT 24 |
| Finished | Jul 13 08:28:40 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-4ff54534-a75b-40b2-a47b-5d63777a396c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567949099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device. 567949099 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.2748111154 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 127962927160 ps |
| CPU time | 2359.58 seconds |
| Started | Jul 13 08:28:20 PM PDT 24 |
| Finished | Jul 13 09:07:41 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-1eeb1dc1-e77e-41e2-b3a2-3761033628ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748111154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.2748111154 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.3831849033 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 1492955544 ps |
| CPU time | 66.87 seconds |
| Started | Jul 13 08:28:23 PM PDT 24 |
| Finished | Jul 13 08:29:31 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-a9af57c3-b549-41ef-9c66-af98808cb61d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831849033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.3831849033 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.1524378965 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 158408756 ps |
| CPU time | 16.19 seconds |
| Started | Jul 13 08:28:14 PM PDT 24 |
| Finished | Jul 13 08:28:31 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-002c0fd7-bf2a-4ca3-982c-48710849b473 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524378965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.1524378965 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.1862210244 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 1102460904 ps |
| CPU time | 38.91 seconds |
| Started | Jul 13 08:28:21 PM PDT 24 |
| Finished | Jul 13 08:29:00 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-8ba170b9-a385-4d77-a79c-621ab129fe9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862210244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.1862210244 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.2198603937 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 84099691840 ps |
| CPU time | 944.27 seconds |
| Started | Jul 13 08:28:21 PM PDT 24 |
| Finished | Jul 13 08:44:06 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-3480ad5f-eb37-446c-852b-e5389fd1fe60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198603937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2198603937 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.2545798550 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 48099410798 ps |
| CPU time | 906.85 seconds |
| Started | Jul 13 08:28:18 PM PDT 24 |
| Finished | Jul 13 08:43:25 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-dfa219e7-7f4f-4a04-88ea-233eea1423f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545798550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2545798550 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.2394110303 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 505955025 ps |
| CPU time | 47.42 seconds |
| Started | Jul 13 08:28:15 PM PDT 24 |
| Finished | Jul 13 08:29:03 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-78251166-70bd-46d8-9737-5ceecf483dec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394110303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.2394110303 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.629933313 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 239608098 ps |
| CPU time | 10.67 seconds |
| Started | Jul 13 08:28:13 PM PDT 24 |
| Finished | Jul 13 08:28:24 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-b5200fa9-398a-4e70-b740-72ce125d5ee7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629933313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.629933313 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.1613886819 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 36538988 ps |
| CPU time | 6.33 seconds |
| Started | Jul 13 08:28:06 PM PDT 24 |
| Finished | Jul 13 08:28:13 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-722846d5-4d16-4183-b8d5-0738b13ec1b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613886819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1613886819 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.1829632386 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 9606710458 ps |
| CPU time | 109.03 seconds |
| Started | Jul 13 08:28:06 PM PDT 24 |
| Finished | Jul 13 08:29:56 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-8665e3aa-8597-4b74-829d-ffc9297ec723 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829632386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1829632386 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.3199333423 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 6360911614 ps |
| CPU time | 112.79 seconds |
| Started | Jul 13 08:28:14 PM PDT 24 |
| Finished | Jul 13 08:30:07 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-c1305fcd-26c6-4e89-8d42-a8fd1e4970ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199333423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3199333423 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.1206832103 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 49425950 ps |
| CPU time | 6.58 seconds |
| Started | Jul 13 08:28:07 PM PDT 24 |
| Finished | Jul 13 08:28:15 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-e70a216b-9731-409b-8bd2-8a4734f051e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206832103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.1206832103 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.264717010 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 12540103160 ps |
| CPU time | 527.08 seconds |
| Started | Jul 13 08:28:23 PM PDT 24 |
| Finished | Jul 13 08:37:11 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-380d18eb-0782-4a6e-b3a1-85e65f173a4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264717010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.264717010 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.843442103 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 3862062924 ps |
| CPU time | 144.25 seconds |
| Started | Jul 13 08:28:24 PM PDT 24 |
| Finished | Jul 13 08:30:51 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-dfe83907-6d66-4b64-8dde-26dd409c2fc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843442103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.843442103 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.2760137643 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 6137042444 ps |
| CPU time | 533.06 seconds |
| Started | Jul 13 08:28:27 PM PDT 24 |
| Finished | Jul 13 08:37:21 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-cf975406-fce3-482c-96eb-7420924efe4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760137643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_rand_reset.2760137643 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.3069304187 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 790156870 ps |
| CPU time | 304.48 seconds |
| Started | Jul 13 08:28:27 PM PDT 24 |
| Finished | Jul 13 08:33:32 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-af9be866-7ccb-481e-93c9-3aa1229398b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069304187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.3069304187 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.3240558334 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 1455242476 ps |
| CPU time | 67.65 seconds |
| Started | Jul 13 08:28:16 PM PDT 24 |
| Finished | Jul 13 08:29:24 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-c7959816-774c-4035-aa59-d843b6fe907a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240558334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3240558334 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.2999876891 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 3820108110 ps |
| CPU time | 335.6 seconds |
| Started | Jul 13 08:16:41 PM PDT 24 |
| Finished | Jul 13 08:22:16 PM PDT 24 |
| Peak memory | 596976 kb |
| Host | smart-2fce398a-fd6e-4a36-b475-0ee9294e9119 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999876891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.2999876891 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.318106108 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 30982002086 ps |
| CPU time | 3660.97 seconds |
| Started | Jul 13 08:16:13 PM PDT 24 |
| Finished | Jul 13 09:17:15 PM PDT 24 |
| Peak memory | 593304 kb |
| Host | smart-cb3686bf-3905-4717-b140-f2496cb5bcd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318106108 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 5.chip_same_csr_outstanding.318106108 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.2668245390 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 4014239840 ps |
| CPU time | 308.11 seconds |
| Started | Jul 13 08:16:10 PM PDT 24 |
| Finished | Jul 13 08:21:18 PM PDT 24 |
| Peak memory | 599868 kb |
| Host | smart-0e0b209e-888e-4c1b-b9d6-05e1c4918d53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668245390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.2668245390 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.243188455 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 788810208 ps |
| CPU time | 66.43 seconds |
| Started | Jul 13 08:16:20 PM PDT 24 |
| Finished | Jul 13 08:17:27 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-fdc5cf32-13b0-4c0e-894f-b0baca60e13f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243188455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.243188455 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.168903812 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 79652804063 ps |
| CPU time | 1483.21 seconds |
| Started | Jul 13 08:16:34 PM PDT 24 |
| Finished | Jul 13 08:41:18 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-71ac0249-ae3e-4058-8fb3-a2faf7c98548 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168903812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_de vice_slow_rsp.168903812 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.870892485 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 93427157 ps |
| CPU time | 12.99 seconds |
| Started | Jul 13 08:16:35 PM PDT 24 |
| Finished | Jul 13 08:16:48 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-85a417a0-fed0-406a-9ac1-31a86ab2a539 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870892485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr. 870892485 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.1513239150 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 1011893810 ps |
| CPU time | 41.31 seconds |
| Started | Jul 13 08:16:30 PM PDT 24 |
| Finished | Jul 13 08:17:12 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-d0a189e0-ed9f-452f-ae28-ae86e51aec5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513239150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1513239150 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.2510212869 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 127786859 ps |
| CPU time | 16.73 seconds |
| Started | Jul 13 08:16:21 PM PDT 24 |
| Finished | Jul 13 08:16:38 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-805eb49c-bcce-4413-b5ff-bb0b8754af53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510212869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.2510212869 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.3860229241 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 5639005112 ps |
| CPU time | 61 seconds |
| Started | Jul 13 08:16:18 PM PDT 24 |
| Finished | Jul 13 08:17:20 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-12890d14-2692-4dd3-b6a6-61e801594a58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860229241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3860229241 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.2037986693 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 67961853089 ps |
| CPU time | 1313.5 seconds |
| Started | Jul 13 08:16:22 PM PDT 24 |
| Finished | Jul 13 08:38:16 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-874206b7-2439-4cf9-8fad-a70faa182699 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037986693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2037986693 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.3110790880 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 421073620 ps |
| CPU time | 38.8 seconds |
| Started | Jul 13 08:16:20 PM PDT 24 |
| Finished | Jul 13 08:16:59 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-f6623077-9462-47c0-9544-e326ad6e515c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110790880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.3110790880 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.1978438606 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 1875251961 ps |
| CPU time | 62.94 seconds |
| Started | Jul 13 08:16:31 PM PDT 24 |
| Finished | Jul 13 08:17:35 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-8eac3bc2-7726-44cb-8e3f-74ad255bde2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978438606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1978438606 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.271018427 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 205688337 ps |
| CPU time | 10.43 seconds |
| Started | Jul 13 08:16:20 PM PDT 24 |
| Finished | Jul 13 08:16:31 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-a3b0e430-d0fa-4936-b386-88989e02aa02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271018427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.271018427 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.4260049048 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 7291917822 ps |
| CPU time | 87.31 seconds |
| Started | Jul 13 08:16:20 PM PDT 24 |
| Finished | Jul 13 08:17:48 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-2f2f2b7a-b8a2-441d-8245-4c5eebb25bd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260049048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.4260049048 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.1428816917 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 6085053305 ps |
| CPU time | 113.6 seconds |
| Started | Jul 13 08:16:20 PM PDT 24 |
| Finished | Jul 13 08:18:14 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-b795b8bd-b0ab-4679-aee4-4af5f1982ab3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428816917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1428816917 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.200828005 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 41570764 ps |
| CPU time | 6.72 seconds |
| Started | Jul 13 08:16:24 PM PDT 24 |
| Finished | Jul 13 08:16:31 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-02b6d10e-4b03-41f6-b125-edecbd9ff0c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200828005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays. 200828005 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.1975535478 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 9369582651 ps |
| CPU time | 352.29 seconds |
| Started | Jul 13 08:16:30 PM PDT 24 |
| Finished | Jul 13 08:22:23 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-3906f63d-fa26-421b-9e45-064fea9e529f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975535478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1975535478 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.2390610439 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 710519107 ps |
| CPU time | 61.84 seconds |
| Started | Jul 13 08:16:39 PM PDT 24 |
| Finished | Jul 13 08:17:41 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-20ebd54e-1bd3-49a0-9383-ed3395556568 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390610439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2390610439 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.739935702 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 129682707 ps |
| CPU time | 126.24 seconds |
| Started | Jul 13 08:16:39 PM PDT 24 |
| Finished | Jul 13 08:18:46 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-f98c6086-1c14-439b-b81f-16d58449b666 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739935702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_w ith_rand_reset.739935702 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.3857389477 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 2789595284 ps |
| CPU time | 137.6 seconds |
| Started | Jul 13 08:16:39 PM PDT 24 |
| Finished | Jul 13 08:18:57 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-9bf039e4-e311-485b-838f-27080d496f97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857389477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.3857389477 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.1615441530 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 187479273 ps |
| CPU time | 25.77 seconds |
| Started | Jul 13 08:16:32 PM PDT 24 |
| Finished | Jul 13 08:16:58 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-961b91c5-e505-4d52-86e6-a469dae733ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615441530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1615441530 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.3279113546 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 468367568 ps |
| CPU time | 30.27 seconds |
| Started | Jul 13 08:28:24 PM PDT 24 |
| Finished | Jul 13 08:28:56 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-f05125b2-a44d-4958-b159-45ee553b0dea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279113546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .3279113546 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.2466442583 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 131498205397 ps |
| CPU time | 2406.1 seconds |
| Started | Jul 13 08:28:24 PM PDT 24 |
| Finished | Jul 13 09:08:33 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-45d655d7-5d8a-4d3d-902e-d03bf7a5bafe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466442583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.2466442583 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.1472850239 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 153158388 ps |
| CPU time | 19.49 seconds |
| Started | Jul 13 08:28:27 PM PDT 24 |
| Finished | Jul 13 08:28:47 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-6a9c58f5-de49-469f-ab96-82f00f163982 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472850239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add r.1472850239 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.2797857904 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 2592111622 ps |
| CPU time | 100.1 seconds |
| Started | Jul 13 08:28:23 PM PDT 24 |
| Finished | Jul 13 08:30:04 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-724e0533-7c1a-4107-bf39-79fb8d24f477 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797857904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.2797857904 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.1344950282 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 1353752543 ps |
| CPU time | 53.87 seconds |
| Started | Jul 13 08:28:25 PM PDT 24 |
| Finished | Jul 13 08:29:20 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-c579c953-6f05-4e4e-a6d8-897749b6d205 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344950282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.1344950282 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.2179462167 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 6242094707 ps |
| CPU time | 70.45 seconds |
| Started | Jul 13 08:28:23 PM PDT 24 |
| Finished | Jul 13 08:29:35 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-fab34ac5-e7b3-476e-a352-fea05a12d7bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179462167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.2179462167 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.1922340025 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 69141088569 ps |
| CPU time | 1248.32 seconds |
| Started | Jul 13 08:28:22 PM PDT 24 |
| Finished | Jul 13 08:49:11 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-a0894dc5-3acb-47a2-86a3-922df1fc9403 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922340025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.1922340025 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.326000223 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 389704795 ps |
| CPU time | 38.88 seconds |
| Started | Jul 13 08:28:23 PM PDT 24 |
| Finished | Jul 13 08:29:03 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-886db32e-34fe-4a2f-b4de-adf03100eb59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326000223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_dela ys.326000223 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.1222877595 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 1107427326 ps |
| CPU time | 35.85 seconds |
| Started | Jul 13 08:28:23 PM PDT 24 |
| Finished | Jul 13 08:28:59 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-0dc2fc4a-dbd2-4215-9940-9d77f8e3beb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222877595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.1222877595 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.428113562 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 50672776 ps |
| CPU time | 7.41 seconds |
| Started | Jul 13 08:28:25 PM PDT 24 |
| Finished | Jul 13 08:28:34 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-30364400-7248-4dc1-8c42-b2775cba00f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428113562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.428113562 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.408033593 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 6633818007 ps |
| CPU time | 76.96 seconds |
| Started | Jul 13 08:28:24 PM PDT 24 |
| Finished | Jul 13 08:29:43 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-bea2068b-b3fd-44b0-9ed9-a255e1801edc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408033593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.408033593 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.1311726178 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 5338773447 ps |
| CPU time | 96.17 seconds |
| Started | Jul 13 08:28:25 PM PDT 24 |
| Finished | Jul 13 08:30:03 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-e144ee1a-3489-48c4-a7e3-e6b7d3d531bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311726178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.1311726178 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.2158553023 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 44905741 ps |
| CPU time | 7.07 seconds |
| Started | Jul 13 08:28:22 PM PDT 24 |
| Finished | Jul 13 08:28:29 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-4ae0d3fc-cc96-47a2-b011-3776732f663c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158553023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay s.2158553023 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.175418545 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 3286233420 ps |
| CPU time | 297.18 seconds |
| Started | Jul 13 08:28:32 PM PDT 24 |
| Finished | Jul 13 08:33:29 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-a5273e32-1a00-4935-a494-4875381c0737 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175418545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.175418545 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.2024263818 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 7143049420 ps |
| CPU time | 257.4 seconds |
| Started | Jul 13 08:28:35 PM PDT 24 |
| Finished | Jul 13 08:32:53 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-877c0415-4731-4771-91fd-0a6a2dfeda45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024263818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.2024263818 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.2857246024 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 1362245743 ps |
| CPU time | 310.3 seconds |
| Started | Jul 13 08:28:35 PM PDT 24 |
| Finished | Jul 13 08:33:45 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-1d4a41ec-7ea2-415d-a1c2-00f523766840 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857246024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.2857246024 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.2848191019 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 11183915441 ps |
| CPU time | 664.8 seconds |
| Started | Jul 13 08:28:31 PM PDT 24 |
| Finished | Jul 13 08:39:36 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-f83cff39-6c47-4494-87d8-eb058da55136 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848191019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al l_with_reset_error.2848191019 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.1977087213 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 288907028 ps |
| CPU time | 35.1 seconds |
| Started | Jul 13 08:28:22 PM PDT 24 |
| Finished | Jul 13 08:28:58 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-148cfd44-6a35-420d-8c00-07f544d63b16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977087213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.1977087213 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.2699054290 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 579667333 ps |
| CPU time | 27.94 seconds |
| Started | Jul 13 08:28:34 PM PDT 24 |
| Finished | Jul 13 08:29:03 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-a5a50dba-8118-4ad1-9f85-ab6ce44bd471 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699054290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .2699054290 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.1823375404 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 15600146021 ps |
| CPU time | 300.47 seconds |
| Started | Jul 13 08:28:43 PM PDT 24 |
| Finished | Jul 13 08:33:45 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-0d40fc75-7229-454a-9910-4d30f85ef64f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823375404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_ device_slow_rsp.1823375404 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.3757183082 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 314914221 ps |
| CPU time | 32.87 seconds |
| Started | Jul 13 08:28:43 PM PDT 24 |
| Finished | Jul 13 08:29:17 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-ec1f686f-6bdc-4d06-972d-078923e61389 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757183082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.3757183082 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.4026857808 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 2532756054 ps |
| CPU time | 92.18 seconds |
| Started | Jul 13 08:28:45 PM PDT 24 |
| Finished | Jul 13 08:30:17 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-c8f9caa4-9766-4bb9-9ccf-446f3793c70c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026857808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.4026857808 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.96043629 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 750996352 ps |
| CPU time | 31.49 seconds |
| Started | Jul 13 08:28:33 PM PDT 24 |
| Finished | Jul 13 08:29:05 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-ea6e62c8-1670-485e-85f3-db0224e0bcf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96043629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.96043629 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.2323631750 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 71498125995 ps |
| CPU time | 809.78 seconds |
| Started | Jul 13 08:28:37 PM PDT 24 |
| Finished | Jul 13 08:42:07 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-b845cff3-b631-446b-944c-c2db608fafdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323631750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.2323631750 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.1410643258 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 50159818199 ps |
| CPU time | 903.82 seconds |
| Started | Jul 13 08:28:34 PM PDT 24 |
| Finished | Jul 13 08:43:38 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-d697aeec-24ed-4f87-bc90-e057de1a7566 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410643258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.1410643258 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.1456518178 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 245176270 ps |
| CPU time | 24.14 seconds |
| Started | Jul 13 08:28:34 PM PDT 24 |
| Finished | Jul 13 08:28:58 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-2178abd1-8a81-48d8-bfc7-ba05b433e60b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456518178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del ays.1456518178 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.2856106050 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 1438907934 ps |
| CPU time | 47.96 seconds |
| Started | Jul 13 08:28:45 PM PDT 24 |
| Finished | Jul 13 08:29:34 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-546bbea3-2bce-4db9-90b3-10417699a6a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856106050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.2856106050 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.4175881188 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 48904290 ps |
| CPU time | 6.77 seconds |
| Started | Jul 13 08:28:33 PM PDT 24 |
| Finished | Jul 13 08:28:40 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-28c6932d-f58b-48e7-a3a0-ec12cacc9bfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175881188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.4175881188 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.876455283 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 8432661504 ps |
| CPU time | 99.34 seconds |
| Started | Jul 13 08:28:34 PM PDT 24 |
| Finished | Jul 13 08:30:14 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-0cd901c9-24c7-46c4-b6b7-a94dc2244d25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876455283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.876455283 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.3301821950 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 6334122528 ps |
| CPU time | 116.89 seconds |
| Started | Jul 13 08:28:33 PM PDT 24 |
| Finished | Jul 13 08:30:31 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-3e24b0ab-8f38-4f89-bd61-974f6e802422 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301821950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.3301821950 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.1591445538 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 37494466 ps |
| CPU time | 6.39 seconds |
| Started | Jul 13 08:28:34 PM PDT 24 |
| Finished | Jul 13 08:28:41 PM PDT 24 |
| Peak memory | 573996 kb |
| Host | smart-772b656a-3e8b-4b00-90c7-b7f4ec2b14d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591445538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay s.1591445538 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.2863267610 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 3460187830 ps |
| CPU time | 300.53 seconds |
| Started | Jul 13 08:28:46 PM PDT 24 |
| Finished | Jul 13 08:33:47 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-38540426-82d0-4582-a1a3-7ecee9e4b72a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863267610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.2863267610 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.1587990564 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 2783714302 ps |
| CPU time | 357.98 seconds |
| Started | Jul 13 08:28:46 PM PDT 24 |
| Finished | Jul 13 08:34:45 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-dea5071b-7291-4fa7-89f9-d029c9907a39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587990564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.1587990564 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1238029372 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 17120920304 ps |
| CPU time | 838.78 seconds |
| Started | Jul 13 08:28:45 PM PDT 24 |
| Finished | Jul 13 08:42:45 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-72652ba3-6f37-4b05-b90a-ac69c384a7b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238029372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al l_with_reset_error.1238029372 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.309411794 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 115907815 ps |
| CPU time | 17.26 seconds |
| Started | Jul 13 08:28:46 PM PDT 24 |
| Finished | Jul 13 08:29:04 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-8c148edb-fb86-4524-bb81-f47c044cbb2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309411794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.309411794 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.1644850774 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 3350054868 ps |
| CPU time | 147.46 seconds |
| Started | Jul 13 08:28:45 PM PDT 24 |
| Finished | Jul 13 08:31:13 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-07490d47-2e47-4ed5-a8fd-a2739ed69556 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644850774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device .1644850774 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.2518874127 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 110340656287 ps |
| CPU time | 2005.95 seconds |
| Started | Jul 13 08:28:46 PM PDT 24 |
| Finished | Jul 13 09:02:13 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-8980dda9-e98e-4e14-9761-e7795a6d773f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518874127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.2518874127 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.3049990815 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 450262939 ps |
| CPU time | 19.49 seconds |
| Started | Jul 13 08:28:43 PM PDT 24 |
| Finished | Jul 13 08:29:03 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-b7cdcf9c-707e-4143-918c-8ba2c48997eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049990815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.3049990815 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.1307560642 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 2238136458 ps |
| CPU time | 92.53 seconds |
| Started | Jul 13 08:28:43 PM PDT 24 |
| Finished | Jul 13 08:30:16 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-4481e012-96c7-4fb5-b148-1543b6d40c64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307560642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.1307560642 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.2646945429 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 33953570 ps |
| CPU time | 7.06 seconds |
| Started | Jul 13 08:28:44 PM PDT 24 |
| Finished | Jul 13 08:28:52 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-431187a4-4790-4ed0-a20c-ce2d09963c2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646945429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.2646945429 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.2198826764 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 74652663240 ps |
| CPU time | 842.84 seconds |
| Started | Jul 13 08:28:46 PM PDT 24 |
| Finished | Jul 13 08:42:49 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-69db3254-5806-48af-a0ce-df7862454efa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198826764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.2198826764 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.170429393 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 35553386258 ps |
| CPU time | 655.43 seconds |
| Started | Jul 13 08:28:47 PM PDT 24 |
| Finished | Jul 13 08:39:43 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-94de378b-fa89-420a-b5a0-374f4d57ba57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170429393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.170429393 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.3927566624 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 352491780 ps |
| CPU time | 36.38 seconds |
| Started | Jul 13 08:28:44 PM PDT 24 |
| Finished | Jul 13 08:29:21 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-72b7811d-8ead-4d12-90f6-9c8993f59459 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927566624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del ays.3927566624 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.2365440736 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 377732815 ps |
| CPU time | 31.47 seconds |
| Started | Jul 13 08:28:49 PM PDT 24 |
| Finished | Jul 13 08:29:21 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-276b687a-005d-468c-84f0-6c000f02b43a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365440736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.2365440736 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.3132272680 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 50436450 ps |
| CPU time | 6.61 seconds |
| Started | Jul 13 08:28:43 PM PDT 24 |
| Finished | Jul 13 08:28:50 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-dfb1bbd7-7776-4c7c-b6b1-01501db4e5c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132272680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.3132272680 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.2921114223 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 8535232203 ps |
| CPU time | 98.27 seconds |
| Started | Jul 13 08:28:49 PM PDT 24 |
| Finished | Jul 13 08:30:27 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-bd33c57f-641b-477c-acbf-f0acfeba80dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921114223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.2921114223 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.398772407 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 4625529859 ps |
| CPU time | 86.13 seconds |
| Started | Jul 13 08:28:48 PM PDT 24 |
| Finished | Jul 13 08:30:14 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-6f4b5c70-4842-43c9-8cca-b4f6604e88a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398772407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.398772407 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.49201325 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 44550020 ps |
| CPU time | 6.9 seconds |
| Started | Jul 13 08:28:46 PM PDT 24 |
| Finished | Jul 13 08:28:53 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-9659da88-c5b5-45ea-a541-9f04f6c563ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49201325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delays.49201325 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.3914273022 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 679719585 ps |
| CPU time | 79.44 seconds |
| Started | Jul 13 08:28:44 PM PDT 24 |
| Finished | Jul 13 08:30:04 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-b533cac0-a076-416a-bfce-6bba9d6a0aef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914273022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.3914273022 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.2089964455 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 1786816166 ps |
| CPU time | 122.71 seconds |
| Started | Jul 13 08:28:46 PM PDT 24 |
| Finished | Jul 13 08:30:49 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-9f1d6335-189a-4db4-afbf-94f5cb0a6861 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089964455 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.2089964455 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.1777299989 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 4117502852 ps |
| CPU time | 569.92 seconds |
| Started | Jul 13 08:28:46 PM PDT 24 |
| Finished | Jul 13 08:38:17 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-c313074d-52a5-46e1-80ca-7a6d5f2cc824 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777299989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all _with_rand_reset.1777299989 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.1810730658 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 13031439745 ps |
| CPU time | 637.4 seconds |
| Started | Jul 13 08:28:54 PM PDT 24 |
| Finished | Jul 13 08:39:33 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-bcf72e25-77d7-4063-9e62-57b50f480b22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810730658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.1810730658 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.223540681 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 169135207 ps |
| CPU time | 23.43 seconds |
| Started | Jul 13 08:28:44 PM PDT 24 |
| Finished | Jul 13 08:29:08 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-b3941642-7adc-4f17-b8a1-d29cdf0fafb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223540681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.223540681 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.3168952523 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 496993561 ps |
| CPU time | 37.59 seconds |
| Started | Jul 13 08:28:55 PM PDT 24 |
| Finished | Jul 13 08:29:34 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-5fbf84c3-81aa-48d6-ac36-9828d0f8e48e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168952523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .3168952523 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.1295784842 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 116502184446 ps |
| CPU time | 2105.84 seconds |
| Started | Jul 13 08:28:53 PM PDT 24 |
| Finished | Jul 13 09:04:00 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-2ca90089-9d36-42e7-942f-f539523034d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295784842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.1295784842 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.3349419442 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 32473461 ps |
| CPU time | 6.16 seconds |
| Started | Jul 13 08:28:56 PM PDT 24 |
| Finished | Jul 13 08:29:02 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-5d57b63e-d38d-41d3-8d56-7ffc4292cea9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349419442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.3349419442 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.4041359320 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 1383187007 ps |
| CPU time | 49.46 seconds |
| Started | Jul 13 08:28:55 PM PDT 24 |
| Finished | Jul 13 08:29:45 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-279e01fe-98e8-434b-bf80-27fe6a64c5fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041359320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.4041359320 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.767582079 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 372686492 ps |
| CPU time | 37.84 seconds |
| Started | Jul 13 08:28:53 PM PDT 24 |
| Finished | Jul 13 08:29:32 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-e25b9e2f-8e8b-4b8c-b6e1-cdc5f9fcdc15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767582079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.767582079 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.2071296845 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 54971635581 ps |
| CPU time | 612.75 seconds |
| Started | Jul 13 08:28:55 PM PDT 24 |
| Finished | Jul 13 08:39:09 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-73f7f1d9-d2cb-4693-84dc-2de0fb99ea4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071296845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.2071296845 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.2467463366 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 31583086725 ps |
| CPU time | 594.46 seconds |
| Started | Jul 13 08:28:52 PM PDT 24 |
| Finished | Jul 13 08:38:47 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-1efd5923-08eb-4e1f-a7ac-614320d206c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467463366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.2467463366 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.2131572379 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 186169861 ps |
| CPU time | 17.61 seconds |
| Started | Jul 13 08:28:55 PM PDT 24 |
| Finished | Jul 13 08:29:14 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-d3f8a828-a6c3-4de8-964c-dad2a94d102b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131572379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del ays.2131572379 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.2892990699 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 239726267 ps |
| CPU time | 21.41 seconds |
| Started | Jul 13 08:28:55 PM PDT 24 |
| Finished | Jul 13 08:29:18 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-7ce7f60b-1ea7-42a3-b855-2dbc5f16f20e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892990699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.2892990699 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.1809306071 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 42534869 ps |
| CPU time | 6.55 seconds |
| Started | Jul 13 08:28:54 PM PDT 24 |
| Finished | Jul 13 08:29:01 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-c72784d7-5ec3-41ce-926f-f8273883318c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809306071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.1809306071 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.1642842831 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 7219803311 ps |
| CPU time | 90 seconds |
| Started | Jul 13 08:28:52 PM PDT 24 |
| Finished | Jul 13 08:30:22 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-0c0e045f-b1bc-4007-a39c-b0fe43507068 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642842831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.1642842831 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.2521959391 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 3806805300 ps |
| CPU time | 70.23 seconds |
| Started | Jul 13 08:28:53 PM PDT 24 |
| Finished | Jul 13 08:30:04 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-882b25cb-9afe-4f3b-82c4-0ba1e3bb55d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521959391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.2521959391 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.2617561792 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 54014818 ps |
| CPU time | 7.55 seconds |
| Started | Jul 13 08:28:54 PM PDT 24 |
| Finished | Jul 13 08:29:02 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-3529e7a2-619e-4232-a53d-302b02bc81ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617561792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delay s.2617561792 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.3106911884 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 10269162194 ps |
| CPU time | 465.2 seconds |
| Started | Jul 13 08:28:53 PM PDT 24 |
| Finished | Jul 13 08:36:38 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-668592e1-36f6-43f8-a9c6-d006cd5d9979 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106911884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.3106911884 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.3612051438 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 2109041465 ps |
| CPU time | 202.38 seconds |
| Started | Jul 13 08:28:55 PM PDT 24 |
| Finished | Jul 13 08:32:18 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-731aa7ed-0747-4a7a-b7d0-a1dee50824ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612051438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.3612051438 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.4036401133 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 791104474 ps |
| CPU time | 116.96 seconds |
| Started | Jul 13 08:28:52 PM PDT 24 |
| Finished | Jul 13 08:30:50 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-b71a277e-0d66-4464-b330-f2c4f2d8b0fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036401133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.4036401133 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.4244953223 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 3063936057 ps |
| CPU time | 289.61 seconds |
| Started | Jul 13 08:28:57 PM PDT 24 |
| Finished | Jul 13 08:33:47 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-cee0df4b-2e1a-45ad-b9eb-5c3dd57cd175 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244953223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.4244953223 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.2095247925 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 1160748041 ps |
| CPU time | 54.26 seconds |
| Started | Jul 13 08:28:55 PM PDT 24 |
| Finished | Jul 13 08:29:50 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-4e4d44de-8da3-4fd2-8a0e-ec4191f252f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095247925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.2095247925 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.4268196849 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 651858840 ps |
| CPU time | 51.24 seconds |
| Started | Jul 13 08:29:06 PM PDT 24 |
| Finished | Jul 13 08:29:58 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-586d80ee-155b-4943-b340-32124facefe8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268196849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .4268196849 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.3178334651 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 79021528334 ps |
| CPU time | 1421.58 seconds |
| Started | Jul 13 08:29:05 PM PDT 24 |
| Finished | Jul 13 08:52:48 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-a9e192c9-835b-4b72-b9af-5728dacfeeb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178334651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_ device_slow_rsp.3178334651 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.3124346114 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 69737764 ps |
| CPU time | 6.76 seconds |
| Started | Jul 13 08:29:06 PM PDT 24 |
| Finished | Jul 13 08:29:14 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-40c40588-2cc1-4ff2-b857-2a8672ec167d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124346114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add r.3124346114 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.2066643401 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 676045450 ps |
| CPU time | 25.69 seconds |
| Started | Jul 13 08:29:05 PM PDT 24 |
| Finished | Jul 13 08:29:32 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-bb76a549-8752-4aa9-b9c2-ef20617f5eea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066643401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.2066643401 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.2202754722 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 978104905 ps |
| CPU time | 32.77 seconds |
| Started | Jul 13 08:29:07 PM PDT 24 |
| Finished | Jul 13 08:29:40 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-21f183b5-9bf3-45a1-add0-e118f6ac8503 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202754722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.2202754722 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.3369327180 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 97300014082 ps |
| CPU time | 1090.72 seconds |
| Started | Jul 13 08:29:06 PM PDT 24 |
| Finished | Jul 13 08:47:18 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-b33e1860-4749-45ba-b626-827134024e17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369327180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.3369327180 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.543405958 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 15295487326 ps |
| CPU time | 284.8 seconds |
| Started | Jul 13 08:29:05 PM PDT 24 |
| Finished | Jul 13 08:33:50 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-7cde675c-0a5d-4a4e-bec2-99017a723e31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543405958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.543405958 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.3803664252 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 167234088 ps |
| CPU time | 18.29 seconds |
| Started | Jul 13 08:29:08 PM PDT 24 |
| Finished | Jul 13 08:29:26 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-aa299cc9-a751-4917-9cf0-adcc820fcc52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803664252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del ays.3803664252 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.1131607020 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 478033542 ps |
| CPU time | 37.49 seconds |
| Started | Jul 13 08:29:10 PM PDT 24 |
| Finished | Jul 13 08:29:47 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-617985da-3677-4d95-9187-afadc3af1b61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131607020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.1131607020 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.2288914257 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 242110788 ps |
| CPU time | 9.07 seconds |
| Started | Jul 13 08:28:53 PM PDT 24 |
| Finished | Jul 13 08:29:03 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-f2cb22e3-3885-4a0f-a3b7-8fbf8637ecd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288914257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.2288914257 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.3836226289 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 8109242266 ps |
| CPU time | 91.47 seconds |
| Started | Jul 13 08:28:53 PM PDT 24 |
| Finished | Jul 13 08:30:25 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-320b3395-5982-4d97-948c-6d9e9a87183d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836226289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.3836226289 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.683657103 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 2607177038 ps |
| CPU time | 46.98 seconds |
| Started | Jul 13 08:28:57 PM PDT 24 |
| Finished | Jul 13 08:29:44 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-83d27b9e-868b-4d72-a6e6-03907dcab0b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683657103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.683657103 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1754858259 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 48314004 ps |
| CPU time | 6.76 seconds |
| Started | Jul 13 08:28:54 PM PDT 24 |
| Finished | Jul 13 08:29:02 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-46af8657-d984-443d-b39b-dd92bc22a75b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754858259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.1754858259 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.3750743282 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 15406513351 ps |
| CPU time | 671.71 seconds |
| Started | Jul 13 08:29:08 PM PDT 24 |
| Finished | Jul 13 08:40:20 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-84322b3c-91dc-4c1e-b47d-6910d966fa5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750743282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.3750743282 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.829614965 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 2342435426 ps |
| CPU time | 206.42 seconds |
| Started | Jul 13 08:29:06 PM PDT 24 |
| Finished | Jul 13 08:32:34 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-551953ca-2839-43dd-bb3d-2c26df7b3464 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829614965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.829614965 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.3123356994 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 8871839356 ps |
| CPU time | 585.26 seconds |
| Started | Jul 13 08:29:06 PM PDT 24 |
| Finished | Jul 13 08:38:53 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-abfe7ffe-fc0a-4093-b8f6-a07c0611d0af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123356994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_rand_reset.3123356994 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.3775211501 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 93431831 ps |
| CPU time | 19.13 seconds |
| Started | Jul 13 08:29:06 PM PDT 24 |
| Finished | Jul 13 08:29:26 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-91aae92d-5c61-47fe-a287-3688b6c31089 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775211501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.3775211501 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.3978080932 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 297088701 ps |
| CPU time | 17.19 seconds |
| Started | Jul 13 08:29:06 PM PDT 24 |
| Finished | Jul 13 08:29:25 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-8d415d44-8ce6-4e3f-b538-a995781cf007 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978080932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.3978080932 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.3179781295 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 2858791473 ps |
| CPU time | 121.97 seconds |
| Started | Jul 13 08:29:19 PM PDT 24 |
| Finished | Jul 13 08:31:21 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-02cf629a-ad66-4ff1-a5d9-934acc4e5273 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179781295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .3179781295 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.4238137734 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 121676770028 ps |
| CPU time | 2092.68 seconds |
| Started | Jul 13 08:29:16 PM PDT 24 |
| Finished | Jul 13 09:04:10 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-cf2ca9cf-f427-4a65-a5b4-56c8b7ea88e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238137734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.4238137734 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.4126896440 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 59985999 ps |
| CPU time | 5.75 seconds |
| Started | Jul 13 08:29:16 PM PDT 24 |
| Finished | Jul 13 08:29:22 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-2bdea89a-fa9e-4fd9-945e-23c648d8a138 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126896440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_add r.4126896440 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.907293186 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 1437308350 ps |
| CPU time | 54.31 seconds |
| Started | Jul 13 08:29:17 PM PDT 24 |
| Finished | Jul 13 08:30:12 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-6df0c541-5262-45be-b3db-95d58bb1449c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907293186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.907293186 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.3771424540 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 206812931 ps |
| CPU time | 12.38 seconds |
| Started | Jul 13 08:29:18 PM PDT 24 |
| Finished | Jul 13 08:29:31 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-02fedbe7-7e11-42db-998a-4f975f771abb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771424540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.3771424540 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.912801686 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 96802625938 ps |
| CPU time | 1073.9 seconds |
| Started | Jul 13 08:29:16 PM PDT 24 |
| Finished | Jul 13 08:47:10 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-293090a2-93ab-4ca8-9bc9-dfe31c7c9e29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912801686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.912801686 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.2349157260 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 4261090297 ps |
| CPU time | 78.4 seconds |
| Started | Jul 13 08:29:19 PM PDT 24 |
| Finished | Jul 13 08:30:38 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-f232f17e-92f9-462c-95fd-fa5f6543a194 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349157260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.2349157260 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.2988922286 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 585675928 ps |
| CPU time | 51.87 seconds |
| Started | Jul 13 08:29:21 PM PDT 24 |
| Finished | Jul 13 08:30:14 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-7d63566e-78a9-4fdc-9c60-23cf439c9a55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988922286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.2988922286 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.4808721 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 141395444 ps |
| CPU time | 13.72 seconds |
| Started | Jul 13 08:29:21 PM PDT 24 |
| Finished | Jul 13 08:29:36 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-739aba80-34be-483b-9aef-d678bfac1ab4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4808721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.4808721 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.1246706004 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 251848438 ps |
| CPU time | 11.25 seconds |
| Started | Jul 13 08:29:06 PM PDT 24 |
| Finished | Jul 13 08:29:19 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-d10d9ccf-d63f-46e1-9c4c-0dd33c37ab83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246706004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.1246706004 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.3610615912 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 5993523897 ps |
| CPU time | 68.58 seconds |
| Started | Jul 13 08:29:07 PM PDT 24 |
| Finished | Jul 13 08:30:16 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-08399b27-ed05-432b-8ccb-8bdb15b81df4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610615912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.3610615912 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.1762130658 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 5262945764 ps |
| CPU time | 98.07 seconds |
| Started | Jul 13 08:29:07 PM PDT 24 |
| Finished | Jul 13 08:30:46 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-3eac313d-a426-491f-b7e9-73ab44f3a9a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762130658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.1762130658 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.3686016358 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 44696806 ps |
| CPU time | 6.37 seconds |
| Started | Jul 13 08:29:07 PM PDT 24 |
| Finished | Jul 13 08:29:14 PM PDT 24 |
| Peak memory | 574012 kb |
| Host | smart-1b5aa167-85eb-459c-af0c-a0a23142d023 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686016358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay s.3686016358 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.185725887 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 2997938107 ps |
| CPU time | 277.85 seconds |
| Started | Jul 13 08:29:18 PM PDT 24 |
| Finished | Jul 13 08:33:57 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-bf5aa680-e285-48a6-9880-1ba8cf69001c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185725887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.185725887 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.3119252346 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 119224255 ps |
| CPU time | 67.94 seconds |
| Started | Jul 13 08:29:15 PM PDT 24 |
| Finished | Jul 13 08:30:24 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-01f6d287-13fb-4fb8-a82b-6308aa7603c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119252346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.3119252346 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.2041434695 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 2467759083 ps |
| CPU time | 289.53 seconds |
| Started | Jul 13 08:29:18 PM PDT 24 |
| Finished | Jul 13 08:34:08 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-9a7bbee3-ff1d-4bc5-be6f-90bbb4087462 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041434695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al l_with_reset_error.2041434695 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.3759899730 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 19866617 ps |
| CPU time | 5.8 seconds |
| Started | Jul 13 08:29:17 PM PDT 24 |
| Finished | Jul 13 08:29:23 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-57ccf1a9-03d9-4293-9ee1-3133f03bd642 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759899730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.3759899730 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.1520494179 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 741992870 ps |
| CPU time | 74.36 seconds |
| Started | Jul 13 08:29:29 PM PDT 24 |
| Finished | Jul 13 08:30:44 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-7047d51f-f0c8-4d53-bcb2-959391da5b2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520494179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .1520494179 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.3253956828 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 72516663113 ps |
| CPU time | 1339.7 seconds |
| Started | Jul 13 08:29:25 PM PDT 24 |
| Finished | Jul 13 08:51:47 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-639c692f-8dd9-40a9-92a5-87de75332994 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253956828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.3253956828 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.2751004770 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 192977999 ps |
| CPU time | 23.94 seconds |
| Started | Jul 13 08:29:26 PM PDT 24 |
| Finished | Jul 13 08:29:51 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-d5bee5ca-6d7f-491a-a19c-0a4e35999a61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751004770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.2751004770 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.2644313936 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 1980434734 ps |
| CPU time | 82.87 seconds |
| Started | Jul 13 08:29:34 PM PDT 24 |
| Finished | Jul 13 08:30:58 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-4c28be54-45e4-4d19-8df0-b8eb46c15991 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644313936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.2644313936 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.2934690323 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 1877856616 ps |
| CPU time | 81.1 seconds |
| Started | Jul 13 08:29:17 PM PDT 24 |
| Finished | Jul 13 08:30:39 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-1ae0f672-70ff-43ce-9a7e-3aae3fa0600c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934690323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.2934690323 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.1549991033 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 6316324182 ps |
| CPU time | 75.11 seconds |
| Started | Jul 13 08:29:25 PM PDT 24 |
| Finished | Jul 13 08:30:43 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-dddd2874-ba4c-434a-b1d9-a9d311ade655 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549991033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.1549991033 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.1539454011 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 56566021292 ps |
| CPU time | 1046.04 seconds |
| Started | Jul 13 08:29:29 PM PDT 24 |
| Finished | Jul 13 08:46:56 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-982665db-de56-4f12-8fc9-42b04d05ddfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539454011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.1539454011 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.3279350363 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 192544399 ps |
| CPU time | 19.81 seconds |
| Started | Jul 13 08:29:19 PM PDT 24 |
| Finished | Jul 13 08:29:39 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-4afa0912-7f48-498a-808c-314edebdcba8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279350363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.3279350363 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.3623039142 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 78815857 ps |
| CPU time | 9.71 seconds |
| Started | Jul 13 08:29:34 PM PDT 24 |
| Finished | Jul 13 08:29:45 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-f5d6e802-1b8a-47e9-9213-443877d2aa1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623039142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.3623039142 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.3332959090 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 218193532 ps |
| CPU time | 10.49 seconds |
| Started | Jul 13 08:29:16 PM PDT 24 |
| Finished | Jul 13 08:29:27 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-6858e9ed-5199-4e25-bf77-10ce3181b419 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332959090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.3332959090 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.3722682634 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 9899543399 ps |
| CPU time | 112.35 seconds |
| Started | Jul 13 08:29:16 PM PDT 24 |
| Finished | Jul 13 08:31:08 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-ff7f8d2d-9456-43c6-8ace-9709d7edfc08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722682634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.3722682634 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.1309742735 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 5498756814 ps |
| CPU time | 100.58 seconds |
| Started | Jul 13 08:29:16 PM PDT 24 |
| Finished | Jul 13 08:30:58 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-b5dd7cc0-6a9f-4f84-97ea-7dd18bef29fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309742735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.1309742735 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.1826938465 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 54289903 ps |
| CPU time | 7.28 seconds |
| Started | Jul 13 08:29:22 PM PDT 24 |
| Finished | Jul 13 08:29:30 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-9bd9b076-6768-49f1-bdb0-131224fa7858 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826938465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.1826938465 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.3487376606 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 2113662367 ps |
| CPU time | 176.95 seconds |
| Started | Jul 13 08:29:30 PM PDT 24 |
| Finished | Jul 13 08:32:27 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-3d8e3484-e86a-429d-a13c-4ec343ddbf43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487376606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.3487376606 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.265209884 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 3043112138 ps |
| CPU time | 260.32 seconds |
| Started | Jul 13 08:29:30 PM PDT 24 |
| Finished | Jul 13 08:33:51 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-63fc4ddc-7aef-4a85-acb3-9f09aa54f372 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265209884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.265209884 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.12817487 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 278188154 ps |
| CPU time | 105.73 seconds |
| Started | Jul 13 08:29:25 PM PDT 24 |
| Finished | Jul 13 08:31:13 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-d0709cbb-109b-4ede-8aff-4e8651ad9900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12817487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_w ith_rand_reset.12817487 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.817225644 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 11018092122 ps |
| CPU time | 597.55 seconds |
| Started | Jul 13 08:29:26 PM PDT 24 |
| Finished | Jul 13 08:39:25 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-59afe790-d861-49d5-ac7a-0b240fcd3871 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817225644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_reset_error.817225644 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.1112327206 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 1002691047 ps |
| CPU time | 44.54 seconds |
| Started | Jul 13 08:29:34 PM PDT 24 |
| Finished | Jul 13 08:30:20 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-4478d49a-93d5-46e9-9549-da10f9efeeb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112327206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.1112327206 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.3500561464 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 126374551 ps |
| CPU time | 9.85 seconds |
| Started | Jul 13 08:29:25 PM PDT 24 |
| Finished | Jul 13 08:29:37 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-12c86d0c-23bb-45be-8705-89aecb855c6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500561464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .3500561464 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.3084907290 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 99983838755 ps |
| CPU time | 1785.37 seconds |
| Started | Jul 13 08:29:45 PM PDT 24 |
| Finished | Jul 13 08:59:31 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-a2c5ab4b-b503-4cf5-a510-dda2629f7174 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084907290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_ device_slow_rsp.3084907290 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.92393513 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 42327916 ps |
| CPU time | 8.07 seconds |
| Started | Jul 13 08:29:33 PM PDT 24 |
| Finished | Jul 13 08:29:42 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-3bc2a4ae-5603-45b1-86b7-b222fd5ba0fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92393513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_addr.92393513 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.4189052268 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 100692861 ps |
| CPU time | 11 seconds |
| Started | Jul 13 08:29:33 PM PDT 24 |
| Finished | Jul 13 08:29:45 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-a4363832-1547-46f5-9ac6-db9f10aefac1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189052268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.4189052268 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.3019102304 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 304997598 ps |
| CPU time | 28.95 seconds |
| Started | Jul 13 08:29:26 PM PDT 24 |
| Finished | Jul 13 08:29:56 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-43f8a7f0-7754-4d77-9c9a-efee4588539b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019102304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.3019102304 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.2602666880 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 87724118589 ps |
| CPU time | 1013.23 seconds |
| Started | Jul 13 08:29:29 PM PDT 24 |
| Finished | Jul 13 08:46:23 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-5ed8dbd5-2e69-4679-bafd-8e13b5b8b21a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602666880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.2602666880 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.920573151 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 23617534318 ps |
| CPU time | 470.06 seconds |
| Started | Jul 13 08:29:29 PM PDT 24 |
| Finished | Jul 13 08:37:20 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-66a76265-0d6b-48da-a8e9-039feadf28ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920573151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.920573151 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.1621855090 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 365383084 ps |
| CPU time | 37.35 seconds |
| Started | Jul 13 08:29:29 PM PDT 24 |
| Finished | Jul 13 08:30:07 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-67004136-e5b2-4d45-8d01-3587ccd8010f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621855090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del ays.1621855090 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.622062522 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 421427178 ps |
| CPU time | 16.54 seconds |
| Started | Jul 13 08:29:37 PM PDT 24 |
| Finished | Jul 13 08:29:53 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-96197fbc-984a-4e2d-b64d-c7cf049bdfbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622062522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.622062522 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.387369122 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 44622276 ps |
| CPU time | 6.64 seconds |
| Started | Jul 13 08:29:25 PM PDT 24 |
| Finished | Jul 13 08:29:34 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-164ed5e7-d38b-4b73-8818-54ef3068a931 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387369122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.387369122 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.357198425 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 10104646925 ps |
| CPU time | 118.6 seconds |
| Started | Jul 13 08:29:25 PM PDT 24 |
| Finished | Jul 13 08:31:26 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-bb7ea04c-5d38-40ee-8387-f37a225db58a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357198425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.357198425 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.2386702273 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 4878043003 ps |
| CPU time | 91.12 seconds |
| Started | Jul 13 08:29:27 PM PDT 24 |
| Finished | Jul 13 08:30:59 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-c6170a49-348f-4d30-9284-5f24997971e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386702273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.2386702273 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.3920383805 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 56461616 ps |
| CPU time | 7.05 seconds |
| Started | Jul 13 08:29:26 PM PDT 24 |
| Finished | Jul 13 08:29:35 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-d7992495-6ccf-4910-b83b-aabf35cf04e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920383805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay s.3920383805 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.2054922578 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 14365917734 ps |
| CPU time | 546.4 seconds |
| Started | Jul 13 08:29:45 PM PDT 24 |
| Finished | Jul 13 08:38:52 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-79a2aec0-5514-40e4-9686-ccdf99f9a338 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054922578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.2054922578 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.3158652324 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 9480705910 ps |
| CPU time | 321.94 seconds |
| Started | Jul 13 08:29:41 PM PDT 24 |
| Finished | Jul 13 08:35:03 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-eca0dde4-df68-400f-a6d2-c3289686bdc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158652324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.3158652324 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.3738894511 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 428546416 ps |
| CPU time | 174.25 seconds |
| Started | Jul 13 08:29:45 PM PDT 24 |
| Finished | Jul 13 08:32:40 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-0cded1f5-0f00-475e-8ef0-162df7dc7a80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738894511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.3738894511 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.2211771404 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 658762069 ps |
| CPU time | 32.92 seconds |
| Started | Jul 13 08:29:35 PM PDT 24 |
| Finished | Jul 13 08:30:08 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-85bd5afe-d896-4039-8c2a-044d216fe8e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211771404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.2211771404 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.2687553790 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 466660360 ps |
| CPU time | 21.25 seconds |
| Started | Jul 13 08:29:37 PM PDT 24 |
| Finished | Jul 13 08:29:59 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-798f6e3b-904b-4cda-801f-0a3b72246f94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687553790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .2687553790 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3837578682 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 20826359230 ps |
| CPU time | 374.58 seconds |
| Started | Jul 13 08:29:45 PM PDT 24 |
| Finished | Jul 13 08:36:00 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-b75fccb0-4e50-4c3d-b0c2-316dbccc46e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837578682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.3837578682 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.4160963457 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 107748920 ps |
| CPU time | 14.83 seconds |
| Started | Jul 13 08:29:44 PM PDT 24 |
| Finished | Jul 13 08:29:59 PM PDT 24 |
| Peak memory | 575068 kb |
| Host | smart-9cec20e9-8a2d-439c-a815-8646aba31112 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160963457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.4160963457 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.1406075036 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 633916625 ps |
| CPU time | 48.16 seconds |
| Started | Jul 13 08:29:47 PM PDT 24 |
| Finished | Jul 13 08:30:36 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-ff234add-6653-4e06-9758-22c93ff6fd34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406075036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.1406075036 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.3034460869 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 407122711 ps |
| CPU time | 16.17 seconds |
| Started | Jul 13 08:29:46 PM PDT 24 |
| Finished | Jul 13 08:30:02 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-93ca19fa-2fa7-4489-9d35-f743c304de8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034460869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.3034460869 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.290350396 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 32343860282 ps |
| CPU time | 375.86 seconds |
| Started | Jul 13 08:29:41 PM PDT 24 |
| Finished | Jul 13 08:35:57 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-7a507659-3303-4f58-968d-0253af2dbefe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290350396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.290350396 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.865564428 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 42322513598 ps |
| CPU time | 773.24 seconds |
| Started | Jul 13 08:29:34 PM PDT 24 |
| Finished | Jul 13 08:42:28 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-de9c80bd-4301-43b7-a3ef-2506bc238759 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865564428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.865564428 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.3200870835 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 151059410 ps |
| CPU time | 17.43 seconds |
| Started | Jul 13 08:29:37 PM PDT 24 |
| Finished | Jul 13 08:29:55 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-a0395dbc-207d-4b10-be9e-e186b2698165 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200870835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del ays.3200870835 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.1904216347 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 319674194 ps |
| CPU time | 12.45 seconds |
| Started | Jul 13 08:29:48 PM PDT 24 |
| Finished | Jul 13 08:30:01 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-f669da39-56b5-414a-aeaa-82a65ad8320f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904216347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.1904216347 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.2846163783 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 161885563 ps |
| CPU time | 8.29 seconds |
| Started | Jul 13 08:29:36 PM PDT 24 |
| Finished | Jul 13 08:29:45 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-0a7c2866-ded9-4c77-abf1-6ff96eb9ed0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846163783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.2846163783 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.508151035 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 7614827318 ps |
| CPU time | 87.44 seconds |
| Started | Jul 13 08:29:36 PM PDT 24 |
| Finished | Jul 13 08:31:04 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-f5cd6a31-1a31-4883-b2a1-0979106ec926 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508151035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.508151035 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.2177220497 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 5989827801 ps |
| CPU time | 109.04 seconds |
| Started | Jul 13 08:29:44 PM PDT 24 |
| Finished | Jul 13 08:31:33 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-37550025-51b8-4542-92c8-73bf8391b662 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177220497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.2177220497 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.1885871835 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 48483750 ps |
| CPU time | 6.67 seconds |
| Started | Jul 13 08:29:41 PM PDT 24 |
| Finished | Jul 13 08:29:48 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-815b677c-d704-4255-9b01-9571b13288e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885871835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.1885871835 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.60416275 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 273198588 ps |
| CPU time | 36.01 seconds |
| Started | Jul 13 08:29:45 PM PDT 24 |
| Finished | Jul 13 08:30:21 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-35671fc4-5364-42ef-94ec-40fd2a4a7910 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60416275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.60416275 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.4084885914 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 13700698571 ps |
| CPU time | 593.66 seconds |
| Started | Jul 13 08:29:44 PM PDT 24 |
| Finished | Jul 13 08:39:38 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-621b491d-aaae-4897-8812-a4c7b3b87a42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084885914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.4084885914 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.3093403097 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 39320598 ps |
| CPU time | 23.79 seconds |
| Started | Jul 13 08:29:44 PM PDT 24 |
| Finished | Jul 13 08:30:09 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-acfe458b-8d70-4fa4-803a-724e78433055 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093403097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_rand_reset.3093403097 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.1440330079 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 4173279083 ps |
| CPU time | 350.02 seconds |
| Started | Jul 13 08:29:45 PM PDT 24 |
| Finished | Jul 13 08:35:36 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-a3421eb1-d792-4523-abe2-75efc01b0043 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440330079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.1440330079 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.2581446564 |
| Short name | T2906 |
| Test name | |
| Test status | |
| Simulation time | 197306364 ps |
| CPU time | 28 seconds |
| Started | Jul 13 08:29:45 PM PDT 24 |
| Finished | Jul 13 08:30:14 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-eff8038d-4812-49cb-9e9d-f4bcf45b433c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581446564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.2581446564 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.539602749 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 2328805434 ps |
| CPU time | 107.1 seconds |
| Started | Jul 13 08:29:54 PM PDT 24 |
| Finished | Jul 13 08:31:41 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-b805ab84-e159-45af-a167-7ef3dc97178c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539602749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device. 539602749 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.1569932936 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 89711980874 ps |
| CPU time | 1640.43 seconds |
| Started | Jul 13 08:29:54 PM PDT 24 |
| Finished | Jul 13 08:57:15 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-f5afea00-0fd4-4ff9-8cc5-ed3a6bbeaf7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569932936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_ device_slow_rsp.1569932936 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.4216780762 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 142742241 ps |
| CPU time | 17.57 seconds |
| Started | Jul 13 08:30:07 PM PDT 24 |
| Finished | Jul 13 08:30:26 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-9ba35a0e-3104-4af3-8dda-e0a949df0e7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216780762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.4216780762 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.760111529 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 502524259 ps |
| CPU time | 40.23 seconds |
| Started | Jul 13 08:29:54 PM PDT 24 |
| Finished | Jul 13 08:30:35 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-bc6025ee-d8bb-4164-b0e6-4b9b8f5bf952 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760111529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.760111529 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.773100548 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 1299610347 ps |
| CPU time | 51.91 seconds |
| Started | Jul 13 08:30:07 PM PDT 24 |
| Finished | Jul 13 08:31:00 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-d2fae902-56bc-4a81-be09-2308f534f1da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773100548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.773100548 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.899713244 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 36521473397 ps |
| CPU time | 400.4 seconds |
| Started | Jul 13 08:29:55 PM PDT 24 |
| Finished | Jul 13 08:36:36 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-3bb0009b-41ec-4d51-af84-d5bbf515ea82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899713244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.899713244 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.1084222702 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 20934280639 ps |
| CPU time | 388.9 seconds |
| Started | Jul 13 08:29:54 PM PDT 24 |
| Finished | Jul 13 08:36:23 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-1f6ed00f-fad8-4b21-8fed-a2279e0e7655 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084222702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.1084222702 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.269641026 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 329672243 ps |
| CPU time | 29.66 seconds |
| Started | Jul 13 08:29:57 PM PDT 24 |
| Finished | Jul 13 08:30:27 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-d6792e7b-0537-498b-861a-575ec7ef3a17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269641026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_dela ys.269641026 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.1764537444 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 71402680 ps |
| CPU time | 9.01 seconds |
| Started | Jul 13 08:30:06 PM PDT 24 |
| Finished | Jul 13 08:30:16 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-ee3ec99b-2bc5-410d-ba06-8ef43a24b68f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764537444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.1764537444 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.3467140271 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 175205646 ps |
| CPU time | 9.45 seconds |
| Started | Jul 13 08:29:49 PM PDT 24 |
| Finished | Jul 13 08:29:59 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-ce8d5d78-7c4e-4e6f-a5fb-38124e15cf47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467140271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.3467140271 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.3548270109 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 9301007540 ps |
| CPU time | 108.14 seconds |
| Started | Jul 13 08:29:52 PM PDT 24 |
| Finished | Jul 13 08:31:41 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-e49bdd5b-5403-4078-9bfd-9ce136472da6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548270109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.3548270109 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.2286091637 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 5015215668 ps |
| CPU time | 94.77 seconds |
| Started | Jul 13 08:30:06 PM PDT 24 |
| Finished | Jul 13 08:31:42 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-95cea1b7-edcd-4919-b686-a5a52817cae4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286091637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.2286091637 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.2914133683 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 56959335 ps |
| CPU time | 6.83 seconds |
| Started | Jul 13 08:29:49 PM PDT 24 |
| Finished | Jul 13 08:29:56 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-a6ddb83e-d022-42a2-9d31-1f2668a43585 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914133683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.2914133683 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.1758170817 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 5796630988 ps |
| CPU time | 233.19 seconds |
| Started | Jul 13 08:30:07 PM PDT 24 |
| Finished | Jul 13 08:34:01 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-3af9bd11-d8c9-40c2-8f04-3581776ada4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758170817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.1758170817 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.4123353293 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 2307459428 ps |
| CPU time | 233.91 seconds |
| Started | Jul 13 08:30:05 PM PDT 24 |
| Finished | Jul 13 08:33:59 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-b84fd3b2-4e2a-4a74-94c5-e349bdb4ec35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123353293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.4123353293 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.1431180174 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 4042983866 ps |
| CPU time | 224.03 seconds |
| Started | Jul 13 08:30:03 PM PDT 24 |
| Finished | Jul 13 08:33:48 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-190a31bb-b85e-4982-8539-1f50ffb948e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431180174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_rand_reset.1431180174 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.270617578 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 161553753 ps |
| CPU time | 48.02 seconds |
| Started | Jul 13 08:30:04 PM PDT 24 |
| Finished | Jul 13 08:30:53 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-a266cc1c-b5f7-4f6c-8ab6-423e5fd5c0f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270617578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_reset_error.270617578 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.3902415096 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 1002428122 ps |
| CPU time | 48.28 seconds |
| Started | Jul 13 08:29:59 PM PDT 24 |
| Finished | Jul 13 08:30:48 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-fd10aa4f-9c8d-4899-a6a1-9e03a6c02ff2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902415096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.3902415096 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.221582540 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 3558990032 ps |
| CPU time | 302.9 seconds |
| Started | Jul 13 08:17:17 PM PDT 24 |
| Finished | Jul 13 08:22:20 PM PDT 24 |
| Peak memory | 597132 kb |
| Host | smart-36e49e32-da59-49a7-804c-68863bf40c65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221582540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.221582540 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.3595432280 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 33583868066 ps |
| CPU time | 3692.46 seconds |
| Started | Jul 13 08:16:52 PM PDT 24 |
| Finished | Jul 13 09:18:26 PM PDT 24 |
| Peak memory | 593700 kb |
| Host | smart-baa881e1-bf8c-4239-915e-09b363bbd8a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595432280 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.3595432280 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.1261676659 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 3184826060 ps |
| CPU time | 165.87 seconds |
| Started | Jul 13 08:16:48 PM PDT 24 |
| Finished | Jul 13 08:19:35 PM PDT 24 |
| Peak memory | 603824 kb |
| Host | smart-100e1e08-c6a3-4aaf-bfaa-506a531ef7b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261676659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.1261676659 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.1233602004 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 2834666388 ps |
| CPU time | 159.19 seconds |
| Started | Jul 13 08:17:01 PM PDT 24 |
| Finished | Jul 13 08:19:41 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-28e75548-0e03-4596-be2e-b8cdf664e08a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233602004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device. 1233602004 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.809691555 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 74543883484 ps |
| CPU time | 1389.21 seconds |
| Started | Jul 13 08:16:58 PM PDT 24 |
| Finished | Jul 13 08:40:08 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-7a02d7c4-a0aa-4ace-b582-6d54e65abb66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809691555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_de vice_slow_rsp.809691555 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.4154732069 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 993946475 ps |
| CPU time | 44.52 seconds |
| Started | Jul 13 08:17:06 PM PDT 24 |
| Finished | Jul 13 08:17:51 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-dbc46ca7-b263-4e6e-9351-c1700f90e72d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154732069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .4154732069 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.307666849 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 1842209517 ps |
| CPU time | 66.34 seconds |
| Started | Jul 13 08:17:14 PM PDT 24 |
| Finished | Jul 13 08:18:21 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-8a3cfabb-a784-4f85-9a3a-f58bc6bad1d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307666849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.307666849 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.97300678 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 155109978 ps |
| CPU time | 9.97 seconds |
| Started | Jul 13 08:16:51 PM PDT 24 |
| Finished | Jul 13 08:17:01 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-8f5d5e09-07f7-443b-a1ec-8420af5f2d8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97300678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.97300678 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.1546588830 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 57181685027 ps |
| CPU time | 683.11 seconds |
| Started | Jul 13 08:16:53 PM PDT 24 |
| Finished | Jul 13 08:28:17 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-b357faca-3d72-4bc3-87f7-b885b66adabd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546588830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1546588830 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.2001653701 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 6793858171 ps |
| CPU time | 128.99 seconds |
| Started | Jul 13 08:17:03 PM PDT 24 |
| Finished | Jul 13 08:19:13 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-dca7305a-abf4-4d0e-9dc6-84390ba149bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001653701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2001653701 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.2675761377 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 411544643 ps |
| CPU time | 34.99 seconds |
| Started | Jul 13 08:16:50 PM PDT 24 |
| Finished | Jul 13 08:17:25 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-2495634d-c752-488c-a4ef-55f2983ae646 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675761377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.2675761377 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.2116435719 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 190666219 ps |
| CPU time | 16.02 seconds |
| Started | Jul 13 08:16:57 PM PDT 24 |
| Finished | Jul 13 08:17:13 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-16d8ce8e-4e7b-4b5d-9815-e8971ceba8bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116435719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2116435719 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.80997642 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 45790432 ps |
| CPU time | 7.27 seconds |
| Started | Jul 13 08:16:50 PM PDT 24 |
| Finished | Jul 13 08:16:58 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-0e9f18e1-4f1a-443d-8d8d-0d4dec213db8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80997642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.80997642 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.1654541674 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 7808235074 ps |
| CPU time | 91.18 seconds |
| Started | Jul 13 08:16:50 PM PDT 24 |
| Finished | Jul 13 08:18:22 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-7728dcab-a106-4ca4-a353-f44eec5138b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654541674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1654541674 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.856701054 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 5031120240 ps |
| CPU time | 89.28 seconds |
| Started | Jul 13 08:16:49 PM PDT 24 |
| Finished | Jul 13 08:18:19 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-f54577c2-bff3-4427-b85f-03eb8e5cb669 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856701054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.856701054 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.710998813 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 56481618 ps |
| CPU time | 7.84 seconds |
| Started | Jul 13 08:16:49 PM PDT 24 |
| Finished | Jul 13 08:16:57 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-f5fb4153-f13e-47b4-a4d0-1da368a6bbec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710998813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays. 710998813 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.3746594174 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 560464207 ps |
| CPU time | 49.95 seconds |
| Started | Jul 13 08:17:09 PM PDT 24 |
| Finished | Jul 13 08:17:59 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-f6acc871-a2e6-4866-9bca-9c23b2590e6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746594174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3746594174 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.450221110 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 10718161315 ps |
| CPU time | 371.11 seconds |
| Started | Jul 13 08:17:08 PM PDT 24 |
| Finished | Jul 13 08:23:19 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-fb5686b4-44e6-472f-8505-d5704a63fe23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450221110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.450221110 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3386998446 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 3752903517 ps |
| CPU time | 387.87 seconds |
| Started | Jul 13 08:17:16 PM PDT 24 |
| Finished | Jul 13 08:23:44 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-b63d626f-254b-4243-9d9b-95f6ab3380c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386998446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.3386998446 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.1388939736 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 1298767817 ps |
| CPU time | 61.13 seconds |
| Started | Jul 13 08:17:10 PM PDT 24 |
| Finished | Jul 13 08:18:12 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-7179353b-0a5d-4d27-ab1d-18bb6d1bc038 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388939736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1388939736 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.4250264518 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 616814245 ps |
| CPU time | 60.22 seconds |
| Started | Jul 13 08:30:12 PM PDT 24 |
| Finished | Jul 13 08:31:13 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-4d9b31a5-e762-4e64-bb84-d43a8c45cbd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250264518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .4250264518 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.1210450091 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 139609430156 ps |
| CPU time | 2474.56 seconds |
| Started | Jul 13 08:30:11 PM PDT 24 |
| Finished | Jul 13 09:11:26 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-5b0ed06a-9b26-4361-a9dd-7d2307c0d75e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210450091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_ device_slow_rsp.1210450091 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.2625453321 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 62593435 ps |
| CPU time | 9.33 seconds |
| Started | Jul 13 08:30:20 PM PDT 24 |
| Finished | Jul 13 08:30:29 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-3ac7bd2a-7afb-44ec-b1ce-7cc9a7e1080e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625453321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.2625453321 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.172579359 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 68973095 ps |
| CPU time | 7.65 seconds |
| Started | Jul 13 08:30:13 PM PDT 24 |
| Finished | Jul 13 08:30:22 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-16c5fc73-2aef-4872-9657-b98a0c5f726a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172579359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.172579359 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.2984265540 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 2345240402 ps |
| CPU time | 102.45 seconds |
| Started | Jul 13 08:30:03 PM PDT 24 |
| Finished | Jul 13 08:31:46 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-1fa5b374-8472-4fa9-9bfa-b2051abae8ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984265540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.2984265540 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.3717621024 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 56101425260 ps |
| CPU time | 617.16 seconds |
| Started | Jul 13 08:30:12 PM PDT 24 |
| Finished | Jul 13 08:40:30 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-6d3ce7dc-3100-477d-b1df-b4c3ffc1dad4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717621024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.3717621024 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.1684059531 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 6382594249 ps |
| CPU time | 118.3 seconds |
| Started | Jul 13 08:30:20 PM PDT 24 |
| Finished | Jul 13 08:32:18 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-d2b478cf-aad1-4f7a-8a1d-1953afd75b61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684059531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.1684059531 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.724247701 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 68073331 ps |
| CPU time | 9.58 seconds |
| Started | Jul 13 08:30:02 PM PDT 24 |
| Finished | Jul 13 08:30:13 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-b85875f5-19da-46b0-8845-03ae23a21d91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724247701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_dela ys.724247701 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.2700255050 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 2262931555 ps |
| CPU time | 75.09 seconds |
| Started | Jul 13 08:30:11 PM PDT 24 |
| Finished | Jul 13 08:31:27 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-a89a8683-d739-42c2-955b-7992790ca90f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700255050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.2700255050 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.2628289810 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 221247436 ps |
| CPU time | 9.85 seconds |
| Started | Jul 13 08:30:06 PM PDT 24 |
| Finished | Jul 13 08:30:16 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-d5890403-684b-4d82-bedb-eb56425c3b1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628289810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.2628289810 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.4030091634 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 5134424542 ps |
| CPU time | 60.77 seconds |
| Started | Jul 13 08:30:04 PM PDT 24 |
| Finished | Jul 13 08:31:06 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-3ff40122-01b7-47d5-b5d3-47c62cf63447 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030091634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.4030091634 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.2403606728 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 6078048867 ps |
| CPU time | 106.65 seconds |
| Started | Jul 13 08:30:04 PM PDT 24 |
| Finished | Jul 13 08:31:52 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-6a591f00-29dc-4bab-b123-293ab18dea11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403606728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.2403606728 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.1863216318 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 39778611 ps |
| CPU time | 5.93 seconds |
| Started | Jul 13 08:30:06 PM PDT 24 |
| Finished | Jul 13 08:30:12 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-d9f8ea62-216b-4264-b255-b4049ea4e628 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863216318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.1863216318 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.2811874689 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 3100442574 ps |
| CPU time | 334.71 seconds |
| Started | Jul 13 08:30:13 PM PDT 24 |
| Finished | Jul 13 08:35:49 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-3747941f-dcb8-467c-866a-a80ed5a9b4e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811874689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.2811874689 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.2666645569 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 10058642103 ps |
| CPU time | 434.2 seconds |
| Started | Jul 13 08:30:12 PM PDT 24 |
| Finished | Jul 13 08:37:27 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-59caf96b-5442-4489-8583-f555c51d515d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666645569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.2666645569 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.196217330 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 638229613 ps |
| CPU time | 95.71 seconds |
| Started | Jul 13 08:30:19 PM PDT 24 |
| Finished | Jul 13 08:31:55 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-64b251d5-3248-4910-b9a8-99a6cc202313 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196217330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_ with_rand_reset.196217330 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.35489616 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 3409765659 ps |
| CPU time | 403.65 seconds |
| Started | Jul 13 08:30:13 PM PDT 24 |
| Finished | Jul 13 08:36:58 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-860a0ae6-a068-4c8f-9cac-17bc742eefd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35489616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_ with_reset_error.35489616 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.3496251789 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 666833115 ps |
| CPU time | 28.1 seconds |
| Started | Jul 13 08:30:13 PM PDT 24 |
| Finished | Jul 13 08:30:42 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-97478572-7eb1-4b5d-aa06-0fb6eeef331d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496251789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.3496251789 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.3968558168 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 2947079485 ps |
| CPU time | 119.15 seconds |
| Started | Jul 13 08:30:14 PM PDT 24 |
| Finished | Jul 13 08:32:14 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-beef45bf-f987-4ad0-b53c-558e21411797 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968558168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device .3968558168 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.3876985205 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 11404030063 ps |
| CPU time | 215.65 seconds |
| Started | Jul 13 08:30:15 PM PDT 24 |
| Finished | Jul 13 08:33:51 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-88886b27-8b90-4483-b23c-d8d49762f4a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876985205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_ device_slow_rsp.3876985205 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.822535315 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 35260268 ps |
| CPU time | 6.93 seconds |
| Started | Jul 13 08:30:23 PM PDT 24 |
| Finished | Jul 13 08:30:30 PM PDT 24 |
| Peak memory | 574036 kb |
| Host | smart-103cbc5c-7dc0-4164-b221-300f1e608f8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822535315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_addr .822535315 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.1459244935 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 36294513 ps |
| CPU time | 6.49 seconds |
| Started | Jul 13 08:30:12 PM PDT 24 |
| Finished | Jul 13 08:30:19 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-d6d4b51e-4d66-4119-994d-b374d0ae2bf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459244935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.1459244935 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.2204266067 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 1392507842 ps |
| CPU time | 50.6 seconds |
| Started | Jul 13 08:30:13 PM PDT 24 |
| Finished | Jul 13 08:31:04 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-39e429fb-e684-4b5b-80a5-8f10984483b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204266067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.2204266067 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.1466931116 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 86906158457 ps |
| CPU time | 1007.68 seconds |
| Started | Jul 13 08:30:19 PM PDT 24 |
| Finished | Jul 13 08:47:08 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-6e32de54-1b7f-4e0e-a3b2-e5dec8ab8170 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466931116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.1466931116 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.2675570559 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 23256134100 ps |
| CPU time | 420.29 seconds |
| Started | Jul 13 08:30:11 PM PDT 24 |
| Finished | Jul 13 08:37:12 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-07bc46aa-8824-4035-adc5-22ef2be8b7bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675570559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.2675570559 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.325480277 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 525114609 ps |
| CPU time | 55.41 seconds |
| Started | Jul 13 08:30:12 PM PDT 24 |
| Finished | Jul 13 08:31:08 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-98aca6e5-620b-4ffb-88dc-fbefebfe64f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325480277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_dela ys.325480277 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.2489483097 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 72845994 ps |
| CPU time | 8.35 seconds |
| Started | Jul 13 08:30:12 PM PDT 24 |
| Finished | Jul 13 08:30:21 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-be2d43b0-6e62-4f84-91cb-0615900e8ce8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489483097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.2489483097 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.2344361221 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 45677203 ps |
| CPU time | 7.11 seconds |
| Started | Jul 13 08:30:11 PM PDT 24 |
| Finished | Jul 13 08:30:19 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-dd0d26a0-d28d-4e27-85ef-09b1aa09a158 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344361221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.2344361221 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.1596178726 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 10343185276 ps |
| CPU time | 118.15 seconds |
| Started | Jul 13 08:30:14 PM PDT 24 |
| Finished | Jul 13 08:32:13 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-cf2b489f-c181-40f2-b209-975439efb5df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596178726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.1596178726 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.1578711363 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 6203278817 ps |
| CPU time | 117.17 seconds |
| Started | Jul 13 08:30:12 PM PDT 24 |
| Finished | Jul 13 08:32:10 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-04568375-7696-4aba-8c0e-d7d7db5ea7d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578711363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.1578711363 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.2708363089 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 49198528 ps |
| CPU time | 7.2 seconds |
| Started | Jul 13 08:30:12 PM PDT 24 |
| Finished | Jul 13 08:30:21 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-749b79ff-38b8-4c58-aa7c-b6b490a8fe76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708363089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.2708363089 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.1599930904 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 3541708489 ps |
| CPU time | 126.54 seconds |
| Started | Jul 13 08:30:21 PM PDT 24 |
| Finished | Jul 13 08:32:28 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-6767b784-db3d-4591-82dd-918c8e682474 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599930904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.1599930904 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.2545393633 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 2231950705 ps |
| CPU time | 92.74 seconds |
| Started | Jul 13 08:30:23 PM PDT 24 |
| Finished | Jul 13 08:31:56 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-b646f5f6-3a4c-4382-ba57-deaf0c80c5b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545393633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.2545393633 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.737246576 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 1581420503 ps |
| CPU time | 206.18 seconds |
| Started | Jul 13 08:30:23 PM PDT 24 |
| Finished | Jul 13 08:33:50 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-a74b438e-4da1-4b19-8d66-c210cefaae5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737246576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_ with_rand_reset.737246576 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.3659762383 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 6802921389 ps |
| CPU time | 424.42 seconds |
| Started | Jul 13 08:30:22 PM PDT 24 |
| Finished | Jul 13 08:37:27 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-366fdd33-b816-4ae0-867d-81830d589c7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659762383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.3659762383 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.3154743161 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 258740188 ps |
| CPU time | 30.02 seconds |
| Started | Jul 13 08:30:12 PM PDT 24 |
| Finished | Jul 13 08:30:43 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-9ec20b2b-e12c-415b-b2a2-d29348bc8320 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154743161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.3154743161 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.719555387 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 196510757 ps |
| CPU time | 17.48 seconds |
| Started | Jul 13 08:30:31 PM PDT 24 |
| Finished | Jul 13 08:30:49 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-a8c8579e-b032-442a-b950-4d82864ceaea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719555387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device. 719555387 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.3841484808 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 138494261966 ps |
| CPU time | 2551.95 seconds |
| Started | Jul 13 08:30:34 PM PDT 24 |
| Finished | Jul 13 09:13:06 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-e5cafa50-a58b-4001-9aa7-2d19c196aae3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841484808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_ device_slow_rsp.3841484808 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.2780347553 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 121448835 ps |
| CPU time | 15.34 seconds |
| Started | Jul 13 08:30:35 PM PDT 24 |
| Finished | Jul 13 08:30:50 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-7136147d-7ec8-4302-be9e-0fc893ebd2b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780347553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add r.2780347553 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.4277998801 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 1168429682 ps |
| CPU time | 41.5 seconds |
| Started | Jul 13 08:30:31 PM PDT 24 |
| Finished | Jul 13 08:31:13 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-92c6194d-267b-43e3-9b2d-ed5617edca93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277998801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.4277998801 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.1207101242 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 1163269726 ps |
| CPU time | 43.21 seconds |
| Started | Jul 13 08:30:32 PM PDT 24 |
| Finished | Jul 13 08:31:16 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-2c9c0d51-ce3c-45c8-8a35-54aa1cbd75c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207101242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.1207101242 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.581475150 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 13436678225 ps |
| CPU time | 157.93 seconds |
| Started | Jul 13 08:30:33 PM PDT 24 |
| Finished | Jul 13 08:33:12 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-c5f8e46a-34ba-47c2-b796-cf7765256520 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581475150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.581475150 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.1081867541 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 56121052105 ps |
| CPU time | 1074.13 seconds |
| Started | Jul 13 08:30:35 PM PDT 24 |
| Finished | Jul 13 08:48:29 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-7e23d7f6-eb5a-4482-9746-c4087668a068 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081867541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.1081867541 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.612425204 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 289708559 ps |
| CPU time | 31.26 seconds |
| Started | Jul 13 08:30:32 PM PDT 24 |
| Finished | Jul 13 08:31:05 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-634d9896-96f0-4680-ad2a-aa18ef7b51b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612425204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_dela ys.612425204 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.2421948202 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 477499737 ps |
| CPU time | 35.64 seconds |
| Started | Jul 13 08:30:31 PM PDT 24 |
| Finished | Jul 13 08:31:07 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-ee8fda3f-a9d4-4445-acd2-8fa537a3e8b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421948202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.2421948202 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.2175229953 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 52769567 ps |
| CPU time | 7.09 seconds |
| Started | Jul 13 08:30:24 PM PDT 24 |
| Finished | Jul 13 08:30:31 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-d4f41a88-d894-4ef9-b729-09b32f467750 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175229953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.2175229953 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.26943888 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 7916816555 ps |
| CPU time | 87.9 seconds |
| Started | Jul 13 08:30:22 PM PDT 24 |
| Finished | Jul 13 08:31:51 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-c7841614-dedb-4820-be76-199697da28d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26943888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.26943888 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.4212703318 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 5661703671 ps |
| CPU time | 105.73 seconds |
| Started | Jul 13 08:30:23 PM PDT 24 |
| Finished | Jul 13 08:32:09 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-c4184cf6-815a-482b-97f9-03748f667e7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212703318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.4212703318 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.1693140419 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 42276304 ps |
| CPU time | 6.49 seconds |
| Started | Jul 13 08:30:22 PM PDT 24 |
| Finished | Jul 13 08:30:29 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-6b7314d4-e816-44b0-a33d-cbc8b6ddb4c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693140419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.1693140419 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.3386572218 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 9357584778 ps |
| CPU time | 351.92 seconds |
| Started | Jul 13 08:30:34 PM PDT 24 |
| Finished | Jul 13 08:36:26 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-76ec4f93-f336-4c86-9a6f-2f8aa98ac45b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386572218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.3386572218 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.1264650833 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 6975071878 ps |
| CPU time | 314.27 seconds |
| Started | Jul 13 08:30:31 PM PDT 24 |
| Finished | Jul 13 08:35:46 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-e99e843e-2ac1-462f-8ae2-411b43422389 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264650833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.1264650833 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.1782138417 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 10780552684 ps |
| CPU time | 643.13 seconds |
| Started | Jul 13 08:30:32 PM PDT 24 |
| Finished | Jul 13 08:41:17 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-1f4dee7a-f813-4946-a10b-99a71d9c8c41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782138417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_rand_reset.1782138417 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2333365574 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 934833978 ps |
| CPU time | 241.05 seconds |
| Started | Jul 13 08:30:33 PM PDT 24 |
| Finished | Jul 13 08:34:35 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-9a3c8056-2a5f-48d4-ada0-fb9c8ced8304 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333365574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.2333365574 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.770306984 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 774544821 ps |
| CPU time | 35.25 seconds |
| Started | Jul 13 08:30:31 PM PDT 24 |
| Finished | Jul 13 08:31:07 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-7f9163eb-0451-4e7c-8406-e5f4a61219a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770306984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.770306984 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.1460996004 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 145484377 ps |
| CPU time | 24.76 seconds |
| Started | Jul 13 08:30:39 PM PDT 24 |
| Finished | Jul 13 08:31:04 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-f4d78d4e-609b-4748-8d2b-956ad2ae7182 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460996004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .1460996004 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.2992993906 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 69400102116 ps |
| CPU time | 1189.32 seconds |
| Started | Jul 13 08:30:43 PM PDT 24 |
| Finished | Jul 13 08:50:33 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-66627699-c1b0-46e1-985b-d1eadbd54a6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992993906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_ device_slow_rsp.2992993906 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.1620175944 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 991043730 ps |
| CPU time | 37.51 seconds |
| Started | Jul 13 08:30:41 PM PDT 24 |
| Finished | Jul 13 08:31:18 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-87d75785-98d3-44ed-8d6a-1ea00a79988a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620175944 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add r.1620175944 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.3532825777 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 1200938407 ps |
| CPU time | 43.55 seconds |
| Started | Jul 13 08:30:43 PM PDT 24 |
| Finished | Jul 13 08:31:27 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-11ad1e3a-83c4-4acc-89ee-170b24ebad77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532825777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.3532825777 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.295047623 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 304803363 ps |
| CPU time | 14.42 seconds |
| Started | Jul 13 08:30:31 PM PDT 24 |
| Finished | Jul 13 08:30:46 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-ac446182-7758-4b9a-845c-edc31d0b939a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295047623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.295047623 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.3198389916 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 27671920577 ps |
| CPU time | 332.79 seconds |
| Started | Jul 13 08:30:40 PM PDT 24 |
| Finished | Jul 13 08:36:14 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-4b253e1c-6d9f-4aca-bdf5-14e75b2949e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198389916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.3198389916 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.4188189152 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 20530064055 ps |
| CPU time | 374.78 seconds |
| Started | Jul 13 08:30:41 PM PDT 24 |
| Finished | Jul 13 08:36:56 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-a9cd2810-7fe8-4f11-bcac-1205d90e7b6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188189152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.4188189152 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.3611904659 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 184635985 ps |
| CPU time | 18.54 seconds |
| Started | Jul 13 08:30:32 PM PDT 24 |
| Finished | Jul 13 08:30:52 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-336e3ffe-cc7c-427c-a75b-e6967d9a06cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611904659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_del ays.3611904659 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.2303729131 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 480192885 ps |
| CPU time | 41.1 seconds |
| Started | Jul 13 08:30:44 PM PDT 24 |
| Finished | Jul 13 08:31:26 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-4724276a-05ae-414e-b2eb-1893a5151652 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303729131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.2303729131 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.2282056435 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 254875073 ps |
| CPU time | 10.38 seconds |
| Started | Jul 13 08:30:34 PM PDT 24 |
| Finished | Jul 13 08:30:44 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-7b71523e-b3e3-443f-bbbe-01381827a154 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282056435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.2282056435 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.1501383337 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 9315458914 ps |
| CPU time | 106.05 seconds |
| Started | Jul 13 08:30:32 PM PDT 24 |
| Finished | Jul 13 08:32:19 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-b839a4eb-75e4-4ee6-ad21-a0e1ee4c3874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501383337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.1501383337 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.1731826936 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 5872983644 ps |
| CPU time | 105.2 seconds |
| Started | Jul 13 08:30:33 PM PDT 24 |
| Finished | Jul 13 08:32:19 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-24260ee1-ecf8-4f33-81f3-f3f09896ff32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731826936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.1731826936 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.1972802206 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 44458941 ps |
| CPU time | 6.94 seconds |
| Started | Jul 13 08:30:31 PM PDT 24 |
| Finished | Jul 13 08:30:39 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-e8883851-4db8-4a7b-af07-0135e94f3f31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972802206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay s.1972802206 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.892582236 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 2502954249 ps |
| CPU time | 206.33 seconds |
| Started | Jul 13 08:30:42 PM PDT 24 |
| Finished | Jul 13 08:34:09 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-683da029-0ad0-48db-a50c-4341e514db0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892582236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.892582236 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.3855643885 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 2175843757 ps |
| CPU time | 165.31 seconds |
| Started | Jul 13 08:30:43 PM PDT 24 |
| Finished | Jul 13 08:33:28 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-e35737ef-e7b2-4472-a2a2-82092357d203 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855643885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.3855643885 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.684156110 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 421117200 ps |
| CPU time | 252.26 seconds |
| Started | Jul 13 08:30:42 PM PDT 24 |
| Finished | Jul 13 08:34:54 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-c9c4f788-8b3d-4c89-ba37-986518069adf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684156110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_ with_rand_reset.684156110 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.2936530273 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 3176966668 ps |
| CPU time | 480.86 seconds |
| Started | Jul 13 08:30:47 PM PDT 24 |
| Finished | Jul 13 08:38:49 PM PDT 24 |
| Peak memory | 580360 kb |
| Host | smart-dfe6ac15-4df1-48bd-92a1-13db63e9a0d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936530273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.2936530273 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.2617388952 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 151454440 ps |
| CPU time | 10.71 seconds |
| Started | Jul 13 08:30:42 PM PDT 24 |
| Finished | Jul 13 08:30:53 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-1559305e-c937-4de7-acb9-603c499b2943 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617388952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.2617388952 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.3768953510 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 225643964 ps |
| CPU time | 14.34 seconds |
| Started | Jul 13 08:30:51 PM PDT 24 |
| Finished | Jul 13 08:31:06 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-917f47c2-b077-40c9-b2aa-eb2c2bd6c541 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768953510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .3768953510 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.2265628908 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 100496389969 ps |
| CPU time | 1776.08 seconds |
| Started | Jul 13 08:30:55 PM PDT 24 |
| Finished | Jul 13 09:00:31 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-e65f126a-6e58-421f-871c-568f632e3989 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265628908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_ device_slow_rsp.2265628908 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.3776861340 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 24947075 ps |
| CPU time | 5.87 seconds |
| Started | Jul 13 08:30:53 PM PDT 24 |
| Finished | Jul 13 08:31:00 PM PDT 24 |
| Peak memory | 573948 kb |
| Host | smart-3d49d863-ce36-4bf6-a25a-99c4f0f06687 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776861340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.3776861340 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.3858502883 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 834599750 ps |
| CPU time | 30.42 seconds |
| Started | Jul 13 08:30:52 PM PDT 24 |
| Finished | Jul 13 08:31:23 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-430de210-e58d-466c-adc1-c15e06995464 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858502883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.3858502883 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.1313429137 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 1213603133 ps |
| CPU time | 46.84 seconds |
| Started | Jul 13 08:30:43 PM PDT 24 |
| Finished | Jul 13 08:31:31 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-68752445-5a4d-41e6-944f-112b6368be97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313429137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.1313429137 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.2400519803 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 95870549236 ps |
| CPU time | 1075.34 seconds |
| Started | Jul 13 08:30:46 PM PDT 24 |
| Finished | Jul 13 08:48:42 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-ba5e11e9-3a86-44a2-8941-9e1f390a9a54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400519803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.2400519803 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.2969175834 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 21256942983 ps |
| CPU time | 386.23 seconds |
| Started | Jul 13 08:30:43 PM PDT 24 |
| Finished | Jul 13 08:37:09 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-11694fc6-9049-4d85-9de9-cb9a1989c176 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969175834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.2969175834 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.851878476 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 72126417 ps |
| CPU time | 9.71 seconds |
| Started | Jul 13 08:30:43 PM PDT 24 |
| Finished | Jul 13 08:30:54 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-2568bb45-dfad-4968-a737-b9ac5d8c4b3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851878476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_dela ys.851878476 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.902044815 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 1403363238 ps |
| CPU time | 45.99 seconds |
| Started | Jul 13 08:30:51 PM PDT 24 |
| Finished | Jul 13 08:31:37 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-e240828e-688c-4218-962a-824066683f5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902044815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.902044815 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.249825309 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 158172187 ps |
| CPU time | 8.74 seconds |
| Started | Jul 13 08:30:44 PM PDT 24 |
| Finished | Jul 13 08:30:54 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-9b607c9d-0884-488a-ad93-59fedc98a2ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249825309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.249825309 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.2136323320 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 8490716977 ps |
| CPU time | 102.25 seconds |
| Started | Jul 13 08:30:43 PM PDT 24 |
| Finished | Jul 13 08:32:26 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-d6246c6a-2942-4a0d-b6e8-e6e04b3c003f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136323320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.2136323320 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.314229262 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 6201189272 ps |
| CPU time | 111.12 seconds |
| Started | Jul 13 08:30:45 PM PDT 24 |
| Finished | Jul 13 08:32:37 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-289ee5d6-7756-4737-b69b-221bee89a309 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314229262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.314229262 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.2604439495 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 50453353 ps |
| CPU time | 7.03 seconds |
| Started | Jul 13 08:30:41 PM PDT 24 |
| Finished | Jul 13 08:30:49 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-f821dcce-33cb-41e8-a86e-d0f736a75ace |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604439495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay s.2604439495 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.2853685423 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 2058927672 ps |
| CPU time | 79.37 seconds |
| Started | Jul 13 08:30:51 PM PDT 24 |
| Finished | Jul 13 08:32:11 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-7b2979fc-0595-48a0-8c5b-b6a9d68965ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853685423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.2853685423 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.2892880809 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 1565192916 ps |
| CPU time | 164.02 seconds |
| Started | Jul 13 08:30:52 PM PDT 24 |
| Finished | Jul 13 08:33:36 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-39da3b3e-a366-4ee5-8185-6341d90ba405 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892880809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.2892880809 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.1452186952 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 527481535 ps |
| CPU time | 305.32 seconds |
| Started | Jul 13 08:30:53 PM PDT 24 |
| Finished | Jul 13 08:35:59 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-4b43b252-b71d-4f95-a1e3-a0d249eb1386 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452186952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_rand_reset.1452186952 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.1143199304 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 72051295 ps |
| CPU time | 35.75 seconds |
| Started | Jul 13 08:30:53 PM PDT 24 |
| Finished | Jul 13 08:31:29 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-52728646-2fcc-4dd3-b8e4-7cdda996ff56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143199304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al l_with_reset_error.1143199304 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.155377756 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 673466310 ps |
| CPU time | 33.85 seconds |
| Started | Jul 13 08:30:52 PM PDT 24 |
| Finished | Jul 13 08:31:26 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-6f66c52b-efc0-40ab-aaa6-9547e9965a5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155377756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.155377756 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.2529717308 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 308766049 ps |
| CPU time | 28.48 seconds |
| Started | Jul 13 08:31:00 PM PDT 24 |
| Finished | Jul 13 08:31:29 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-7edfe3ab-35b6-479f-ae75-8f2393b83bd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529717308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .2529717308 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.3077567311 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 42757478215 ps |
| CPU time | 828.79 seconds |
| Started | Jul 13 08:30:59 PM PDT 24 |
| Finished | Jul 13 08:44:49 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-b56ababe-cff1-4588-837a-0fbf08a5ab02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077567311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.3077567311 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.1196224215 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 749383409 ps |
| CPU time | 36.16 seconds |
| Started | Jul 13 08:31:01 PM PDT 24 |
| Finished | Jul 13 08:31:38 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-34144e13-8b83-4d78-bada-b135a804a4fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196224215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add r.1196224215 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.345022143 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 538858590 ps |
| CPU time | 23.28 seconds |
| Started | Jul 13 08:31:00 PM PDT 24 |
| Finished | Jul 13 08:31:24 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-c1ba1e65-3b04-4b48-bf39-09a36acb77e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345022143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.345022143 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.3563928477 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 148827579 ps |
| CPU time | 17.09 seconds |
| Started | Jul 13 08:30:53 PM PDT 24 |
| Finished | Jul 13 08:31:10 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-b8605a5f-823d-459a-8e70-bacaa7c406b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563928477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.3563928477 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.1005570416 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 40029685319 ps |
| CPU time | 500.14 seconds |
| Started | Jul 13 08:31:06 PM PDT 24 |
| Finished | Jul 13 08:39:27 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-6245a57b-b887-431e-b66a-e45b984f9887 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005570416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.1005570416 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.3974725169 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 42034557923 ps |
| CPU time | 767.03 seconds |
| Started | Jul 13 08:31:01 PM PDT 24 |
| Finished | Jul 13 08:43:49 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-4380c6e0-c8d2-4c81-89fb-b9e4d8cceebd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974725169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.3974725169 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.3332177413 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 258597773 ps |
| CPU time | 25.21 seconds |
| Started | Jul 13 08:30:59 PM PDT 24 |
| Finished | Jul 13 08:31:25 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-6ff02c2e-1505-4765-a56b-44bbde4f9c19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332177413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del ays.3332177413 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.1496078933 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 554351936 ps |
| CPU time | 40.86 seconds |
| Started | Jul 13 08:31:00 PM PDT 24 |
| Finished | Jul 13 08:31:41 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-bbd5ef9f-f500-44f6-a0fc-e1b0545b666e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496078933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.1496078933 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.3175084604 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 40414105 ps |
| CPU time | 6.16 seconds |
| Started | Jul 13 08:30:50 PM PDT 24 |
| Finished | Jul 13 08:30:56 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-3f9eb052-116c-42a5-a496-378230cac175 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175084604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.3175084604 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.1933609661 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 6554934624 ps |
| CPU time | 76.58 seconds |
| Started | Jul 13 08:30:51 PM PDT 24 |
| Finished | Jul 13 08:32:08 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-b0e9ee69-6308-441a-af0f-49945bf29feb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933609661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.1933609661 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.3018577558 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 5740752946 ps |
| CPU time | 100.9 seconds |
| Started | Jul 13 08:30:49 PM PDT 24 |
| Finished | Jul 13 08:32:31 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-2cfb94a4-2aee-4187-80ad-ed40af9319d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018577558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.3018577558 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.9381105 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 53859231 ps |
| CPU time | 7.2 seconds |
| Started | Jul 13 08:30:57 PM PDT 24 |
| Finished | Jul 13 08:31:04 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-c1ffd1c7-e34b-4284-9a15-ae162d1dbe90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9381105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delays.9381105 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.3495044329 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 3206782659 ps |
| CPU time | 309.58 seconds |
| Started | Jul 13 08:31:01 PM PDT 24 |
| Finished | Jul 13 08:36:11 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-1d0144de-2644-47ae-aa18-441d6bc47c8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495044329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.3495044329 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.4097610898 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 1483292003 ps |
| CPU time | 114.8 seconds |
| Started | Jul 13 08:31:01 PM PDT 24 |
| Finished | Jul 13 08:32:56 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-f4b6fe9c-5c0b-4cc2-929c-ed8f167d51e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097610898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.4097610898 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.1863846769 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 300697542 ps |
| CPU time | 125.06 seconds |
| Started | Jul 13 08:31:06 PM PDT 24 |
| Finished | Jul 13 08:33:11 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-74320032-3406-493d-9a22-f763010fdcf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863846769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_rand_reset.1863846769 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.1100983845 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 1094424736 ps |
| CPU time | 151.07 seconds |
| Started | Jul 13 08:30:59 PM PDT 24 |
| Finished | Jul 13 08:33:31 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-086cf3ca-1e9d-4da5-8472-dc37ff785c5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100983845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.1100983845 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.1624301094 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 148586831 ps |
| CPU time | 9.64 seconds |
| Started | Jul 13 08:31:06 PM PDT 24 |
| Finished | Jul 13 08:31:16 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-e24d949f-b57d-4fa9-9a2d-78e0c0cbdf3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624301094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.1624301094 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.2937633606 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 3165884999 ps |
| CPU time | 151.73 seconds |
| Started | Jul 13 08:31:14 PM PDT 24 |
| Finished | Jul 13 08:33:46 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-c8a22c02-1ca6-4299-beae-17a63631e2ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937633606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .2937633606 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.1179003079 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 4299789729 ps |
| CPU time | 85.15 seconds |
| Started | Jul 13 08:31:12 PM PDT 24 |
| Finished | Jul 13 08:32:38 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-0450849f-8d8c-4c26-b8fd-e088124409b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179003079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_ device_slow_rsp.1179003079 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.3800107991 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 72716059 ps |
| CPU time | 10.62 seconds |
| Started | Jul 13 08:31:13 PM PDT 24 |
| Finished | Jul 13 08:31:24 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-a1fb8c48-120e-4f82-b4f9-8b810d8cd7e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800107991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add r.3800107991 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.932007599 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 2471419923 ps |
| CPU time | 91.9 seconds |
| Started | Jul 13 08:31:13 PM PDT 24 |
| Finished | Jul 13 08:32:46 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-770e6c61-4f78-4dc7-83be-7b3c848d62ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932007599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.932007599 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.647315005 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 1212073447 ps |
| CPU time | 50.43 seconds |
| Started | Jul 13 08:31:05 PM PDT 24 |
| Finished | Jul 13 08:31:56 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-400e999f-eaca-4398-ac78-6ded0e022793 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647315005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.647315005 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.2215278790 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 64583361642 ps |
| CPU time | 791.86 seconds |
| Started | Jul 13 08:31:14 PM PDT 24 |
| Finished | Jul 13 08:44:27 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-88a923d1-667b-4ccd-ad91-dcf41210b40d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215278790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.2215278790 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.3497304927 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 60789479326 ps |
| CPU time | 1133.83 seconds |
| Started | Jul 13 08:31:15 PM PDT 24 |
| Finished | Jul 13 08:50:09 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-6645934b-c4af-4afc-b5a7-5f88dc7eb60f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497304927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.3497304927 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.1584044505 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 297522447 ps |
| CPU time | 29.01 seconds |
| Started | Jul 13 08:31:00 PM PDT 24 |
| Finished | Jul 13 08:31:29 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-2937636c-27cf-4e5a-afb4-2aa4752c00b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584044505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del ays.1584044505 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.2460036070 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 1988557776 ps |
| CPU time | 62.4 seconds |
| Started | Jul 13 08:31:16 PM PDT 24 |
| Finished | Jul 13 08:32:18 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-e2430919-ad3d-42a0-881c-328f034660b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460036070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.2460036070 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.1129493761 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 253064766 ps |
| CPU time | 11.73 seconds |
| Started | Jul 13 08:30:59 PM PDT 24 |
| Finished | Jul 13 08:31:11 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-6fb70653-892f-419b-aec6-1790de258e20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129493761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.1129493761 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.3160212000 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 6855530412 ps |
| CPU time | 77.89 seconds |
| Started | Jul 13 08:31:06 PM PDT 24 |
| Finished | Jul 13 08:32:24 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-aa5e539e-efc5-48ca-81b2-e9c83c714283 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160212000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.3160212000 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.1901967056 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 4238110674 ps |
| CPU time | 77.21 seconds |
| Started | Jul 13 08:30:58 PM PDT 24 |
| Finished | Jul 13 08:32:15 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-64de40f9-20fa-4246-9b8c-71d30653ba31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901967056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.1901967056 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.4089097798 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 53969779 ps |
| CPU time | 7.36 seconds |
| Started | Jul 13 08:31:00 PM PDT 24 |
| Finished | Jul 13 08:31:08 PM PDT 24 |
| Peak memory | 575116 kb |
| Host | smart-33727c8a-ac12-4179-a1a6-f1dfef511ea7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089097798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delay s.4089097798 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.3546284886 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 1579365754 ps |
| CPU time | 141.68 seconds |
| Started | Jul 13 08:31:12 PM PDT 24 |
| Finished | Jul 13 08:33:35 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-ae85d21e-c941-40d2-96e1-375e11786ff4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546284886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.3546284886 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.3693242546 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 8334121877 ps |
| CPU time | 319.15 seconds |
| Started | Jul 13 08:31:13 PM PDT 24 |
| Finished | Jul 13 08:36:33 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-2a67e2db-3a34-4893-80be-23b03dfa56b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693242546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.3693242546 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.3978012642 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 220456940 ps |
| CPU time | 67.47 seconds |
| Started | Jul 13 08:31:17 PM PDT 24 |
| Finished | Jul 13 08:32:25 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-df57222a-3cf6-4f94-a757-9ebe9dde9d63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978012642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_rand_reset.3978012642 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.371430721 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 13605141131 ps |
| CPU time | 605.15 seconds |
| Started | Jul 13 08:31:17 PM PDT 24 |
| Finished | Jul 13 08:41:23 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-b2efd745-f87f-437b-80dc-e04b7168e817 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371430721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_reset_error.371430721 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.574650598 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 89572053 ps |
| CPU time | 14.14 seconds |
| Started | Jul 13 08:31:13 PM PDT 24 |
| Finished | Jul 13 08:31:28 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-47b1baba-5a3a-4707-b319-f103c9b0d8f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574650598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.574650598 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.3919740141 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 663316683 ps |
| CPU time | 54.74 seconds |
| Started | Jul 13 08:31:37 PM PDT 24 |
| Finished | Jul 13 08:32:33 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-9bdf6a3b-4c8a-4efa-b793-713d149b4ae9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919740141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .3919740141 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.2609878935 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 111030822146 ps |
| CPU time | 2062.6 seconds |
| Started | Jul 13 08:31:23 PM PDT 24 |
| Finished | Jul 13 09:05:46 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-5438b154-3ef4-45af-9539-f59522c664ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609878935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.2609878935 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.3035560708 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 546231903 ps |
| CPU time | 28.55 seconds |
| Started | Jul 13 08:31:22 PM PDT 24 |
| Finished | Jul 13 08:31:52 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-8d678bbc-a9ee-46b1-85bf-902c83b936f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035560708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.3035560708 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.764102765 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 1623447562 ps |
| CPU time | 59.86 seconds |
| Started | Jul 13 08:31:22 PM PDT 24 |
| Finished | Jul 13 08:32:23 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-5f45bfad-24d9-401d-9c5e-a767ce0bd665 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764102765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.764102765 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.2603564063 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 626903648 ps |
| CPU time | 26.96 seconds |
| Started | Jul 13 08:31:13 PM PDT 24 |
| Finished | Jul 13 08:31:41 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-f928e711-d836-4ad4-8e18-7ddf369c0fe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603564063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.2603564063 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.4156576634 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 4445338764 ps |
| CPU time | 51.28 seconds |
| Started | Jul 13 08:31:24 PM PDT 24 |
| Finished | Jul 13 08:32:17 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-18398113-014f-4345-b8e1-2971ef74f971 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156576634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.4156576634 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.2133088782 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 7554707293 ps |
| CPU time | 142.64 seconds |
| Started | Jul 13 08:31:23 PM PDT 24 |
| Finished | Jul 13 08:33:46 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-419eb17c-6e66-47c8-95db-18d8e5102b05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133088782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.2133088782 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.517410720 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 599753390 ps |
| CPU time | 56.96 seconds |
| Started | Jul 13 08:31:23 PM PDT 24 |
| Finished | Jul 13 08:32:20 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-7778ffe5-1d5d-47dd-9b4c-390904c91ab9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517410720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_dela ys.517410720 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.689184732 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 304594606 ps |
| CPU time | 24.79 seconds |
| Started | Jul 13 08:31:23 PM PDT 24 |
| Finished | Jul 13 08:31:49 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-010dbb18-2cbd-43d7-868b-0f6ca139e379 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689184732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.689184732 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.1901520421 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 182293566 ps |
| CPU time | 9.04 seconds |
| Started | Jul 13 08:31:14 PM PDT 24 |
| Finished | Jul 13 08:31:24 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-f2bae7b5-c6ec-4ef7-ad9f-a584281a9ec3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901520421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.1901520421 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.2020175313 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 9325873332 ps |
| CPU time | 114.1 seconds |
| Started | Jul 13 08:31:12 PM PDT 24 |
| Finished | Jul 13 08:33:07 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-bfa0621b-78f7-4421-a82a-85d9d44442ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020175313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.2020175313 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.3397041607 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 5534480192 ps |
| CPU time | 100.83 seconds |
| Started | Jul 13 08:31:13 PM PDT 24 |
| Finished | Jul 13 08:32:54 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-62f0fa6c-c266-47b1-96ef-9df9d8ee3b06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397041607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.3397041607 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.2524717815 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 43053092 ps |
| CPU time | 5.89 seconds |
| Started | Jul 13 08:31:12 PM PDT 24 |
| Finished | Jul 13 08:31:18 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-1112632a-e7fc-417f-bb62-bb9af57fb2a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524717815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.2524717815 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.23748222 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 4921064166 ps |
| CPU time | 426.4 seconds |
| Started | Jul 13 08:31:26 PM PDT 24 |
| Finished | Jul 13 08:38:33 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-3e4422b8-0fc8-49fb-bffa-633235379b8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23748222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.23748222 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.1402062945 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 2635711250 ps |
| CPU time | 232 seconds |
| Started | Jul 13 08:31:25 PM PDT 24 |
| Finished | Jul 13 08:35:19 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-860de993-a0c9-4671-ae3f-56c9307bcf1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402062945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.1402062945 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.1250925408 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 162715317 ps |
| CPU time | 98.04 seconds |
| Started | Jul 13 08:31:36 PM PDT 24 |
| Finished | Jul 13 08:33:15 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-27140d2c-7703-4d11-b6b7-8bf0d13537ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250925408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.1250925408 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.1588462450 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 760529287 ps |
| CPU time | 269.34 seconds |
| Started | Jul 13 08:31:22 PM PDT 24 |
| Finished | Jul 13 08:35:52 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-c49efe34-25cd-41fd-a76b-dea7f62e13a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588462450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.1588462450 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.4233391484 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 295872637 ps |
| CPU time | 17.95 seconds |
| Started | Jul 13 08:31:24 PM PDT 24 |
| Finished | Jul 13 08:31:44 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-bf3d7b05-4c94-4907-be86-0acd0b16ea6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233391484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.4233391484 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.4198729794 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 2513606266 ps |
| CPU time | 130.61 seconds |
| Started | Jul 13 08:31:36 PM PDT 24 |
| Finished | Jul 13 08:33:47 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-9414e55b-d1c2-426e-a71f-140a6f551f9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198729794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device .4198729794 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.2339004889 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 113757013946 ps |
| CPU time | 2117.59 seconds |
| Started | Jul 13 08:31:33 PM PDT 24 |
| Finished | Jul 13 09:06:51 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-3d10acf5-f154-4017-8a90-05e6d1a5d19f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339004889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.2339004889 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.4129221361 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 114571375 ps |
| CPU time | 16.2 seconds |
| Started | Jul 13 08:31:32 PM PDT 24 |
| Finished | Jul 13 08:31:49 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-48a77f53-c83d-4931-970e-6b2336998f3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129221361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add r.4129221361 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.3980811152 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 308828264 ps |
| CPU time | 27.37 seconds |
| Started | Jul 13 08:31:34 PM PDT 24 |
| Finished | Jul 13 08:32:02 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-91c6d4a6-db8b-4844-8a82-6b7d88a50c1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980811152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.3980811152 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.3837064423 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 1073075666 ps |
| CPU time | 41.05 seconds |
| Started | Jul 13 08:31:22 PM PDT 24 |
| Finished | Jul 13 08:32:04 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-6914a442-02af-4e86-a88c-a57ad44fa2b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837064423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.3837064423 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.1406477962 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 66276419148 ps |
| CPU time | 808.25 seconds |
| Started | Jul 13 08:31:23 PM PDT 24 |
| Finished | Jul 13 08:44:52 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-d32b22cc-df49-434f-92d1-672ff4e64ea6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406477962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.1406477962 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.294224719 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 35750151138 ps |
| CPU time | 721.01 seconds |
| Started | Jul 13 08:31:24 PM PDT 24 |
| Finished | Jul 13 08:43:25 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-500477f8-dd60-4215-b022-7aad87d0e600 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294224719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.294224719 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.3177363304 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 527123817 ps |
| CPU time | 50.72 seconds |
| Started | Jul 13 08:31:23 PM PDT 24 |
| Finished | Jul 13 08:32:15 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-a5b5f094-a5e3-4764-a672-8caed4a0e9fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177363304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del ays.3177363304 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.2394463102 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 316175612 ps |
| CPU time | 26.56 seconds |
| Started | Jul 13 08:31:46 PM PDT 24 |
| Finished | Jul 13 08:32:13 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-5936538b-11cc-4351-8010-81235faaeffa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394463102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.2394463102 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.2983114292 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 236422263 ps |
| CPU time | 11.2 seconds |
| Started | Jul 13 08:31:37 PM PDT 24 |
| Finished | Jul 13 08:31:49 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-1dbd9f27-1160-40ce-9b24-be8b7df0b006 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983114292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.2983114292 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.1452578510 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 9830043384 ps |
| CPU time | 115.04 seconds |
| Started | Jul 13 08:31:26 PM PDT 24 |
| Finished | Jul 13 08:33:22 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-fe57a7ea-897c-4631-a32a-628e374cb860 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452578510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.1452578510 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.1315504147 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 5176345625 ps |
| CPU time | 90.84 seconds |
| Started | Jul 13 08:31:37 PM PDT 24 |
| Finished | Jul 13 08:33:08 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-f38f866f-70a7-4b94-8858-5c240c9c7177 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315504147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.1315504147 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.307694611 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 53655897 ps |
| CPU time | 6.71 seconds |
| Started | Jul 13 08:31:22 PM PDT 24 |
| Finished | Jul 13 08:31:29 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-69cde489-ff16-4a98-aacb-dce357de5cb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307694611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delays .307694611 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.1457668764 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 238746623 ps |
| CPU time | 14.2 seconds |
| Started | Jul 13 08:31:33 PM PDT 24 |
| Finished | Jul 13 08:31:48 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-d4349636-f93a-4749-97bc-d1c9a387ab5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457668764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.1457668764 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.510124397 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 2548123093 ps |
| CPU time | 72.79 seconds |
| Started | Jul 13 08:31:31 PM PDT 24 |
| Finished | Jul 13 08:32:44 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-c381711a-36d5-4fab-b3d6-92e4a9e86804 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510124397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.510124397 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.4237526854 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 1110454358 ps |
| CPU time | 48.38 seconds |
| Started | Jul 13 08:31:46 PM PDT 24 |
| Finished | Jul 13 08:32:35 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-a9a60ae6-391d-4edc-b776-a66500dde389 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237526854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all _with_rand_reset.4237526854 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.3907083947 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 3035365154 ps |
| CPU time | 372.64 seconds |
| Started | Jul 13 08:31:33 PM PDT 24 |
| Finished | Jul 13 08:37:47 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-c6ec04cd-48fa-4557-8bb3-04da73f95bd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907083947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.3907083947 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.1029685211 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 898965489 ps |
| CPU time | 38.66 seconds |
| Started | Jul 13 08:31:31 PM PDT 24 |
| Finished | Jul 13 08:32:10 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-ce6267e0-b688-47ef-8dcd-8c653dda2ffb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029685211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.1029685211 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.1690871015 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 2575993522 ps |
| CPU time | 119.25 seconds |
| Started | Jul 13 08:31:33 PM PDT 24 |
| Finished | Jul 13 08:33:32 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-8bca1e7d-2203-481f-b9d9-4a8150ae94d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690871015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device .1690871015 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.2020434648 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 139153245763 ps |
| CPU time | 2771.25 seconds |
| Started | Jul 13 08:31:35 PM PDT 24 |
| Finished | Jul 13 09:17:48 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-c9da6ca8-b639-41d6-ae19-4886aa784caa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020434648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.2020434648 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.120093335 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 223534974 ps |
| CPU time | 11.46 seconds |
| Started | Jul 13 08:31:43 PM PDT 24 |
| Finished | Jul 13 08:31:55 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-5dbbaa90-6e87-46bc-8fbc-ad461c49449d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120093335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_addr .120093335 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.2009938976 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 828380605 ps |
| CPU time | 33.18 seconds |
| Started | Jul 13 08:31:42 PM PDT 24 |
| Finished | Jul 13 08:32:16 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-027cba38-d9ac-4ab4-ab4c-222ceef0acfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009938976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.2009938976 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.595926347 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 1261048994 ps |
| CPU time | 52.96 seconds |
| Started | Jul 13 08:31:34 PM PDT 24 |
| Finished | Jul 13 08:32:27 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-ded6d977-1a83-4795-bd74-5ddc5c405d41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595926347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.595926347 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.3987861274 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 104854197900 ps |
| CPU time | 1213.73 seconds |
| Started | Jul 13 08:31:46 PM PDT 24 |
| Finished | Jul 13 08:52:00 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-01b9a95b-497c-43e5-bcdb-b3b514cb7cc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987861274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.3987861274 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.2951777343 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 30849306668 ps |
| CPU time | 571.02 seconds |
| Started | Jul 13 08:31:34 PM PDT 24 |
| Finished | Jul 13 08:41:05 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-8d95f2e8-4eba-4273-a9b3-0c91095577b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951777343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.2951777343 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.2485525116 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 187795496 ps |
| CPU time | 20.24 seconds |
| Started | Jul 13 08:31:46 PM PDT 24 |
| Finished | Jul 13 08:32:07 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-e95afff0-9bf7-4877-9825-63746a66dfd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485525116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del ays.2485525116 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.4242739901 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 2174520409 ps |
| CPU time | 70.32 seconds |
| Started | Jul 13 08:31:34 PM PDT 24 |
| Finished | Jul 13 08:32:45 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-e641b1ad-ceb1-4843-b267-0a15bfa6254d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242739901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.4242739901 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.396265267 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 51193305 ps |
| CPU time | 7.01 seconds |
| Started | Jul 13 08:31:34 PM PDT 24 |
| Finished | Jul 13 08:31:42 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-57f2058c-63ed-433e-83b4-f48bf8fa7235 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396265267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.396265267 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.1503380791 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 10096371250 ps |
| CPU time | 113.25 seconds |
| Started | Jul 13 08:31:46 PM PDT 24 |
| Finished | Jul 13 08:33:40 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-202b38e5-f72c-4794-95e2-d8ee679e8668 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503380791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.1503380791 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.891280894 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 4250948487 ps |
| CPU time | 77.68 seconds |
| Started | Jul 13 08:31:46 PM PDT 24 |
| Finished | Jul 13 08:33:04 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-292edef3-27eb-4a44-8495-2f73bd7c72f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891280894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.891280894 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.3378752724 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 52536877 ps |
| CPU time | 6.55 seconds |
| Started | Jul 13 08:31:33 PM PDT 24 |
| Finished | Jul 13 08:31:41 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-7061aa9e-95c0-43f9-9111-24beaad44af0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378752724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay s.3378752724 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.2650947744 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 2926435914 ps |
| CPU time | 117.16 seconds |
| Started | Jul 13 08:31:53 PM PDT 24 |
| Finished | Jul 13 08:33:51 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-a47c24ce-cc0e-49ef-bc86-78083de23f20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650947744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.2650947744 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.845165993 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 5582665502 ps |
| CPU time | 221.26 seconds |
| Started | Jul 13 08:31:52 PM PDT 24 |
| Finished | Jul 13 08:35:34 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-a468208d-42bf-4e6b-a938-091f482f72e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845165993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.845165993 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.3459923465 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 888423814 ps |
| CPU time | 321.79 seconds |
| Started | Jul 13 08:31:40 PM PDT 24 |
| Finished | Jul 13 08:37:02 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-fd5a52f6-1e23-427c-b6dd-7ec7b28e73c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459923465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.3459923465 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.910642267 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 3666398246 ps |
| CPU time | 446.74 seconds |
| Started | Jul 13 08:31:42 PM PDT 24 |
| Finished | Jul 13 08:39:09 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-16a3e6dc-b527-4cd1-9ddc-c8c01720b563 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910642267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_reset_error.910642267 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.2392060300 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 257607583 ps |
| CPU time | 34.96 seconds |
| Started | Jul 13 08:31:40 PM PDT 24 |
| Finished | Jul 13 08:32:16 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-40165f2b-3c41-4310-a165-1f79b9bde321 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392060300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.2392060300 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.316812638 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 3909358932 ps |
| CPU time | 437.66 seconds |
| Started | Jul 13 08:17:52 PM PDT 24 |
| Finished | Jul 13 08:25:10 PM PDT 24 |
| Peak memory | 598352 kb |
| Host | smart-20fb8969-3416-4b0a-aa19-b191b84fd77c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316812638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.316812638 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.1624566236 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 3468852510 ps |
| CPU time | 326.81 seconds |
| Started | Jul 13 08:17:28 PM PDT 24 |
| Finished | Jul 13 08:22:55 PM PDT 24 |
| Peak memory | 603760 kb |
| Host | smart-c897b2dc-4b1f-42f9-b9ef-bc977a10dc0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624566236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.1624566236 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.622908669 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 2439903689 ps |
| CPU time | 96.28 seconds |
| Started | Jul 13 08:17:41 PM PDT 24 |
| Finished | Jul 13 08:19:17 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-05a30f0c-4d64-4652-9cc6-c3d13ef79ea4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622908669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.622908669 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.767193000 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 136771988371 ps |
| CPU time | 2294.19 seconds |
| Started | Jul 13 08:17:41 PM PDT 24 |
| Finished | Jul 13 08:55:55 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-af1e6c26-f5f9-460a-8b30-281eda41dde2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767193000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_de vice_slow_rsp.767193000 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.751584599 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 575296425 ps |
| CPU time | 30.24 seconds |
| Started | Jul 13 08:17:44 PM PDT 24 |
| Finished | Jul 13 08:18:15 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-907b93c4-23d6-4fa7-b6a4-312ee2e574b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751584599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr. 751584599 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.997877836 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 427797445 ps |
| CPU time | 19.75 seconds |
| Started | Jul 13 08:17:45 PM PDT 24 |
| Finished | Jul 13 08:18:06 PM PDT 24 |
| Peak memory | 575012 kb |
| Host | smart-f075edd5-2f03-4b60-837b-4bef11edf8b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997877836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.997877836 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.2696498741 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 1701046264 ps |
| CPU time | 70.61 seconds |
| Started | Jul 13 08:17:37 PM PDT 24 |
| Finished | Jul 13 08:18:48 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-c774dfde-eb73-4992-b1ef-15cde2ceb1d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696498741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.2696498741 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.3350713579 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 69465837477 ps |
| CPU time | 792.7 seconds |
| Started | Jul 13 08:17:34 PM PDT 24 |
| Finished | Jul 13 08:30:47 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-95989b81-306b-4d9f-aca6-f66d2f429c91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350713579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3350713579 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.1466016683 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 7707960088 ps |
| CPU time | 150.78 seconds |
| Started | Jul 13 08:17:37 PM PDT 24 |
| Finished | Jul 13 08:20:08 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-b24310bd-e949-461a-a7b0-5a50ef64dc80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466016683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1466016683 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.3401511678 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 228544359 ps |
| CPU time | 24.8 seconds |
| Started | Jul 13 08:17:35 PM PDT 24 |
| Finished | Jul 13 08:18:00 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-f9c98994-0d51-4803-a1c1-b3590296e35d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401511678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela ys.3401511678 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.4187059676 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 1123135248 ps |
| CPU time | 34.79 seconds |
| Started | Jul 13 08:17:52 PM PDT 24 |
| Finished | Jul 13 08:18:27 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-154bb988-4f2f-4d9a-8f62-2cd52a661728 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187059676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.4187059676 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.929503923 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 42664038 ps |
| CPU time | 6.28 seconds |
| Started | Jul 13 08:17:28 PM PDT 24 |
| Finished | Jul 13 08:17:35 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-12e5b764-fe7b-4144-bc65-7cb5b12d5709 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929503923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.929503923 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.2277690471 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 7874819086 ps |
| CPU time | 100.58 seconds |
| Started | Jul 13 08:17:25 PM PDT 24 |
| Finished | Jul 13 08:19:07 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-58e238db-bd8c-4de0-9757-eac4886e66cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277690471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2277690471 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.2681910998 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 5012443375 ps |
| CPU time | 91.22 seconds |
| Started | Jul 13 08:17:35 PM PDT 24 |
| Finished | Jul 13 08:19:07 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-a9535dfe-dca5-4856-894f-9dc8c5e49506 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681910998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2681910998 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.348226681 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 44754736 ps |
| CPU time | 6.94 seconds |
| Started | Jul 13 08:17:29 PM PDT 24 |
| Finished | Jul 13 08:17:36 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-a4f94346-501e-427b-a7af-1521bee7fdcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348226681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays. 348226681 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.2716518042 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 334209013 ps |
| CPU time | 29.87 seconds |
| Started | Jul 13 08:17:52 PM PDT 24 |
| Finished | Jul 13 08:18:23 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-9525bdb9-0341-41b8-84cd-366676997ddd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716518042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2716518042 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.2751975021 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 5787885157 ps |
| CPU time | 188.93 seconds |
| Started | Jul 13 08:17:57 PM PDT 24 |
| Finished | Jul 13 08:21:06 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-6120d575-8fae-4780-9251-ae005160ee7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751975021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2751975021 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.552307809 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 1034275722 ps |
| CPU time | 200.13 seconds |
| Started | Jul 13 08:17:54 PM PDT 24 |
| Finished | Jul 13 08:21:14 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-672ebb24-cb9e-41a9-8893-22b91c5fde8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552307809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_w ith_rand_reset.552307809 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.2551315250 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 899344442 ps |
| CPU time | 123.37 seconds |
| Started | Jul 13 08:17:56 PM PDT 24 |
| Finished | Jul 13 08:19:59 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-7c3fe672-b3b6-451e-87f4-0ffa181666a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551315250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.2551315250 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.3767172508 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 710176001 ps |
| CPU time | 33.8 seconds |
| Started | Jul 13 08:17:47 PM PDT 24 |
| Finished | Jul 13 08:18:21 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-c635a0d5-2815-462b-8f23-e7d710f0c169 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767172508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3767172508 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.3309288297 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 509692707 ps |
| CPU time | 35.52 seconds |
| Started | Jul 13 08:31:53 PM PDT 24 |
| Finished | Jul 13 08:32:28 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-b83f42d6-1555-456e-99b6-52fb4f37d606 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309288297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .3309288297 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.2701762776 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 93981447498 ps |
| CPU time | 1859.19 seconds |
| Started | Jul 13 08:31:50 PM PDT 24 |
| Finished | Jul 13 09:02:50 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-600513a9-ea35-401b-bcf8-11482434f518 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701762776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.2701762776 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.3880191056 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 57691149 ps |
| CPU time | 8.83 seconds |
| Started | Jul 13 08:31:52 PM PDT 24 |
| Finished | Jul 13 08:32:01 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-93957d8e-9552-4a82-bc1c-26a54a07f5e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880191056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add r.3880191056 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.3211460996 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 162301445 ps |
| CPU time | 15.24 seconds |
| Started | Jul 13 08:31:53 PM PDT 24 |
| Finished | Jul 13 08:32:09 PM PDT 24 |
| Peak memory | 575000 kb |
| Host | smart-99ebd93b-fbc4-489d-9346-377bf160b473 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211460996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.3211460996 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.255311601 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 2169361949 ps |
| CPU time | 85.39 seconds |
| Started | Jul 13 08:31:41 PM PDT 24 |
| Finished | Jul 13 08:33:07 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-e618ce07-e338-4181-b4c8-12d7b2945844 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255311601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.255311601 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.1982585444 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 27145410575 ps |
| CPU time | 300.93 seconds |
| Started | Jul 13 08:31:40 PM PDT 24 |
| Finished | Jul 13 08:36:42 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-c105a612-16e7-4f76-8117-56dc3028b6dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982585444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.1982585444 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.3843932668 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 37494945838 ps |
| CPU time | 673.67 seconds |
| Started | Jul 13 08:31:42 PM PDT 24 |
| Finished | Jul 13 08:42:56 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-ee3c108a-b342-4c6c-b4e9-c451e06d8d03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843932668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.3843932668 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.1050834747 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 241783803 ps |
| CPU time | 24.02 seconds |
| Started | Jul 13 08:31:42 PM PDT 24 |
| Finished | Jul 13 08:32:07 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-659e610c-73c3-46ea-9817-0c3fe6fc7e3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050834747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del ays.1050834747 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.490243562 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 342099936 ps |
| CPU time | 14.33 seconds |
| Started | Jul 13 08:31:50 PM PDT 24 |
| Finished | Jul 13 08:32:05 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-53b670db-7f08-4074-a71e-140c3d0a79bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490243562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.490243562 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.1016822023 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 260700742 ps |
| CPU time | 11.16 seconds |
| Started | Jul 13 08:31:43 PM PDT 24 |
| Finished | Jul 13 08:31:55 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-43e9f6f3-27e8-426f-b961-d01b615df189 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016822023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.1016822023 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.3907383267 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 9326130155 ps |
| CPU time | 116.37 seconds |
| Started | Jul 13 08:31:53 PM PDT 24 |
| Finished | Jul 13 08:33:50 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-de98417f-cc3b-48fb-b664-60311011b1ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907383267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.3907383267 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.1157713349 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 3649244716 ps |
| CPU time | 66.11 seconds |
| Started | Jul 13 08:31:43 PM PDT 24 |
| Finished | Jul 13 08:32:50 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-5dcd0976-8718-46aa-8f09-b9ef1094a3cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157713349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.1157713349 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.4049140491 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 45355906 ps |
| CPU time | 6.05 seconds |
| Started | Jul 13 08:31:40 PM PDT 24 |
| Finished | Jul 13 08:31:47 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-4f337e16-66e8-48a3-b47b-9c14238f7723 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049140491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay s.4049140491 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.3172535116 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 1072458358 ps |
| CPU time | 107.44 seconds |
| Started | Jul 13 08:31:51 PM PDT 24 |
| Finished | Jul 13 08:33:39 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-0efb98eb-6c64-464b-9d5a-26bba6a2953e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172535116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.3172535116 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.92871489 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 2619972848 ps |
| CPU time | 108.16 seconds |
| Started | Jul 13 08:31:55 PM PDT 24 |
| Finished | Jul 13 08:33:44 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-6b337ed7-6eab-40ea-8c58-23ed490850fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92871489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.92871489 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.3248420413 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 8291909563 ps |
| CPU time | 937.76 seconds |
| Started | Jul 13 08:31:50 PM PDT 24 |
| Finished | Jul 13 08:47:28 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-5aa81f23-bd88-4f40-b0c4-5aeeb187f91f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248420413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.3248420413 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.2514340571 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 2230387568 ps |
| CPU time | 181.49 seconds |
| Started | Jul 13 08:31:55 PM PDT 24 |
| Finished | Jul 13 08:34:57 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-e6a19002-859a-4766-8f3a-b61f67d7aeae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514340571 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al l_with_reset_error.2514340571 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.628566639 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 161641608 ps |
| CPU time | 20 seconds |
| Started | Jul 13 08:31:55 PM PDT 24 |
| Finished | Jul 13 08:32:15 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-afc386bb-da30-4639-b091-f6f1a8bee6c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628566639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.628566639 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.3051951868 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 1345403534 ps |
| CPU time | 73.38 seconds |
| Started | Jul 13 08:32:09 PM PDT 24 |
| Finished | Jul 13 08:33:24 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-1737ab1d-fecd-421b-a74a-1107cc972d8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051951868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .3051951868 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.1395312599 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 20587215102 ps |
| CPU time | 380.96 seconds |
| Started | Jul 13 08:32:00 PM PDT 24 |
| Finished | Jul 13 08:38:21 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-b4611bb5-e3ce-4a8b-b8c1-e7d96fe238c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395312599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.1395312599 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.3306892878 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 85781015 ps |
| CPU time | 12.84 seconds |
| Started | Jul 13 08:31:59 PM PDT 24 |
| Finished | Jul 13 08:32:12 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-c852cfc9-fed9-4fcb-81b2-fa38ebd3756b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306892878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add r.3306892878 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.130754210 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 440780686 ps |
| CPU time | 41.32 seconds |
| Started | Jul 13 08:32:09 PM PDT 24 |
| Finished | Jul 13 08:32:52 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-5310f4fd-ea29-4ab2-8033-0a20e0277beb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130754210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.130754210 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.712131395 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 145546528 ps |
| CPU time | 8.88 seconds |
| Started | Jul 13 08:32:01 PM PDT 24 |
| Finished | Jul 13 08:32:10 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-378ebb06-d118-4f8a-a5e7-109a3f8266e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712131395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.712131395 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.4255129140 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 75820868241 ps |
| CPU time | 881.78 seconds |
| Started | Jul 13 08:32:00 PM PDT 24 |
| Finished | Jul 13 08:46:42 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-59d15415-8a94-4697-887e-b36f7b7dadf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255129140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.4255129140 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.2705596624 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 13361823898 ps |
| CPU time | 237.26 seconds |
| Started | Jul 13 08:31:58 PM PDT 24 |
| Finished | Jul 13 08:35:56 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-e45d86b7-c744-49c4-9191-4df6f5b5f2cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705596624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.2705596624 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.3246460131 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 274431422 ps |
| CPU time | 25.97 seconds |
| Started | Jul 13 08:32:00 PM PDT 24 |
| Finished | Jul 13 08:32:26 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-ec941684-8ca4-4ca2-8086-25f060188a87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246460131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.3246460131 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.761552713 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 1528066216 ps |
| CPU time | 52.32 seconds |
| Started | Jul 13 08:31:59 PM PDT 24 |
| Finished | Jul 13 08:32:52 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-be9232fe-dcfb-490d-83a4-b4f87ec9dea1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761552713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.761552713 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.460091199 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 178842811 ps |
| CPU time | 9.24 seconds |
| Started | Jul 13 08:31:50 PM PDT 24 |
| Finished | Jul 13 08:32:00 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-7344a883-6d0f-4dec-83e1-a443eef31d3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460091199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.460091199 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.1837553013 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 7521603243 ps |
| CPU time | 85.9 seconds |
| Started | Jul 13 08:31:59 PM PDT 24 |
| Finished | Jul 13 08:33:26 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-2c5e37b2-54cb-472e-9fe6-46f4b6e6fe85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837553013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.1837553013 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.26536401 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 5168348997 ps |
| CPU time | 98.3 seconds |
| Started | Jul 13 08:31:58 PM PDT 24 |
| Finished | Jul 13 08:33:36 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-84b84ee4-345c-4942-bbc1-6bb6e0419bbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26536401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.26536401 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.2153637508 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 42368197 ps |
| CPU time | 6.39 seconds |
| Started | Jul 13 08:31:53 PM PDT 24 |
| Finished | Jul 13 08:31:59 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-18b97307-1030-4502-8ed5-3817573b8b0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153637508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.2153637508 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.3600659116 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 17904618471 ps |
| CPU time | 636.95 seconds |
| Started | Jul 13 08:32:10 PM PDT 24 |
| Finished | Jul 13 08:42:48 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-93e994d8-dbe3-42e0-9c0e-c90571140508 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600659116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.3600659116 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.2553072002 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 2514273325 ps |
| CPU time | 242.29 seconds |
| Started | Jul 13 08:32:00 PM PDT 24 |
| Finished | Jul 13 08:36:03 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-a8130efc-e72d-4f49-b452-cfdf75bc0dd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553072002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.2553072002 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.896023560 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 101966469 ps |
| CPU time | 36.14 seconds |
| Started | Jul 13 08:32:00 PM PDT 24 |
| Finished | Jul 13 08:32:37 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-9e9116f3-e1b1-4ab0-86e3-c62d2be45dfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896023560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_ with_rand_reset.896023560 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.3681913089 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 6882432988 ps |
| CPU time | 432.35 seconds |
| Started | Jul 13 08:32:10 PM PDT 24 |
| Finished | Jul 13 08:39:24 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-b41ff213-5904-48dc-85d1-53c17b0344dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681913089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al l_with_reset_error.3681913089 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.3546558882 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 658191990 ps |
| CPU time | 32.29 seconds |
| Started | Jul 13 08:32:01 PM PDT 24 |
| Finished | Jul 13 08:32:33 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-c58efd3c-bb46-41fb-8659-7dedb293e2e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546558882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.3546558882 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.2869439205 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 1547573214 ps |
| CPU time | 71.22 seconds |
| Started | Jul 13 08:32:09 PM PDT 24 |
| Finished | Jul 13 08:33:22 PM PDT 24 |
| Peak memory | 575180 kb |
| Host | smart-981ce211-bfac-4fad-a53a-7c64fa714ae8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869439205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device .2869439205 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.3361948122 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 94395227028 ps |
| CPU time | 1653.62 seconds |
| Started | Jul 13 08:32:10 PM PDT 24 |
| Finished | Jul 13 08:59:45 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-8f46ba6c-1862-4b33-b95d-f3ab87fa5b7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361948122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.3361948122 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.2268074639 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 81269889 ps |
| CPU time | 6.41 seconds |
| Started | Jul 13 08:32:09 PM PDT 24 |
| Finished | Jul 13 08:32:17 PM PDT 24 |
| Peak memory | 573328 kb |
| Host | smart-99f8aa59-aae0-4e99-b4d1-01ec5c38b9b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268074639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.2268074639 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.3947423037 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 2290453913 ps |
| CPU time | 92.72 seconds |
| Started | Jul 13 08:32:09 PM PDT 24 |
| Finished | Jul 13 08:33:43 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-bbe4a963-8da5-44a1-be76-29779eebec02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947423037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.3947423037 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.537799602 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 2660499605 ps |
| CPU time | 113.93 seconds |
| Started | Jul 13 08:32:09 PM PDT 24 |
| Finished | Jul 13 08:34:05 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-684a198a-724d-463d-a3b7-a59dffafb900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537799602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.537799602 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.695366948 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 96651161983 ps |
| CPU time | 1109.34 seconds |
| Started | Jul 13 08:32:09 PM PDT 24 |
| Finished | Jul 13 08:50:39 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-021b964a-5517-4a33-8f1b-28f36bde8536 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695366948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.695366948 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.2235386209 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 59705873547 ps |
| CPU time | 1153.34 seconds |
| Started | Jul 13 08:32:09 PM PDT 24 |
| Finished | Jul 13 08:51:23 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-94bdcbea-4c6d-4540-9a81-5460156b3f65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235386209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.2235386209 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.3098217964 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 270934734 ps |
| CPU time | 27.07 seconds |
| Started | Jul 13 08:32:09 PM PDT 24 |
| Finished | Jul 13 08:32:38 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-3b5763d0-e5e9-441f-8f40-709d6ca47b9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098217964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.3098217964 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.3165809411 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 728598845 ps |
| CPU time | 25.42 seconds |
| Started | Jul 13 08:32:08 PM PDT 24 |
| Finished | Jul 13 08:32:34 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-a8caf472-c1a2-407d-86ac-cc4c7c2e0ff7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165809411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.3165809411 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.1708638286 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 163838795 ps |
| CPU time | 8.68 seconds |
| Started | Jul 13 08:32:01 PM PDT 24 |
| Finished | Jul 13 08:32:10 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-b9fc087b-5119-48cf-85b6-7849e11889a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708638286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.1708638286 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.2884050328 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 6481090973 ps |
| CPU time | 71.34 seconds |
| Started | Jul 13 08:32:10 PM PDT 24 |
| Finished | Jul 13 08:33:23 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-f8a5ec4f-bb68-41c5-8b23-9bf95b68ea63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884050328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.2884050328 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.2915579991 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 4571232035 ps |
| CPU time | 87.72 seconds |
| Started | Jul 13 08:32:08 PM PDT 24 |
| Finished | Jul 13 08:33:37 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-2d43fd8a-4112-4eec-8206-e6ffc6d92d3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915579991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.2915579991 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.4034563972 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 53600587 ps |
| CPU time | 7.46 seconds |
| Started | Jul 13 08:31:59 PM PDT 24 |
| Finished | Jul 13 08:32:07 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-224d6b6d-2e21-4c74-9b96-4472a7defcc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034563972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay s.4034563972 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.1139804140 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 2407635972 ps |
| CPU time | 194.03 seconds |
| Started | Jul 13 08:32:07 PM PDT 24 |
| Finished | Jul 13 08:35:22 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-12151718-9a88-4890-b17a-bb2f265ec986 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139804140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.1139804140 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.1957061214 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 2383124687 ps |
| CPU time | 199.45 seconds |
| Started | Jul 13 08:32:16 PM PDT 24 |
| Finished | Jul 13 08:35:36 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-ce817e5a-9f65-4579-8a55-565236ddc3b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957061214 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.1957061214 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.1651612097 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 5459974514 ps |
| CPU time | 362.25 seconds |
| Started | Jul 13 08:32:08 PM PDT 24 |
| Finished | Jul 13 08:38:11 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-2bda5419-1653-4ab1-b87f-46e1270d6265 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651612097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.1651612097 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.2977770368 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 274181350 ps |
| CPU time | 72.69 seconds |
| Started | Jul 13 08:32:18 PM PDT 24 |
| Finished | Jul 13 08:33:31 PM PDT 24 |
| Peak memory | 575208 kb |
| Host | smart-ff6a3023-d104-4bd0-9b10-cb9e91bce3b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977770368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.2977770368 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.824278839 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 946939522 ps |
| CPU time | 49.29 seconds |
| Started | Jul 13 08:32:09 PM PDT 24 |
| Finished | Jul 13 08:33:00 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-bcf448a3-79b9-4f8d-9484-f3374cba7b29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824278839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.824278839 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.3551942945 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 577010259 ps |
| CPU time | 26.27 seconds |
| Started | Jul 13 08:32:17 PM PDT 24 |
| Finished | Jul 13 08:32:44 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-d655df92-213c-4def-92c7-c57671433f5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551942945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device .3551942945 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.1864743526 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 132571119987 ps |
| CPU time | 2306.96 seconds |
| Started | Jul 13 08:32:17 PM PDT 24 |
| Finished | Jul 13 09:10:45 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-05b0caa6-3f6d-4285-9c64-6aa086e02830 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864743526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.1864743526 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.691546949 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 1352168248 ps |
| CPU time | 52.14 seconds |
| Started | Jul 13 08:32:19 PM PDT 24 |
| Finished | Jul 13 08:33:12 PM PDT 24 |
| Peak memory | 574920 kb |
| Host | smart-24bd6cb0-ea6c-4955-ae99-96647bfb5b6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691546949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_addr .691546949 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.1059138723 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 468632714 ps |
| CPU time | 38.76 seconds |
| Started | Jul 13 08:32:25 PM PDT 24 |
| Finished | Jul 13 08:33:06 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-9d878ea2-4987-4c42-960c-6b9f8c2dcd09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059138723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.1059138723 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.2664533428 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 1326787343 ps |
| CPU time | 50.3 seconds |
| Started | Jul 13 08:32:15 PM PDT 24 |
| Finished | Jul 13 08:33:05 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-df1933eb-73da-4a37-b94c-68eccd70403c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664533428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.2664533428 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.396016850 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 90884953948 ps |
| CPU time | 1115.04 seconds |
| Started | Jul 13 08:32:16 PM PDT 24 |
| Finished | Jul 13 08:50:52 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-81c4d28c-7304-4be4-95ab-8d42789291df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396016850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.396016850 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.1876616099 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 3435492445 ps |
| CPU time | 62 seconds |
| Started | Jul 13 08:32:19 PM PDT 24 |
| Finished | Jul 13 08:33:21 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-69c6429b-6537-4c82-b1e7-3cb709eb50c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876616099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.1876616099 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.1380725391 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 615493489 ps |
| CPU time | 48.66 seconds |
| Started | Jul 13 08:32:17 PM PDT 24 |
| Finished | Jul 13 08:33:06 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-4938b1fe-103f-4e7a-80ea-92af7e1eb029 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380725391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.1380725391 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.1769662394 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 1036481085 ps |
| CPU time | 36.06 seconds |
| Started | Jul 13 08:32:21 PM PDT 24 |
| Finished | Jul 13 08:32:57 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-7249d9e5-8e39-4250-b197-7d97dbb09927 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769662394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.1769662394 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.603814919 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 196094474 ps |
| CPU time | 9.69 seconds |
| Started | Jul 13 08:32:17 PM PDT 24 |
| Finished | Jul 13 08:32:27 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-2fd569d2-ea76-459b-b693-31da6519d8a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603814919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.603814919 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.1431179583 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 5517762638 ps |
| CPU time | 61.43 seconds |
| Started | Jul 13 08:32:18 PM PDT 24 |
| Finished | Jul 13 08:33:20 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-fba3b144-125e-4b3e-b876-8f7d5644f459 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431179583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.1431179583 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.773470250 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 3445237726 ps |
| CPU time | 64.45 seconds |
| Started | Jul 13 08:32:25 PM PDT 24 |
| Finished | Jul 13 08:33:32 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-0bd2c4ff-77ff-43a3-82a9-afc159b5701f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773470250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.773470250 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.2195396425 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 44525281 ps |
| CPU time | 6.28 seconds |
| Started | Jul 13 08:32:16 PM PDT 24 |
| Finished | Jul 13 08:32:23 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-eb80811e-1a8d-45a3-b021-c58a8ef47871 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195396425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay s.2195396425 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.238441214 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 1044854734 ps |
| CPU time | 87.66 seconds |
| Started | Jul 13 08:32:17 PM PDT 24 |
| Finished | Jul 13 08:33:45 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-c91efa31-dc2d-43e5-85e8-5dad2386e197 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238441214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.238441214 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.2145216692 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 1266877820 ps |
| CPU time | 124.53 seconds |
| Started | Jul 13 08:32:20 PM PDT 24 |
| Finished | Jul 13 08:34:26 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-bef4c6d9-8bb3-40bd-9e82-8e7caf084494 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145216692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.2145216692 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.1733063113 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 198880126 ps |
| CPU time | 86.18 seconds |
| Started | Jul 13 08:32:17 PM PDT 24 |
| Finished | Jul 13 08:33:44 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-17e1a689-fd41-41bf-8935-4c7b5a1e4e49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733063113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_rand_reset.1733063113 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.1378452514 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 329658241 ps |
| CPU time | 73.81 seconds |
| Started | Jul 13 08:32:17 PM PDT 24 |
| Finished | Jul 13 08:33:31 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-7941f708-66cc-4909-b51f-efe179e366c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378452514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.1378452514 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.2474966092 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 225843647 ps |
| CPU time | 13.21 seconds |
| Started | Jul 13 08:32:25 PM PDT 24 |
| Finished | Jul 13 08:32:40 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-67e74b1c-d597-4f19-9133-bae46d4197cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474966092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.2474966092 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.3719406650 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 746794081 ps |
| CPU time | 68.01 seconds |
| Started | Jul 13 08:32:25 PM PDT 24 |
| Finished | Jul 13 08:33:35 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-b988ae62-113f-4e3a-a0da-60796acc9fbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719406650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .3719406650 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.1459069071 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 2792143495 ps |
| CPU time | 51.23 seconds |
| Started | Jul 13 08:32:25 PM PDT 24 |
| Finished | Jul 13 08:33:18 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-e7dc237c-0499-436a-9c67-ec22f18e8d5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459069071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.1459069071 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.1537988479 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 655371411 ps |
| CPU time | 28.95 seconds |
| Started | Jul 13 08:32:27 PM PDT 24 |
| Finished | Jul 13 08:32:57 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-ae041779-16fa-42e8-b6b8-edc8e0287703 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537988479 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.1537988479 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.1085379114 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 100506555 ps |
| CPU time | 7.92 seconds |
| Started | Jul 13 08:32:33 PM PDT 24 |
| Finished | Jul 13 08:32:41 PM PDT 24 |
| Peak memory | 574960 kb |
| Host | smart-20cc4682-149c-49ff-a606-0f05818361b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085379114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.1085379114 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.2244185656 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 2019102789 ps |
| CPU time | 87.39 seconds |
| Started | Jul 13 08:32:27 PM PDT 24 |
| Finished | Jul 13 08:33:56 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-c0e4527f-9483-4f4c-927a-69deac81c802 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244185656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.2244185656 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.2336210840 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 113574454008 ps |
| CPU time | 1191.47 seconds |
| Started | Jul 13 08:32:24 PM PDT 24 |
| Finished | Jul 13 08:52:18 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-06cb45e8-055d-40e2-9a43-a5a8a0a8bbf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336210840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.2336210840 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.2636011098 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 21732476599 ps |
| CPU time | 404.06 seconds |
| Started | Jul 13 08:32:26 PM PDT 24 |
| Finished | Jul 13 08:39:12 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-b526c36b-1e8d-4bf2-8762-a57cb1736695 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636011098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.2636011098 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.1098283718 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 376875296 ps |
| CPU time | 36.07 seconds |
| Started | Jul 13 08:32:33 PM PDT 24 |
| Finished | Jul 13 08:33:10 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-2f693a98-37ec-46b3-a9b1-5aa370e47bb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098283718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.1098283718 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.1606420151 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 1571739691 ps |
| CPU time | 51.98 seconds |
| Started | Jul 13 08:32:26 PM PDT 24 |
| Finished | Jul 13 08:33:19 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-c5d6cc49-2c70-46f8-8caa-eb7638a9609b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606420151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.1606420151 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.3578352899 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 204707233 ps |
| CPU time | 9.24 seconds |
| Started | Jul 13 08:32:24 PM PDT 24 |
| Finished | Jul 13 08:32:36 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-92ddf584-113b-43b6-8d2f-593bc43f8b57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578352899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.3578352899 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.3210535979 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 10548523958 ps |
| CPU time | 121.95 seconds |
| Started | Jul 13 08:32:26 PM PDT 24 |
| Finished | Jul 13 08:34:29 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-57c6ecb4-f540-48cf-b368-f473455a69e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210535979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.3210535979 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.1440967996 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 4776757082 ps |
| CPU time | 91.83 seconds |
| Started | Jul 13 08:32:24 PM PDT 24 |
| Finished | Jul 13 08:33:58 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-6027de56-ba96-4172-8587-8a1a0c97bc5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440967996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.1440967996 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.493916936 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 41875006 ps |
| CPU time | 5.97 seconds |
| Started | Jul 13 08:32:24 PM PDT 24 |
| Finished | Jul 13 08:32:30 PM PDT 24 |
| Peak memory | 573948 kb |
| Host | smart-804b0aa5-a24d-47ce-8457-2ce838fdc01e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493916936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delays .493916936 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.1266642284 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 3254349518 ps |
| CPU time | 125.17 seconds |
| Started | Jul 13 08:32:26 PM PDT 24 |
| Finished | Jul 13 08:34:33 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-65b6306b-9aac-478b-9ac5-f754a1db9830 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266642284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.1266642284 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.572932272 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 8717578814 ps |
| CPU time | 384.88 seconds |
| Started | Jul 13 08:32:38 PM PDT 24 |
| Finished | Jul 13 08:39:04 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-5d10308b-9937-4f86-90b3-0beb9bf3b0a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572932272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.572932272 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.246370132 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 6374335491 ps |
| CPU time | 346.63 seconds |
| Started | Jul 13 08:32:32 PM PDT 24 |
| Finished | Jul 13 08:38:19 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-82ac75a7-87c4-4a8e-979b-19c762e3ba8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246370132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_ with_rand_reset.246370132 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.382662077 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 96036236 ps |
| CPU time | 31.65 seconds |
| Started | Jul 13 08:32:36 PM PDT 24 |
| Finished | Jul 13 08:33:08 PM PDT 24 |
| Peak memory | 575196 kb |
| Host | smart-fc3f2ee3-007b-44e7-b6c1-86cf7e242feb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382662077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_reset_error.382662077 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.3751356256 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 189404981 ps |
| CPU time | 26.08 seconds |
| Started | Jul 13 08:32:25 PM PDT 24 |
| Finished | Jul 13 08:32:53 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-782fcbfa-b2dc-4c8f-845a-3b524ff9fce9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751356256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.3751356256 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.840441715 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 1635295133 ps |
| CPU time | 77.5 seconds |
| Started | Jul 13 08:32:36 PM PDT 24 |
| Finished | Jul 13 08:33:54 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-d0839324-8487-4a69-b4a1-2db299065409 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840441715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device. 840441715 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.1082229065 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 47770619925 ps |
| CPU time | 943.05 seconds |
| Started | Jul 13 08:32:39 PM PDT 24 |
| Finished | Jul 13 08:48:22 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-9d349b44-2183-4ab6-8a6c-d68abc293a13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082229065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_ device_slow_rsp.1082229065 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.23099526 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 1041504264 ps |
| CPU time | 41.58 seconds |
| Started | Jul 13 08:32:47 PM PDT 24 |
| Finished | Jul 13 08:33:29 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-5de8cb79-26cd-4e2c-9b4a-725adbb3f02c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23099526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_addr.23099526 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.2925794839 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 383388549 ps |
| CPU time | 30.13 seconds |
| Started | Jul 13 08:32:35 PM PDT 24 |
| Finished | Jul 13 08:33:06 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-f29abdfe-3241-4c78-b5a7-b23db1bb9293 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925794839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.2925794839 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.3780306445 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 296499326 ps |
| CPU time | 14.07 seconds |
| Started | Jul 13 08:32:35 PM PDT 24 |
| Finished | Jul 13 08:32:50 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-35698efa-4c43-4d1b-a7e4-839001242c77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780306445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.3780306445 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.2877811553 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 74709480738 ps |
| CPU time | 869.19 seconds |
| Started | Jul 13 08:32:37 PM PDT 24 |
| Finished | Jul 13 08:47:06 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-0bc9cefc-835c-4bdb-8e91-61a1bc7d9f48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877811553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.2877811553 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.2971373150 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 42996447636 ps |
| CPU time | 748.83 seconds |
| Started | Jul 13 08:32:36 PM PDT 24 |
| Finished | Jul 13 08:45:06 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-35059981-d8a4-4f06-ada9-cd394da92e32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971373150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.2971373150 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.2320650711 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 97530002 ps |
| CPU time | 11.24 seconds |
| Started | Jul 13 08:32:34 PM PDT 24 |
| Finished | Jul 13 08:32:46 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-f275663e-2a96-4609-b85e-6860bf77adad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320650711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.2320650711 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.1416346115 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 2503550917 ps |
| CPU time | 85.1 seconds |
| Started | Jul 13 08:32:35 PM PDT 24 |
| Finished | Jul 13 08:34:00 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-4295b2dd-73eb-4463-b780-757692d643be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416346115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.1416346115 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.2391940436 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 140392966 ps |
| CPU time | 8.4 seconds |
| Started | Jul 13 08:32:36 PM PDT 24 |
| Finished | Jul 13 08:32:45 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-9fa79bf3-fdaf-4ed9-ace6-f98e90756ada |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391940436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.2391940436 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.1395522262 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 6826802895 ps |
| CPU time | 77.71 seconds |
| Started | Jul 13 08:32:37 PM PDT 24 |
| Finished | Jul 13 08:33:55 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-693458c2-4f9d-4575-8326-0836bcc2b857 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395522262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.1395522262 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.3213103558 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 4282904505 ps |
| CPU time | 78.81 seconds |
| Started | Jul 13 08:32:38 PM PDT 24 |
| Finished | Jul 13 08:33:58 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-386e25e1-2645-4a89-aea6-49799785c644 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213103558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.3213103558 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.662863393 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 55805914 ps |
| CPU time | 7.03 seconds |
| Started | Jul 13 08:32:36 PM PDT 24 |
| Finished | Jul 13 08:32:44 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-a51e1f9a-561c-4914-9974-e43688e1c729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662863393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delays .662863393 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.4119463227 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 2762986925 ps |
| CPU time | 115.5 seconds |
| Started | Jul 13 08:32:47 PM PDT 24 |
| Finished | Jul 13 08:34:43 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-af5ab93e-758d-454a-aacb-f153b4169260 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119463227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.4119463227 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.478275748 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 7687564017 ps |
| CPU time | 302.42 seconds |
| Started | Jul 13 08:32:45 PM PDT 24 |
| Finished | Jul 13 08:37:47 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-1b6be636-68e5-4081-b696-9306c64abff2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478275748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.478275748 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1178994242 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 102997230 ps |
| CPU time | 21.76 seconds |
| Started | Jul 13 08:32:52 PM PDT 24 |
| Finished | Jul 13 08:33:14 PM PDT 24 |
| Peak memory | 574956 kb |
| Host | smart-38bf3b8f-46c7-405c-b080-051158cf3db1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178994242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.1178994242 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.3257983595 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 1100335678 ps |
| CPU time | 50.46 seconds |
| Started | Jul 13 08:32:39 PM PDT 24 |
| Finished | Jul 13 08:33:30 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-6407f0b9-a547-4746-9053-a3b084d59ec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257983595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.3257983595 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.3650057515 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 1932865806 ps |
| CPU time | 86.79 seconds |
| Started | Jul 13 08:32:45 PM PDT 24 |
| Finished | Jul 13 08:34:12 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-d5bbe842-dcb0-4814-bdc0-d1a0efadae5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650057515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .3650057515 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.976329810 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 29710790221 ps |
| CPU time | 552.4 seconds |
| Started | Jul 13 08:32:57 PM PDT 24 |
| Finished | Jul 13 08:42:09 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-abb917b2-0350-4679-ab17-cd1124f1627c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976329810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_d evice_slow_rsp.976329810 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.1699141848 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 68130992 ps |
| CPU time | 10.46 seconds |
| Started | Jul 13 08:32:55 PM PDT 24 |
| Finished | Jul 13 08:33:05 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-e70cb4c7-6e56-49e6-b308-d4b7d395e55e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699141848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.1699141848 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.2614398489 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 44007076 ps |
| CPU time | 6.74 seconds |
| Started | Jul 13 08:32:57 PM PDT 24 |
| Finished | Jul 13 08:33:04 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-6683d04a-6d47-4f8b-823b-a7b67a4e1f23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614398489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.2614398489 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.1892230455 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 40214790 ps |
| CPU time | 6.42 seconds |
| Started | Jul 13 08:32:52 PM PDT 24 |
| Finished | Jul 13 08:32:59 PM PDT 24 |
| Peak memory | 575084 kb |
| Host | smart-a0260e51-f9d3-456d-9375-9fce29df8bf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892230455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.1892230455 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.2499437639 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 37319191263 ps |
| CPU time | 412.85 seconds |
| Started | Jul 13 08:32:43 PM PDT 24 |
| Finished | Jul 13 08:39:36 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-6385cf68-93e7-47a8-92b0-aae2a94e92b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499437639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.2499437639 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.2881132188 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 16705398661 ps |
| CPU time | 297.29 seconds |
| Started | Jul 13 08:32:44 PM PDT 24 |
| Finished | Jul 13 08:37:42 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-1125ff0b-2e3b-413d-b6df-b17815bc2089 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881132188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.2881132188 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.3084628596 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 603888533 ps |
| CPU time | 49.2 seconds |
| Started | Jul 13 08:32:53 PM PDT 24 |
| Finished | Jul 13 08:33:42 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-3cc28855-ba05-400e-86cf-c367c921ea67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084628596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del ays.3084628596 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.1560448816 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 1077880390 ps |
| CPU time | 33.68 seconds |
| Started | Jul 13 08:32:56 PM PDT 24 |
| Finished | Jul 13 08:33:30 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-eddb5cb4-d758-4e49-83c8-b1379b01c22d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560448816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.1560448816 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.286942835 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 220178594 ps |
| CPU time | 10.2 seconds |
| Started | Jul 13 08:32:44 PM PDT 24 |
| Finished | Jul 13 08:32:55 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-536fe1bd-0028-4950-ba8e-f34c6a2a2d18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286942835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.286942835 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.22113253 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 8716305170 ps |
| CPU time | 96.18 seconds |
| Started | Jul 13 08:32:46 PM PDT 24 |
| Finished | Jul 13 08:34:22 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-35064683-c3bd-4dd3-a77a-9145ff4185e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22113253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.22113253 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.3425834663 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 5897453374 ps |
| CPU time | 106.99 seconds |
| Started | Jul 13 08:32:52 PM PDT 24 |
| Finished | Jul 13 08:34:40 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-0bddf4a6-f6a2-446c-9bce-389dbc38f991 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425834663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.3425834663 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.3408455714 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 52080682 ps |
| CPU time | 7.54 seconds |
| Started | Jul 13 08:32:45 PM PDT 24 |
| Finished | Jul 13 08:32:53 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-dc8691cc-634d-43ac-b126-1fd04e436b12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408455714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delay s.3408455714 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.3961374603 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 6703479752 ps |
| CPU time | 277.39 seconds |
| Started | Jul 13 08:32:54 PM PDT 24 |
| Finished | Jul 13 08:37:31 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-473a9710-c991-4bfa-aab2-308584ff596e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961374603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.3961374603 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.997973421 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 5444295418 ps |
| CPU time | 201.98 seconds |
| Started | Jul 13 08:32:53 PM PDT 24 |
| Finished | Jul 13 08:36:15 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-25ec9f66-530f-44be-a858-7c95a87c2c65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997973421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.997973421 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.837255767 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 623623599 ps |
| CPU time | 296.58 seconds |
| Started | Jul 13 08:32:55 PM PDT 24 |
| Finished | Jul 13 08:37:52 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-83397550-81d3-4840-b9a4-d027e4f8e299 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837255767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_ with_rand_reset.837255767 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.1906601317 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 1214086531 ps |
| CPU time | 151.44 seconds |
| Started | Jul 13 08:32:53 PM PDT 24 |
| Finished | Jul 13 08:35:25 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-105c9d42-924c-47e3-8cc8-b5c4cc5897ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906601317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.1906601317 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.1194440022 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 381908899 ps |
| CPU time | 20.49 seconds |
| Started | Jul 13 08:32:55 PM PDT 24 |
| Finished | Jul 13 08:33:16 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-82a77ffc-cec6-40ed-9056-c898356b193e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194440022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.1194440022 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.3591407068 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 597424733 ps |
| CPU time | 48.61 seconds |
| Started | Jul 13 08:32:55 PM PDT 24 |
| Finished | Jul 13 08:33:44 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-a2f0d664-5864-4d3b-a2d6-460ed9412961 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591407068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .3591407068 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.3598938847 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 125761920202 ps |
| CPU time | 2302.76 seconds |
| Started | Jul 13 08:33:09 PM PDT 24 |
| Finished | Jul 13 09:11:32 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-d41ac5f4-98e5-4c3e-a6ed-7b5448936011 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598938847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.3598938847 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.2923613598 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 308511823 ps |
| CPU time | 16.41 seconds |
| Started | Jul 13 08:33:02 PM PDT 24 |
| Finished | Jul 13 08:33:19 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-a6ee18fc-0930-4324-9681-a8b722bdac4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923613598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add r.2923613598 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.3074919769 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 512608132 ps |
| CPU time | 41.35 seconds |
| Started | Jul 13 08:33:02 PM PDT 24 |
| Finished | Jul 13 08:33:44 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-d98696b5-7e43-4bd9-a586-1f9af2ae4310 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074919769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.3074919769 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.489670862 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 140756725 ps |
| CPU time | 9.93 seconds |
| Started | Jul 13 08:32:56 PM PDT 24 |
| Finished | Jul 13 08:33:07 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-31b9c02e-2348-438b-98df-8d4f53febb8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489670862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.489670862 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.3130692733 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 80326523172 ps |
| CPU time | 1004.11 seconds |
| Started | Jul 13 08:32:56 PM PDT 24 |
| Finished | Jul 13 08:49:40 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-2196259d-4527-424a-ac5a-358b08a33b29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130692733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.3130692733 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.1790151506 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 55016728877 ps |
| CPU time | 1004.48 seconds |
| Started | Jul 13 08:32:53 PM PDT 24 |
| Finished | Jul 13 08:49:38 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-a0840229-c673-414b-8a89-dc4abe426b58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790151506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.1790151506 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.2253242823 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 570825426 ps |
| CPU time | 55.23 seconds |
| Started | Jul 13 08:32:55 PM PDT 24 |
| Finished | Jul 13 08:33:51 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-f0c2b1e7-86af-4406-b65a-70cd7ef751d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253242823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.2253242823 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.3940643861 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 2324607336 ps |
| CPU time | 75.59 seconds |
| Started | Jul 13 08:33:03 PM PDT 24 |
| Finished | Jul 13 08:34:19 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-c3f3b1ff-0345-45be-a569-f99d1a781898 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940643861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.3940643861 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.1041674110 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 192602377 ps |
| CPU time | 9.53 seconds |
| Started | Jul 13 08:32:53 PM PDT 24 |
| Finished | Jul 13 08:33:03 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-cabd0b01-835e-4a9c-99f7-fb937228d4d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041674110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.1041674110 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.1675633655 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 7142752467 ps |
| CPU time | 80.83 seconds |
| Started | Jul 13 08:32:51 PM PDT 24 |
| Finished | Jul 13 08:34:12 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-a0485f74-1d44-4c84-b7f9-b479bef5908c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675633655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.1675633655 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.432308751 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 5385300289 ps |
| CPU time | 95.22 seconds |
| Started | Jul 13 08:32:55 PM PDT 24 |
| Finished | Jul 13 08:34:31 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-bc7c90e0-0f8f-4972-8dc9-7204c8482fc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432308751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.432308751 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.3032743155 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 41491365 ps |
| CPU time | 6.21 seconds |
| Started | Jul 13 08:32:53 PM PDT 24 |
| Finished | Jul 13 08:33:00 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-5dc360f3-dae6-43be-9b6b-b0633ba7b0a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032743155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay s.3032743155 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.2160513391 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 611151098 ps |
| CPU time | 58.19 seconds |
| Started | Jul 13 08:33:08 PM PDT 24 |
| Finished | Jul 13 08:34:07 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-27591151-57dd-47ae-876b-49c4902847ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160513391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.2160513391 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.2427382235 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 5834931 ps |
| CPU time | 3.85 seconds |
| Started | Jul 13 08:33:08 PM PDT 24 |
| Finished | Jul 13 08:33:12 PM PDT 24 |
| Peak memory | 565712 kb |
| Host | smart-efeb0a87-e263-4daa-91a4-841c5d898d99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427382235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.2427382235 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.3490519887 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 4330205469 ps |
| CPU time | 583.32 seconds |
| Started | Jul 13 08:33:04 PM PDT 24 |
| Finished | Jul 13 08:42:48 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-5874e12e-0676-49a8-882a-af65ca1fcd05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490519887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_rand_reset.3490519887 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.2109097184 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 77870013 ps |
| CPU time | 17.97 seconds |
| Started | Jul 13 08:33:04 PM PDT 24 |
| Finished | Jul 13 08:33:23 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-ce879682-ab76-4deb-aa7c-fa22b214aef6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109097184 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.2109097184 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.4126337479 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 450869718 ps |
| CPU time | 22.4 seconds |
| Started | Jul 13 08:33:02 PM PDT 24 |
| Finished | Jul 13 08:33:24 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-a5645e38-d2be-4892-884b-3fe5a98d98ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126337479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.4126337479 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.2937372333 |
| Short name | T2909 |
| Test name | |
| Test status | |
| Simulation time | 3434612777 ps |
| CPU time | 163.42 seconds |
| Started | Jul 13 08:33:10 PM PDT 24 |
| Finished | Jul 13 08:35:54 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-19c9018c-5a9f-4fe2-932c-64923f4ada63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937372333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device .2937372333 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2537360872 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 43739783420 ps |
| CPU time | 825.13 seconds |
| Started | Jul 13 08:33:11 PM PDT 24 |
| Finished | Jul 13 08:46:57 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-133acb62-c9f4-4bb3-8a36-883658d6dc60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537360872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_ device_slow_rsp.2537360872 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.2301915744 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 188108430 ps |
| CPU time | 22.61 seconds |
| Started | Jul 13 08:33:11 PM PDT 24 |
| Finished | Jul 13 08:33:34 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-60f243b3-c76f-4b54-811e-eecafc9c70c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301915744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.2301915744 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.623449943 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 155850551 ps |
| CPU time | 15.97 seconds |
| Started | Jul 13 08:33:12 PM PDT 24 |
| Finished | Jul 13 08:33:29 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-e8bb50ec-e147-43a3-94f2-fe68e2164391 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623449943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.623449943 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.1761668421 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 78739763 ps |
| CPU time | 7.12 seconds |
| Started | Jul 13 08:33:09 PM PDT 24 |
| Finished | Jul 13 08:33:17 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-c4730f23-4f41-4a8d-bf86-5b2e0d24d892 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761668421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.1761668421 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.363505754 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 63765185070 ps |
| CPU time | 764.01 seconds |
| Started | Jul 13 08:33:10 PM PDT 24 |
| Finished | Jul 13 08:45:55 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-5cdd7d1a-ac97-4a84-90f5-8f09cec19176 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363505754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.363505754 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.4185745667 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 1754540187 ps |
| CPU time | 31.05 seconds |
| Started | Jul 13 08:33:12 PM PDT 24 |
| Finished | Jul 13 08:33:43 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-7c5ac47f-fa67-4ba1-96dd-f3d40478d2f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185745667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.4185745667 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.2016367844 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 173082288 ps |
| CPU time | 18.9 seconds |
| Started | Jul 13 08:33:12 PM PDT 24 |
| Finished | Jul 13 08:33:32 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-bce6ca4a-072c-4c12-b089-3e7777da02e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016367844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.2016367844 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.1506619451 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 731197885 ps |
| CPU time | 26.66 seconds |
| Started | Jul 13 08:33:11 PM PDT 24 |
| Finished | Jul 13 08:33:38 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-5885b38a-15a5-40ac-9111-19447aaac8d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506619451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.1506619451 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.2770841875 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 176654403 ps |
| CPU time | 9.04 seconds |
| Started | Jul 13 08:33:03 PM PDT 24 |
| Finished | Jul 13 08:33:13 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-48fd2c3b-53e8-4694-a2db-2c628b42ea80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770841875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.2770841875 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.3965337948 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 10930249407 ps |
| CPU time | 120.27 seconds |
| Started | Jul 13 08:33:02 PM PDT 24 |
| Finished | Jul 13 08:35:03 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-1c8d01ff-a522-44bb-a403-6addbce6e77a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965337948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.3965337948 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.14805852 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 6258146043 ps |
| CPU time | 120.59 seconds |
| Started | Jul 13 08:33:03 PM PDT 24 |
| Finished | Jul 13 08:35:04 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-a7c69f3a-6ace-437c-8513-2bef16858c2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14805852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.14805852 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.4118754358 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 46900103 ps |
| CPU time | 6.86 seconds |
| Started | Jul 13 08:33:04 PM PDT 24 |
| Finished | Jul 13 08:33:11 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-c113adc8-297e-4929-b636-5772926053e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118754358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.4118754358 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.527451543 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 9347869691 ps |
| CPU time | 417.54 seconds |
| Started | Jul 13 08:33:24 PM PDT 24 |
| Finished | Jul 13 08:40:23 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-896378d3-972a-4e78-add6-c0727afe7ced |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527451543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.527451543 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.3255629532 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 12732458410 ps |
| CPU time | 443.86 seconds |
| Started | Jul 13 08:33:24 PM PDT 24 |
| Finished | Jul 13 08:40:48 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-54d4db1d-734d-4da8-83a2-7b48f851677e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255629532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.3255629532 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.3725237565 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 602201704 ps |
| CPU time | 284.96 seconds |
| Started | Jul 13 08:33:25 PM PDT 24 |
| Finished | Jul 13 08:38:11 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-9058a5ca-6b50-46d0-821d-c760d1709020 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725237565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.3725237565 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1019429122 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 277200218 ps |
| CPU time | 112.47 seconds |
| Started | Jul 13 08:33:24 PM PDT 24 |
| Finished | Jul 13 08:35:17 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-cfacd636-1457-496b-b4ec-9eaef35187c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019429122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al l_with_reset_error.1019429122 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.197731707 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 124601397 ps |
| CPU time | 17.3 seconds |
| Started | Jul 13 08:33:11 PM PDT 24 |
| Finished | Jul 13 08:33:28 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-9235dfc1-49fc-4707-8245-b30f79ae97d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197731707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.197731707 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.356205691 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 1038198748 ps |
| CPU time | 52.49 seconds |
| Started | Jul 13 08:33:26 PM PDT 24 |
| Finished | Jul 13 08:34:19 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-bd8eed22-6dc7-4250-a252-be665a296b34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356205691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device. 356205691 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.526289213 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 101906360649 ps |
| CPU time | 1851.98 seconds |
| Started | Jul 13 08:33:25 PM PDT 24 |
| Finished | Jul 13 09:04:18 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-dc58e78a-5f13-49c7-b6a8-393c7f4271a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526289213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_d evice_slow_rsp.526289213 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.2212698261 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 23584328 ps |
| CPU time | 5.71 seconds |
| Started | Jul 13 08:33:44 PM PDT 24 |
| Finished | Jul 13 08:33:50 PM PDT 24 |
| Peak memory | 575204 kb |
| Host | smart-7b9b9f1d-ce0d-49d4-a723-23f487007556 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212698261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.2212698261 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.478041809 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 118805315 ps |
| CPU time | 13.16 seconds |
| Started | Jul 13 08:33:35 PM PDT 24 |
| Finished | Jul 13 08:33:48 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-cec51843-6940-4db9-9240-7c10dd0359f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478041809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.478041809 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.2545018936 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 1063089207 ps |
| CPU time | 45.13 seconds |
| Started | Jul 13 08:33:26 PM PDT 24 |
| Finished | Jul 13 08:34:12 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-62ceddd0-e0b5-4462-8f0c-796ec8ddc68b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545018936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.2545018936 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.587996349 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 66425806924 ps |
| CPU time | 739.62 seconds |
| Started | Jul 13 08:33:27 PM PDT 24 |
| Finished | Jul 13 08:45:47 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-4cc742ad-a5e0-41e5-953b-7d53a24d1d74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587996349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.587996349 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.958953080 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 21759116848 ps |
| CPU time | 405.98 seconds |
| Started | Jul 13 08:33:24 PM PDT 24 |
| Finished | Jul 13 08:40:12 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-82277a64-80af-438d-9fe3-eeb45556d1c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958953080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.958953080 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.1982702642 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 187890072 ps |
| CPU time | 19.61 seconds |
| Started | Jul 13 08:33:24 PM PDT 24 |
| Finished | Jul 13 08:33:45 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-112cb45d-8ce0-476a-b426-339ebb0553b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982702642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del ays.1982702642 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.610841771 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 237613199 ps |
| CPU time | 21.41 seconds |
| Started | Jul 13 08:33:33 PM PDT 24 |
| Finished | Jul 13 08:33:55 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-5549b0aa-c7cf-4413-a1ed-8af81c083c07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610841771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.610841771 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.105883397 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 47189040 ps |
| CPU time | 7.12 seconds |
| Started | Jul 13 08:33:27 PM PDT 24 |
| Finished | Jul 13 08:33:34 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-2555042c-ad45-4a1e-923a-aa2b0399edaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105883397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.105883397 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.2711069492 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 7629287939 ps |
| CPU time | 87.24 seconds |
| Started | Jul 13 08:33:26 PM PDT 24 |
| Finished | Jul 13 08:34:54 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-983a5713-dfd7-4e2f-9554-b6f48fefa1d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711069492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.2711069492 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.2221313262 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 5406523565 ps |
| CPU time | 101.53 seconds |
| Started | Jul 13 08:33:25 PM PDT 24 |
| Finished | Jul 13 08:35:07 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-e69b9de3-7465-4f8c-bc50-862f54ea5bde |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221313262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.2221313262 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.2605175973 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 50626353 ps |
| CPU time | 7.37 seconds |
| Started | Jul 13 08:33:24 PM PDT 24 |
| Finished | Jul 13 08:33:33 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-0afd0d24-a969-495b-9431-7d94fa086f8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605175973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.2605175973 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.2473714562 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 2686471252 ps |
| CPU time | 205.47 seconds |
| Started | Jul 13 08:33:43 PM PDT 24 |
| Finished | Jul 13 08:37:09 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-5d16b38c-eaab-4394-bf0c-a9a2d1019713 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473714562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.2473714562 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.1747638602 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 285006531 ps |
| CPU time | 31.67 seconds |
| Started | Jul 13 08:33:36 PM PDT 24 |
| Finished | Jul 13 08:34:08 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-e52eb247-b326-4b44-a794-5e130956f284 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747638602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.1747638602 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.523835246 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 10430233772 ps |
| CPU time | 617.93 seconds |
| Started | Jul 13 08:33:33 PM PDT 24 |
| Finished | Jul 13 08:43:51 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-7421bb38-a046-4a1b-938d-fedd0684a76d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523835246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_ with_rand_reset.523835246 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.2714039269 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 18413004287 ps |
| CPU time | 851.42 seconds |
| Started | Jul 13 08:33:33 PM PDT 24 |
| Finished | Jul 13 08:47:45 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-77ec9512-09ed-4370-8479-216209d26d83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714039269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.2714039269 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.678207652 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 1201171093 ps |
| CPU time | 49.36 seconds |
| Started | Jul 13 08:33:44 PM PDT 24 |
| Finished | Jul 13 08:34:34 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-c2a1f902-6c95-474c-8860-c64e35491930 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678207652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.678207652 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.99777381 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 5449316892 ps |
| CPU time | 810.7 seconds |
| Started | Jul 13 08:18:26 PM PDT 24 |
| Finished | Jul 13 08:31:57 PM PDT 24 |
| Peak memory | 598920 kb |
| Host | smart-550b04d7-73c0-442f-b05f-3bacb8f11f7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99777381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.99777381 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.3725095271 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 28911118526 ps |
| CPU time | 3872.59 seconds |
| Started | Jul 13 08:18:02 PM PDT 24 |
| Finished | Jul 13 09:22:35 PM PDT 24 |
| Peak memory | 593028 kb |
| Host | smart-c36e8a2c-b50b-44ab-830d-95e0eb45ba24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725095271 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.3725095271 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.1380947583 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 3531803184 ps |
| CPU time | 235.02 seconds |
| Started | Jul 13 08:18:01 PM PDT 24 |
| Finished | Jul 13 08:21:57 PM PDT 24 |
| Peak memory | 598676 kb |
| Host | smart-239735f4-2262-4424-8b76-c45681fa1e39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380947583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.1380947583 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.3441608171 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 549388891 ps |
| CPU time | 30.3 seconds |
| Started | Jul 13 08:18:16 PM PDT 24 |
| Finished | Jul 13 08:18:47 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-0ba155f1-eec5-43be-b60c-9676894bed8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441608171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 3441608171 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.1237860931 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 67172108260 ps |
| CPU time | 1210.84 seconds |
| Started | Jul 13 08:18:12 PM PDT 24 |
| Finished | Jul 13 08:38:24 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-fb30bd7f-ba79-4874-badb-6f82d43eada1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237860931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_d evice_slow_rsp.1237860931 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.3445135213 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 1311565457 ps |
| CPU time | 56.85 seconds |
| Started | Jul 13 08:18:13 PM PDT 24 |
| Finished | Jul 13 08:19:11 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-b648745c-b697-41e4-aea9-29d03bf6a395 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445135213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr .3445135213 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.3020573613 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 284701591 ps |
| CPU time | 28.92 seconds |
| Started | Jul 13 08:18:15 PM PDT 24 |
| Finished | Jul 13 08:18:44 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-8215dbca-e2c5-44c8-a609-9230e0717fee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020573613 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3020573613 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.4188784463 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 1231035715 ps |
| CPU time | 55.46 seconds |
| Started | Jul 13 08:18:06 PM PDT 24 |
| Finished | Jul 13 08:19:02 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-0ff08b62-6ca7-4735-8bfb-5823ebee28eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188784463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.4188784463 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.4011073254 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 66630875674 ps |
| CPU time | 743.61 seconds |
| Started | Jul 13 08:18:12 PM PDT 24 |
| Finished | Jul 13 08:30:36 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-1fb76c77-912d-4fe2-b630-2c5862cabe34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011073254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.4011073254 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.3377423589 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 17862909390 ps |
| CPU time | 339.35 seconds |
| Started | Jul 13 08:18:13 PM PDT 24 |
| Finished | Jul 13 08:23:52 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-58c82111-742f-4fa7-abe0-aee9e860ca5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377423589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3377423589 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.4054689424 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 42086503 ps |
| CPU time | 6.82 seconds |
| Started | Jul 13 08:18:11 PM PDT 24 |
| Finished | Jul 13 08:18:19 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-1776fd92-9b0f-4f92-95a8-ba60ebb7ff24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054689424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.4054689424 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.726669289 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1580395694 ps |
| CPU time | 58.45 seconds |
| Started | Jul 13 08:18:13 PM PDT 24 |
| Finished | Jul 13 08:19:11 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-ccc437a4-0564-4788-aded-401395514d54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726669289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.726669289 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.1614656367 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 54217123 ps |
| CPU time | 7.69 seconds |
| Started | Jul 13 08:17:59 PM PDT 24 |
| Finished | Jul 13 08:18:07 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-c65a90b6-4151-4295-ae88-bea8923a90fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614656367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1614656367 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.1059733761 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 7128791236 ps |
| CPU time | 86.55 seconds |
| Started | Jul 13 08:18:02 PM PDT 24 |
| Finished | Jul 13 08:19:29 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-4a6ca7c4-1805-4490-9ab1-7d2e40a841a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059733761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1059733761 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3515693006 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 3766922619 ps |
| CPU time | 74.11 seconds |
| Started | Jul 13 08:18:03 PM PDT 24 |
| Finished | Jul 13 08:19:17 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-927afc6b-92d7-4d97-a1ad-e46bc474925b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515693006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3515693006 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.2536583873 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 46580096 ps |
| CPU time | 6.54 seconds |
| Started | Jul 13 08:18:01 PM PDT 24 |
| Finished | Jul 13 08:18:08 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-ac68a127-4c6b-4887-b556-80f8dc8f5653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536583873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .2536583873 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.1896356063 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 13851873206 ps |
| CPU time | 586.15 seconds |
| Started | Jul 13 08:18:24 PM PDT 24 |
| Finished | Jul 13 08:28:10 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-14164941-04cf-4417-b409-f3cd20fa8522 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896356063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1896356063 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.3648615503 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 6025096649 ps |
| CPU time | 281.71 seconds |
| Started | Jul 13 08:18:25 PM PDT 24 |
| Finished | Jul 13 08:23:07 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-4c0c46f7-2b22-4d6a-af15-672e5ddceef3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648615503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3648615503 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.2067314358 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 60417962 ps |
| CPU time | 24.25 seconds |
| Started | Jul 13 08:18:27 PM PDT 24 |
| Finished | Jul 13 08:18:52 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-a944e7dd-1d68-4606-aad3-6820f7bbd11f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067314358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_rand_reset.2067314358 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.1156616187 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 799866038 ps |
| CPU time | 160.9 seconds |
| Started | Jul 13 08:18:25 PM PDT 24 |
| Finished | Jul 13 08:21:07 PM PDT 24 |
| Peak memory | 575188 kb |
| Host | smart-42f4a94e-b143-4c0d-b87e-019096101e64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156616187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.1156616187 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.3339687351 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 760703820 ps |
| CPU time | 34.32 seconds |
| Started | Jul 13 08:18:13 PM PDT 24 |
| Finished | Jul 13 08:18:48 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-e683a68b-44e1-458a-ba80-28c4dbf48988 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339687351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.3339687351 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.1077188733 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 122197199 ps |
| CPU time | 11.1 seconds |
| Started | Jul 13 08:33:32 PM PDT 24 |
| Finished | Jul 13 08:33:44 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-a593fbd9-3258-4ced-9799-603ad9962ef3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077188733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .1077188733 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.204085507 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 16809618177 ps |
| CPU time | 319.5 seconds |
| Started | Jul 13 08:33:44 PM PDT 24 |
| Finished | Jul 13 08:39:05 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-efd82339-dd8e-479c-a26b-bc1527825d43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204085507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_d evice_slow_rsp.204085507 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2415255480 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 330312387 ps |
| CPU time | 15.82 seconds |
| Started | Jul 13 08:33:49 PM PDT 24 |
| Finished | Jul 13 08:34:05 PM PDT 24 |
| Peak memory | 575080 kb |
| Host | smart-99821291-0326-400a-a7c5-39e8e49b3c8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415255480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add r.2415255480 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.1136170267 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 539791136 ps |
| CPU time | 20.48 seconds |
| Started | Jul 13 08:33:35 PM PDT 24 |
| Finished | Jul 13 08:33:56 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-0ddad4f7-d8eb-43da-9481-93f11bf7e62e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136170267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.1136170267 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.1484853040 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 93917406409 ps |
| CPU time | 1032.34 seconds |
| Started | Jul 13 08:33:34 PM PDT 24 |
| Finished | Jul 13 08:50:47 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-8db1d884-788d-42c4-b63e-c98ae710b45d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484853040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.1484853040 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.2336127202 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 62478598967 ps |
| CPU time | 1090.93 seconds |
| Started | Jul 13 08:33:33 PM PDT 24 |
| Finished | Jul 13 08:51:45 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-c3b356e1-59c7-4116-b7dc-b3be072bf858 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336127202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.2336127202 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.1010979597 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 476240169 ps |
| CPU time | 49.4 seconds |
| Started | Jul 13 08:33:36 PM PDT 24 |
| Finished | Jul 13 08:34:26 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-b90513ec-23cf-440f-a6a4-403ba4884017 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010979597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.1010979597 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.589642466 |
| Short name | T2908 |
| Test name | |
| Test status | |
| Simulation time | 166915985 ps |
| CPU time | 7.91 seconds |
| Started | Jul 13 08:33:40 PM PDT 24 |
| Finished | Jul 13 08:33:48 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-9754ce28-1fba-41b9-b47d-dc8eff976f99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589642466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.589642466 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.1693332129 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 244233413 ps |
| CPU time | 10.76 seconds |
| Started | Jul 13 08:33:43 PM PDT 24 |
| Finished | Jul 13 08:33:54 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-822dc58d-61f4-438e-9574-25474bd06a5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693332129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.1693332129 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.2153972693 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 7650474653 ps |
| CPU time | 88.73 seconds |
| Started | Jul 13 08:33:34 PM PDT 24 |
| Finished | Jul 13 08:35:03 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-f55adf97-2ee2-46e7-9c00-b8b763831594 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153972693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.2153972693 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.2216233431 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 4988415688 ps |
| CPU time | 90.58 seconds |
| Started | Jul 13 08:33:34 PM PDT 24 |
| Finished | Jul 13 08:35:05 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-b6676ecd-46cd-4867-b3d6-3d81c67c191f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216233431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.2216233431 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.3026983818 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 42365323 ps |
| CPU time | 6.62 seconds |
| Started | Jul 13 08:33:35 PM PDT 24 |
| Finished | Jul 13 08:33:42 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-b15d6f26-f801-416f-9653-26aabfa531b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026983818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.3026983818 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.1264628570 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 4683935759 ps |
| CPU time | 166.94 seconds |
| Started | Jul 13 08:33:45 PM PDT 24 |
| Finished | Jul 13 08:36:33 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-821c8ba4-b780-4b5a-91c6-600bce8a5bad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264628570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.1264628570 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.2822407267 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 1463729115 ps |
| CPU time | 129.12 seconds |
| Started | Jul 13 08:33:46 PM PDT 24 |
| Finished | Jul 13 08:35:55 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-f12b9dbf-8b0a-42be-90d5-2f8a869ce8e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822407267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.2822407267 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.3306222893 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 299112260 ps |
| CPU time | 100.11 seconds |
| Started | Jul 13 08:33:44 PM PDT 24 |
| Finished | Jul 13 08:35:25 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-e65ac5e5-a891-44d6-aad3-3a7e86202b8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306222893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.3306222893 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.3515536947 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 147680949 ps |
| CPU time | 9.76 seconds |
| Started | Jul 13 08:33:38 PM PDT 24 |
| Finished | Jul 13 08:33:47 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-7e9003f0-cb1c-4a6c-ba5d-2a103694cadc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515536947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.3515536947 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.1999002859 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 2050700896 ps |
| CPU time | 85.02 seconds |
| Started | Jul 13 08:33:59 PM PDT 24 |
| Finished | Jul 13 08:35:24 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-5b05c6ed-c92d-4b90-9d58-3f914718ec44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999002859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .1999002859 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.1857358115 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 123446051434 ps |
| CPU time | 2339.96 seconds |
| Started | Jul 13 08:33:59 PM PDT 24 |
| Finished | Jul 13 09:12:59 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-9876e7ea-44f4-4bc8-9ace-bc135e9d9b7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857358115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.1857358115 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.3272817038 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 1391937607 ps |
| CPU time | 58.25 seconds |
| Started | Jul 13 08:33:54 PM PDT 24 |
| Finished | Jul 13 08:34:52 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-37c84904-6a47-44e2-8e05-0825549256ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272817038 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.3272817038 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.1294516957 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 2140165314 ps |
| CPU time | 73.86 seconds |
| Started | Jul 13 08:33:55 PM PDT 24 |
| Finished | Jul 13 08:35:10 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-be389b4d-216c-41f4-ad45-746d319a4416 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294516957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.1294516957 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.3411734244 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 121317646 ps |
| CPU time | 13.28 seconds |
| Started | Jul 13 08:33:49 PM PDT 24 |
| Finished | Jul 13 08:34:02 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-1b83b45d-0c4f-4f66-8c1f-087d0a00821d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411734244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.3411734244 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.510895840 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 12374801096 ps |
| CPU time | 150.45 seconds |
| Started | Jul 13 08:33:58 PM PDT 24 |
| Finished | Jul 13 08:36:29 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-3d439aff-c2a4-4ae3-8ec9-9ea5f76b5e32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510895840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.510895840 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.382855612 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 599430038 ps |
| CPU time | 49.74 seconds |
| Started | Jul 13 08:33:45 PM PDT 24 |
| Finished | Jul 13 08:34:35 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-aeac5ce3-1a26-4a1f-8b83-07c1a5bdcecf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382855612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_dela ys.382855612 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.3540805746 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 320620644 ps |
| CPU time | 13.13 seconds |
| Started | Jul 13 08:33:58 PM PDT 24 |
| Finished | Jul 13 08:34:12 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-832e13d5-ffd6-40dd-998d-0aab7a1a5d50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540805746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.3540805746 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.3271423424 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 233795866 ps |
| CPU time | 9.72 seconds |
| Started | Jul 13 08:33:44 PM PDT 24 |
| Finished | Jul 13 08:33:54 PM PDT 24 |
| Peak memory | 573996 kb |
| Host | smart-6fdb57e0-6ed1-4a1f-a265-b073db45d357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271423424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.3271423424 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.1442944670 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 4999023820 ps |
| CPU time | 59.32 seconds |
| Started | Jul 13 08:33:45 PM PDT 24 |
| Finished | Jul 13 08:34:45 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-f3e3c5d4-a1b8-4a2d-8276-8c3817996657 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442944670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.1442944670 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.2881794235 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 3544840924 ps |
| CPU time | 70.1 seconds |
| Started | Jul 13 08:33:58 PM PDT 24 |
| Finished | Jul 13 08:35:09 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-e5d9caef-2726-4643-b07f-01b130af2c05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881794235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.2881794235 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.1920022653 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 45652360 ps |
| CPU time | 6.51 seconds |
| Started | Jul 13 08:33:58 PM PDT 24 |
| Finished | Jul 13 08:34:05 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-52339ff2-f5f3-460b-af2b-fd26171a38ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920022653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.1920022653 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.2334302540 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 7555913545 ps |
| CPU time | 289.13 seconds |
| Started | Jul 13 08:33:57 PM PDT 24 |
| Finished | Jul 13 08:38:46 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-a47d7108-56c8-433a-9dbd-31f73ba12262 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334302540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.2334302540 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.212028000 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 13724175758 ps |
| CPU time | 566.22 seconds |
| Started | Jul 13 08:33:58 PM PDT 24 |
| Finished | Jul 13 08:43:25 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-168aafe8-7183-480d-a4d8-948c8aaf5c73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212028000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.212028000 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.1336252718 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 1046418713 ps |
| CPU time | 385.23 seconds |
| Started | Jul 13 08:33:53 PM PDT 24 |
| Finished | Jul 13 08:40:19 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-8f4fdf98-c810-440a-8208-f6e77bfc8f72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336252718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.1336252718 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.1755504155 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 690772703 ps |
| CPU time | 252.26 seconds |
| Started | Jul 13 08:33:54 PM PDT 24 |
| Finished | Jul 13 08:38:06 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-6f19cc9a-a8ca-464c-93fc-a6e7cd61b886 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755504155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.1755504155 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.467355344 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 225476557 ps |
| CPU time | 30.68 seconds |
| Started | Jul 13 08:33:55 PM PDT 24 |
| Finished | Jul 13 08:34:26 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-21743e1e-2e7e-4937-8016-11be2ae46dbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467355344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.467355344 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.1270893608 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 162552555 ps |
| CPU time | 15.96 seconds |
| Started | Jul 13 08:33:56 PM PDT 24 |
| Finished | Jul 13 08:34:13 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-8bd8f8a4-7f00-40d9-8e72-65f94bf36a33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270893608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .1270893608 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.3218475554 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 162862309306 ps |
| CPU time | 3112.86 seconds |
| Started | Jul 13 08:33:55 PM PDT 24 |
| Finished | Jul 13 09:25:49 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-5003ce32-8559-4905-8f8b-f7eb1c9a5d17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218475554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_ device_slow_rsp.3218475554 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.1180091636 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 33119894 ps |
| CPU time | 7.41 seconds |
| Started | Jul 13 08:34:03 PM PDT 24 |
| Finished | Jul 13 08:34:11 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-c9cb67b6-5a82-41b7-8591-95a1b6808d1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180091636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.1180091636 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.1164577487 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 704756583 ps |
| CPU time | 30.74 seconds |
| Started | Jul 13 08:34:02 PM PDT 24 |
| Finished | Jul 13 08:34:33 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-92a0f660-a943-45be-a6c0-d3b7854c75f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164577487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.1164577487 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.3758921286 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 573147484 ps |
| CPU time | 52.36 seconds |
| Started | Jul 13 08:33:55 PM PDT 24 |
| Finished | Jul 13 08:34:47 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-6b978c94-fa44-4462-b8c4-608fc3c01008 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758921286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.3758921286 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.2163082924 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 53986750281 ps |
| CPU time | 597.2 seconds |
| Started | Jul 13 08:33:54 PM PDT 24 |
| Finished | Jul 13 08:43:52 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-7c0666ed-29c9-4ede-be90-a78ad7362196 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163082924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.2163082924 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.1944814676 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 43890026267 ps |
| CPU time | 791.77 seconds |
| Started | Jul 13 08:33:57 PM PDT 24 |
| Finished | Jul 13 08:47:10 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-64699182-06e2-42b7-aacd-535350f818e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944814676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.1944814676 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.196835044 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 79352004 ps |
| CPU time | 10.27 seconds |
| Started | Jul 13 08:33:55 PM PDT 24 |
| Finished | Jul 13 08:34:06 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-763af6cf-1aa3-4c7e-9103-87a5c7d6b4ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196835044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_dela ys.196835044 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.2664965546 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 684146833 ps |
| CPU time | 25.41 seconds |
| Started | Jul 13 08:33:54 PM PDT 24 |
| Finished | Jul 13 08:34:20 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-30c88cc3-b603-49ee-a524-7c3c9d4d450a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664965546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.2664965546 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.1558206463 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 44595658 ps |
| CPU time | 6.22 seconds |
| Started | Jul 13 08:33:53 PM PDT 24 |
| Finished | Jul 13 08:34:00 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-07d598c1-f0f9-4170-8b2e-bfc3283582d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558206463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.1558206463 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.3433055344 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 6669088476 ps |
| CPU time | 78.02 seconds |
| Started | Jul 13 08:33:54 PM PDT 24 |
| Finished | Jul 13 08:35:12 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-f64526f4-a34c-42dd-a67b-651d5280b5c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433055344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.3433055344 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.2932486908 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 4392662327 ps |
| CPU time | 80.01 seconds |
| Started | Jul 13 08:33:57 PM PDT 24 |
| Finished | Jul 13 08:35:17 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-0fd36940-9dbb-4fb5-bfcc-e6ae9f2b4621 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932486908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.2932486908 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.203048559 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 51555216 ps |
| CPU time | 6.58 seconds |
| Started | Jul 13 08:33:55 PM PDT 24 |
| Finished | Jul 13 08:34:03 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-5972fbbe-3b1f-4ece-be51-2bdd1babe1c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203048559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delays .203048559 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.3985292142 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 899334974 ps |
| CPU time | 76.13 seconds |
| Started | Jul 13 08:34:03 PM PDT 24 |
| Finished | Jul 13 08:35:19 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-602fed44-07dd-42b3-88cd-b73ebcf28efd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985292142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.3985292142 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.2303932164 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 8239658903 ps |
| CPU time | 335.15 seconds |
| Started | Jul 13 08:34:03 PM PDT 24 |
| Finished | Jul 13 08:39:39 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-ac8e7fea-ae6b-4405-b1b7-dd37e63b9c63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303932164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.2303932164 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.2008610590 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 711672755 ps |
| CPU time | 229.03 seconds |
| Started | Jul 13 08:34:02 PM PDT 24 |
| Finished | Jul 13 08:37:51 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-76542645-26e4-4687-9c9f-f50989c2465c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008610590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_rand_reset.2008610590 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.1042638936 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 439603783 ps |
| CPU time | 247.64 seconds |
| Started | Jul 13 08:34:05 PM PDT 24 |
| Finished | Jul 13 08:38:12 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-82d08c64-9c60-4cc7-a349-de872578ba98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042638936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al l_with_reset_error.1042638936 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.3651450809 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 238421299 ps |
| CPU time | 30.98 seconds |
| Started | Jul 13 08:34:02 PM PDT 24 |
| Finished | Jul 13 08:34:34 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-9afc6a7e-65dd-46f7-bbd8-576c30f24cf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651450809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.3651450809 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.218312444 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 3037061754 ps |
| CPU time | 136.19 seconds |
| Started | Jul 13 08:34:12 PM PDT 24 |
| Finished | Jul 13 08:36:28 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-4f60cdec-7526-4822-af7b-9b515c8deca0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218312444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device. 218312444 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.1544985054 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 92919852724 ps |
| CPU time | 1768.48 seconds |
| Started | Jul 13 08:34:13 PM PDT 24 |
| Finished | Jul 13 09:03:42 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-9b4a786b-8fcc-4d24-a515-9f9e422816ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544985054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.1544985054 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.3376533585 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 326485244 ps |
| CPU time | 17.63 seconds |
| Started | Jul 13 08:34:13 PM PDT 24 |
| Finished | Jul 13 08:34:31 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-70e463c7-e76f-4423-bdd9-bd0d29037945 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376533585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.3376533585 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.2067172707 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 816619424 ps |
| CPU time | 31.43 seconds |
| Started | Jul 13 08:34:13 PM PDT 24 |
| Finished | Jul 13 08:34:45 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-bc3efd94-560c-4fac-96ea-7b381b1bd458 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067172707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.2067172707 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.2445393369 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 565646694 ps |
| CPU time | 51.97 seconds |
| Started | Jul 13 08:34:02 PM PDT 24 |
| Finished | Jul 13 08:34:54 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-3c57b94b-be8c-496b-8a94-107ee710ed8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445393369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.2445393369 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.3783539033 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 98897272172 ps |
| CPU time | 1167.91 seconds |
| Started | Jul 13 08:34:14 PM PDT 24 |
| Finished | Jul 13 08:53:42 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-c9d8bd1a-92b4-42e7-8bbf-b7167eeadbb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783539033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.3783539033 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.3854894794 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 61617415231 ps |
| CPU time | 1136.5 seconds |
| Started | Jul 13 08:34:13 PM PDT 24 |
| Finished | Jul 13 08:53:10 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-c8017624-cedc-4527-a5e0-e9d8649dc23d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854894794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.3854894794 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.1039304516 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 402659132 ps |
| CPU time | 41.01 seconds |
| Started | Jul 13 08:34:13 PM PDT 24 |
| Finished | Jul 13 08:34:55 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-3ad33b34-2d19-44a6-8db1-8984a1b4630d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039304516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.1039304516 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.2113759622 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 1987972962 ps |
| CPU time | 64.85 seconds |
| Started | Jul 13 08:34:10 PM PDT 24 |
| Finished | Jul 13 08:35:16 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-e0aedbf6-748f-4eae-bcda-77e36a79265a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113759622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.2113759622 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.3695194455 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 167316373 ps |
| CPU time | 9.36 seconds |
| Started | Jul 13 08:34:04 PM PDT 24 |
| Finished | Jul 13 08:34:13 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-ca222b24-9b2c-49cd-8393-61349947ac89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695194455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.3695194455 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.802607664 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 7844639029 ps |
| CPU time | 89.85 seconds |
| Started | Jul 13 08:34:01 PM PDT 24 |
| Finished | Jul 13 08:35:31 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-a2acc41c-ab0a-4b9e-b788-10bce3157ff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802607664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.802607664 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.2618378702 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 5777048586 ps |
| CPU time | 104.02 seconds |
| Started | Jul 13 08:34:02 PM PDT 24 |
| Finished | Jul 13 08:35:47 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-30c296e1-9a85-4b2f-9d5b-91d4a8832daf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618378702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.2618378702 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.1105023849 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 52754691 ps |
| CPU time | 7.17 seconds |
| Started | Jul 13 08:34:03 PM PDT 24 |
| Finished | Jul 13 08:34:10 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-fb5f5c1a-b47c-486a-bbfc-4a9db3c5541f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105023849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.1105023849 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.3256360118 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 2576798077 ps |
| CPU time | 233.41 seconds |
| Started | Jul 13 08:34:15 PM PDT 24 |
| Finished | Jul 13 08:38:09 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-a6ef0fac-3bd9-4037-bfe7-cc2b21cda472 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256360118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.3256360118 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.3092549233 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 6971121125 ps |
| CPU time | 298.69 seconds |
| Started | Jul 13 08:34:12 PM PDT 24 |
| Finished | Jul 13 08:39:11 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-00769562-c19f-4038-a885-a76f021ea6cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092549233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.3092549233 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.112440684 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 383012072 ps |
| CPU time | 168.71 seconds |
| Started | Jul 13 08:34:12 PM PDT 24 |
| Finished | Jul 13 08:37:01 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-8e65e0a0-79a8-4e82-98d4-ed534024e933 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112440684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_ with_rand_reset.112440684 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.4270132529 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 4296704970 ps |
| CPU time | 231.74 seconds |
| Started | Jul 13 08:34:20 PM PDT 24 |
| Finished | Jul 13 08:38:13 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-8e7899ae-bee9-4381-8513-29832ae27876 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270132529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.4270132529 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.3986533856 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 176691853 ps |
| CPU time | 11.51 seconds |
| Started | Jul 13 08:34:12 PM PDT 24 |
| Finished | Jul 13 08:34:24 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-c72effdf-d0d2-4fe3-8b72-1ecda01015d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986533856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.3986533856 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.2725139456 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 1413769273 ps |
| CPU time | 63.36 seconds |
| Started | Jul 13 08:34:20 PM PDT 24 |
| Finished | Jul 13 08:35:24 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-0650b907-fe5f-4fa5-9d03-6fb65cf6aa7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725139456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device .2725139456 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.47376329 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 76316674833 ps |
| CPU time | 1415.19 seconds |
| Started | Jul 13 08:34:22 PM PDT 24 |
| Finished | Jul 13 08:57:57 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-bc1f5cd2-7869-488e-bed5-0a0d16cf42b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47376329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_de vice_slow_rsp.47376329 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.2918298384 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 21191695 ps |
| CPU time | 5.65 seconds |
| Started | Jul 13 08:34:29 PM PDT 24 |
| Finished | Jul 13 08:34:35 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-d632f4d9-a1ce-4ad0-ad40-342f0ec5a70d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918298384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.2918298384 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.3926295491 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 1799883424 ps |
| CPU time | 64.07 seconds |
| Started | Jul 13 08:34:21 PM PDT 24 |
| Finished | Jul 13 08:35:25 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-9562ce1f-6fb4-401b-a19c-f121468fa868 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926295491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.3926295491 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.3205059285 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 395539881 ps |
| CPU time | 41.64 seconds |
| Started | Jul 13 08:34:22 PM PDT 24 |
| Finished | Jul 13 08:35:04 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-bfcdd8c3-46dc-4c95-91ea-7361441f66fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205059285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.3205059285 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.694210320 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 103072172551 ps |
| CPU time | 1201.78 seconds |
| Started | Jul 13 08:34:29 PM PDT 24 |
| Finished | Jul 13 08:54:31 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-b3cbbc59-847a-40ec-a013-fb788a2e7f77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694210320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.694210320 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.2984432071 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 19783067948 ps |
| CPU time | 389.75 seconds |
| Started | Jul 13 08:34:23 PM PDT 24 |
| Finished | Jul 13 08:40:53 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-fdb8b996-00bd-42dc-b533-2d85fe8b0d07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984432071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.2984432071 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.3687726831 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 221134211 ps |
| CPU time | 25.29 seconds |
| Started | Jul 13 08:37:19 PM PDT 24 |
| Finished | Jul 13 08:37:45 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-f3206523-eb0d-4bb6-822e-3a69f280e7d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687726831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_del ays.3687726831 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.3678719543 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 162629775 ps |
| CPU time | 9.02 seconds |
| Started | Jul 13 08:34:23 PM PDT 24 |
| Finished | Jul 13 08:34:32 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-e89be01f-0cf0-4e37-b203-5ec4df96c2b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678719543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.3678719543 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.1581319078 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 243623287 ps |
| CPU time | 10.83 seconds |
| Started | Jul 13 08:34:24 PM PDT 24 |
| Finished | Jul 13 08:34:35 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-c201b341-5286-4835-9d18-a75023ad2929 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581319078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.1581319078 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.1936869664 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 8262472374 ps |
| CPU time | 98.67 seconds |
| Started | Jul 13 08:34:22 PM PDT 24 |
| Finished | Jul 13 08:36:01 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-a564d32b-0b84-4d6b-88dc-42094eb42317 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936869664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.1936869664 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.3978127462 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 5016716251 ps |
| CPU time | 88.99 seconds |
| Started | Jul 13 08:34:24 PM PDT 24 |
| Finished | Jul 13 08:35:53 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-b7db0c45-8b39-42d5-b8c4-70973e460ee1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978127462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.3978127462 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.29783016 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 59280097 ps |
| CPU time | 8.05 seconds |
| Started | Jul 13 08:34:25 PM PDT 24 |
| Finished | Jul 13 08:34:34 PM PDT 24 |
| Peak memory | 573852 kb |
| Host | smart-54caab4c-dbab-475f-9271-b37f4a8cdf3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29783016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delays.29783016 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.2370419944 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 1173693215 ps |
| CPU time | 110.07 seconds |
| Started | Jul 13 08:34:21 PM PDT 24 |
| Finished | Jul 13 08:36:12 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-0ef81a60-83b9-4207-9253-b7e5cc41d7eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370419944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.2370419944 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.1674532529 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 10089948909 ps |
| CPU time | 357.32 seconds |
| Started | Jul 13 08:34:22 PM PDT 24 |
| Finished | Jul 13 08:40:19 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-180f95d8-0995-4468-8847-96542c221a1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674532529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.1674532529 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.2213912404 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 114616512 ps |
| CPU time | 31.54 seconds |
| Started | Jul 13 08:34:20 PM PDT 24 |
| Finished | Jul 13 08:34:52 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-8a07b6b1-c033-47b7-baec-1e21b0021310 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213912404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_rand_reset.2213912404 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.4065002558 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 224007478 ps |
| CPU time | 78.82 seconds |
| Started | Jul 13 08:34:22 PM PDT 24 |
| Finished | Jul 13 08:35:41 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-9b0cdd76-58e6-4fd6-9a2f-52603937c44a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065002558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.4065002558 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.105914851 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 52521172 ps |
| CPU time | 9.09 seconds |
| Started | Jul 13 08:34:20 PM PDT 24 |
| Finished | Jul 13 08:34:30 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-bb1a6d46-f428-4806-aec6-ec4588129a98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105914851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.105914851 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.39511209 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 513159063 ps |
| CPU time | 26.57 seconds |
| Started | Jul 13 08:34:31 PM PDT 24 |
| Finished | Jul 13 08:34:58 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-d566812a-15ef-4058-9f0b-4ca442a11058 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39511209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device.39511209 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.3853673817 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 53225407998 ps |
| CPU time | 1008.32 seconds |
| Started | Jul 13 08:34:30 PM PDT 24 |
| Finished | Jul 13 08:51:19 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-e0b1c819-95d4-44ea-bdfb-a099ea762038 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853673817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_ device_slow_rsp.3853673817 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1449520532 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 1394570293 ps |
| CPU time | 66.55 seconds |
| Started | Jul 13 08:34:29 PM PDT 24 |
| Finished | Jul 13 08:35:36 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-0c8d1b8d-3992-4983-bd9d-f51a3929e8f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449520532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add r.1449520532 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.14892993 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 1236200020 ps |
| CPU time | 46.71 seconds |
| Started | Jul 13 08:34:33 PM PDT 24 |
| Finished | Jul 13 08:35:20 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-67bfc644-b7a4-436e-865b-a2df7941c7c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14892993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.14892993 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.2524493737 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 1644689333 ps |
| CPU time | 64.43 seconds |
| Started | Jul 13 08:34:33 PM PDT 24 |
| Finished | Jul 13 08:35:38 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-4d4ef727-fcf9-40bf-9af5-bf593b5a9ea6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524493737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.2524493737 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.256164597 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 96028424779 ps |
| CPU time | 1120.89 seconds |
| Started | Jul 13 08:34:31 PM PDT 24 |
| Finished | Jul 13 08:53:12 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-85d7cbd4-5911-468b-8b75-4997775442c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256164597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.256164597 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.986990173 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 6418861854 ps |
| CPU time | 119.58 seconds |
| Started | Jul 13 08:34:34 PM PDT 24 |
| Finished | Jul 13 08:36:34 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-41ad0bb7-8683-4025-b348-8a16e005f6d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986990173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.986990173 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.547720538 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 368280831 ps |
| CPU time | 36.38 seconds |
| Started | Jul 13 08:34:28 PM PDT 24 |
| Finished | Jul 13 08:35:05 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-88313a05-f7c7-4d36-ad9d-37128d6f0537 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547720538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_dela ys.547720538 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.905830130 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 1522883742 ps |
| CPU time | 51 seconds |
| Started | Jul 13 08:34:33 PM PDT 24 |
| Finished | Jul 13 08:35:24 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-dadb21a2-e5c2-42fa-94e4-52c66532296a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905830130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.905830130 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.1913779817 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 170462638 ps |
| CPU time | 9.28 seconds |
| Started | Jul 13 08:34:23 PM PDT 24 |
| Finished | Jul 13 08:34:32 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-a35dcf9c-98e0-40e2-bf64-d36ef4b186f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913779817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.1913779817 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.2759826447 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 8992606385 ps |
| CPU time | 107.15 seconds |
| Started | Jul 13 08:34:24 PM PDT 24 |
| Finished | Jul 13 08:36:12 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-ac96505b-055b-4c77-9066-77b83252fa3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759826447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.2759826447 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.2840023677 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 6949271196 ps |
| CPU time | 125.18 seconds |
| Started | Jul 13 08:34:29 PM PDT 24 |
| Finished | Jul 13 08:36:34 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-2b282b95-bf48-44aa-ad65-7a0a85fc9626 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840023677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.2840023677 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.3115177931 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 49681757 ps |
| CPU time | 6.35 seconds |
| Started | Jul 13 08:34:21 PM PDT 24 |
| Finished | Jul 13 08:34:28 PM PDT 24 |
| Peak memory | 575188 kb |
| Host | smart-92f4dee7-5faa-4d89-a201-d8c0d9aa0881 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115177931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.3115177931 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.3612714546 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 2694514059 ps |
| CPU time | 215.59 seconds |
| Started | Jul 13 08:34:30 PM PDT 24 |
| Finished | Jul 13 08:38:06 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-3d450e64-5129-4444-8187-dfa90dac2677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612714546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.3612714546 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.1112692837 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 3119338955 ps |
| CPU time | 124.77 seconds |
| Started | Jul 13 08:34:35 PM PDT 24 |
| Finished | Jul 13 08:36:40 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-76d7d558-96d5-4571-a5dd-8f22baff7cff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112692837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.1112692837 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.3775576021 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 588058901 ps |
| CPU time | 166.69 seconds |
| Started | Jul 13 08:34:32 PM PDT 24 |
| Finished | Jul 13 08:37:19 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-eb68d61c-ce1e-4fd3-aaed-631ceb21d543 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775576021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_rand_reset.3775576021 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.2086819172 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 13756542651 ps |
| CPU time | 594.78 seconds |
| Started | Jul 13 08:34:31 PM PDT 24 |
| Finished | Jul 13 08:44:26 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-04b07c0d-e830-441f-8437-74770ff4b26b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086819172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al l_with_reset_error.2086819172 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.1665733626 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 404729926 ps |
| CPU time | 20.88 seconds |
| Started | Jul 13 08:34:33 PM PDT 24 |
| Finished | Jul 13 08:34:55 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-4bb6f5ef-2183-4661-840c-67ea290714ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665733626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.1665733626 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.2239769392 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 1118771573 ps |
| CPU time | 50.4 seconds |
| Started | Jul 13 08:34:41 PM PDT 24 |
| Finished | Jul 13 08:35:32 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-1d25a02f-1ee6-4033-a98e-4ba464a9d059 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239769392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .2239769392 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.1647746271 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 124553380941 ps |
| CPU time | 2384.56 seconds |
| Started | Jul 13 08:34:40 PM PDT 24 |
| Finished | Jul 13 09:14:26 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-12d3fcf3-be3b-4642-afd4-381cb51289e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647746271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.1647746271 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3776390741 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 791323937 ps |
| CPU time | 34.56 seconds |
| Started | Jul 13 08:34:41 PM PDT 24 |
| Finished | Jul 13 08:35:16 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-d0c6fe40-fc12-48f3-a3ca-faafabf5708d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776390741 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.3776390741 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.2201985991 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 213884491 ps |
| CPU time | 20.2 seconds |
| Started | Jul 13 08:34:43 PM PDT 24 |
| Finished | Jul 13 08:35:04 PM PDT 24 |
| Peak memory | 575076 kb |
| Host | smart-c5279713-19f3-4fd5-9170-e168cd687d69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201985991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.2201985991 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.1091225096 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 203675161 ps |
| CPU time | 21.07 seconds |
| Started | Jul 13 08:34:41 PM PDT 24 |
| Finished | Jul 13 08:35:03 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-2645fd46-67c9-4018-8464-ce1261d48a16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091225096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.1091225096 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.4215504825 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 33214337475 ps |
| CPU time | 359.91 seconds |
| Started | Jul 13 08:34:43 PM PDT 24 |
| Finished | Jul 13 08:40:43 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-b50df24c-2bf6-4ee7-afdb-e3be41ead297 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215504825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.4215504825 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.2406806004 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 61770903787 ps |
| CPU time | 1107.31 seconds |
| Started | Jul 13 08:34:40 PM PDT 24 |
| Finished | Jul 13 08:53:08 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-448a88af-93ee-4ec6-ae43-87e87c3f6bed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406806004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.2406806004 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.4202640242 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 587477165 ps |
| CPU time | 53.95 seconds |
| Started | Jul 13 08:34:41 PM PDT 24 |
| Finished | Jul 13 08:35:36 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-a30df28b-f0d8-4832-a218-fca0020d9bb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202640242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.4202640242 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.3065826790 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 2224967098 ps |
| CPU time | 77.34 seconds |
| Started | Jul 13 08:34:40 PM PDT 24 |
| Finished | Jul 13 08:35:58 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-4d73ad78-46a4-4c66-9bd9-fe5680941bf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065826790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.3065826790 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.2650083450 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 171373603 ps |
| CPU time | 8.96 seconds |
| Started | Jul 13 08:34:41 PM PDT 24 |
| Finished | Jul 13 08:34:50 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-e4be6ca8-8bd0-4472-a8f8-fb047c1b8f6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650083450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.2650083450 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.1117495461 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 7328270461 ps |
| CPU time | 86.68 seconds |
| Started | Jul 13 08:34:43 PM PDT 24 |
| Finished | Jul 13 08:36:10 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-35ae46da-9d68-4190-952b-dded2d168593 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117495461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.1117495461 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.847200990 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 5008300395 ps |
| CPU time | 96.75 seconds |
| Started | Jul 13 08:34:42 PM PDT 24 |
| Finished | Jul 13 08:36:19 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-84e63d99-c7e1-4228-ac21-be773f86dc4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847200990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.847200990 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.3426229170 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 35131543 ps |
| CPU time | 6.01 seconds |
| Started | Jul 13 08:34:39 PM PDT 24 |
| Finished | Jul 13 08:34:46 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-5c06737a-9361-420d-b7b4-4d9dcb67f88c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426229170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.3426229170 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.3309060661 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 5163223626 ps |
| CPU time | 210.77 seconds |
| Started | Jul 13 08:34:39 PM PDT 24 |
| Finished | Jul 13 08:38:10 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-47f5fb96-0836-4efa-8406-0170d62527d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309060661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.3309060661 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.3966149500 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 1572527892 ps |
| CPU time | 121.55 seconds |
| Started | Jul 13 08:34:40 PM PDT 24 |
| Finished | Jul 13 08:36:43 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-8579649c-7962-4ca3-8b77-ad97fdce280a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966149500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.3966149500 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.402672226 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 374496771 ps |
| CPU time | 192.11 seconds |
| Started | Jul 13 08:34:43 PM PDT 24 |
| Finished | Jul 13 08:37:55 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-d30d45d9-dd6b-40d7-aa4f-4b91c9e6981a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402672226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_ with_rand_reset.402672226 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.2151488912 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 223934151 ps |
| CPU time | 70.08 seconds |
| Started | Jul 13 08:34:39 PM PDT 24 |
| Finished | Jul 13 08:35:49 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-c7cbbf38-38d7-49b3-9e16-271f113fcecf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151488912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al l_with_reset_error.2151488912 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.372351978 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 254934586 ps |
| CPU time | 13.44 seconds |
| Started | Jul 13 08:34:40 PM PDT 24 |
| Finished | Jul 13 08:34:53 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-2ca0aa8d-fd11-4f2f-b2d0-3f966cc9280c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372351978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.372351978 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.4068499659 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 2980222257 ps |
| CPU time | 149.7 seconds |
| Started | Jul 13 08:34:49 PM PDT 24 |
| Finished | Jul 13 08:37:20 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-f583b216-e491-4c63-89cc-43ee4178845f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068499659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device .4068499659 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.2567141933 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 305106523 ps |
| CPU time | 36.74 seconds |
| Started | Jul 13 08:34:56 PM PDT 24 |
| Finished | Jul 13 08:35:33 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-aa1d86cc-a767-457d-b9c0-f950e392e1e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567141933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_add r.2567141933 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.1693999493 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 521518422 ps |
| CPU time | 43.45 seconds |
| Started | Jul 13 08:34:49 PM PDT 24 |
| Finished | Jul 13 08:35:33 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-875328f8-ccc7-4af5-bf20-0ae6bef58809 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693999493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.1693999493 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.3717353854 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 490017521 ps |
| CPU time | 40.95 seconds |
| Started | Jul 13 08:34:50 PM PDT 24 |
| Finished | Jul 13 08:35:31 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-2d6b1191-ec12-42d3-b062-03bb506fc306 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717353854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.3717353854 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.1876353325 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 114084281125 ps |
| CPU time | 1248.28 seconds |
| Started | Jul 13 08:34:47 PM PDT 24 |
| Finished | Jul 13 08:55:36 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-0ed48390-94f5-47ab-922b-9ffe72b39eb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876353325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.1876353325 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.114004357 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 17673556441 ps |
| CPU time | 317.04 seconds |
| Started | Jul 13 08:34:50 PM PDT 24 |
| Finished | Jul 13 08:40:08 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-ca498579-2e8f-4955-8a25-83a2540726ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114004357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.114004357 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.2597804140 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 565070698 ps |
| CPU time | 54.45 seconds |
| Started | Jul 13 08:34:51 PM PDT 24 |
| Finished | Jul 13 08:35:46 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-dd6ed9c5-a06e-41ff-882a-51bbb2cadce9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597804140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.2597804140 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.3673969065 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 592385106 ps |
| CPU time | 48.59 seconds |
| Started | Jul 13 08:34:57 PM PDT 24 |
| Finished | Jul 13 08:35:45 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-db678fb5-7c88-43d9-a4e7-66a1dae9b363 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673969065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.3673969065 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.823146065 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 51502724 ps |
| CPU time | 6.73 seconds |
| Started | Jul 13 08:34:43 PM PDT 24 |
| Finished | Jul 13 08:34:50 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-d071daee-69bd-440d-9ce0-d1a116ca5b39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823146065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.823146065 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.3518442313 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 7315764822 ps |
| CPU time | 84.19 seconds |
| Started | Jul 13 08:34:50 PM PDT 24 |
| Finished | Jul 13 08:36:16 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-3c2b61c5-61dd-4a9c-ab5c-c739df3c7e3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518442313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.3518442313 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.2188092920 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 6978740680 ps |
| CPU time | 125.59 seconds |
| Started | Jul 13 08:34:49 PM PDT 24 |
| Finished | Jul 13 08:36:55 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-b93d146e-5cd1-4514-8644-acd99c8067a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188092920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.2188092920 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.2235314129 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 42973867 ps |
| CPU time | 6.43 seconds |
| Started | Jul 13 08:34:40 PM PDT 24 |
| Finished | Jul 13 08:34:47 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-66e0f27b-5268-4898-bfa7-5952de94cbf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235314129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.2235314129 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.1657855690 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 11635800368 ps |
| CPU time | 520.46 seconds |
| Started | Jul 13 08:34:50 PM PDT 24 |
| Finished | Jul 13 08:43:32 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-b1329547-11cc-4294-a467-af3156206ac8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657855690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.1657855690 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.2018819111 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 4374682552 ps |
| CPU time | 186.7 seconds |
| Started | Jul 13 08:34:49 PM PDT 24 |
| Finished | Jul 13 08:37:57 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-ccbb2be3-37fa-40cb-aba5-fc76963cedc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018819111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.2018819111 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.1016024398 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 99485377 ps |
| CPU time | 17.51 seconds |
| Started | Jul 13 08:34:50 PM PDT 24 |
| Finished | Jul 13 08:35:08 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-a1b4b2e9-cd83-44df-9b6c-caa05b19496a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016024398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_rand_reset.1016024398 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3619444813 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 360022081 ps |
| CPU time | 143 seconds |
| Started | Jul 13 08:34:50 PM PDT 24 |
| Finished | Jul 13 08:37:14 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-069372f8-6b47-41aa-b4e3-616f77f59432 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619444813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al l_with_reset_error.3619444813 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.3659058945 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 318907920 ps |
| CPU time | 18.01 seconds |
| Started | Jul 13 08:34:57 PM PDT 24 |
| Finished | Jul 13 08:35:15 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-f51d94a9-db7b-4daa-8784-795b3de7cf3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659058945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.3659058945 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.3509860216 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 631740786 ps |
| CPU time | 24.45 seconds |
| Started | Jul 13 08:35:05 PM PDT 24 |
| Finished | Jul 13 08:35:30 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-c07fbd19-c77d-4a0e-98fb-5b02169dd99b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509860216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .3509860216 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.2710131159 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 17677853222 ps |
| CPU time | 324.74 seconds |
| Started | Jul 13 08:35:04 PM PDT 24 |
| Finished | Jul 13 08:40:29 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-7ec74523-0aae-4e18-9600-a7b7eac2ed39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710131159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.2710131159 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.3557125652 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 27174695 ps |
| CPU time | 6.29 seconds |
| Started | Jul 13 08:35:01 PM PDT 24 |
| Finished | Jul 13 08:35:08 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-5573c9b6-afb6-46dd-aaa0-d0a70cbe80ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557125652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add r.3557125652 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.2273542166 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 2149549528 ps |
| CPU time | 80.33 seconds |
| Started | Jul 13 08:35:02 PM PDT 24 |
| Finished | Jul 13 08:36:23 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-35a71525-cbce-4f16-865f-87547e12f22b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273542166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.2273542166 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.4070624778 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 517143262 ps |
| CPU time | 49.88 seconds |
| Started | Jul 13 08:35:02 PM PDT 24 |
| Finished | Jul 13 08:35:52 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-a2af1b87-f842-4c6d-8de5-a960a6ffe3ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070624778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.4070624778 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.3854981702 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 23939896766 ps |
| CPU time | 287.66 seconds |
| Started | Jul 13 08:35:04 PM PDT 24 |
| Finished | Jul 13 08:39:52 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-812ed42d-0f37-4fed-98c5-3ab66d262219 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854981702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.3854981702 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.1855458805 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 36098817421 ps |
| CPU time | 660.13 seconds |
| Started | Jul 13 08:35:00 PM PDT 24 |
| Finished | Jul 13 08:46:01 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-9ffbef1a-c469-4f9b-9a2f-aa77ac02299a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855458805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.1855458805 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.1322757984 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 181472232 ps |
| CPU time | 17.22 seconds |
| Started | Jul 13 08:35:04 PM PDT 24 |
| Finished | Jul 13 08:35:22 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-03c98ea2-5930-447b-8f09-301d5935bf9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322757984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del ays.1322757984 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.3942553231 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 191540894 ps |
| CPU time | 9.25 seconds |
| Started | Jul 13 08:35:01 PM PDT 24 |
| Finished | Jul 13 08:35:11 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-bc38aed2-8e70-44cb-aa42-b16e8df68afe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942553231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.3942553231 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.366373774 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 200706323 ps |
| CPU time | 10.38 seconds |
| Started | Jul 13 08:34:49 PM PDT 24 |
| Finished | Jul 13 08:35:00 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-aaf62659-8c7e-4728-9116-52b1728e12b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366373774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.366373774 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.1199757066 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 8657944219 ps |
| CPU time | 101.92 seconds |
| Started | Jul 13 08:35:01 PM PDT 24 |
| Finished | Jul 13 08:36:44 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-a872284f-67fd-4a34-84b1-3930a8f8da4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199757066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.1199757066 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.785906218 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 5181185050 ps |
| CPU time | 99.51 seconds |
| Started | Jul 13 08:35:00 PM PDT 24 |
| Finished | Jul 13 08:36:40 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-74ef4f24-9aa1-41c0-9cce-da642a451d6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785906218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.785906218 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.1188662262 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 38086771 ps |
| CPU time | 6.36 seconds |
| Started | Jul 13 08:34:52 PM PDT 24 |
| Finished | Jul 13 08:34:58 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-9c08b95f-b807-4b59-a137-1a6b9bfe1b2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188662262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.1188662262 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.4227031619 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 4304628108 ps |
| CPU time | 158.49 seconds |
| Started | Jul 13 08:35:05 PM PDT 24 |
| Finished | Jul 13 08:37:44 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-e88d545d-c67a-4249-b242-bb654ec1abb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227031619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.4227031619 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.434158359 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 2071123049 ps |
| CPU time | 141.29 seconds |
| Started | Jul 13 08:35:00 PM PDT 24 |
| Finished | Jul 13 08:37:22 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-bd1bf9b9-f1dd-434f-899f-39681ae3d366 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434158359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.434158359 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.1436866684 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 4589269987 ps |
| CPU time | 559.42 seconds |
| Started | Jul 13 08:35:00 PM PDT 24 |
| Finished | Jul 13 08:44:21 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-da16e012-01f6-4ffc-b980-800640f9236c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436866684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.1436866684 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.2173277810 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 516852145 ps |
| CPU time | 25.27 seconds |
| Started | Jul 13 08:35:02 PM PDT 24 |
| Finished | Jul 13 08:35:28 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-5b7a102f-ee4f-4496-bbc2-3ff4f2095f77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173277810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.2173277810 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.2241981703 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 1125496697 ps |
| CPU time | 100.79 seconds |
| Started | Jul 13 08:35:01 PM PDT 24 |
| Finished | Jul 13 08:36:42 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-c9feba7c-801f-464a-9722-8545a926dc48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241981703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device .2241981703 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.4271119382 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 68214338423 ps |
| CPU time | 1211.9 seconds |
| Started | Jul 13 08:35:04 PM PDT 24 |
| Finished | Jul 13 08:55:16 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-12a25f7d-525b-44b6-ac7d-75cf5f745f36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271119382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_ device_slow_rsp.4271119382 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.1962286103 |
| Short name | T2911 |
| Test name | |
| Test status | |
| Simulation time | 454201597 ps |
| CPU time | 19.61 seconds |
| Started | Jul 13 08:35:02 PM PDT 24 |
| Finished | Jul 13 08:35:23 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-76b85da1-7a4c-4073-8726-b2e29d38b2e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962286103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add r.1962286103 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.1042758767 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 684963662 ps |
| CPU time | 27.8 seconds |
| Started | Jul 13 08:35:04 PM PDT 24 |
| Finished | Jul 13 08:35:32 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-8ef585da-862f-4fa7-900b-87761d1d3281 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042758767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.1042758767 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.1081853723 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 37128048 ps |
| CPU time | 6.56 seconds |
| Started | Jul 13 08:35:00 PM PDT 24 |
| Finished | Jul 13 08:35:07 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-2d14776f-0651-4d16-8554-cca3a5852803 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081853723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.1081853723 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.127136556 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 88985222660 ps |
| CPU time | 1002.35 seconds |
| Started | Jul 13 08:35:04 PM PDT 24 |
| Finished | Jul 13 08:51:47 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-f4631c08-701c-43b7-a0b0-04b459288173 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127136556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.127136556 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.3198198482 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 53126731260 ps |
| CPU time | 870.92 seconds |
| Started | Jul 13 08:35:06 PM PDT 24 |
| Finished | Jul 13 08:49:37 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-64627473-4881-41c8-9272-7153943480be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198198482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.3198198482 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.4029164668 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 430307916 ps |
| CPU time | 46.38 seconds |
| Started | Jul 13 08:35:01 PM PDT 24 |
| Finished | Jul 13 08:35:48 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-4d1ab309-78f3-4e46-af57-9e460b7853ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029164668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_del ays.4029164668 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.2312088435 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 758464176 ps |
| CPU time | 27.89 seconds |
| Started | Jul 13 08:35:00 PM PDT 24 |
| Finished | Jul 13 08:35:29 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-c657dcb6-8786-44e9-89d6-55843541be2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312088435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.2312088435 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.3058174036 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 242069814 ps |
| CPU time | 10.45 seconds |
| Started | Jul 13 08:34:59 PM PDT 24 |
| Finished | Jul 13 08:35:10 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-b8168995-5e02-4814-bd74-a52bb9e16152 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058174036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.3058174036 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.3913511072 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 7887001269 ps |
| CPU time | 91.11 seconds |
| Started | Jul 13 08:35:01 PM PDT 24 |
| Finished | Jul 13 08:36:33 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-83738129-6a1c-49ee-8db1-b7e7929c5553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913511072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.3913511072 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.1558895226 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 5316112050 ps |
| CPU time | 97.16 seconds |
| Started | Jul 13 08:35:02 PM PDT 24 |
| Finished | Jul 13 08:36:39 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-084cefbe-566b-4d7d-92ad-e53c8e08f0f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558895226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.1558895226 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.4161242702 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 39729392 ps |
| CPU time | 6.35 seconds |
| Started | Jul 13 08:35:01 PM PDT 24 |
| Finished | Jul 13 08:35:08 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-fa9497cc-a78b-4fec-822b-9fd3a9676de5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161242702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay s.4161242702 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.1807213766 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 9253613539 ps |
| CPU time | 342.98 seconds |
| Started | Jul 13 08:35:19 PM PDT 24 |
| Finished | Jul 13 08:41:03 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-ea9828c8-ebae-4242-afe3-808ad38c1041 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807213766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.1807213766 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.1632813819 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 1611628410 ps |
| CPU time | 54.01 seconds |
| Started | Jul 13 08:35:09 PM PDT 24 |
| Finished | Jul 13 08:36:03 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-1c6582bb-4320-4b98-890b-0e00a0b92fce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632813819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.1632813819 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.3794725473 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 110524594 ps |
| CPU time | 78.06 seconds |
| Started | Jul 13 08:35:11 PM PDT 24 |
| Finished | Jul 13 08:36:30 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-502fe7cc-7c6a-4299-9fce-6a4509fe6bed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794725473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.3794725473 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.1017806179 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 6799428490 ps |
| CPU time | 353.37 seconds |
| Started | Jul 13 08:35:10 PM PDT 24 |
| Finished | Jul 13 08:41:05 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-86d20dcb-052f-4d7c-8934-56839bed921a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017806179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_al l_with_reset_error.1017806179 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.1866527127 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 22710903 ps |
| CPU time | 5.63 seconds |
| Started | Jul 13 08:35:03 PM PDT 24 |
| Finished | Jul 13 08:35:09 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-57f0b3cc-b50f-4a21-b831-802820419f04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866527127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.1866527127 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.731195980 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 5429717530 ps |
| CPU time | 660.84 seconds |
| Started | Jul 13 08:18:43 PM PDT 24 |
| Finished | Jul 13 08:29:44 PM PDT 24 |
| Peak memory | 597420 kb |
| Host | smart-401de4ee-890b-42c9-a359-ebe7e6cda160 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731195980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.731195980 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.2919878202 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 16691240471 ps |
| CPU time | 1782.92 seconds |
| Started | Jul 13 08:18:24 PM PDT 24 |
| Finished | Jul 13 08:48:08 PM PDT 24 |
| Peak memory | 593268 kb |
| Host | smart-9a480073-ba29-43ac-af45-b6c9b1bc5914 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919878202 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.2919878202 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.4001044720 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 4057655312 ps |
| CPU time | 313.58 seconds |
| Started | Jul 13 08:18:28 PM PDT 24 |
| Finished | Jul 13 08:23:42 PM PDT 24 |
| Peak memory | 598780 kb |
| Host | smart-b79b170f-e3ad-4025-9bc0-80080e5cec7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001044720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.4001044720 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.1127751825 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 805834008 ps |
| CPU time | 66.96 seconds |
| Started | Jul 13 08:18:35 PM PDT 24 |
| Finished | Jul 13 08:19:43 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-2263a20f-9444-42ff-84c2-f180cd2ecb4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127751825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 1127751825 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2223796176 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 144837772206 ps |
| CPU time | 2590.79 seconds |
| Started | Jul 13 08:18:34 PM PDT 24 |
| Finished | Jul 13 09:01:46 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-cf705896-224a-4e45-bb36-73563ef9424e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223796176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.2223796176 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.4021872535 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 266997104 ps |
| CPU time | 28.87 seconds |
| Started | Jul 13 08:18:39 PM PDT 24 |
| Finished | Jul 13 08:19:09 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-e1eb04fd-b4d4-421c-a43b-ef8dc99d8742 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021872535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .4021872535 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.2703638404 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 2147265478 ps |
| CPU time | 83.68 seconds |
| Started | Jul 13 08:18:35 PM PDT 24 |
| Finished | Jul 13 08:19:59 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-34ad9357-0933-4830-8148-2bb0aa2c473f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703638404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2703638404 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.3231649752 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 1950020141 ps |
| CPU time | 80.42 seconds |
| Started | Jul 13 08:18:40 PM PDT 24 |
| Finished | Jul 13 08:20:01 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-bfa6de89-9fec-47ac-9280-c032656a1bd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231649752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.3231649752 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.1886806054 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 71308546590 ps |
| CPU time | 832.73 seconds |
| Started | Jul 13 08:18:34 PM PDT 24 |
| Finished | Jul 13 08:32:27 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-bc9d18a1-54fd-4da2-a818-a149e1949afc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886806054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1886806054 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.132458459 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 44602653629 ps |
| CPU time | 773.63 seconds |
| Started | Jul 13 08:18:39 PM PDT 24 |
| Finished | Jul 13 08:31:33 PM PDT 24 |
| Peak memory | 574944 kb |
| Host | smart-d2dc87a9-75a1-4c1e-9106-cfb2e3637f36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132458459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.132458459 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.3652524869 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 504684248 ps |
| CPU time | 48.62 seconds |
| Started | Jul 13 08:18:35 PM PDT 24 |
| Finished | Jul 13 08:19:25 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-2d78e669-7687-471f-984a-6f4f572dbbe8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652524869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.3652524869 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.3905481563 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 1545101672 ps |
| CPU time | 49.18 seconds |
| Started | Jul 13 08:18:37 PM PDT 24 |
| Finished | Jul 13 08:19:27 PM PDT 24 |
| Peak memory | 575188 kb |
| Host | smart-61df6a65-f9d2-468d-9fed-d2b7915c1645 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905481563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3905481563 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.2313265512 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 46467923 ps |
| CPU time | 7.43 seconds |
| Started | Jul 13 08:18:32 PM PDT 24 |
| Finished | Jul 13 08:18:40 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-17e942f1-8289-4bc7-af52-328a1be3529a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313265512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2313265512 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.1751168412 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 10980091149 ps |
| CPU time | 124.9 seconds |
| Started | Jul 13 08:18:39 PM PDT 24 |
| Finished | Jul 13 08:20:45 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-5140afdf-2845-404e-9268-1a1c834c6118 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751168412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1751168412 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.325374998 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 4749252273 ps |
| CPU time | 89.81 seconds |
| Started | Jul 13 08:18:37 PM PDT 24 |
| Finished | Jul 13 08:20:07 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-6c98efc1-7842-4bf1-9585-1db7f1edaa52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325374998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.325374998 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2064932438 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 49280035 ps |
| CPU time | 7.15 seconds |
| Started | Jul 13 08:18:37 PM PDT 24 |
| Finished | Jul 13 08:18:44 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-17b78e2a-b20e-4ea1-95fc-358a4c64a38a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064932438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays .2064932438 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.185554045 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 209908094 ps |
| CPU time | 29.08 seconds |
| Started | Jul 13 08:18:37 PM PDT 24 |
| Finished | Jul 13 08:19:06 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-768bab9d-3344-413a-902c-894910f7577e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185554045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.185554045 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.2187040474 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 3733051787 ps |
| CPU time | 287.41 seconds |
| Started | Jul 13 08:18:46 PM PDT 24 |
| Finished | Jul 13 08:23:34 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-6c2471a2-c5ea-4647-b7a5-8ef4320709d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187040474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2187040474 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.2152483686 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 3263657346 ps |
| CPU time | 538.83 seconds |
| Started | Jul 13 08:18:40 PM PDT 24 |
| Finished | Jul 13 08:27:39 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-5a4aedd2-1e57-44c0-ae14-8710a5e6fc84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152483686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.2152483686 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.2874687957 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 99577412 ps |
| CPU time | 24.21 seconds |
| Started | Jul 13 08:18:46 PM PDT 24 |
| Finished | Jul 13 08:19:11 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-a859e4e3-1e26-45b5-b7fd-0bd863e5657b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874687957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all _with_reset_error.2874687957 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.2926440070 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 110080842 ps |
| CPU time | 9.48 seconds |
| Started | Jul 13 08:18:34 PM PDT 24 |
| Finished | Jul 13 08:18:44 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-ce06685d-04e7-48a5-a2b4-823528a0445b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926440070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2926440070 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.1696761556 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 1512865442 ps |
| CPU time | 61.46 seconds |
| Started | Jul 13 08:35:18 PM PDT 24 |
| Finished | Jul 13 08:36:20 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-cd8e6d40-2b06-4abf-ad29-e07c21a286f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696761556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device .1696761556 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.1153238821 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 72406749356 ps |
| CPU time | 1335.47 seconds |
| Started | Jul 13 08:35:15 PM PDT 24 |
| Finished | Jul 13 08:57:30 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-b4edd4f5-5c63-4270-b213-e78fa96d59e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153238821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_ device_slow_rsp.1153238821 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.3215077812 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 124568861 ps |
| CPU time | 16.38 seconds |
| Started | Jul 13 08:35:10 PM PDT 24 |
| Finished | Jul 13 08:35:28 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-6c1d7fb3-58f6-4495-be6e-294ce2c5fe2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215077812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.3215077812 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.367162591 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 2317512130 ps |
| CPU time | 72.8 seconds |
| Started | Jul 13 08:35:20 PM PDT 24 |
| Finished | Jul 13 08:36:33 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-ba0a5732-548b-4fa2-a078-06df72e04f57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367162591 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.367162591 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.1234463370 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 1877189965 ps |
| CPU time | 71.62 seconds |
| Started | Jul 13 08:35:11 PM PDT 24 |
| Finished | Jul 13 08:36:23 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-f106d94a-2301-4b90-910a-ed274b339218 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234463370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.1234463370 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.3056552763 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 36429658469 ps |
| CPU time | 412.01 seconds |
| Started | Jul 13 08:35:10 PM PDT 24 |
| Finished | Jul 13 08:42:03 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-8c0f206d-df06-4aef-9a0e-dccd8b514b81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056552763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.3056552763 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.2771101257 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 7937495494 ps |
| CPU time | 146.79 seconds |
| Started | Jul 13 08:35:10 PM PDT 24 |
| Finished | Jul 13 08:37:38 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-a6aa4740-ffbd-404b-bb34-62d32c1dadc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771101257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.2771101257 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.628902117 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 356839925 ps |
| CPU time | 37.17 seconds |
| Started | Jul 13 08:35:11 PM PDT 24 |
| Finished | Jul 13 08:35:49 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-6e352208-8c01-46fc-bd56-5951dd4b8846 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628902117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_dela ys.628902117 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.717123803 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 474098327 ps |
| CPU time | 32.94 seconds |
| Started | Jul 13 08:35:20 PM PDT 24 |
| Finished | Jul 13 08:35:53 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-3c0ad02b-91d4-49b3-b098-242703e8502e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717123803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.717123803 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.866196476 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 53458679 ps |
| CPU time | 7.49 seconds |
| Started | Jul 13 08:35:08 PM PDT 24 |
| Finished | Jul 13 08:35:16 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-fe06c2c9-1011-49e4-9be9-d8b29d1c8c41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866196476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.866196476 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.1383014632 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 7131203290 ps |
| CPU time | 81.54 seconds |
| Started | Jul 13 08:35:12 PM PDT 24 |
| Finished | Jul 13 08:36:34 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-2ec3cc8a-f1c0-45dc-88a9-c52bcc2cf2c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383014632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.1383014632 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.4168407609 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 5449976769 ps |
| CPU time | 104.8 seconds |
| Started | Jul 13 08:35:08 PM PDT 24 |
| Finished | Jul 13 08:36:53 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-1b074826-20a4-4c10-a308-ee94b8742366 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168407609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.4168407609 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.2454604869 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 56232871 ps |
| CPU time | 6.73 seconds |
| Started | Jul 13 08:35:09 PM PDT 24 |
| Finished | Jul 13 08:35:17 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-9d467888-3db6-4a9f-b5d7-52bd9b133412 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454604869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.2454604869 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.122319626 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 7198449721 ps |
| CPU time | 297.74 seconds |
| Started | Jul 13 08:35:14 PM PDT 24 |
| Finished | Jul 13 08:40:12 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-b305a638-6c78-4da4-aded-052455f9bcec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122319626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.122319626 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.922193777 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 4016721128 ps |
| CPU time | 156.82 seconds |
| Started | Jul 13 08:35:25 PM PDT 24 |
| Finished | Jul 13 08:38:03 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-ed2f0fe7-0f6f-4251-b895-17395305ddbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922193777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.922193777 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.3871238997 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 322833972 ps |
| CPU time | 156.28 seconds |
| Started | Jul 13 08:35:11 PM PDT 24 |
| Finished | Jul 13 08:37:48 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-1e7e07d8-d100-4ec8-9959-2e3fc2ae9346 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871238997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_rand_reset.3871238997 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.216644855 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 215224139 ps |
| CPU time | 50.9 seconds |
| Started | Jul 13 08:35:19 PM PDT 24 |
| Finished | Jul 13 08:36:11 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-6f71f3fd-e3f6-451e-b70d-01ba264e5140 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216644855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_reset_error.216644855 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.3140674058 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 166266369 ps |
| CPU time | 11.44 seconds |
| Started | Jul 13 08:35:10 PM PDT 24 |
| Finished | Jul 13 08:35:22 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-954503c7-acb6-4a99-bf3c-e3507971d78c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140674058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.3140674058 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.1333791121 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 1463728412 ps |
| CPU time | 69.97 seconds |
| Started | Jul 13 08:35:19 PM PDT 24 |
| Finished | Jul 13 08:36:30 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-015e0b75-93d0-4928-86d7-f3e2f1d7d5a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333791121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .1333791121 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.4085416696 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 71370182135 ps |
| CPU time | 1249.81 seconds |
| Started | Jul 13 08:35:21 PM PDT 24 |
| Finished | Jul 13 08:56:11 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-dbbd16e2-57a8-4e4a-9f84-99cdddaf11a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085416696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.4085416696 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.59878506 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 1248188540 ps |
| CPU time | 50.67 seconds |
| Started | Jul 13 08:35:24 PM PDT 24 |
| Finished | Jul 13 08:36:16 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-440f0956-31ed-4042-8913-1f72b9d4b0bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59878506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_addr.59878506 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.2759289728 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 1543304425 ps |
| CPU time | 54.32 seconds |
| Started | Jul 13 08:35:22 PM PDT 24 |
| Finished | Jul 13 08:36:16 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-023ce3cc-b5a5-4018-9e36-ea3d89de1467 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759289728 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.2759289728 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.229010346 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 2363292079 ps |
| CPU time | 95.54 seconds |
| Started | Jul 13 08:35:18 PM PDT 24 |
| Finished | Jul 13 08:36:54 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-8de3e573-9884-4966-a0f8-34c7f620de9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229010346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.229010346 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.2080100521 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 27139708923 ps |
| CPU time | 290.17 seconds |
| Started | Jul 13 08:35:22 PM PDT 24 |
| Finished | Jul 13 08:40:13 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-1c3ee5c4-d3fc-4499-b391-efa45f85bd90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080100521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.2080100521 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.3454449758 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 33736163979 ps |
| CPU time | 603.1 seconds |
| Started | Jul 13 08:35:19 PM PDT 24 |
| Finished | Jul 13 08:45:23 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-1ab95323-5535-4d36-9f56-55ba4a6d9037 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454449758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.3454449758 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.2523882068 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 306903498 ps |
| CPU time | 33.18 seconds |
| Started | Jul 13 08:35:19 PM PDT 24 |
| Finished | Jul 13 08:35:52 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-9a67bf01-0917-4e27-9178-83f381fb46a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523882068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.2523882068 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.1294245522 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 1839341980 ps |
| CPU time | 60.87 seconds |
| Started | Jul 13 08:35:21 PM PDT 24 |
| Finished | Jul 13 08:36:22 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-a1a943e0-ed57-4390-b95f-3801fb24287f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294245522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.1294245522 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.3586878138 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 41649663 ps |
| CPU time | 6.14 seconds |
| Started | Jul 13 08:35:20 PM PDT 24 |
| Finished | Jul 13 08:35:27 PM PDT 24 |
| Peak memory | 573924 kb |
| Host | smart-a4500b2e-75b2-492b-ad3e-89078f5714eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586878138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.3586878138 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.2232100883 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 8403695633 ps |
| CPU time | 93.42 seconds |
| Started | Jul 13 08:35:21 PM PDT 24 |
| Finished | Jul 13 08:36:55 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-9aea0599-8760-4f24-a8e5-4a20eaf9746e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232100883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.2232100883 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.572412173 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 4691153264 ps |
| CPU time | 85.37 seconds |
| Started | Jul 13 08:35:24 PM PDT 24 |
| Finished | Jul 13 08:36:51 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-4fabab0a-dae9-4bd3-9c6b-5caf61bd20ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572412173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.572412173 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.3334557807 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 44414863 ps |
| CPU time | 6.23 seconds |
| Started | Jul 13 08:35:18 PM PDT 24 |
| Finished | Jul 13 08:35:25 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-b1289bb4-c6e0-40f3-8540-d1bc5d0af6ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334557807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay s.3334557807 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.1559080107 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 4094362209 ps |
| CPU time | 160.83 seconds |
| Started | Jul 13 08:35:20 PM PDT 24 |
| Finished | Jul 13 08:38:01 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-fcd8a698-9f28-46ec-a408-e99ee33ad448 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559080107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.1559080107 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.1332888999 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 2055036841 ps |
| CPU time | 227.68 seconds |
| Started | Jul 13 08:35:30 PM PDT 24 |
| Finished | Jul 13 08:39:18 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-163c9773-9230-488c-942b-661eb64a6d32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332888999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.1332888999 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.1090926195 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 134593495 ps |
| CPU time | 37.55 seconds |
| Started | Jul 13 08:35:31 PM PDT 24 |
| Finished | Jul 13 08:36:09 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-61001111-fea2-4c46-87c1-8ebf085bf53c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090926195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_rand_reset.1090926195 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.1900452308 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 535722110 ps |
| CPU time | 196.02 seconds |
| Started | Jul 13 08:35:32 PM PDT 24 |
| Finished | Jul 13 08:38:48 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-f773aebc-18f1-4ab2-b287-d63c67850d18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900452308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.1900452308 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.1450835633 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 160488420 ps |
| CPU time | 11 seconds |
| Started | Jul 13 08:35:21 PM PDT 24 |
| Finished | Jul 13 08:35:32 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-1edf2652-c89d-4d02-8f41-83212d9478f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450835633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.1450835633 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.4053200962 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 881562969 ps |
| CPU time | 69.72 seconds |
| Started | Jul 13 08:35:43 PM PDT 24 |
| Finished | Jul 13 08:36:53 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-1c2e5724-d205-4103-845b-817adc369b44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053200962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .4053200962 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.270518117 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 138141267771 ps |
| CPU time | 2514.59 seconds |
| Started | Jul 13 08:35:43 PM PDT 24 |
| Finished | Jul 13 09:17:38 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-cbd92d95-410d-4ab2-9ea8-87b9c5c1349a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270518117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_d evice_slow_rsp.270518117 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.1844433052 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 360897043 ps |
| CPU time | 19.09 seconds |
| Started | Jul 13 08:35:41 PM PDT 24 |
| Finished | Jul 13 08:36:01 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-edb73ac5-b8ac-4231-b880-29eef4a3bba7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844433052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.1844433052 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.2301324067 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 1159432935 ps |
| CPU time | 42.33 seconds |
| Started | Jul 13 08:35:42 PM PDT 24 |
| Finished | Jul 13 08:36:24 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-ee04844f-417c-4165-bb46-2711d7e9975f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301324067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.2301324067 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.254642172 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 596934853 ps |
| CPU time | 25.85 seconds |
| Started | Jul 13 08:35:29 PM PDT 24 |
| Finished | Jul 13 08:35:55 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-f2ae124e-1084-40ca-a9aa-e10feddf60d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254642172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.254642172 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.4102850892 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 77993306183 ps |
| CPU time | 931.73 seconds |
| Started | Jul 13 08:35:33 PM PDT 24 |
| Finished | Jul 13 08:51:05 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-bc639671-290f-45c4-b616-fce3e4c921e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102850892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.4102850892 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.2788047954 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 68033261595 ps |
| CPU time | 1225.88 seconds |
| Started | Jul 13 08:35:42 PM PDT 24 |
| Finished | Jul 13 08:56:08 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-4c9ba8a5-cd83-4ca1-aa88-5e5808c9c8fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788047954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.2788047954 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.1856997578 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 247497512 ps |
| CPU time | 25.95 seconds |
| Started | Jul 13 08:35:29 PM PDT 24 |
| Finished | Jul 13 08:35:55 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-c2b00167-492d-4771-ad2b-03bbbe85d47c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856997578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del ays.1856997578 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.108224506 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 329932645 ps |
| CPU time | 25.22 seconds |
| Started | Jul 13 08:35:44 PM PDT 24 |
| Finished | Jul 13 08:36:09 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-444f4eac-7c54-4ea6-b588-29f8324a8e10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108224506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.108224506 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.981758189 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 192621658 ps |
| CPU time | 8.4 seconds |
| Started | Jul 13 08:35:29 PM PDT 24 |
| Finished | Jul 13 08:35:38 PM PDT 24 |
| Peak memory | 573952 kb |
| Host | smart-7c23d5a6-303c-4f63-9ce0-09479177a016 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981758189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.981758189 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.1415831441 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 9852012300 ps |
| CPU time | 115.83 seconds |
| Started | Jul 13 08:35:30 PM PDT 24 |
| Finished | Jul 13 08:37:26 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-968a086c-f3a4-4d78-b518-60647dcb28f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415831441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.1415831441 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.1145070815 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 4809252351 ps |
| CPU time | 85.64 seconds |
| Started | Jul 13 08:35:29 PM PDT 24 |
| Finished | Jul 13 08:36:55 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-57bb9ee2-c4fc-416b-a10c-fdeb9aa37ad1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145070815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.1145070815 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.2522375020 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 45768963 ps |
| CPU time | 6.99 seconds |
| Started | Jul 13 08:35:31 PM PDT 24 |
| Finished | Jul 13 08:35:39 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-e37682c2-d771-4e84-bf69-a6fdc58002f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522375020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.2522375020 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.2961628077 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 1180332069 ps |
| CPU time | 104.81 seconds |
| Started | Jul 13 08:35:42 PM PDT 24 |
| Finished | Jul 13 08:37:27 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-3f7b9de8-325a-4ac6-916c-a6b9635a8fdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961628077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.2961628077 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.2007025439 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 2483119253 ps |
| CPU time | 100.92 seconds |
| Started | Jul 13 08:35:44 PM PDT 24 |
| Finished | Jul 13 08:37:25 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-0dc92481-4eff-4d4c-bbad-43f492345fc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007025439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.2007025439 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.1487624093 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 383976933 ps |
| CPU time | 220.16 seconds |
| Started | Jul 13 08:35:42 PM PDT 24 |
| Finished | Jul 13 08:39:22 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-3eaa290f-fc89-48bf-94d9-4e3b96626770 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487624093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_rand_reset.1487624093 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.1490426971 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 12963962243 ps |
| CPU time | 603.16 seconds |
| Started | Jul 13 08:35:43 PM PDT 24 |
| Finished | Jul 13 08:45:47 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-25b8f483-6282-4d98-861f-0144ce01217c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490426971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.1490426971 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.2958825472 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 692635796 ps |
| CPU time | 32.36 seconds |
| Started | Jul 13 08:35:43 PM PDT 24 |
| Finished | Jul 13 08:36:16 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-573c69d9-8557-448a-9485-dad61908f8a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958825472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.2958825472 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.1224833921 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 1530309088 ps |
| CPU time | 62.47 seconds |
| Started | Jul 13 08:35:51 PM PDT 24 |
| Finished | Jul 13 08:36:54 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-644fa28e-179c-4414-b276-eb655c328cc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224833921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .1224833921 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.4256851115 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 147995663204 ps |
| CPU time | 2809.62 seconds |
| Started | Jul 13 08:35:53 PM PDT 24 |
| Finished | Jul 13 09:22:44 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-82d74b71-70ff-4e5e-9379-810894a0ade4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256851115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.4256851115 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.3980028225 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 233007557 ps |
| CPU time | 26.51 seconds |
| Started | Jul 13 08:35:54 PM PDT 24 |
| Finished | Jul 13 08:36:20 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-1a2e4c00-0d76-429e-a26d-5189d11b9c87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980028225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.3980028225 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.3949305406 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 2113823644 ps |
| CPU time | 81.5 seconds |
| Started | Jul 13 08:35:51 PM PDT 24 |
| Finished | Jul 13 08:37:13 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-74552510-073b-4786-a7bc-ce8b4613b160 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949305406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.3949305406 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.2552477915 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 74874617 ps |
| CPU time | 10.64 seconds |
| Started | Jul 13 08:35:51 PM PDT 24 |
| Finished | Jul 13 08:36:02 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-66632110-661d-496a-b4bf-0802927d485f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552477915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.2552477915 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.2103325825 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 100220869769 ps |
| CPU time | 1208.79 seconds |
| Started | Jul 13 08:35:57 PM PDT 24 |
| Finished | Jul 13 08:56:06 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-58bf99c4-dbae-4224-9a14-101dda846ea1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103325825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.2103325825 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.3300307359 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 19715475201 ps |
| CPU time | 373.32 seconds |
| Started | Jul 13 08:35:53 PM PDT 24 |
| Finished | Jul 13 08:42:06 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-8327dd06-14fd-45d4-8592-28d14def6c84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300307359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.3300307359 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.1121241973 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 163515201 ps |
| CPU time | 18.88 seconds |
| Started | Jul 13 08:35:50 PM PDT 24 |
| Finished | Jul 13 08:36:10 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-1521f1de-f40f-4ce8-b78f-d0d72c8b04d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121241973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.1121241973 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.2749805463 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 615402686 ps |
| CPU time | 21.24 seconds |
| Started | Jul 13 08:35:53 PM PDT 24 |
| Finished | Jul 13 08:36:15 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-11f995f6-7eb9-424d-8f1a-45fa0fea7a0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749805463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.2749805463 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.3262001120 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 209680035 ps |
| CPU time | 10.15 seconds |
| Started | Jul 13 08:35:50 PM PDT 24 |
| Finished | Jul 13 08:36:00 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-459afee5-410e-483d-ab94-b24b5a993ea5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262001120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.3262001120 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.2927027433 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 7840898837 ps |
| CPU time | 89.62 seconds |
| Started | Jul 13 08:35:51 PM PDT 24 |
| Finished | Jul 13 08:37:21 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-c194f00f-2d62-4cd9-8370-61887be93709 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927027433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.2927027433 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.3636176534 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 4408234963 ps |
| CPU time | 77.96 seconds |
| Started | Jul 13 08:35:50 PM PDT 24 |
| Finished | Jul 13 08:37:08 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-0779b3ca-c944-4ddb-8f90-a71079c0f06b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636176534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.3636176534 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.2211653660 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 42312539 ps |
| CPU time | 6.34 seconds |
| Started | Jul 13 08:35:50 PM PDT 24 |
| Finished | Jul 13 08:35:57 PM PDT 24 |
| Peak memory | 575084 kb |
| Host | smart-9afba64d-5048-46f7-85ab-bba864857a63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211653660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay s.2211653660 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.1019448636 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 11700308220 ps |
| CPU time | 428.5 seconds |
| Started | Jul 13 08:35:53 PM PDT 24 |
| Finished | Jul 13 08:43:02 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-803384c6-bd56-45f4-8995-7ca3efeed01c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019448636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.1019448636 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.3384928610 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 7565378 ps |
| CPU time | 13.45 seconds |
| Started | Jul 13 08:35:57 PM PDT 24 |
| Finished | Jul 13 08:36:11 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-47f34fec-e513-465a-9b08-39ebf7020625 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384928610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.3384928610 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.2100559489 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 393930137 ps |
| CPU time | 84.99 seconds |
| Started | Jul 13 08:35:53 PM PDT 24 |
| Finished | Jul 13 08:37:19 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-fa1dfc92-e504-466f-aa74-a41f5a28ea5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100559489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al l_with_reset_error.2100559489 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.1208810708 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 170010238 ps |
| CPU time | 10.53 seconds |
| Started | Jul 13 08:35:57 PM PDT 24 |
| Finished | Jul 13 08:36:08 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-faecce1a-22bd-410a-a8a6-b131257914f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208810708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.1208810708 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.1014415730 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 929023512 ps |
| CPU time | 81.55 seconds |
| Started | Jul 13 08:36:02 PM PDT 24 |
| Finished | Jul 13 08:37:24 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-0e42bad5-18c2-4931-a1b6-1d0305874885 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014415730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .1014415730 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.2198423443 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 28993624011 ps |
| CPU time | 519.49 seconds |
| Started | Jul 13 08:36:00 PM PDT 24 |
| Finished | Jul 13 08:44:40 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-27ad42b9-7bb4-4a04-869d-e1b4add84271 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198423443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.2198423443 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.790896350 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 431763592 ps |
| CPU time | 21.54 seconds |
| Started | Jul 13 08:36:10 PM PDT 24 |
| Finished | Jul 13 08:36:31 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-7f2376ef-6f45-485d-8b07-54d502cf473b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790896350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_addr .790896350 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.3710862191 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 1674211093 ps |
| CPU time | 64.48 seconds |
| Started | Jul 13 08:36:00 PM PDT 24 |
| Finished | Jul 13 08:37:04 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-e7286a12-a46c-433e-8a2f-810e81d416d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710862191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.3710862191 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.3900616569 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 319748949 ps |
| CPU time | 36.04 seconds |
| Started | Jul 13 08:36:00 PM PDT 24 |
| Finished | Jul 13 08:36:36 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-433a0f58-aec0-409f-ad16-696694d9d270 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900616569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.3900616569 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.973985794 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 24616976531 ps |
| CPU time | 299.77 seconds |
| Started | Jul 13 08:36:00 PM PDT 24 |
| Finished | Jul 13 08:41:00 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-1da4099a-8b50-44f9-b881-958e1674a7af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973985794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.973985794 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.3079077958 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 37007925193 ps |
| CPU time | 685.3 seconds |
| Started | Jul 13 08:36:03 PM PDT 24 |
| Finished | Jul 13 08:47:28 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-41219a24-994b-43cc-a6ff-9276961820cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079077958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.3079077958 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.1180188721 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 549539543 ps |
| CPU time | 46.03 seconds |
| Started | Jul 13 08:35:59 PM PDT 24 |
| Finished | Jul 13 08:36:45 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-1be8e71c-6714-48ca-a2ce-10ec9fd97891 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180188721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.1180188721 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.3648419213 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 1049610100 ps |
| CPU time | 34.68 seconds |
| Started | Jul 13 08:36:01 PM PDT 24 |
| Finished | Jul 13 08:36:36 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-8d47e2ea-05fe-41b7-90c4-f32e5f5b286e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648419213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.3648419213 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.3083160173 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 207077737 ps |
| CPU time | 9.52 seconds |
| Started | Jul 13 08:36:01 PM PDT 24 |
| Finished | Jul 13 08:36:11 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-2020c6b1-c326-4d05-96b3-9c8f58983fec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083160173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.3083160173 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.317737530 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 5147987342 ps |
| CPU time | 57.28 seconds |
| Started | Jul 13 08:36:04 PM PDT 24 |
| Finished | Jul 13 08:37:01 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-df946417-f60e-465b-8688-7b348e64cd82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317737530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.317737530 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.911891772 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 6284692205 ps |
| CPU time | 117.57 seconds |
| Started | Jul 13 08:36:04 PM PDT 24 |
| Finished | Jul 13 08:38:02 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-3136443f-3087-4952-99dc-e9c73bae1d63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911891772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.911891772 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.355716553 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 50166367 ps |
| CPU time | 7.26 seconds |
| Started | Jul 13 08:36:01 PM PDT 24 |
| Finished | Jul 13 08:36:09 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-15a23fdf-1770-4f84-b963-1785512c3654 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355716553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delays .355716553 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.3376655166 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 7419739840 ps |
| CPU time | 296.44 seconds |
| Started | Jul 13 08:36:13 PM PDT 24 |
| Finished | Jul 13 08:41:10 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-631b41ad-5472-43c8-971a-d61e973f108a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376655166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.3376655166 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.3865749882 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 10843815829 ps |
| CPU time | 405.2 seconds |
| Started | Jul 13 08:36:14 PM PDT 24 |
| Finished | Jul 13 08:42:59 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-1dfc59bd-9d86-4b9e-884f-02d536a81453 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865749882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.3865749882 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.4276039760 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 4489866703 ps |
| CPU time | 414.23 seconds |
| Started | Jul 13 08:36:11 PM PDT 24 |
| Finished | Jul 13 08:43:05 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-fbee0cbb-3721-4edd-9c34-ef7426feebd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276039760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.4276039760 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.2079400773 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 332883892 ps |
| CPU time | 113.73 seconds |
| Started | Jul 13 08:36:10 PM PDT 24 |
| Finished | Jul 13 08:38:05 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-09277137-181c-46ca-87f2-cb727bd3c80d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079400773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al l_with_reset_error.2079400773 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.1582219678 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 1388182434 ps |
| CPU time | 58.23 seconds |
| Started | Jul 13 08:36:14 PM PDT 24 |
| Finished | Jul 13 08:37:13 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-2dee9b6f-df71-4bd2-a224-f4ce0c99e9f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582219678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.1582219678 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.3279854507 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 102032657 ps |
| CPU time | 8.93 seconds |
| Started | Jul 13 08:36:33 PM PDT 24 |
| Finished | Jul 13 08:36:42 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-c18d9a3b-77ee-4ed7-85f3-05db1adffbc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279854507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .3279854507 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.1578061148 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 108625318860 ps |
| CPU time | 1906.66 seconds |
| Started | Jul 13 08:36:19 PM PDT 24 |
| Finished | Jul 13 09:08:06 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-f5825867-aa7e-4325-a63b-25a5e51c4fa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578061148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_ device_slow_rsp.1578061148 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.2768934982 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 562093057 ps |
| CPU time | 22.62 seconds |
| Started | Jul 13 08:36:20 PM PDT 24 |
| Finished | Jul 13 08:36:43 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-c20a8722-a686-4b8a-a439-f21537b35db3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768934982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.2768934982 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.1666485835 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 803961695 ps |
| CPU time | 30.01 seconds |
| Started | Jul 13 08:36:26 PM PDT 24 |
| Finished | Jul 13 08:36:57 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-091b7442-2911-4d73-adf5-5fc53fee124f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666485835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.1666485835 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.1759058400 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 300162519 ps |
| CPU time | 30.68 seconds |
| Started | Jul 13 08:36:14 PM PDT 24 |
| Finished | Jul 13 08:36:45 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-0845ac92-2680-4a0e-9f65-26dba942c02f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759058400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.1759058400 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.3007267968 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 91958545736 ps |
| CPU time | 1044.98 seconds |
| Started | Jul 13 08:36:09 PM PDT 24 |
| Finished | Jul 13 08:53:34 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-479ea39c-2804-4009-ac48-f42b3069c6da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007267968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.3007267968 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.340081293 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 34992123392 ps |
| CPU time | 663.58 seconds |
| Started | Jul 13 08:36:13 PM PDT 24 |
| Finished | Jul 13 08:47:17 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-27be9a4c-d998-46c8-a2c9-da97d2aaac56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340081293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.340081293 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.3854703452 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 331162534 ps |
| CPU time | 34.11 seconds |
| Started | Jul 13 08:36:17 PM PDT 24 |
| Finished | Jul 13 08:36:51 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-6b3f976a-ee27-4b54-b4f8-a614d7cb409d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854703452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del ays.3854703452 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.4290976243 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 292987855 ps |
| CPU time | 23.62 seconds |
| Started | Jul 13 08:36:18 PM PDT 24 |
| Finished | Jul 13 08:36:42 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-52125bea-4e12-4c07-8efb-8858a48c2bb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290976243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.4290976243 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.4046704228 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 45104684 ps |
| CPU time | 6.66 seconds |
| Started | Jul 13 08:36:11 PM PDT 24 |
| Finished | Jul 13 08:36:18 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-fcd98dba-74af-489d-948a-d105d3ff7645 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046704228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.4046704228 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.4040213957 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 8288206190 ps |
| CPU time | 92.98 seconds |
| Started | Jul 13 08:36:11 PM PDT 24 |
| Finished | Jul 13 08:37:45 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-afa152e3-a896-4514-a8d9-c5a7eef17f94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040213957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.4040213957 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.3512834119 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 6845896429 ps |
| CPU time | 129.42 seconds |
| Started | Jul 13 08:36:10 PM PDT 24 |
| Finished | Jul 13 08:38:20 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-262a063d-c9fa-4ba8-8d6b-90e6a9302887 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512834119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.3512834119 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.2061489164 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 41364770 ps |
| CPU time | 6.41 seconds |
| Started | Jul 13 08:36:13 PM PDT 24 |
| Finished | Jul 13 08:36:20 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-01e4ac17-af18-4215-b37b-bd6c647315c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061489164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.2061489164 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.138929373 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 7130730387 ps |
| CPU time | 264.05 seconds |
| Started | Jul 13 08:36:19 PM PDT 24 |
| Finished | Jul 13 08:40:44 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-b21a7f82-b595-41d2-bfc9-3e38beced8f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138929373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.138929373 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.3732423980 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 46701190 ps |
| CPU time | 6.31 seconds |
| Started | Jul 13 08:36:21 PM PDT 24 |
| Finished | Jul 13 08:36:27 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-278346a8-3a2a-42e4-acdf-1ea96e750b7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732423980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.3732423980 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.1263770483 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 427558157 ps |
| CPU time | 178.62 seconds |
| Started | Jul 13 08:36:18 PM PDT 24 |
| Finished | Jul 13 08:39:16 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-168d0e5d-263b-4284-9386-304ce9bf27ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263770483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.1263770483 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.685211630 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 10752150441 ps |
| CPU time | 518.86 seconds |
| Started | Jul 13 08:36:23 PM PDT 24 |
| Finished | Jul 13 08:45:03 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-2b652c34-cfb0-4d8e-8091-a920e56f8cfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685211630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_reset_error.685211630 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.2100796371 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 1071910426 ps |
| CPU time | 48.49 seconds |
| Started | Jul 13 08:36:21 PM PDT 24 |
| Finished | Jul 13 08:37:09 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-94509407-df13-41e4-ad2f-bdb1572b5aab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100796371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.2100796371 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.3435563400 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 99467165 ps |
| CPU time | 11.35 seconds |
| Started | Jul 13 08:36:19 PM PDT 24 |
| Finished | Jul 13 08:36:31 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-178dd1ce-640b-4ae0-a581-b483a5894192 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435563400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .3435563400 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2880276382 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 55737543446 ps |
| CPU time | 977.13 seconds |
| Started | Jul 13 08:36:26 PM PDT 24 |
| Finished | Jul 13 08:52:44 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-8a2bc52f-8914-48e6-a133-d8f528508e8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880276382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.2880276382 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.1157758117 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 155926580 ps |
| CPU time | 16.25 seconds |
| Started | Jul 13 08:36:33 PM PDT 24 |
| Finished | Jul 13 08:36:49 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-37494cea-ade7-4849-8908-b0e87a716d06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157758117 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.1157758117 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.3623775033 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 420062379 ps |
| CPU time | 16.87 seconds |
| Started | Jul 13 08:36:23 PM PDT 24 |
| Finished | Jul 13 08:36:40 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-dffff593-dc70-4548-a875-329a71aeb647 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623775033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.3623775033 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.4181597286 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 726337702 ps |
| CPU time | 29.75 seconds |
| Started | Jul 13 08:36:34 PM PDT 24 |
| Finished | Jul 13 08:37:04 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-0ca0dd35-4abd-468a-87dd-5b1405ccfd96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181597286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.4181597286 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.342664829 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 33117760525 ps |
| CPU time | 358.88 seconds |
| Started | Jul 13 08:36:19 PM PDT 24 |
| Finished | Jul 13 08:42:18 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-9fd74b0a-04e8-42b4-9ae6-00218304e6e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342664829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.342664829 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.4260194812 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 57856138950 ps |
| CPU time | 1084.11 seconds |
| Started | Jul 13 08:36:35 PM PDT 24 |
| Finished | Jul 13 08:54:40 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-df661ccb-0855-4672-81dc-6b7e4798dcb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260194812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.4260194812 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.2883417587 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 211666153 ps |
| CPU time | 21.51 seconds |
| Started | Jul 13 08:36:20 PM PDT 24 |
| Finished | Jul 13 08:36:42 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-c30b0ca2-d9ac-4994-a2ea-3a4d27ded29a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883417587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del ays.2883417587 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.836316181 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 199555381 ps |
| CPU time | 9.19 seconds |
| Started | Jul 13 08:36:27 PM PDT 24 |
| Finished | Jul 13 08:36:36 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-325e6f22-6adb-4bc5-9a27-0efda9e829a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836316181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.836316181 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.4232423654 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 213489109 ps |
| CPU time | 9.51 seconds |
| Started | Jul 13 08:36:34 PM PDT 24 |
| Finished | Jul 13 08:36:44 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-c5434686-efb8-44cf-9f4c-1021ac844c9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232423654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.4232423654 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.419669977 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 8368330755 ps |
| CPU time | 90.94 seconds |
| Started | Jul 13 08:36:33 PM PDT 24 |
| Finished | Jul 13 08:38:04 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-4576489d-37ae-43e6-81ac-5a16ee427cca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419669977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.419669977 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.3546992083 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 6086327381 ps |
| CPU time | 106.77 seconds |
| Started | Jul 13 08:36:18 PM PDT 24 |
| Finished | Jul 13 08:38:05 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-f3385bab-8cc4-4cdc-84a1-39c92da614b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546992083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.3546992083 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.4283474766 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 51949367 ps |
| CPU time | 7.07 seconds |
| Started | Jul 13 08:36:20 PM PDT 24 |
| Finished | Jul 13 08:36:28 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-7214991e-2845-4864-b893-534520ddcb51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283474766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.4283474766 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.1570271083 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 13339092937 ps |
| CPU time | 426.11 seconds |
| Started | Jul 13 08:36:29 PM PDT 24 |
| Finished | Jul 13 08:43:35 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-f386a62a-fb99-4cc4-8ac6-bcd186066be9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570271083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.1570271083 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.1893432645 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 4937086136 ps |
| CPU time | 185.55 seconds |
| Started | Jul 13 08:36:32 PM PDT 24 |
| Finished | Jul 13 08:39:38 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-ffb2cd18-e359-4441-ae25-89fc1a090546 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893432645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.1893432645 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.4148155825 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 3119699870 ps |
| CPU time | 349.82 seconds |
| Started | Jul 13 08:36:30 PM PDT 24 |
| Finished | Jul 13 08:42:20 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-0e370779-e21d-47eb-aacc-7cf39f758f6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148155825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_rand_reset.4148155825 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.3818135549 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 193152259 ps |
| CPU time | 44.23 seconds |
| Started | Jul 13 08:36:30 PM PDT 24 |
| Finished | Jul 13 08:37:15 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-6c6e2a7a-b83f-411f-9bac-62626b63d778 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818135549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al l_with_reset_error.3818135549 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.2408189250 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 435038071 ps |
| CPU time | 20.48 seconds |
| Started | Jul 13 08:36:29 PM PDT 24 |
| Finished | Jul 13 08:36:50 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-6c2da417-02cd-4294-9c0e-2e64fad92359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408189250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.2408189250 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.1922817006 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 1960532736 ps |
| CPU time | 89.04 seconds |
| Started | Jul 13 08:36:40 PM PDT 24 |
| Finished | Jul 13 08:38:09 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-35ef5a48-ca39-4a7e-8fe7-55453e40e72f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922817006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device .1922817006 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.2922357942 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 2531151949 ps |
| CPU time | 48.1 seconds |
| Started | Jul 13 08:36:45 PM PDT 24 |
| Finished | Jul 13 08:37:33 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-ae5fa05c-f11e-4d14-9744-4de639d03776 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922357942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.2922357942 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.3532825793 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 520038546 ps |
| CPU time | 22.46 seconds |
| Started | Jul 13 08:36:40 PM PDT 24 |
| Finished | Jul 13 08:37:03 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-9a80b2b3-06dc-47e1-b33c-29b01c3f5670 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532825793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.3532825793 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.4286989614 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 34757750 ps |
| CPU time | 6.73 seconds |
| Started | Jul 13 08:36:45 PM PDT 24 |
| Finished | Jul 13 08:36:52 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-c64556a6-ec59-4516-b9fb-73d62c2e21e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286989614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.4286989614 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.3511983201 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 504459484 ps |
| CPU time | 42.79 seconds |
| Started | Jul 13 08:36:32 PM PDT 24 |
| Finished | Jul 13 08:37:15 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-f24ef0b8-7c3c-4a5a-9b90-531d51b1028f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511983201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.3511983201 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.3393534672 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 100645266762 ps |
| CPU time | 1254.38 seconds |
| Started | Jul 13 08:36:31 PM PDT 24 |
| Finished | Jul 13 08:57:26 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-8c7a4c69-07d6-4cce-9f6e-782f5c401668 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393534672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.3393534672 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.801680342 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 21721066785 ps |
| CPU time | 413.54 seconds |
| Started | Jul 13 08:36:32 PM PDT 24 |
| Finished | Jul 13 08:43:26 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-56cc888a-0f44-4263-851f-49ef21616d4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801680342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.801680342 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.2587854389 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 508905521 ps |
| CPU time | 51.93 seconds |
| Started | Jul 13 08:36:29 PM PDT 24 |
| Finished | Jul 13 08:37:21 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-2c3bd113-3e97-4833-8cb4-af5594e02904 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587854389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del ays.2587854389 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.2054647757 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 1482669732 ps |
| CPU time | 40.05 seconds |
| Started | Jul 13 08:36:41 PM PDT 24 |
| Finished | Jul 13 08:37:21 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-98f4447a-fc1f-4303-8947-5de8a8e0d100 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054647757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.2054647757 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.4070963625 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 57202111 ps |
| CPU time | 7.66 seconds |
| Started | Jul 13 08:36:29 PM PDT 24 |
| Finished | Jul 13 08:36:37 PM PDT 24 |
| Peak memory | 574012 kb |
| Host | smart-f1fab311-09d0-40fc-989c-93cf327b56c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070963625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.4070963625 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.1751533295 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 10166445739 ps |
| CPU time | 110.97 seconds |
| Started | Jul 13 08:36:32 PM PDT 24 |
| Finished | Jul 13 08:38:23 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-374f3fe3-b929-452a-be7f-7908cbb27522 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751533295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.1751533295 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.255995787 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 5246263640 ps |
| CPU time | 99.1 seconds |
| Started | Jul 13 08:36:28 PM PDT 24 |
| Finished | Jul 13 08:38:07 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-b17c4d84-a0db-4643-acb6-15a479287054 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255995787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.255995787 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.2090084258 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 44546481 ps |
| CPU time | 6.58 seconds |
| Started | Jul 13 08:36:29 PM PDT 24 |
| Finished | Jul 13 08:36:36 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-aa41a6e3-6b79-4427-8303-693b7fde149b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090084258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.2090084258 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.2344185068 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 6104035442 ps |
| CPU time | 203.28 seconds |
| Started | Jul 13 08:36:43 PM PDT 24 |
| Finished | Jul 13 08:40:07 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-880eeb92-5e95-4fc8-b20e-eed2c1278ee7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344185068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.2344185068 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.1730329539 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 245564120 ps |
| CPU time | 66.14 seconds |
| Started | Jul 13 08:36:43 PM PDT 24 |
| Finished | Jul 13 08:37:50 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-f6d339ee-42c0-4ccf-b7ee-216093aa6ff8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730329539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.1730329539 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.2815572855 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 61959744 ps |
| CPU time | 25.59 seconds |
| Started | Jul 13 08:36:40 PM PDT 24 |
| Finished | Jul 13 08:37:06 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-dec5ac94-d51c-4e93-98f7-00c91dbea1d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815572855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al l_with_reset_error.2815572855 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.3245958959 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 277045350 ps |
| CPU time | 32.2 seconds |
| Started | Jul 13 08:36:40 PM PDT 24 |
| Finished | Jul 13 08:37:13 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-bfc9fbb1-3bfa-4bdb-9655-1f6880a759dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245958959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.3245958959 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.2018040995 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 3086637953 ps |
| CPU time | 135.83 seconds |
| Started | Jul 13 08:36:43 PM PDT 24 |
| Finished | Jul 13 08:38:59 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-0b165d70-5ed2-4ed4-91d1-cd9f82590d65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018040995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .2018040995 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.2530489428 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 57490435578 ps |
| CPU time | 1045.65 seconds |
| Started | Jul 13 08:36:53 PM PDT 24 |
| Finished | Jul 13 08:54:19 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-bc374c2a-9bd3-4979-9866-fc073e3b1faf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530489428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_ device_slow_rsp.2530489428 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.3920321522 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 172067904 ps |
| CPU time | 9.39 seconds |
| Started | Jul 13 08:36:50 PM PDT 24 |
| Finished | Jul 13 08:37:00 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-2c30834f-8db4-465a-8633-510c3ab03363 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920321522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add r.3920321522 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.143833312 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 418177026 ps |
| CPU time | 29.6 seconds |
| Started | Jul 13 08:36:50 PM PDT 24 |
| Finished | Jul 13 08:37:20 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-936e986c-28ca-4a56-bca6-ee908092bb37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143833312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.143833312 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.1005002269 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 323992004 ps |
| CPU time | 35.84 seconds |
| Started | Jul 13 08:36:43 PM PDT 24 |
| Finished | Jul 13 08:37:19 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-3e7d31f0-4c34-4aae-abfe-deed841db277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005002269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.1005002269 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.843196272 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 89139093674 ps |
| CPU time | 1094.01 seconds |
| Started | Jul 13 08:36:41 PM PDT 24 |
| Finished | Jul 13 08:54:56 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-a2183033-3b34-4b1f-80fe-7eaff4a939b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843196272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.843196272 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.308808560 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 58031972715 ps |
| CPU time | 1010.26 seconds |
| Started | Jul 13 08:36:45 PM PDT 24 |
| Finished | Jul 13 08:53:35 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-96b1b54b-a999-4540-99c7-6c9e374d6c8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308808560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.308808560 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.59528404 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 617789844 ps |
| CPU time | 63.35 seconds |
| Started | Jul 13 08:36:43 PM PDT 24 |
| Finished | Jul 13 08:37:47 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-b8f58918-c60d-425c-b3fb-bc421bd42d97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59528404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_delay s.59528404 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.874969678 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 2591149725 ps |
| CPU time | 83.3 seconds |
| Started | Jul 13 08:36:49 PM PDT 24 |
| Finished | Jul 13 08:38:12 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-3150f4ca-1929-4252-bc63-d529cf276d4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874969678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.874969678 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.3361806819 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 143263880 ps |
| CPU time | 8.31 seconds |
| Started | Jul 13 08:36:39 PM PDT 24 |
| Finished | Jul 13 08:36:48 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-5278884b-50f1-4b3d-a701-107ad0d7389d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361806819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.3361806819 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.3917727627 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 8049987654 ps |
| CPU time | 92.74 seconds |
| Started | Jul 13 08:36:39 PM PDT 24 |
| Finished | Jul 13 08:38:12 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-91d96202-7731-4fac-b6f6-a7f2c73866b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917727627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.3917727627 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.2813867599 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 4566540213 ps |
| CPU time | 88.89 seconds |
| Started | Jul 13 08:36:43 PM PDT 24 |
| Finished | Jul 13 08:38:12 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-6470b00c-c6ea-4332-b103-13f9baacc81e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813867599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.2813867599 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.1979643163 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 44774370 ps |
| CPU time | 7.08 seconds |
| Started | Jul 13 08:36:42 PM PDT 24 |
| Finished | Jul 13 08:36:49 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-bd5ea68d-a5f2-4961-ac8a-ac8038129e15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979643163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay s.1979643163 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.2281858751 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 1825939504 ps |
| CPU time | 78.84 seconds |
| Started | Jul 13 08:36:49 PM PDT 24 |
| Finished | Jul 13 08:38:08 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-f484c0c9-e509-438a-9dcc-7ac5b7c18d2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281858751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.2281858751 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.3707132158 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 6283209303 ps |
| CPU time | 208.85 seconds |
| Started | Jul 13 08:36:53 PM PDT 24 |
| Finished | Jul 13 08:40:22 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-46e1a5a8-5d1b-4e81-a2c1-70b15de941be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707132158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.3707132158 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.3474363989 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 369043670 ps |
| CPU time | 192.75 seconds |
| Started | Jul 13 08:36:47 PM PDT 24 |
| Finished | Jul 13 08:40:01 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-4713729c-72f3-4152-9d1b-6a5a90367ae8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474363989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.3474363989 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.3286160483 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 7253549865 ps |
| CPU time | 327.24 seconds |
| Started | Jul 13 08:36:50 PM PDT 24 |
| Finished | Jul 13 08:42:17 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-fd25ce06-c4bc-409d-a176-ddfd4edfc3e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286160483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_al l_with_reset_error.3286160483 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.2805096350 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 126436715 ps |
| CPU time | 17 seconds |
| Started | Jul 13 08:36:49 PM PDT 24 |
| Finished | Jul 13 08:37:06 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-b8a9aec9-4453-415f-bf69-e7632e9e4900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805096350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.2805096350 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.2240989216 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 1126763380 ps |
| CPU time | 66.07 seconds |
| Started | Jul 13 08:36:58 PM PDT 24 |
| Finished | Jul 13 08:38:04 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-6bcd24ed-41dc-4223-8331-51b925a4008c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240989216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device .2240989216 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.1023897857 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 93476854816 ps |
| CPU time | 1619.64 seconds |
| Started | Jul 13 08:36:58 PM PDT 24 |
| Finished | Jul 13 09:03:58 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-4bd95064-f3dd-48a7-9409-32efe5dd716c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023897857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_ device_slow_rsp.1023897857 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.4028772596 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 903002428 ps |
| CPU time | 34.24 seconds |
| Started | Jul 13 08:36:58 PM PDT 24 |
| Finished | Jul 13 08:37:32 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-1d21aa84-5bc6-4917-a2b7-4874cfa021d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028772596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.4028772596 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.2252273692 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 2141353914 ps |
| CPU time | 74.58 seconds |
| Started | Jul 13 08:36:59 PM PDT 24 |
| Finished | Jul 13 08:38:14 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-7eb3a78f-e12e-4b42-9890-2c7ebf0cbf9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252273692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.2252273692 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.3087600570 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 234360899 ps |
| CPU time | 25.02 seconds |
| Started | Jul 13 08:36:48 PM PDT 24 |
| Finished | Jul 13 08:37:13 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-bce3805a-d8ed-4679-9dad-8c0c8681c802 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087600570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.3087600570 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.3915798078 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 24848860350 ps |
| CPU time | 269.59 seconds |
| Started | Jul 13 08:36:50 PM PDT 24 |
| Finished | Jul 13 08:41:20 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-f179fbe6-9468-4c3a-b214-1459e2268cb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915798078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.3915798078 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.4149796035 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 54147722335 ps |
| CPU time | 967.58 seconds |
| Started | Jul 13 08:36:57 PM PDT 24 |
| Finished | Jul 13 08:53:05 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-f44890d2-d818-4a6b-89ea-606c70a327a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149796035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.4149796035 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.1286667581 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 174474972 ps |
| CPU time | 17.94 seconds |
| Started | Jul 13 08:36:49 PM PDT 24 |
| Finished | Jul 13 08:37:07 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-f57ee3f9-d3bd-4cb4-913f-ba6c34595f65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286667581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.1286667581 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.1210160972 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 1661070255 ps |
| CPU time | 56.99 seconds |
| Started | Jul 13 08:36:58 PM PDT 24 |
| Finished | Jul 13 08:37:56 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-2525e331-ffec-4885-abc2-0fa800e8da09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210160972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.1210160972 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.3674714560 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 47524215 ps |
| CPU time | 6.46 seconds |
| Started | Jul 13 08:36:57 PM PDT 24 |
| Finished | Jul 13 08:37:03 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-2ba8655a-adae-4361-ac8a-5b89c8cf938a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674714560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.3674714560 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.2683398199 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 9869689622 ps |
| CPU time | 114.18 seconds |
| Started | Jul 13 08:36:53 PM PDT 24 |
| Finished | Jul 13 08:38:47 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-e52cbaa6-3f43-40c7-926f-36753502b073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683398199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.2683398199 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.3316381095 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 5419089470 ps |
| CPU time | 95.91 seconds |
| Started | Jul 13 08:36:48 PM PDT 24 |
| Finished | Jul 13 08:38:24 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-d0682422-a2a7-408f-9ce3-7ffd9a22e76b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316381095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.3316381095 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.1527296870 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 40577237 ps |
| CPU time | 6.21 seconds |
| Started | Jul 13 08:36:57 PM PDT 24 |
| Finished | Jul 13 08:37:03 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-7036b01b-8cbd-409d-be33-6cd844c7c900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527296870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay s.1527296870 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.2468740193 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 5747218 ps |
| CPU time | 4.05 seconds |
| Started | Jul 13 08:36:59 PM PDT 24 |
| Finished | Jul 13 08:37:03 PM PDT 24 |
| Peak memory | 565728 kb |
| Host | smart-856f1c79-fb72-4daa-9268-6a961972efca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468740193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.2468740193 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.1750358655 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 8810653317 ps |
| CPU time | 304.52 seconds |
| Started | Jul 13 08:37:00 PM PDT 24 |
| Finished | Jul 13 08:42:05 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-71ddd1b1-90ee-4acf-8c22-e2d3d24b4abb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750358655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.1750358655 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.3291970050 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 2932425216 ps |
| CPU time | 359.28 seconds |
| Started | Jul 13 08:36:59 PM PDT 24 |
| Finished | Jul 13 08:42:59 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-2d9fa5d6-0f8c-48ef-a100-95e0d849cc37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291970050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_rand_reset.3291970050 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.1815561942 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 3415286710 ps |
| CPU time | 316.64 seconds |
| Started | Jul 13 08:36:57 PM PDT 24 |
| Finished | Jul 13 08:42:14 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-5392ffb7-7079-48b3-8d5e-35c787704857 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815561942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_al l_with_reset_error.1815561942 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.2251492168 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 1040920083 ps |
| CPU time | 44.71 seconds |
| Started | Jul 13 08:37:00 PM PDT 24 |
| Finished | Jul 13 08:37:45 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-622a756e-513a-476b-8670-593743aef74b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251492168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.2251492168 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.1520684233 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 10366413690 ps |
| CPU time | 1511.29 seconds |
| Started | Jul 13 07:36:04 PM PDT 24 |
| Finished | Jul 13 08:01:16 PM PDT 24 |
| Peak memory | 607324 kb |
| Host | smart-aceffab2-4fe3-4bf0-94fb-a079c397c368 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520684233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.1520684233 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.840449222 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 13074836885 ps |
| CPU time | 1378.08 seconds |
| Started | Jul 13 07:36:01 PM PDT 24 |
| Finished | Jul 13 07:59:00 PM PDT 24 |
| Peak memory | 607232 kb |
| Host | smart-f97024b7-5b81-438e-81a9-47138e446f9f |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840449222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.840449222 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.3113020690 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 3680012588 ps |
| CPU time | 344.15 seconds |
| Started | Jul 13 07:43:33 PM PDT 24 |
| Finished | Jul 13 07:49:21 PM PDT 24 |
| Peak memory | 608684 kb |
| Host | smart-f6d7da08-3be1-4483-b415-4bd1cdf4ff19 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3113020690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.3113020690 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.1326607519 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 2516927400 ps |
| CPU time | 158.66 seconds |
| Started | Jul 13 07:42:19 PM PDT 24 |
| Finished | Jul 13 07:44:59 PM PDT 24 |
| Peak memory | 608648 kb |
| Host | smart-ae0546c3-5fdf-47bc-8be0-1860b4fbf3da |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326607519 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.1326607519 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2642177272 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 2281915261 ps |
| CPU time | 239.31 seconds |
| Started | Jul 13 07:44:30 PM PDT 24 |
| Finished | Jul 13 07:48:32 PM PDT 24 |
| Peak memory | 608708 kb |
| Host | smart-e82a42e4-2ace-465b-bd43-89a3fa36eb49 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642 177272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.2642177272 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1777820171 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 2539497623 ps |
| CPU time | 236.16 seconds |
| Started | Jul 13 07:48:14 PM PDT 24 |
| Finished | Jul 13 07:52:11 PM PDT 24 |
| Peak memory | 609204 kb |
| Host | smart-3e3fd3d1-5bed-45e1-981a-5633ee7bb02d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777820171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.1777820171 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.1654800024 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 2647134012 ps |
| CPU time | 307.01 seconds |
| Started | Jul 13 07:45:38 PM PDT 24 |
| Finished | Jul 13 07:50:46 PM PDT 24 |
| Peak memory | 608696 kb |
| Host | smart-ebef01d9-3a63-4d1e-a7cb-6a60973196da |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654800024 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.1654800024 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.2874318070 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 2838963600 ps |
| CPU time | 233.76 seconds |
| Started | Jul 13 07:48:25 PM PDT 24 |
| Finished | Jul 13 07:52:20 PM PDT 24 |
| Peak memory | 608692 kb |
| Host | smart-ccbaa69f-57af-4c60-9d46-b6783afd64e2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874318070 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.2874318070 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.2874987758 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 2867641210 ps |
| CPU time | 235.42 seconds |
| Started | Jul 13 07:45:51 PM PDT 24 |
| Finished | Jul 13 07:49:47 PM PDT 24 |
| Peak memory | 609348 kb |
| Host | smart-d409f6f7-6906-4b63-b221-07fb0afa5627 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874987758 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.2874987758 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.390373744 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 2882998600 ps |
| CPU time | 266.94 seconds |
| Started | Jul 13 07:47:59 PM PDT 24 |
| Finished | Jul 13 07:52:29 PM PDT 24 |
| Peak memory | 609116 kb |
| Host | smart-20b9b9e5-8eb8-4b8b-9880-52f611dad34a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390373744 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.390373744 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3443889182 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 3579739061 ps |
| CPU time | 287.97 seconds |
| Started | Jul 13 07:44:55 PM PDT 24 |
| Finished | Jul 13 07:49:44 PM PDT 24 |
| Peak memory | 608972 kb |
| Host | smart-043e4bcb-3072-4c46-9d7c-2f9ee1a3ed59 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3443889182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.3443889182 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3211209649 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 5040457558 ps |
| CPU time | 494.13 seconds |
| Started | Jul 13 07:46:10 PM PDT 24 |
| Finished | Jul 13 07:54:25 PM PDT 24 |
| Peak memory | 618820 kb |
| Host | smart-ba71ff35-6b9b-4c0b-8ad6-95800bf9a1ef |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3211209649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.3211209649 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.55391835 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 6584719920 ps |
| CPU time | 1263.94 seconds |
| Started | Jul 13 07:47:46 PM PDT 24 |
| Finished | Jul 13 08:08:51 PM PDT 24 |
| Peak memory | 609856 kb |
| Host | smart-0b6a2e90-bb7d-46ca-b38f-3bb0d654dec7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=55391835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.55391835 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3400064263 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 7315815900 ps |
| CPU time | 1299.96 seconds |
| Started | Jul 13 07:42:29 PM PDT 24 |
| Finished | Jul 13 08:04:10 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-1882355c-bc04-49d8-b227-0d3250bb1586 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400064263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.3400064263 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2030295800 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 11479484842 ps |
| CPU time | 1273.03 seconds |
| Started | Jul 13 07:48:08 PM PDT 24 |
| Finished | Jul 13 08:09:22 PM PDT 24 |
| Peak memory | 610128 kb |
| Host | smart-ebeac7d2-536d-40a7-8b19-a9a203601b45 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030295800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.2030295800 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.2224108204 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 8403428836 ps |
| CPU time | 1506.87 seconds |
| Started | Jul 13 07:45:34 PM PDT 24 |
| Finished | Jul 13 08:10:43 PM PDT 24 |
| Peak memory | 608376 kb |
| Host | smart-94fb3562-9af7-47fe-b720-f30b2126523b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2224108204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.2224108204 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3637477382 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 4455518712 ps |
| CPU time | 598.53 seconds |
| Started | Jul 13 07:47:18 PM PDT 24 |
| Finished | Jul 13 07:57:18 PM PDT 24 |
| Peak memory | 609664 kb |
| Host | smart-e086a1c5-f260-4426-b30b-5fbab244c291 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3637477382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.3637477382 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.2193020695 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 3326442792 ps |
| CPU time | 485.19 seconds |
| Started | Jul 13 07:47:23 PM PDT 24 |
| Finished | Jul 13 07:55:29 PM PDT 24 |
| Peak memory | 608120 kb |
| Host | smart-05e99149-96b7-429d-8d69-81fc5d30fd19 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193020695 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.2193020695 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3327637103 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 7026291382 ps |
| CPU time | 493.25 seconds |
| Started | Jul 13 07:45:22 PM PDT 24 |
| Finished | Jul 13 07:53:36 PM PDT 24 |
| Peak memory | 608944 kb |
| Host | smart-0612b83a-65b3-4472-83bc-0790d4a8724b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3327637103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3327637103 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.445962578 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 2711568144 ps |
| CPU time | 315.82 seconds |
| Started | Jul 13 07:45:46 PM PDT 24 |
| Finished | Jul 13 07:51:04 PM PDT 24 |
| Peak memory | 609060 kb |
| Host | smart-b76ebe29-c2f3-4fa6-87c4-9f3b8f055c9b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445962578 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_aon_timer_smoketest.445962578 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2130917756 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 7433124400 ps |
| CPU time | 824.01 seconds |
| Started | Jul 13 07:43:22 PM PDT 24 |
| Finished | Jul 13 07:57:07 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-5fe431f8-10e8-424c-8357-432b91dd7954 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2130917756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.2130917756 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1029444508 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 5164843800 ps |
| CPU time | 431.28 seconds |
| Started | Jul 13 07:47:55 PM PDT 24 |
| Finished | Jul 13 07:55:07 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-0dfdde9c-6c10-44f2-aa78-13b9df0d1672 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1029444508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.1029444508 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.1219599213 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 8138122740 ps |
| CPU time | 1193.78 seconds |
| Started | Jul 13 07:48:40 PM PDT 24 |
| Finished | Jul 13 08:08:36 PM PDT 24 |
| Peak memory | 616628 kb |
| Host | smart-9dc341e6-f12f-4ef4-a454-531d95d7dd5b |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219599213 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.1219599213 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2300608779 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 5023912022 ps |
| CPU time | 425.76 seconds |
| Started | Jul 13 07:44:42 PM PDT 24 |
| Finished | Jul 13 07:51:51 PM PDT 24 |
| Peak memory | 620696 kb |
| Host | smart-9b726f8f-60a6-4390-b7ec-bc780f32fbca |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2300608779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.2300608779 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1147872993 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 4539027516 ps |
| CPU time | 622.85 seconds |
| Started | Jul 13 07:44:45 PM PDT 24 |
| Finished | Jul 13 07:55:09 PM PDT 24 |
| Peak memory | 612348 kb |
| Host | smart-8bfb05a8-9bde-4439-8b89-5599ec66fc67 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147872993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.1147872993 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2321281876 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 4180546116 ps |
| CPU time | 713.47 seconds |
| Started | Jul 13 07:46:51 PM PDT 24 |
| Finished | Jul 13 07:58:45 PM PDT 24 |
| Peak memory | 612344 kb |
| Host | smart-dc71b41e-b1bf-4529-aee3-09e77aab0619 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321281876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2321281876 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2434291291 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 5419130828 ps |
| CPU time | 716.44 seconds |
| Started | Jul 13 07:46:29 PM PDT 24 |
| Finished | Jul 13 07:58:26 PM PDT 24 |
| Peak memory | 612352 kb |
| Host | smart-6a558471-0c5e-4812-9de0-0999fc5c2eee |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434291291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2434291291 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3250238928 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 4463089208 ps |
| CPU time | 666.84 seconds |
| Started | Jul 13 07:48:34 PM PDT 24 |
| Finished | Jul 13 07:59:42 PM PDT 24 |
| Peak memory | 612408 kb |
| Host | smart-4a84686f-c209-420e-b5b7-fe70ac6d58b9 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250238928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.3250238928 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.654658733 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 4761433820 ps |
| CPU time | 673.09 seconds |
| Started | Jul 13 07:48:01 PM PDT 24 |
| Finished | Jul 13 07:59:16 PM PDT 24 |
| Peak memory | 612396 kb |
| Host | smart-a49cd0e3-ffb5-4820-916b-d57cabd2bf93 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654658733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.654658733 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3389813493 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 2635329826 ps |
| CPU time | 232.53 seconds |
| Started | Jul 13 07:49:17 PM PDT 24 |
| Finished | Jul 13 07:53:11 PM PDT 24 |
| Peak memory | 609052 kb |
| Host | smart-c47032bf-c19d-4ad1-b38e-e1ef0de3284d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389813493 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.3389813493 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2741799285 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 3353050632 ps |
| CPU time | 419.73 seconds |
| Started | Jul 13 07:45:56 PM PDT 24 |
| Finished | Jul 13 07:52:57 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-45b1453b-2a0e-49f2-80d6-281f5eaed0a1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741799285 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.2741799285 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1947869473 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 3311273925 ps |
| CPU time | 186.86 seconds |
| Started | Jul 13 07:45:58 PM PDT 24 |
| Finished | Jul 13 07:49:06 PM PDT 24 |
| Peak memory | 608892 kb |
| Host | smart-18de42d7-fbaa-4ea5-8459-4e1701561081 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947869473 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.1947869473 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.851833670 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 4488190264 ps |
| CPU time | 377.65 seconds |
| Started | Jul 13 07:51:25 PM PDT 24 |
| Finished | Jul 13 07:57:44 PM PDT 24 |
| Peak memory | 609748 kb |
| Host | smart-a71f139b-e579-46b3-92b0-cdaa72604d73 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851833670 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.851833670 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2515420700 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 4100209676 ps |
| CPU time | 467.69 seconds |
| Started | Jul 13 07:45:18 PM PDT 24 |
| Finished | Jul 13 07:53:07 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-c3450392-854c-433b-8973-f9b6ed09c1c1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515420700 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.2515420700 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2279327163 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 5018182392 ps |
| CPU time | 481.93 seconds |
| Started | Jul 13 07:45:47 PM PDT 24 |
| Finished | Jul 13 07:53:51 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-c273db7b-3e11-45c8-9561-1d84fb432422 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279327163 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.2279327163 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.896324446 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 5946487062 ps |
| CPU time | 477.01 seconds |
| Started | Jul 13 07:46:30 PM PDT 24 |
| Finished | Jul 13 07:54:28 PM PDT 24 |
| Peak memory | 609764 kb |
| Host | smart-5860e68c-8c1e-4ffe-b2b1-70d644f81713 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896324446 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.896324446 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.4021072659 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 10679541944 ps |
| CPU time | 1626.1 seconds |
| Started | Jul 13 07:47:00 PM PDT 24 |
| Finished | Jul 13 08:14:07 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-9e74e1b4-ea30-4bd4-ab1f-5cfbc029c8a3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021072659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.4021072659 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1249817283 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 3184504872 ps |
| CPU time | 418.84 seconds |
| Started | Jul 13 07:47:33 PM PDT 24 |
| Finished | Jul 13 07:54:33 PM PDT 24 |
| Peak memory | 608768 kb |
| Host | smart-03ad415f-03ae-4dfb-a868-4f2fca78c48d |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249817283 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.1249817283 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.996557199 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 4382716456 ps |
| CPU time | 635.44 seconds |
| Started | Jul 13 07:44:36 PM PDT 24 |
| Finished | Jul 13 07:55:13 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-f68b7b6d-9ac9-4d0e-aacf-26e95191a4c9 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996557199 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.996557199 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3985923950 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 3003525000 ps |
| CPU time | 191.95 seconds |
| Started | Jul 13 07:45:27 PM PDT 24 |
| Finished | Jul 13 07:48:41 PM PDT 24 |
| Peak memory | 608652 kb |
| Host | smart-3f0b749a-d1ce-45a8-b193-42d31a5fe92b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985923950 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.3985923950 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_coremark.1441060769 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 71969186020 ps |
| CPU time | 15047 seconds |
| Started | Jul 13 07:44:35 PM PDT 24 |
| Finished | Jul 13 11:55:27 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-76bdcaee-ac4d-4c65-bd4a-f96b89b1648d |
| User | root |
| Command | /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1441060769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.1441060769 |
| Directory | /workspace/0.chip_sw_coremark/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.551518812 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 23107944483 ps |
| CPU time | 4908.4 seconds |
| Started | Jul 13 07:45:46 PM PDT 24 |
| Finished | Jul 13 09:07:38 PM PDT 24 |
| Peak memory | 610128 kb |
| Host | smart-d5f35402-7a3f-43df-ac8b-f4c6c6f76539 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=551518812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.551518812 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1353296302 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 4457732056 ps |
| CPU time | 435.93 seconds |
| Started | Jul 13 07:44:35 PM PDT 24 |
| Finished | Jul 13 07:51:54 PM PDT 24 |
| Peak memory | 609004 kb |
| Host | smart-67a6db37-4131-4518-9b69-65f255f7642d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13532 96302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.1353296302 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.279696729 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 2995118376 ps |
| CPU time | 251.35 seconds |
| Started | Jul 13 07:42:46 PM PDT 24 |
| Finished | Jul 13 07:46:58 PM PDT 24 |
| Peak memory | 608672 kb |
| Host | smart-ef6cb4a2-1679-4cd9-b45e-614d9416788d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279696729 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.279696729 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.2751746611 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 2361083688 ps |
| CPU time | 243.4 seconds |
| Started | Jul 13 07:45:38 PM PDT 24 |
| Finished | Jul 13 07:49:42 PM PDT 24 |
| Peak memory | 609084 kb |
| Host | smart-40a80f3f-5e24-42d1-8833-79fbc966252d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751746611 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.2751746611 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.4268619928 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 5211708918 ps |
| CPU time | 834.24 seconds |
| Started | Jul 13 07:45:52 PM PDT 24 |
| Finished | Jul 13 07:59:48 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-5549910f-9e04-4eb5-a1cd-b4fb259561fb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4268619928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.4268619928 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.991628650 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 4755664724 ps |
| CPU time | 1133.45 seconds |
| Started | Jul 13 07:48:53 PM PDT 24 |
| Finished | Jul 13 08:07:48 PM PDT 24 |
| Peak memory | 608624 kb |
| Host | smart-8f9fad99-b67f-4085-bd23-9c3d8f68913d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991628650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_a uto_mode.991628650 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3996522385 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 6961625122 ps |
| CPU time | 1319.96 seconds |
| Started | Jul 13 07:47:48 PM PDT 24 |
| Finished | Jul 13 08:09:49 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-5204b0b8-abd3-4e29-8b3a-c31595053aa3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3996522385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.3996522385 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.2531646861 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 3323459366 ps |
| CPU time | 795.63 seconds |
| Started | Jul 13 07:43:23 PM PDT 24 |
| Finished | Jul 13 07:56:40 PM PDT 24 |
| Peak memory | 614964 kb |
| Host | smart-7cfa1376-e4b9-4699-b09f-aefef2095147 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531646861 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.2531646861 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.3726587543 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 5671714622 ps |
| CPU time | 1230.91 seconds |
| Started | Jul 13 07:47:41 PM PDT 24 |
| Finished | Jul 13 08:08:13 PM PDT 24 |
| Peak memory | 608680 kb |
| Host | smart-86d68dbf-599b-482b-a34b-f56cfe161c65 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726587543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.3726587543 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3299129128 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 3276697512 ps |
| CPU time | 253.64 seconds |
| Started | Jul 13 07:48:52 PM PDT 24 |
| Finished | Jul 13 07:53:07 PM PDT 24 |
| Peak memory | 609340 kb |
| Host | smart-52f09979-46a2-446b-b3d1-97990407656c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32 99129128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.3299129128 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.269033287 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 2863422120 ps |
| CPU time | 308.44 seconds |
| Started | Jul 13 07:43:38 PM PDT 24 |
| Finished | Jul 13 07:48:49 PM PDT 24 |
| Peak memory | 608680 kb |
| Host | smart-51c34fa4-e955-490a-a26f-84f9ab8814aa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269033287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.269033287 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.4052505824 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 3600077900 ps |
| CPU time | 463.87 seconds |
| Started | Jul 13 07:46:30 PM PDT 24 |
| Finished | Jul 13 07:54:15 PM PDT 24 |
| Peak memory | 608696 kb |
| Host | smart-91bf3c06-afb3-4ecd-89aa-0aa2c7318608 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4052505824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.4052505824 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.655034699 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 2925576860 ps |
| CPU time | 186.15 seconds |
| Started | Jul 13 07:43:01 PM PDT 24 |
| Finished | Jul 13 07:46:07 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-f51ec8a7-b577-4f3e-be6f-1812b4d5cb2a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655034699 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_concurrency.655034699 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.3816343447 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 2966377114 ps |
| CPU time | 298.23 seconds |
| Started | Jul 13 07:46:18 PM PDT 24 |
| Finished | Jul 13 07:51:17 PM PDT 24 |
| Peak memory | 609128 kb |
| Host | smart-1e7a0695-78d7-43ff-8900-5217f48b7d51 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816343447 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.3816343447 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.1326341205 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 2716141286 ps |
| CPU time | 200.46 seconds |
| Started | Jul 13 07:43:11 PM PDT 24 |
| Finished | Jul 13 07:46:35 PM PDT 24 |
| Peak memory | 608604 kb |
| Host | smart-129a2997-58b9-490e-97ab-ca90e8fa17e6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326341205 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.1326341205 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.1429470229 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2209062380 ps |
| CPU time | 128.65 seconds |
| Started | Jul 13 07:42:52 PM PDT 24 |
| Finished | Jul 13 07:45:01 PM PDT 24 |
| Peak memory | 608888 kb |
| Host | smart-21ba62d6-c941-4478-b85b-b92c1cae00bb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429470229 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_rom.1429470229 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.816042413 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 58970058170 ps |
| CPU time | 11145 seconds |
| Started | Jul 13 07:44:23 PM PDT 24 |
| Finished | Jul 13 10:50:11 PM PDT 24 |
| Peak memory | 624216 kb |
| Host | smart-0a9dc1d3-f6ee-4f16-adc3-804dd4d3ea95 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=816042413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.816042413 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.177572915 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 5726371368 ps |
| CPU time | 738.29 seconds |
| Started | Jul 13 07:47:43 PM PDT 24 |
| Finished | Jul 13 08:00:02 PM PDT 24 |
| Peak memory | 610176 kb |
| Host | smart-68def75f-6eb7-4c3b-9d7d-feae1ea82ce1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=177572915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.177572915 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3525704796 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 5618587418 ps |
| CPU time | 1090.28 seconds |
| Started | Jul 13 07:46:30 PM PDT 24 |
| Finished | Jul 13 08:04:41 PM PDT 24 |
| Peak memory | 609324 kb |
| Host | smart-9837c491-2411-40d5-8867-1f15c707583d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525704796 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.3525704796 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.711858575 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 5821251920 ps |
| CPU time | 1110.11 seconds |
| Started | Jul 13 07:44:57 PM PDT 24 |
| Finished | Jul 13 08:03:30 PM PDT 24 |
| Peak memory | 608676 kb |
| Host | smart-6bd7a8c6-4ae9-4538-ab69-7cb53307b2c7 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711858575 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.711858575 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2490097664 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 7306553697 ps |
| CPU time | 1369.37 seconds |
| Started | Jul 13 07:45:52 PM PDT 24 |
| Finished | Jul 13 08:08:42 PM PDT 24 |
| Peak memory | 608712 kb |
| Host | smart-6a42b142-775f-4d91-bb59-f0bc4d6bf68d |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490097664 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2490097664 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1655994393 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 5330561044 ps |
| CPU time | 1092.95 seconds |
| Started | Jul 13 07:45:43 PM PDT 24 |
| Finished | Jul 13 08:03:58 PM PDT 24 |
| Peak memory | 608252 kb |
| Host | smart-c947b8ab-c011-4395-a52f-2ef298cbf9a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655994393 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.1655994393 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1038221045 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 3473763400 ps |
| CPU time | 357.35 seconds |
| Started | Jul 13 07:44:34 PM PDT 24 |
| Finished | Jul 13 07:50:35 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-ff68501e-0c41-48c9-9755-09cea177f746 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038221045 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.1038221045 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3398082937 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 5448847840 ps |
| CPU time | 1048.59 seconds |
| Started | Jul 13 07:44:10 PM PDT 24 |
| Finished | Jul 13 08:01:40 PM PDT 24 |
| Peak memory | 609588 kb |
| Host | smart-ba1f8232-b0ec-4181-8763-3c703433af0e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398082937 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.3398082937 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3337392293 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 4959962504 ps |
| CPU time | 745.43 seconds |
| Started | Jul 13 07:44:39 PM PDT 24 |
| Finished | Jul 13 07:57:06 PM PDT 24 |
| Peak memory | 609600 kb |
| Host | smart-d476fb3d-0d94-4740-8439-c44b28bfffbf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3337392293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3337392293 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.122427979 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 3695866104 ps |
| CPU time | 352.51 seconds |
| Started | Jul 13 07:48:09 PM PDT 24 |
| Finished | Jul 13 07:54:03 PM PDT 24 |
| Peak memory | 607948 kb |
| Host | smart-98d1ff3b-de9d-4b95-84ed-979e492bc6e4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224279 79 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.122427979 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.237482108 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 20772262218 ps |
| CPU time | 2575.7 seconds |
| Started | Jul 13 07:44:59 PM PDT 24 |
| Finished | Jul 13 08:27:57 PM PDT 24 |
| Peak memory | 612784 kb |
| Host | smart-1462bfa6-f9b8-41dc-bd98-39a64e9e2fb3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237482108 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.237482108 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.882515580 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 20854663067 ps |
| CPU time | 1882.41 seconds |
| Started | Jul 13 07:43:36 PM PDT 24 |
| Finished | Jul 13 08:15:02 PM PDT 24 |
| Peak memory | 611776 kb |
| Host | smart-eb88fa90-1045-44b2-afdc-86a3aee3f1a0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=882515580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.882515580 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1203097381 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 2520164044 ps |
| CPU time | 297.86 seconds |
| Started | Jul 13 07:54:18 PM PDT 24 |
| Finished | Jul 13 07:59:17 PM PDT 24 |
| Peak memory | 609092 kb |
| Host | smart-1c5c073a-bf7f-4a4e-9a1d-242dd08cfd2f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1203097381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.1203097381 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.3935470310 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 2600761030 ps |
| CPU time | 217.35 seconds |
| Started | Jul 13 07:46:17 PM PDT 24 |
| Finished | Jul 13 07:49:55 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-59441308-6e39-4e4c-b1ce-9167a5822b60 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935470310 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.3935470310 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.2371918538 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 2926682438 ps |
| CPU time | 264.47 seconds |
| Started | Jul 13 07:45:54 PM PDT 24 |
| Finished | Jul 13 07:50:19 PM PDT 24 |
| Peak memory | 609152 kb |
| Host | smart-ee5acb58-2284-4e06-bebc-37c1c6c8d8df |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371918538 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.2371918538 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3976379395 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 2837900167 ps |
| CPU time | 278.27 seconds |
| Started | Jul 13 07:45:25 PM PDT 24 |
| Finished | Jul 13 07:50:06 PM PDT 24 |
| Peak memory | 608684 kb |
| Host | smart-cc3c9b15-3b3b-4e73-b357-5fe263c5dc0f |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976379395 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.3976379395 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.690444166 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 3096412514 ps |
| CPU time | 218.92 seconds |
| Started | Jul 13 07:46:20 PM PDT 24 |
| Finished | Jul 13 07:49:59 PM PDT 24 |
| Peak memory | 608712 kb |
| Host | smart-fd276269-a085-47c0-8d22-69849ec03ae3 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690444166 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.690444166 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.1490913515 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 7578999376 ps |
| CPU time | 2031.19 seconds |
| Started | Jul 13 07:44:28 PM PDT 24 |
| Finished | Jul 13 08:18:23 PM PDT 24 |
| Peak memory | 609532 kb |
| Host | smart-08fa3535-fce3-4218-82b9-be6975d4b6e7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490913515 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.1490913515 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.3922833113 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 3020786612 ps |
| CPU time | 310.6 seconds |
| Started | Jul 13 07:48:34 PM PDT 24 |
| Finished | Jul 13 07:53:45 PM PDT 24 |
| Peak memory | 608672 kb |
| Host | smart-27b29e99-f2d0-4343-89c2-8b8e343153ab |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922833113 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.3922833113 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.3977963279 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 3306191400 ps |
| CPU time | 460.13 seconds |
| Started | Jul 13 07:48:24 PM PDT 24 |
| Finished | Jul 13 07:56:06 PM PDT 24 |
| Peak memory | 609224 kb |
| Host | smart-ce25cfbe-8f86-4891-9d25-bcc52ef89785 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977963279 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.3977963279 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1484666781 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 3607865144 ps |
| CPU time | 545.99 seconds |
| Started | Jul 13 07:47:48 PM PDT 24 |
| Finished | Jul 13 07:56:55 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-2a39ea81-7dc1-4591-9742-1f857a14c824 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484666781 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.1484666781 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.660997739 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 5868721974 ps |
| CPU time | 814.27 seconds |
| Started | Jul 13 07:43:34 PM PDT 24 |
| Finished | Jul 13 07:57:12 PM PDT 24 |
| Peak memory | 608608 kb |
| Host | smart-2d1c2c3c-7cb6-4e97-b518-da091c5a7eac |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660997739 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.660997739 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.4125091058 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 64712620919 ps |
| CPU time | 12155.2 seconds |
| Started | Jul 13 07:45:20 PM PDT 24 |
| Finished | Jul 13 11:07:57 PM PDT 24 |
| Peak memory | 624200 kb |
| Host | smart-bd7f7f0d-3525-421e-b6d6-ac270d0f19e7 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4125091058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.4125091058 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3584340485 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 9472914505 ps |
| CPU time | 1787.36 seconds |
| Started | Jul 13 07:44:33 PM PDT 24 |
| Finished | Jul 13 08:14:24 PM PDT 24 |
| Peak memory | 617220 kb |
| Host | smart-69bc5b35-c547-4a3a-afa8-5e2a3b73c093 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3584340485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.3584340485 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1796086300 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 13374586791 ps |
| CPU time | 2459.43 seconds |
| Started | Jul 13 07:43:45 PM PDT 24 |
| Finished | Jul 13 08:24:46 PM PDT 24 |
| Peak memory | 616296 kb |
| Host | smart-e2fa3b8e-ebcf-46f7-97a9-17994b1ab8b8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1796086300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1796086300 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.948541209 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 9081303612 ps |
| CPU time | 2026.53 seconds |
| Started | Jul 13 07:51:34 PM PDT 24 |
| Finished | Jul 13 08:25:21 PM PDT 24 |
| Peak memory | 617232 kb |
| Host | smart-48b550e1-34b8-48be-9660-0d030c1b5826 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=948541209 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.948541209 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1616118255 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 6250472168 ps |
| CPU time | 1239.1 seconds |
| Started | Jul 13 07:43:19 PM PDT 24 |
| Finished | Jul 13 08:04:00 PM PDT 24 |
| Peak memory | 610752 kb |
| Host | smart-6542c071-067e-451a-b1c8-b72ab3c2d896 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16161 18255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.1616118255 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.3182242223 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 2643608920 ps |
| CPU time | 170.46 seconds |
| Started | Jul 13 07:49:29 PM PDT 24 |
| Finished | Jul 13 07:52:22 PM PDT 24 |
| Peak memory | 609208 kb |
| Host | smart-66a69955-8f80-4a42-8475-5577fa36cbc4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182242223 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.3182242223 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.911249414 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 3464390470 ps |
| CPU time | 251.93 seconds |
| Started | Jul 13 07:41:54 PM PDT 24 |
| Finished | Jul 13 07:46:07 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-f3e88279-5aa2-4f2d-adce-a9dc110b4025 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911249414 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_kmac_entropy.911249414 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.3646303016 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 2972815316 ps |
| CPU time | 233.94 seconds |
| Started | Jul 13 07:44:58 PM PDT 24 |
| Finished | Jul 13 07:48:55 PM PDT 24 |
| Peak memory | 609060 kb |
| Host | smart-7bb2a23b-4204-4f62-978f-0137f6eb18fc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646303016 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.3646303016 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1808312833 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 2933699970 ps |
| CPU time | 179.82 seconds |
| Started | Jul 13 07:43:30 PM PDT 24 |
| Finished | Jul 13 07:46:33 PM PDT 24 |
| Peak memory | 609212 kb |
| Host | smart-a578ecbd-eaa1-436d-8deb-63481c76a173 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808312833 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.1808312833 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.405751254 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 3202559790 ps |
| CPU time | 372.63 seconds |
| Started | Jul 13 07:46:30 PM PDT 24 |
| Finished | Jul 13 07:52:44 PM PDT 24 |
| Peak memory | 607940 kb |
| Host | smart-16e66fbf-d738-46f2-9944-00dc5bb57072 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405751254 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_kmac_mode_kmac.405751254 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2743011978 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 2888905219 ps |
| CPU time | 299.94 seconds |
| Started | Jul 13 07:46:16 PM PDT 24 |
| Finished | Jul 13 07:51:16 PM PDT 24 |
| Peak memory | 609056 kb |
| Host | smart-06f423cb-1a8a-4751-833e-647f8b29a918 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743011978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.2743011978 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1195849981 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 3103797625 ps |
| CPU time | 319.97 seconds |
| Started | Jul 13 07:45:14 PM PDT 24 |
| Finished | Jul 13 07:50:35 PM PDT 24 |
| Peak memory | 608700 kb |
| Host | smart-d81742e9-ca2c-4d13-b08e-c47d2742a5da |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11958499 81 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1195849981 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.4070555791 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 2847146088 ps |
| CPU time | 238.88 seconds |
| Started | Jul 13 07:46:07 PM PDT 24 |
| Finished | Jul 13 07:50:07 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-04ecce19-e6e1-44bb-9af8-7701c07178a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070555791 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.4070555791 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.794745688 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 2791275406 ps |
| CPU time | 228.88 seconds |
| Started | Jul 13 07:42:39 PM PDT 24 |
| Finished | Jul 13 07:46:29 PM PDT 24 |
| Peak memory | 609076 kb |
| Host | smart-27d163fd-c7ef-4027-8d4e-3d640bdeae06 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794745688 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.794745688 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1733371184 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 3030275617 ps |
| CPU time | 123.96 seconds |
| Started | Jul 13 07:47:29 PM PDT 24 |
| Finished | Jul 13 07:49:34 PM PDT 24 |
| Peak memory | 619840 kb |
| Host | smart-b6d2b52d-caa3-420d-8ce1-f3134f37dfff |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733371184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.1733371184 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3999252661 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 3253655916 ps |
| CPU time | 155.54 seconds |
| Started | Jul 13 07:46:28 PM PDT 24 |
| Finished | Jul 13 07:49:05 PM PDT 24 |
| Peak memory | 619992 kb |
| Host | smart-f8cce024-2b4a-46d1-b94d-fe80fb4cd4ea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999252661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.3999252661 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2794830427 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 3643800279 ps |
| CPU time | 161.02 seconds |
| Started | Jul 13 07:44:57 PM PDT 24 |
| Finished | Jul 13 07:47:40 PM PDT 24 |
| Peak memory | 619452 kb |
| Host | smart-0687df50-6200-454d-baf6-c831e46c22fb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2794830427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.2794830427 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1064730131 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 9211589137 ps |
| CPU time | 702.08 seconds |
| Started | Jul 13 07:41:59 PM PDT 24 |
| Finished | Jul 13 07:53:41 PM PDT 24 |
| Peak memory | 622520 kb |
| Host | smart-b280548a-095d-414e-ace7-005dff9934e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064730131 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.1064730131 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3179803334 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 2995730086 ps |
| CPU time | 98.78 seconds |
| Started | Jul 13 07:43:14 PM PDT 24 |
| Finished | Jul 13 07:44:57 PM PDT 24 |
| Peak memory | 614336 kb |
| Host | smart-027068ea-6058-4c7b-92b3-f06fa21aeff0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3179803334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.3179803334 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2109266633 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 2611935315 ps |
| CPU time | 115.94 seconds |
| Started | Jul 13 07:46:59 PM PDT 24 |
| Finished | Jul 13 07:48:55 PM PDT 24 |
| Peak memory | 616428 kb |
| Host | smart-eb5f677a-f6f0-4de7-8a32-a691c3c3b887 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109266633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2109266633 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.4084489466 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 49129256500 ps |
| CPU time | 6922.17 seconds |
| Started | Jul 13 07:46:52 PM PDT 24 |
| Finished | Jul 13 09:42:17 PM PDT 24 |
| Peak memory | 619684 kb |
| Host | smart-e8cfef4a-17b5-4f21-a924-25b4ee275b0b |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084489466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_lc_walkthrough_prod.4084489466 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.44463187 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 9866937151 ps |
| CPU time | 912.04 seconds |
| Started | Jul 13 07:50:08 PM PDT 24 |
| Finished | Jul 13 08:05:23 PM PDT 24 |
| Peak memory | 618332 kb |
| Host | smart-82106a4a-5e34-4ec0-ab31-2f9de0f06d6e |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=44463187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.44463187 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2032123878 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 48181938779 ps |
| CPU time | 5981.25 seconds |
| Started | Jul 13 07:43:45 PM PDT 24 |
| Finished | Jul 13 09:23:29 PM PDT 24 |
| Peak memory | 619632 kb |
| Host | smart-3443535f-9b28-4de5-8310-7dd99f6e1b6d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032123878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.2032123878 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.355695526 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 18551216405 ps |
| CPU time | 4332.31 seconds |
| Started | Jul 13 07:49:19 PM PDT 24 |
| Finished | Jul 13 09:01:33 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-caf0276f-9528-4e9b-8a19-924f05aa0fc7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=355695526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.355695526 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2714243682 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 25577834079 ps |
| CPU time | 4902.95 seconds |
| Started | Jul 13 07:45:48 PM PDT 24 |
| Finished | Jul 13 09:07:33 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-5d168973-d1ec-4982-b252-a67ebc5773e7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714243682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.2714243682 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1899270424 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 3776966430 ps |
| CPU time | 399.08 seconds |
| Started | Jul 13 07:45:07 PM PDT 24 |
| Finished | Jul 13 07:51:49 PM PDT 24 |
| Peak memory | 608600 kb |
| Host | smart-5c3120e6-67f7-4a19-87a2-1d361a7f2dae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899270424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.1899270424 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.243690222 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 5589537458 ps |
| CPU time | 1071.42 seconds |
| Started | Jul 13 07:45:28 PM PDT 24 |
| Finished | Jul 13 08:03:21 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-08cdff62-009e-431e-a44e-73fb2046b6c1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=243690222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.243690222 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.2611971852 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 10010252930 ps |
| CPU time | 2442.13 seconds |
| Started | Jul 13 07:48:43 PM PDT 24 |
| Finished | Jul 13 08:29:26 PM PDT 24 |
| Peak memory | 609532 kb |
| Host | smart-7ee8a852-42f1-4deb-aa8d-d5493e2a2393 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611971852 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.2611971852 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.3215478981 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 26944247074 ps |
| CPU time | 5308.6 seconds |
| Started | Jul 13 07:48:39 PM PDT 24 |
| Finished | Jul 13 09:17:08 PM PDT 24 |
| Peak memory | 609004 kb |
| Host | smart-7e1668f0-b56b-4d4a-8843-7ff8c3d43682 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321547 8981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.3215478981 |
| Directory | /workspace/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2931731446 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 2740823117 ps |
| CPU time | 276.91 seconds |
| Started | Jul 13 07:46:11 PM PDT 24 |
| Finished | Jul 13 07:50:49 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-aae12d49-f536-472b-893a-d2414931f9ea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931731446 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.2931731446 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3800723563 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 6165222708 ps |
| CPU time | 684.92 seconds |
| Started | Jul 13 07:46:13 PM PDT 24 |
| Finished | Jul 13 07:57:40 PM PDT 24 |
| Peak memory | 610428 kb |
| Host | smart-134dad3a-d3ee-4fb1-8700-50b0e1a47dd9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3800723563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.3800723563 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.4172447214 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 8086984096 ps |
| CPU time | 1510.57 seconds |
| Started | Jul 13 07:46:26 PM PDT 24 |
| Finished | Jul 13 08:11:38 PM PDT 24 |
| Peak memory | 609948 kb |
| Host | smart-62285b6c-e47e-4a27-878d-a0f8a256a19d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4172447214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.4172447214 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.343758955 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 8015676912 ps |
| CPU time | 1414.64 seconds |
| Started | Jul 13 07:43:25 PM PDT 24 |
| Finished | Jul 13 08:07:01 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-c7096611-e54c-4b4f-bcb7-2c4247d1a77d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=343758955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.343758955 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3719005807 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 7330840728 ps |
| CPU time | 1364.26 seconds |
| Started | Jul 13 07:43:56 PM PDT 24 |
| Finished | Jul 13 08:06:42 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-2e737b9f-cd1f-44e1-86a6-f7807386ef57 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3719005807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.3719005807 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3919820751 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 4037013680 ps |
| CPU time | 778.61 seconds |
| Started | Jul 13 07:44:28 PM PDT 24 |
| Finished | Jul 13 07:57:30 PM PDT 24 |
| Peak memory | 608556 kb |
| Host | smart-893d265f-431a-424d-94ff-96b27e3ba6db |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3919820751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3919820751 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2462844332 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 3097484810 ps |
| CPU time | 242.86 seconds |
| Started | Jul 13 07:45:06 PM PDT 24 |
| Finished | Jul 13 07:49:11 PM PDT 24 |
| Peak memory | 609216 kb |
| Host | smart-3af4373f-5dbd-49df-bbc5-2d8e37420efe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462844332 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.2462844332 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.4248889763 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 3046852768 ps |
| CPU time | 336.39 seconds |
| Started | Jul 13 07:46:50 PM PDT 24 |
| Finished | Jul 13 07:52:27 PM PDT 24 |
| Peak memory | 609064 kb |
| Host | smart-6d83328d-52a5-41a7-b267-f7043ce09f7e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248889763 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.4248889763 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.2825506853 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 10483696976 ps |
| CPU time | 542.97 seconds |
| Started | Jul 13 07:46:21 PM PDT 24 |
| Finished | Jul 13 07:55:25 PM PDT 24 |
| Peak memory | 608940 kb |
| Host | smart-6b3e2089-ed20-4ce8-8a1f-1d9981307054 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825506853 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.2825506853 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3383206843 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 13026961937 ps |
| CPU time | 2041.33 seconds |
| Started | Jul 13 07:46:41 PM PDT 24 |
| Finished | Jul 13 08:20:44 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-2c4ad0e3-bd2a-4f71-8ebe-5228653938ad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383 206843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.3383206843 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2122761772 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 19577498616 ps |
| CPU time | 2429.81 seconds |
| Started | Jul 13 07:43:44 PM PDT 24 |
| Finished | Jul 13 08:24:16 PM PDT 24 |
| Peak memory | 610044 kb |
| Host | smart-68610c11-ba2a-44fc-83a3-33645c8b1522 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212 2761772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.2122761772 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.69266634 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 15067102609 ps |
| CPU time | 1674.83 seconds |
| Started | Jul 13 07:47:38 PM PDT 24 |
| Finished | Jul 13 08:15:34 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-f0b54dda-08aa-4268-baeb-c048bd8c787e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=69266634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.69266634 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3701452495 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 23859482232 ps |
| CPU time | 1717.66 seconds |
| Started | Jul 13 07:44:29 PM PDT 24 |
| Finished | Jul 13 08:13:10 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-79999291-9dcb-42f7-95e5-605424e7f13b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3701452495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3701452495 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1357974650 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 9480961416 ps |
| CPU time | 724.67 seconds |
| Started | Jul 13 07:44:44 PM PDT 24 |
| Finished | Jul 13 07:56:51 PM PDT 24 |
| Peak memory | 610112 kb |
| Host | smart-b206ab65-06e0-4f45-a268-f5d586c1d819 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357974650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.1357974650 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1480390573 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 6520744140 ps |
| CPU time | 645.41 seconds |
| Started | Jul 13 07:46:31 PM PDT 24 |
| Finished | Jul 13 07:57:17 PM PDT 24 |
| Peak memory | 616784 kb |
| Host | smart-4c90dc69-38df-4d5d-80fa-18f99b637659 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1480390573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1480390573 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1173172706 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 9487461544 ps |
| CPU time | 561.82 seconds |
| Started | Jul 13 07:44:25 PM PDT 24 |
| Finished | Jul 13 07:53:49 PM PDT 24 |
| Peak memory | 609084 kb |
| Host | smart-541d77af-f4d9-4a83-b906-fc6e6347d3e5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173172706 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.1173172706 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2979314096 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 10881339262 ps |
| CPU time | 1708.48 seconds |
| Started | Jul 13 07:45:12 PM PDT 24 |
| Finished | Jul 13 08:13:42 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-0c86dfcf-527e-45c7-a316-cc0387f28c9d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979314096 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2979314096 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2179774929 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 7162078990 ps |
| CPU time | 419.96 seconds |
| Started | Jul 13 07:45:09 PM PDT 24 |
| Finished | Jul 13 07:52:10 PM PDT 24 |
| Peak memory | 609896 kb |
| Host | smart-30e3afed-4949-4af7-91b3-27ef5f473330 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179774929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2179774929 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1201152817 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 6084694390 ps |
| CPU time | 616.27 seconds |
| Started | Jul 13 07:45:09 PM PDT 24 |
| Finished | Jul 13 07:55:26 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-addc2d61-150b-4a35-96ef-23789191e6a7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201152817 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.1201152817 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3851731466 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 20012914124 ps |
| CPU time | 2475.33 seconds |
| Started | Jul 13 07:44:25 PM PDT 24 |
| Finished | Jul 13 08:25:43 PM PDT 24 |
| Peak memory | 610664 kb |
| Host | smart-eb8c978e-b532-4992-b363-eec3ee0b849b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3851731466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3851731466 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.310700884 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 33837565076 ps |
| CPU time | 3632.32 seconds |
| Started | Jul 13 07:44:00 PM PDT 24 |
| Finished | Jul 13 08:44:34 PM PDT 24 |
| Peak memory | 611296 kb |
| Host | smart-f1cd4a92-fe75-4859-a840-04a4a379401c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310700884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.310700884 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.4236243364 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 3372655516 ps |
| CPU time | 339.95 seconds |
| Started | Jul 13 07:44:31 PM PDT 24 |
| Finished | Jul 13 07:50:13 PM PDT 24 |
| Peak memory | 608972 kb |
| Host | smart-c6029d78-496b-450a-be67-3d30f74a6ba2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236243364 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.4236243364 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3686446216 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 7235422880 ps |
| CPU time | 493.12 seconds |
| Started | Jul 13 07:43:52 PM PDT 24 |
| Finished | Jul 13 07:52:08 PM PDT 24 |
| Peak memory | 615892 kb |
| Host | smart-de476955-2615-4041-85ff-b7c4a685e395 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3686446216 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.3686446216 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.836829810 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 4875528132 ps |
| CPU time | 418.45 seconds |
| Started | Jul 13 07:48:53 PM PDT 24 |
| Finished | Jul 13 07:55:52 PM PDT 24 |
| Peak memory | 608228 kb |
| Host | smart-3052f216-e55a-4c61-860d-f8b3180d48f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83682981 0 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.836829810 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.617114740 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 5719177840 ps |
| CPU time | 490.14 seconds |
| Started | Jul 13 07:45:01 PM PDT 24 |
| Finished | Jul 13 07:53:12 PM PDT 24 |
| Peak memory | 609516 kb |
| Host | smart-4af43a0e-0501-4880-a003-55a29d5ffa49 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617114740 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.617114740 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3960389475 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 8063191077 ps |
| CPU time | 1180.72 seconds |
| Started | Jul 13 07:47:52 PM PDT 24 |
| Finished | Jul 13 08:07:34 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-f5605516-1dee-4c2b-af07-4ee13dc37432 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960389475 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.3960389475 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.334838379 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 4424469210 ps |
| CPU time | 674.88 seconds |
| Started | Jul 13 07:45:03 PM PDT 24 |
| Finished | Jul 13 07:56:20 PM PDT 24 |
| Peak memory | 609748 kb |
| Host | smart-6011231f-d127-479d-bf13-4a67f7bcfc0a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334838379 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.334838379 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1121946871 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 5744314104 ps |
| CPU time | 596.3 seconds |
| Started | Jul 13 07:48:21 PM PDT 24 |
| Finished | Jul 13 07:58:18 PM PDT 24 |
| Peak memory | 609428 kb |
| Host | smart-ee81240d-4c5d-404c-ad63-c92fef3685b5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121946871 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.1121946871 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3258043408 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 5341642056 ps |
| CPU time | 594.52 seconds |
| Started | Jul 13 07:44:55 PM PDT 24 |
| Finished | Jul 13 07:54:51 PM PDT 24 |
| Peak memory | 608944 kb |
| Host | smart-e86296e6-0900-417d-97f7-c50f2ac76c99 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325 8043408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.3258043408 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3218254863 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 9194472098 ps |
| CPU time | 431.94 seconds |
| Started | Jul 13 07:45:58 PM PDT 24 |
| Finished | Jul 13 07:53:11 PM PDT 24 |
| Peak memory | 624128 kb |
| Host | smart-713e376b-ab11-4519-ade1-b283a1929511 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218254863 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.3218254863 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3329030512 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 6020032160 ps |
| CPU time | 808.44 seconds |
| Started | Jul 13 07:44:28 PM PDT 24 |
| Finished | Jul 13 07:58:00 PM PDT 24 |
| Peak memory | 640884 kb |
| Host | smart-7c2bd8ff-f50d-46d3-aa1d-6076c78f24dc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3329030512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.3329030512 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3691342740 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 3225561204 ps |
| CPU time | 289.62 seconds |
| Started | Jul 13 07:43:43 PM PDT 24 |
| Finished | Jul 13 07:48:33 PM PDT 24 |
| Peak memory | 609084 kb |
| Host | smart-40ae7c22-ec2e-40b8-bcc7-69ef649394c3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691342740 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.3691342740 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2895284278 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 3806484160 ps |
| CPU time | 514.12 seconds |
| Started | Jul 13 07:47:45 PM PDT 24 |
| Finished | Jul 13 07:56:20 PM PDT 24 |
| Peak memory | 609448 kb |
| Host | smart-da11c2ec-0bc6-47df-ba6f-31adb3d0f505 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895284278 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.2895284278 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1406208397 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 3245889376 ps |
| CPU time | 248.59 seconds |
| Started | Jul 13 07:45:07 PM PDT 24 |
| Finished | Jul 13 07:49:17 PM PDT 24 |
| Peak memory | 607936 kb |
| Host | smart-8f432143-b69e-4f92-999c-b17e3f1ae0f3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406208397 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.1406208397 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1904101098 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 3473642886 ps |
| CPU time | 241.63 seconds |
| Started | Jul 13 07:44:26 PM PDT 24 |
| Finished | Jul 13 07:48:30 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-f128ec28-c8ab-4e0b-93fc-0a636d121935 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904101098 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.1904101098 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.4222142840 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2610572280 ps |
| CPU time | 238.79 seconds |
| Started | Jul 13 07:45:35 PM PDT 24 |
| Finished | Jul 13 07:49:35 PM PDT 24 |
| Peak memory | 616220 kb |
| Host | smart-c4b73979-60b2-4ac3-9292-7a6774bd1d07 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222142840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.4222142840 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.417760374 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 5466501256 ps |
| CPU time | 1072.01 seconds |
| Started | Jul 13 07:43:33 PM PDT 24 |
| Finished | Jul 13 08:01:29 PM PDT 24 |
| Peak memory | 608688 kb |
| Host | smart-5c6e8ef8-dfad-4732-acca-4d11c221ee02 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=417760374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.417760374 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.3261092640 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 5850947226 ps |
| CPU time | 436.79 seconds |
| Started | Jul 13 07:43:55 PM PDT 24 |
| Finished | Jul 13 07:51:13 PM PDT 24 |
| Peak memory | 619380 kb |
| Host | smart-a7087b1d-cfa6-4b9c-b989-f6ac764b20f8 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261092640 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.3261092640 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1903326639 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 4819054676 ps |
| CPU time | 354.85 seconds |
| Started | Jul 13 07:45:02 PM PDT 24 |
| Finished | Jul 13 07:50:58 PM PDT 24 |
| Peak memory | 618496 kb |
| Host | smart-956875ba-218a-4cf9-b2e5-4cc0dbebac41 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190332 6639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1903326639 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2377546541 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 2732903720 ps |
| CPU time | 253.93 seconds |
| Started | Jul 13 07:45:03 PM PDT 24 |
| Finished | Jul 13 07:49:19 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-9fb93dad-036d-4447-b029-8f6e69eda837 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377546541 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.2377546541 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.3128122530 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 3035192360 ps |
| CPU time | 244.25 seconds |
| Started | Jul 13 07:48:28 PM PDT 24 |
| Finished | Jul 13 07:52:33 PM PDT 24 |
| Peak memory | 608000 kb |
| Host | smart-df773806-71a8-40c9-8d5e-4ea3941f4d1d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128122530 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.3128122530 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2865694883 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 2644202512 ps |
| CPU time | 238.46 seconds |
| Started | Jul 13 07:47:33 PM PDT 24 |
| Finished | Jul 13 07:51:32 PM PDT 24 |
| Peak memory | 609220 kb |
| Host | smart-debe00c5-e1fb-44f3-a804-9caa18c480a5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865694883 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.2865694883 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3948821723 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 8562168152 ps |
| CPU time | 1431.05 seconds |
| Started | Jul 13 07:43:41 PM PDT 24 |
| Finished | Jul 13 08:07:34 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-ec87b495-056f-4e75-b9b7-662a3360aeac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948821723 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.3948821723 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1880542439 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 6895714660 ps |
| CPU time | 1000.68 seconds |
| Started | Jul 13 07:49:21 PM PDT 24 |
| Finished | Jul 13 08:06:03 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-a385382d-6130-467e-b8c4-00f8cfc66a9c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880542439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.1880542439 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3427287018 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 7743961904 ps |
| CPU time | 784.65 seconds |
| Started | Jul 13 07:50:15 PM PDT 24 |
| Finished | Jul 13 08:03:22 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-2ffe54d2-af3e-4007-8abe-4b449c795cc5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427287018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.3427287018 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.997975122 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3074460220 ps |
| CPU time | 334.42 seconds |
| Started | Jul 13 07:43:40 PM PDT 24 |
| Finished | Jul 13 07:49:16 PM PDT 24 |
| Peak memory | 618840 kb |
| Host | smart-ecbe5c47-0d26-4177-b3a9-8cd40403633c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997975122 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.997975122 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1734405815 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3472263928 ps |
| CPU time | 376.42 seconds |
| Started | Jul 13 07:42:06 PM PDT 24 |
| Finished | Jul 13 07:48:24 PM PDT 24 |
| Peak memory | 609736 kb |
| Host | smart-724bdfa9-8644-4d54-9ea3-68eb401b783c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734405815 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.1734405815 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1832379181 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 8623010062 ps |
| CPU time | 1009.67 seconds |
| Started | Jul 13 07:46:38 PM PDT 24 |
| Finished | Jul 13 08:03:28 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-cb55fbd3-09b4-4a27-b5fa-1ffcdcae3396 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832379181 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.1832379181 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.844101613 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 3694863720 ps |
| CPU time | 606.21 seconds |
| Started | Jul 13 07:50:12 PM PDT 24 |
| Finished | Jul 13 08:00:22 PM PDT 24 |
| Peak memory | 609024 kb |
| Host | smart-d6d11390-4ef5-48cd-b64e-42a60c8c7bc0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844101613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ sram_ctrl_scrambled_access.844101613 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.770554685 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 4241149284 ps |
| CPU time | 702.56 seconds |
| Started | Jul 13 07:46:18 PM PDT 24 |
| Finished | Jul 13 07:58:01 PM PDT 24 |
| Peak memory | 609120 kb |
| Host | smart-7ccd54ac-d70e-4740-a0bf-af37c096dccc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770554685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.770554685 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.51187004 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 5168770575 ps |
| CPU time | 532.22 seconds |
| Started | Jul 13 07:45:21 PM PDT 24 |
| Finished | Jul 13 07:54:15 PM PDT 24 |
| Peak memory | 609236 kb |
| Host | smart-ec5ea759-0e34-41af-ab8d-fc8f4b5ed778 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51187004 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.51187004 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.96683121 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 2977442856 ps |
| CPU time | 228.43 seconds |
| Started | Jul 13 07:48:16 PM PDT 24 |
| Finished | Jul 13 07:52:05 PM PDT 24 |
| Peak memory | 609116 kb |
| Host | smart-1bf87947-cca4-43ca-a9b9-a1d9a208a15c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96683121 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_sram_ctrl_smoketest.96683121 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2115561382 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 20876363113 ps |
| CPU time | 3662.07 seconds |
| Started | Jul 13 07:48:05 PM PDT 24 |
| Finished | Jul 13 08:49:09 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-4377a93b-15c0-45da-a3d1-ba4fe36e6505 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115561382 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.2115561382 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1118133354 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 5016835520 ps |
| CPU time | 667.81 seconds |
| Started | Jul 13 07:44:19 PM PDT 24 |
| Finished | Jul 13 07:55:29 PM PDT 24 |
| Peak memory | 613108 kb |
| Host | smart-d747f9d6-6def-4bdf-82b4-e177987ac135 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118133354 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.1118133354 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.807374469 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 2795040602 ps |
| CPU time | 301.66 seconds |
| Started | Jul 13 07:46:16 PM PDT 24 |
| Finished | Jul 13 07:51:21 PM PDT 24 |
| Peak memory | 612416 kb |
| Host | smart-4699b807-c705-475f-937c-4bb5915668c2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807374469 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.807374469 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.1059564671 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 3395685752 ps |
| CPU time | 324.58 seconds |
| Started | Jul 13 07:48:31 PM PDT 24 |
| Finished | Jul 13 07:53:57 PM PDT 24 |
| Peak memory | 609436 kb |
| Host | smart-fccd9e11-c12c-437a-9c30-bf94f501b77a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059564671 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.1059564671 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3070442802 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 22766803174 ps |
| CPU time | 1985.06 seconds |
| Started | Jul 13 07:45:33 PM PDT 24 |
| Finished | Jul 13 08:18:41 PM PDT 24 |
| Peak memory | 614020 kb |
| Host | smart-cec3a68c-1b9b-4dc6-873a-b67f67792d25 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30704428 02 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.3070442802 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1483824633 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5850419558 ps |
| CPU time | 522.06 seconds |
| Started | Jul 13 07:46:17 PM PDT 24 |
| Finished | Jul 13 07:55:00 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-889a880b-1d48-45d7-92ad-60cd233a2bfa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483824633 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1483824633 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1036590268 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 12691236400 ps |
| CPU time | 2890.51 seconds |
| Started | Jul 13 07:45:10 PM PDT 24 |
| Finished | Jul 13 08:33:23 PM PDT 24 |
| Peak memory | 618244 kb |
| Host | smart-0b9f9223-4af3-4316-bc97-f8adbc6a1920 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1036590268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.1036590268 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.3149196722 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 3063331272 ps |
| CPU time | 324.8 seconds |
| Started | Jul 13 07:46:04 PM PDT 24 |
| Finished | Jul 13 07:51:31 PM PDT 24 |
| Peak memory | 615728 kb |
| Host | smart-a1d09d36-37b1-4cae-a90c-eed029112356 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149196722 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_uart_smoketest.3149196722 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.3572370580 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 3761327880 ps |
| CPU time | 520.32 seconds |
| Started | Jul 13 07:46:16 PM PDT 24 |
| Finished | Jul 13 07:54:58 PM PDT 24 |
| Peak memory | 621900 kb |
| Host | smart-f1741dfe-4824-4d7d-90dc-089c87b45da0 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572370580 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.3572370580 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.4079182899 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 8603749732 ps |
| CPU time | 1770.63 seconds |
| Started | Jul 13 07:47:17 PM PDT 24 |
| Finished | Jul 13 08:16:50 PM PDT 24 |
| Peak memory | 624160 kb |
| Host | smart-24dc4b0c-7ef7-44ea-bf98-0b1b562a617f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079182899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq.4079182899 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.210957343 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 13425331956 ps |
| CPU time | 2156.63 seconds |
| Started | Jul 13 07:43:45 PM PDT 24 |
| Finished | Jul 13 08:19:44 PM PDT 24 |
| Peak memory | 624140 kb |
| Host | smart-87e82619-a1d5-4510-8b12-d22d375e0052 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210957343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.210957343 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1300759978 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 77713531996 ps |
| CPU time | 14056.2 seconds |
| Started | Jul 13 07:45:34 PM PDT 24 |
| Finished | Jul 13 11:39:53 PM PDT 24 |
| Peak memory | 633504 kb |
| Host | smart-4000a659-1d40-432d-bcac-9cf05ce62f41 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1300759978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.1300759978 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2349570810 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 4048283824 ps |
| CPU time | 557.97 seconds |
| Started | Jul 13 07:43:02 PM PDT 24 |
| Finished | Jul 13 07:52:20 PM PDT 24 |
| Peak memory | 623224 kb |
| Host | smart-84ba3ddc-90a6-4ab4-b1ba-7b0d181658d3 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349570810 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.2349570810 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2157803642 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 4476213222 ps |
| CPU time | 646.47 seconds |
| Started | Jul 13 07:42:58 PM PDT 24 |
| Finished | Jul 13 07:53:46 PM PDT 24 |
| Peak memory | 623476 kb |
| Host | smart-e0576a0b-7354-4f5d-9d60-134c3b159944 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157803642 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.2157803642 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1924197137 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 3312232027 ps |
| CPU time | 443.94 seconds |
| Started | Jul 13 07:44:51 PM PDT 24 |
| Finished | Jul 13 07:52:16 PM PDT 24 |
| Peak memory | 608428 kb |
| Host | smart-25dce6dc-bacb-4e81-8d4e-e204c1732006 |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924197137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.1924197137 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.130325546 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 7965146510 ps |
| CPU time | 2002.64 seconds |
| Started | Jul 13 07:45:23 PM PDT 24 |
| Finished | Jul 13 08:18:47 PM PDT 24 |
| Peak memory | 608668 kb |
| Host | smart-5c0f0fbd-6d1c-4e39-b764-77d8036e2bef |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13032 5546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.130325546 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.2801943208 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 11605563614 ps |
| CPU time | 3468.84 seconds |
| Started | Jul 13 07:43:07 PM PDT 24 |
| Finished | Jul 13 08:40:58 PM PDT 24 |
| Peak memory | 609808 kb |
| Host | smart-04cc1e46-8a0c-4cf4-9dc3-8b41dfad1a75 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2801943208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.2801943208 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.2415393657 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 3218943276 ps |
| CPU time | 355.13 seconds |
| Started | Jul 13 07:42:27 PM PDT 24 |
| Finished | Jul 13 07:48:23 PM PDT 24 |
| Peak memory | 608676 kb |
| Host | smart-ae7d1c02-0528-4d90-9543-a576c5c01fd7 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415393657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.2415393657 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2621133435 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 4138809212 ps |
| CPU time | 686.76 seconds |
| Started | Jul 13 07:43:10 PM PDT 24 |
| Finished | Jul 13 07:54:40 PM PDT 24 |
| Peak memory | 608688 kb |
| Host | smart-56b0ec70-d525-4297-8172-2e436d66c6af |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262113343 5 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.2621133435 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.2765360260 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 18405040176 ps |
| CPU time | 5203.39 seconds |
| Started | Jul 13 07:44:57 PM PDT 24 |
| Finished | Jul 13 09:11:44 PM PDT 24 |
| Peak memory | 608764 kb |
| Host | smart-904ece72-2cc0-4f7b-a7b7-7578ed1edcee |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=2765360260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.2765360260 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.3431073356 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 2920106044 ps |
| CPU time | 268.21 seconds |
| Started | Jul 13 07:42:38 PM PDT 24 |
| Finished | Jul 13 07:47:08 PM PDT 24 |
| Peak memory | 608676 kb |
| Host | smart-b5e2faa8-a21d-4870-a36e-2250c6a18b0c |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431073356 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.3431073356 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.703302788 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 14366934535 ps |
| CPU time | 1489.15 seconds |
| Started | Jul 13 07:43:03 PM PDT 24 |
| Finished | Jul 13 08:07:53 PM PDT 24 |
| Peak memory | 620380 kb |
| Host | smart-01ef76f7-7b71-4809-a1d4-600d0ca78ebb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=703302788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.703302788 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.3653757203 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 10398663032 ps |
| CPU time | 1243.12 seconds |
| Started | Jul 13 07:46:25 PM PDT 24 |
| Finished | Jul 13 08:07:10 PM PDT 24 |
| Peak memory | 623972 kb |
| Host | smart-f8fe1b13-d086-41a1-806d-bcc0e98adb48 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653757203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.3653757203 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.2360945864 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 15978242868 ps |
| CPU time | 4079.27 seconds |
| Started | Jul 13 07:49:29 PM PDT 24 |
| Finished | Jul 13 08:57:30 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-19ba5029-21a2-4af0-b44d-23620aab43f4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360945864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.2360945864 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.2942132278 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 15446506642 ps |
| CPU time | 3846.43 seconds |
| Started | Jul 13 07:51:12 PM PDT 24 |
| Finished | Jul 13 08:55:19 PM PDT 24 |
| Peak memory | 610524 kb |
| Host | smart-bf2a0a2b-d871-45db-8034-8774be1fbeb3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942132278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.2942132278 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.177851495 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 14872163156 ps |
| CPU time | 4094.19 seconds |
| Started | Jul 13 07:52:56 PM PDT 24 |
| Finished | Jul 13 09:01:11 PM PDT 24 |
| Peak memory | 609568 kb |
| Host | smart-201bad2a-ed53-491e-a01e-3866b1853be6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177851495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.rom_e2e_asm_init_prod_end.177851495 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.2310428352 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 14928871149 ps |
| CPU time | 4585.62 seconds |
| Started | Jul 13 07:52:22 PM PDT 24 |
| Finished | Jul 13 09:08:50 PM PDT 24 |
| Peak memory | 609580 kb |
| Host | smart-14603769-24b6-4696-8237-aed8c7194b1b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310428352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.2310428352 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3917311001 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 11229398189 ps |
| CPU time | 2873.08 seconds |
| Started | Jul 13 07:53:35 PM PDT 24 |
| Finished | Jul 13 08:41:29 PM PDT 24 |
| Peak memory | 609964 kb |
| Host | smart-2234840f-6bbc-4936-98ef-abdada21ca78 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917311001 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.3917311001 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.4180384761 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 24866411464 ps |
| CPU time | 6575.99 seconds |
| Started | Jul 13 07:49:06 PM PDT 24 |
| Finished | Jul 13 09:38:45 PM PDT 24 |
| Peak memory | 608884 kb |
| Host | smart-f9bccbb6-8d73-4b9b-8152-8d2cd8b93ced |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4180384761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.4180384761 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3800340839 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 24839647240 ps |
| CPU time | 6376.54 seconds |
| Started | Jul 13 07:58:46 PM PDT 24 |
| Finished | Jul 13 09:45:04 PM PDT 24 |
| Peak memory | 609692 kb |
| Host | smart-923f0651-1373-4149-85be-e8be684080b5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3800340839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3800340839 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2929598568 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 23554465692 ps |
| CPU time | 5875.35 seconds |
| Started | Jul 13 07:53:33 PM PDT 24 |
| Finished | Jul 13 09:31:29 PM PDT 24 |
| Peak memory | 608888 kb |
| Host | smart-061dca7c-564b-4fe4-b880-6bea63fd03f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2929598568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2929598568 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3583971562 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 18146541640 ps |
| CPU time | 5938.65 seconds |
| Started | Jul 13 08:00:14 PM PDT 24 |
| Finished | Jul 13 09:39:13 PM PDT 24 |
| Peak memory | 608860 kb |
| Host | smart-ebf8ab59-1efc-480f-8a7e-66cf9ad83229 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583971562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3583971562 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3981516230 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 14974826094 ps |
| CPU time | 4084.81 seconds |
| Started | Jul 13 07:49:51 PM PDT 24 |
| Finished | Jul 13 08:57:58 PM PDT 24 |
| Peak memory | 608884 kb |
| Host | smart-4f00754a-2975-4dc0-9bdb-5bb7760ef08a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3981516230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3981516230 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.311917946 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 15025053584 ps |
| CPU time | 4625.79 seconds |
| Started | Jul 13 07:49:38 PM PDT 24 |
| Finished | Jul 13 09:06:45 PM PDT 24 |
| Peak memory | 608888 kb |
| Host | smart-8bf039b0-efdd-443c-adfb-ea1fef9dca1f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=311917946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.311917946 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.4057600907 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 15013984960 ps |
| CPU time | 4736.63 seconds |
| Started | Jul 13 07:59:57 PM PDT 24 |
| Finished | Jul 13 09:18:54 PM PDT 24 |
| Peak memory | 608856 kb |
| Host | smart-b53b2b59-8983-413e-b7e2-dad3061d8836 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4057600907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.4057600907 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2428526743 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 15054200936 ps |
| CPU time | 3974.35 seconds |
| Started | Jul 13 07:50:30 PM PDT 24 |
| Finished | Jul 13 08:56:47 PM PDT 24 |
| Peak memory | 608832 kb |
| Host | smart-693a4f80-452a-4981-bc13-3c4e34483adf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2428526743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2428526743 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1001200924 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 10836505944 ps |
| CPU time | 3192.48 seconds |
| Started | Jul 13 07:52:46 PM PDT 24 |
| Finished | Jul 13 08:45:59 PM PDT 24 |
| Peak memory | 608868 kb |
| Host | smart-e6a0ff28-0e14-4972-a58a-279c42750ccf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001200924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1001200924 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3577729389 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 15631032798 ps |
| CPU time | 4992.37 seconds |
| Started | Jul 13 07:55:48 PM PDT 24 |
| Finished | Jul 13 09:19:02 PM PDT 24 |
| Peak memory | 608860 kb |
| Host | smart-d494f8bf-ac2e-4ff5-a1dd-6edc70bbc737 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577729389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3577729389 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1216618793 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 15313738660 ps |
| CPU time | 4789.26 seconds |
| Started | Jul 13 08:00:07 PM PDT 24 |
| Finished | Jul 13 09:19:58 PM PDT 24 |
| Peak memory | 608804 kb |
| Host | smart-0dab7749-25c9-42aa-b457-8157a5b58bd5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216618793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1216618793 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3923762681 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 15239770880 ps |
| CPU time | 4565.49 seconds |
| Started | Jul 13 07:50:57 PM PDT 24 |
| Finished | Jul 13 09:07:09 PM PDT 24 |
| Peak memory | 608824 kb |
| Host | smart-5d739586-0daa-49ff-aee9-37bbe1240cf7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392376 2681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3923762681 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3204243977 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 14335439620 ps |
| CPU time | 4017.73 seconds |
| Started | Jul 13 07:51:51 PM PDT 24 |
| Finished | Jul 13 08:58:50 PM PDT 24 |
| Peak memory | 608832 kb |
| Host | smart-dd4f62ae-c70e-459c-bd15-47be4b42e09c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204243977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3204243977 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2358321142 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 11127385126 ps |
| CPU time | 3830.03 seconds |
| Started | Jul 13 07:55:43 PM PDT 24 |
| Finished | Jul 13 08:59:34 PM PDT 24 |
| Peak memory | 608824 kb |
| Host | smart-515b1280-1811-4286-a7c7-6ce78cadf254 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2358321142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2358321142 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.2513352750 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 11521822823 ps |
| CPU time | 2544.45 seconds |
| Started | Jul 13 07:48:05 PM PDT 24 |
| Finished | Jul 13 08:30:31 PM PDT 24 |
| Peak memory | 623588 kb |
| Host | smart-2404a79b-58b7-46b7-aba6-739a9d26d4f3 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25133 52750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.2513352750 |
| Directory | /workspace/0.rom_e2e_jtag_debug_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2939937229 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 10120948090 ps |
| CPU time | 2183.69 seconds |
| Started | Jul 13 07:46:02 PM PDT 24 |
| Finished | Jul 13 08:22:28 PM PDT 24 |
| Peak memory | 623064 kb |
| Host | smart-1e7f8db1-cd7a-4c7a-8b95-d74d5a4e2c08 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2939937229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.2939937229 |
| Directory | /workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3442334368 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 32055784271 ps |
| CPU time | 2991.48 seconds |
| Started | Jul 13 07:47:17 PM PDT 24 |
| Finished | Jul 13 08:37:09 PM PDT 24 |
| Peak memory | 622768 kb |
| Host | smart-1e1a9cc9-c9ec-4f37-8c39-6c37ef96957c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3442334368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.3442334368 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.2863676538 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 24266022633 ps |
| CPU time | 3046.05 seconds |
| Started | Jul 13 07:45:54 PM PDT 24 |
| Finished | Jul 13 08:36:42 PM PDT 24 |
| Peak memory | 619556 kb |
| Host | smart-5dde0b91-9a3c-4e00-aede-a503467d629c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2863676538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.2863676538 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.3888613735 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 32317339545 ps |
| CPU time | 2623.79 seconds |
| Started | Jul 13 07:51:59 PM PDT 24 |
| Finished | Jul 13 08:35:44 PM PDT 24 |
| Peak memory | 620380 kb |
| Host | smart-e71ab0b1-0399-4c19-8521-af0ea1a498e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888613735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_ inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject _test_unlocked0.3888613735 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3473872408 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 15715239816 ps |
| CPU time | 4411.33 seconds |
| Started | Jul 13 07:53:14 PM PDT 24 |
| Finished | Jul 13 09:06:46 PM PDT 24 |
| Peak memory | 609676 kb |
| Host | smart-5e3d80bb-e3f7-4ce3-b0eb-98b20cc6b1ce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473872408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3473872408 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2898856566 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 15123690684 ps |
| CPU time | 4020.58 seconds |
| Started | Jul 13 07:50:28 PM PDT 24 |
| Finished | Jul 13 08:57:30 PM PDT 24 |
| Peak memory | 609820 kb |
| Host | smart-df247301-8fee-402e-9925-48848dd991ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898856566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.2898856566 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.3236549142 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 15131501730 ps |
| CPU time | 3296.23 seconds |
| Started | Jul 13 07:52:53 PM PDT 24 |
| Finished | Jul 13 08:47:50 PM PDT 24 |
| Peak memory | 609736 kb |
| Host | smart-b7874fc4-b30c-4874-b71a-d782f0755bb4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236549142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.3236549142 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.201376138 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 14979934866 ps |
| CPU time | 3853.07 seconds |
| Started | Jul 13 07:49:11 PM PDT 24 |
| Finished | Jul 13 08:53:26 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-28f11759-3de7-4b22-b15a-e8acf0bd8f4f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201376138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shut down_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_s hutdown_exception_c.201376138 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.3107746186 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 26522859577 ps |
| CPU time | 3370.59 seconds |
| Started | Jul 13 07:48:36 PM PDT 24 |
| Finished | Jul 13 08:44:47 PM PDT 24 |
| Peak memory | 611268 kb |
| Host | smart-9eb3e055-65f5-4f4f-a044-c2a01c15ff99 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107746186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.3107746186 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.760701131 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 24115584241 ps |
| CPU time | 6762.87 seconds |
| Started | Jul 13 07:59:59 PM PDT 24 |
| Finished | Jul 13 09:52:43 PM PDT 24 |
| Peak memory | 608916 kb |
| Host | smart-9645c8f9-1e3c-459c-90f6-1236027d669a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=760701131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.760701131 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2859165637 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 23464499044 ps |
| CPU time | 6175.23 seconds |
| Started | Jul 13 07:51:22 PM PDT 24 |
| Finished | Jul 13 09:34:20 PM PDT 24 |
| Peak memory | 608936 kb |
| Host | smart-a9a99295-ee3f-469b-9e30-b0ab1a3507a0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2859165637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_ b_bad_prod.2859165637 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3737651267 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 23611325525 ps |
| CPU time | 6049.07 seconds |
| Started | Jul 13 07:50:44 PM PDT 24 |
| Finished | Jul 13 09:31:35 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-c44324d1-7167-408f-a2cc-220174d29227 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3737651267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_ bad_b_bad_prod_end.3737651267 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3375920645 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 22516091530 ps |
| CPU time | 7047.8 seconds |
| Started | Jul 13 07:52:59 PM PDT 24 |
| Finished | Jul 13 09:50:28 PM PDT 24 |
| Peak memory | 608948 kb |
| Host | smart-179e32ae-84eb-4b33-a26c-2d8b4a912600 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3375920645 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b _bad_rma.3375920645 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3862808821 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 18675895100 ps |
| CPU time | 5376.71 seconds |
| Started | Jul 13 07:50:03 PM PDT 24 |
| Finished | Jul 13 09:19:41 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-f2d0060c-843b-4b7a-951e-01c1637030ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3862808821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b _bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw ays_a_bad_b_bad_test_unlocked0.3862808821 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3074612028 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 14401085904 ps |
| CPU time | 4276.8 seconds |
| Started | Jul 13 07:50:41 PM PDT 24 |
| Finished | Jul 13 09:02:00 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-11376258-5a8f-4af0-93a9-8edcc83d726c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074612028 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3074612028 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3991836143 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 14541674484 ps |
| CPU time | 4149.99 seconds |
| Started | Jul 13 07:55:25 PM PDT 24 |
| Finished | Jul 13 09:04:36 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-456928da-a149-455b-940a-e12f4fe8d9ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991836143 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3991836143 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3321533072 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 15196973899 ps |
| CPU time | 3873.61 seconds |
| Started | Jul 13 07:54:04 PM PDT 24 |
| Finished | Jul 13 08:58:39 PM PDT 24 |
| Peak memory | 609916 kb |
| Host | smart-8f7fdb1d-acee-497c-93ba-34e36f8f8b3a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321533072 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3321533072 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.479878036 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 13961348920 ps |
| CPU time | 4114.17 seconds |
| Started | Jul 13 07:53:54 PM PDT 24 |
| Finished | Jul 13 09:02:30 PM PDT 24 |
| Peak memory | 608956 kb |
| Host | smart-63898de1-91e2-4403-8c8f-158e0a839c50 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479878036 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.479878036 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3937503317 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 10747697848 ps |
| CPU time | 3071.48 seconds |
| Started | Jul 13 07:51:11 PM PDT 24 |
| Finished | Jul 13 08:42:23 PM PDT 24 |
| Peak memory | 609000 kb |
| Host | smart-5936a06b-24d7-4105-82cd-c272cdd7706b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937503317 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3937503317 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2095075591 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 14364204890 ps |
| CPU time | 4283.04 seconds |
| Started | Jul 13 07:53:34 PM PDT 24 |
| Finished | Jul 13 09:04:58 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-6b1a2e6f-72ee-46e7-a21a-33698a6b4dc6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095075591 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2095075591 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2042633920 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 14462457310 ps |
| CPU time | 3994.28 seconds |
| Started | Jul 13 07:50:17 PM PDT 24 |
| Finished | Jul 13 08:56:53 PM PDT 24 |
| Peak memory | 608928 kb |
| Host | smart-b9f10b22-2361-49b3-a4bd-f699e228876e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042633920 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2042633920 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3615133281 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 14889820895 ps |
| CPU time | 4276.38 seconds |
| Started | Jul 13 07:49:17 PM PDT 24 |
| Finished | Jul 13 09:00:35 PM PDT 24 |
| Peak memory | 608948 kb |
| Host | smart-28a17d1f-6406-430e-b1a3-497b03c3da31 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615133281 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3615133281 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1433294170 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 14219104812 ps |
| CPU time | 3634.27 seconds |
| Started | Jul 13 07:51:07 PM PDT 24 |
| Finished | Jul 13 08:51:44 PM PDT 24 |
| Peak memory | 608932 kb |
| Host | smart-d23eb29e-254f-4a27-a7e0-a6195a488e99 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433294170 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1433294170 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2837538706 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 11229787287 ps |
| CPU time | 3216.11 seconds |
| Started | Jul 13 07:49:08 PM PDT 24 |
| Finished | Jul 13 08:42:45 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-d36cb5ce-efee-4eea-a27c-5e871ad820fa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837538706 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2837538706 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.2588053913 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 14740974198 ps |
| CPU time | 4783.53 seconds |
| Started | Jul 13 07:54:48 PM PDT 24 |
| Finished | Jul 13 09:14:34 PM PDT 24 |
| Peak memory | 609604 kb |
| Host | smart-b4709c5f-b731-4cfa-b8c5-d43a1e481ae7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=2588053913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.2588053913 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.2585489851 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 17632414136 ps |
| CPU time | 4349.28 seconds |
| Started | Jul 13 07:49:49 PM PDT 24 |
| Finished | Jul 13 09:02:22 PM PDT 24 |
| Peak memory | 609816 kb |
| Host | smart-0511d685-5bb2-4c54-97d0-7ad3ebf27556 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585489851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.2585489851 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_raw_unlock.109553559 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 6533772746 ps |
| CPU time | 276.42 seconds |
| Started | Jul 13 07:46:40 PM PDT 24 |
| Finished | Jul 13 07:51:17 PM PDT 24 |
| Peak memory | 623176 kb |
| Host | smart-23fde3be-c00d-48b0-a914-77a22260c80d |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=109553559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.109553559 |
| Directory | /workspace/0.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.4022240744 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 2781164396 ps |
| CPU time | 124.31 seconds |
| Started | Jul 13 07:45:18 PM PDT 24 |
| Finished | Jul 13 07:47:23 PM PDT 24 |
| Peak memory | 617248 kb |
| Host | smart-42c114fa-807c-416c-a058-7ae7456a3279 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022240744 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.4022240744 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.3051630492 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 13733609364 ps |
| CPU time | 1672.16 seconds |
| Started | Jul 13 07:45:33 PM PDT 24 |
| Finished | Jul 13 08:13:27 PM PDT 24 |
| Peak memory | 607228 kb |
| Host | smart-ad7d5e61-7c7b-41bf-a015-8ceafb452df8 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051630492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.3 051630492 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.960119414 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 4469923460 ps |
| CPU time | 506.51 seconds |
| Started | Jul 13 07:54:47 PM PDT 24 |
| Finished | Jul 13 08:03:14 PM PDT 24 |
| Peak memory | 618168 kb |
| Host | smart-19e756e4-86a2-48df-b30f-42f0ad586712 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9 60119414 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.960119414 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.1804126120 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 2630827860 ps |
| CPU time | 253.64 seconds |
| Started | Jul 13 07:45:35 PM PDT 24 |
| Finished | Jul 13 07:49:49 PM PDT 24 |
| Peak memory | 608708 kb |
| Host | smart-4c194f13-3046-437e-810a-11be12cdbece |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1804126120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.1804126120 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2484117692 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 18390047864 ps |
| CPU time | 443.05 seconds |
| Started | Jul 13 07:49:00 PM PDT 24 |
| Finished | Jul 13 07:56:24 PM PDT 24 |
| Peak memory | 618268 kb |
| Host | smart-8a19d062-4e53-487e-aa51-800069c19962 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2484117692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2484117692 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.706108978 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 3465142072 ps |
| CPU time | 286.44 seconds |
| Started | Jul 13 07:49:06 PM PDT 24 |
| Finished | Jul 13 07:53:55 PM PDT 24 |
| Peak memory | 609264 kb |
| Host | smart-4f9bb6ca-1f59-4237-91f7-737854b4b39d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706108978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.706108978 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1518425994 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 3133209361 ps |
| CPU time | 372.72 seconds |
| Started | Jul 13 07:47:59 PM PDT 24 |
| Finished | Jul 13 07:54:13 PM PDT 24 |
| Peak memory | 609216 kb |
| Host | smart-41c08479-ec0b-4f5f-9c6a-0578e7bc14a0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518 425994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.1518425994 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.1669369237 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 2422087042 ps |
| CPU time | 233.77 seconds |
| Started | Jul 13 07:56:12 PM PDT 24 |
| Finished | Jul 13 08:00:06 PM PDT 24 |
| Peak memory | 608680 kb |
| Host | smart-bbf12667-989b-4a5a-99fd-cce718f18b4e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669369237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.1669369237 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.3536735142 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 2838860478 ps |
| CPU time | 235 seconds |
| Started | Jul 13 07:49:37 PM PDT 24 |
| Finished | Jul 13 07:53:33 PM PDT 24 |
| Peak memory | 608676 kb |
| Host | smart-357c0bbe-10ba-4e05-8b23-b0958f006cc4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536735142 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.3536735142 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.3720885182 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 3308384188 ps |
| CPU time | 260.44 seconds |
| Started | Jul 13 07:49:05 PM PDT 24 |
| Finished | Jul 13 07:53:27 PM PDT 24 |
| Peak memory | 608688 kb |
| Host | smart-a71922ec-f073-42e5-bac9-15c580588814 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720885182 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.3720885182 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.152377506 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 2376342712 ps |
| CPU time | 283.23 seconds |
| Started | Jul 13 07:55:01 PM PDT 24 |
| Finished | Jul 13 07:59:46 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-f8310698-ca26-4d24-8bb4-8069137829f1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152377506 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.152377506 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.2048429924 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 3016531880 ps |
| CPU time | 283.96 seconds |
| Started | Jul 13 07:57:12 PM PDT 24 |
| Finished | Jul 13 08:01:58 PM PDT 24 |
| Peak memory | 609060 kb |
| Host | smart-3e5e0334-344f-41e9-a521-96a28f251787 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048429924 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.2048429924 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.1515559621 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 3390833508 ps |
| CPU time | 350.09 seconds |
| Started | Jul 13 07:48:40 PM PDT 24 |
| Finished | Jul 13 07:54:31 PM PDT 24 |
| Peak memory | 609132 kb |
| Host | smart-fe8622d6-0b18-41b3-87e5-19cb6607659c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1515559621 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.1515559621 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.205262097 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 4362658800 ps |
| CPU time | 389.2 seconds |
| Started | Jul 13 07:49:04 PM PDT 24 |
| Finished | Jul 13 07:55:35 PM PDT 24 |
| Peak memory | 618560 kb |
| Host | smart-c985f8f6-b04e-467d-8876-31922ec25b9b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=205262097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.205262097 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3676489466 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 6660831276 ps |
| CPU time | 1619.87 seconds |
| Started | Jul 13 07:53:53 PM PDT 24 |
| Finished | Jul 13 08:20:55 PM PDT 24 |
| Peak memory | 609620 kb |
| Host | smart-05f49fac-9234-4cba-9d1e-31b060f2f4d5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3676489466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.3676489466 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2000682980 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 7758026228 ps |
| CPU time | 2126.39 seconds |
| Started | Jul 13 07:51:42 PM PDT 24 |
| Finished | Jul 13 08:27:10 PM PDT 24 |
| Peak memory | 609848 kb |
| Host | smart-27d55b73-083d-44b8-8b7d-761837c4168b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000682980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.2000682980 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1476315742 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 8173603480 ps |
| CPU time | 1401.12 seconds |
| Started | Jul 13 07:49:53 PM PDT 24 |
| Finished | Jul 13 08:13:15 PM PDT 24 |
| Peak memory | 609664 kb |
| Host | smart-0d54e66e-a622-4dcd-920a-48112c1b5e59 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1476315742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.1476315742 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.668933118 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3778419716 ps |
| CPU time | 353.25 seconds |
| Started | Jul 13 07:47:38 PM PDT 24 |
| Finished | Jul 13 07:53:32 PM PDT 24 |
| Peak memory | 609460 kb |
| Host | smart-3b42fdf4-94e4-4ac6-9fcf-165dc814dab9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=668933118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.668933118 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.184964396 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 255101002800 ps |
| CPU time | 11684.1 seconds |
| Started | Jul 13 07:51:35 PM PDT 24 |
| Finished | Jul 13 11:06:20 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-e1a6bcf7-f5cc-46d0-b3e9-ca31a3b8b74b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=184964396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.184964396 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.3344386949 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 3235137344 ps |
| CPU time | 302.54 seconds |
| Started | Jul 13 07:51:06 PM PDT 24 |
| Finished | Jul 13 07:56:10 PM PDT 24 |
| Peak memory | 609252 kb |
| Host | smart-a3d559c6-09a1-4b24-a17f-20545d09f4c2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344386949 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.3344386949 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.3642823880 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 4193844068 ps |
| CPU time | 424.69 seconds |
| Started | Jul 13 07:49:41 PM PDT 24 |
| Finished | Jul 13 07:56:46 PM PDT 24 |
| Peak memory | 609404 kb |
| Host | smart-10d60ada-24dc-44f3-99c5-6405984d6d1c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642823880 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.3642823880 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3582413881 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 7408992732 ps |
| CPU time | 568.55 seconds |
| Started | Jul 13 07:49:44 PM PDT 24 |
| Finished | Jul 13 07:59:15 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-1863cc3a-a088-4f0b-9b7e-03f5ed9e905f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3582413881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3582413881 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3723058825 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 2917290056 ps |
| CPU time | 232.94 seconds |
| Started | Jul 13 07:57:51 PM PDT 24 |
| Finished | Jul 13 08:01:44 PM PDT 24 |
| Peak memory | 609040 kb |
| Host | smart-1de56bbc-26b1-4220-ae87-9208d3c90f52 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723058825 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.3723058825 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1917131256 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 10401034892 ps |
| CPU time | 949 seconds |
| Started | Jul 13 07:50:46 PM PDT 24 |
| Finished | Jul 13 08:06:36 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-aadf2b94-1b14-4929-80da-e08b8f2f0d11 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1917131256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.1917131256 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2291824745 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 5219156460 ps |
| CPU time | 485.36 seconds |
| Started | Jul 13 07:48:40 PM PDT 24 |
| Finished | Jul 13 07:56:47 PM PDT 24 |
| Peak memory | 609052 kb |
| Host | smart-fc6eb633-21f9-4234-90f8-321d1182fb95 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2291824745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.2291824745 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.406351618 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 6966725456 ps |
| CPU time | 968.81 seconds |
| Started | Jul 13 07:52:45 PM PDT 24 |
| Finished | Jul 13 08:08:54 PM PDT 24 |
| Peak memory | 616280 kb |
| Host | smart-44ad33d2-652e-4357-b30b-1b6b76351982 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406351618 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.406351618 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1080260622 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 8925433501 ps |
| CPU time | 786.13 seconds |
| Started | Jul 13 07:52:40 PM PDT 24 |
| Finished | Jul 13 08:05:47 PM PDT 24 |
| Peak memory | 620696 kb |
| Host | smart-2b2b7b4b-da09-4ebf-84e7-01016c37ab21 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1080260622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.1080260622 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.672869646 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 4245563192 ps |
| CPU time | 640.43 seconds |
| Started | Jul 13 07:52:36 PM PDT 24 |
| Finished | Jul 13 08:03:18 PM PDT 24 |
| Peak memory | 611124 kb |
| Host | smart-d6cd559f-1af9-4216-b107-75dab55beba6 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672869646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.672869646 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3000858459 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 4566039226 ps |
| CPU time | 725.21 seconds |
| Started | Jul 13 07:52:31 PM PDT 24 |
| Finished | Jul 13 08:04:37 PM PDT 24 |
| Peak memory | 612348 kb |
| Host | smart-b25cdd5f-b85f-41b6-b779-4518e2909a3a |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000858459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3000858459 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2968073772 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 4277268708 ps |
| CPU time | 653.91 seconds |
| Started | Jul 13 07:52:36 PM PDT 24 |
| Finished | Jul 13 08:03:31 PM PDT 24 |
| Peak memory | 612388 kb |
| Host | smart-541d0445-d311-4446-857e-44d7cf546bf3 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968073772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2968073772 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2818245843 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 4916942314 ps |
| CPU time | 767.52 seconds |
| Started | Jul 13 07:53:44 PM PDT 24 |
| Finished | Jul 13 08:06:32 PM PDT 24 |
| Peak memory | 611116 kb |
| Host | smart-55a1df4f-baa0-4304-9eb6-d1b6c3df2025 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818245843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2818245843 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2161871461 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 5054641224 ps |
| CPU time | 683 seconds |
| Started | Jul 13 07:52:34 PM PDT 24 |
| Finished | Jul 13 08:03:58 PM PDT 24 |
| Peak memory | 612572 kb |
| Host | smart-2e46f6d6-5262-4675-a51b-8fb0677bde37 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161871461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2161871461 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3957064274 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 4885404082 ps |
| CPU time | 811.17 seconds |
| Started | Jul 13 07:52:17 PM PDT 24 |
| Finished | Jul 13 08:05:49 PM PDT 24 |
| Peak memory | 612408 kb |
| Host | smart-c477c29c-d206-43f9-9eeb-77916c1f9ec1 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957064274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3957064274 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3739748736 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 2191705340 ps |
| CPU time | 212.02 seconds |
| Started | Jul 13 07:52:54 PM PDT 24 |
| Finished | Jul 13 07:56:27 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-c5a35162-ab51-4312-9968-f99043086950 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739748736 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.3739748736 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2381830500 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 3266481080 ps |
| CPU time | 390.3 seconds |
| Started | Jul 13 07:53:12 PM PDT 24 |
| Finished | Jul 13 07:59:44 PM PDT 24 |
| Peak memory | 609072 kb |
| Host | smart-b0e9867b-f39c-4be5-8c7d-dd8a8e1bd3b8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381830500 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.2381830500 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.4009231338 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 2328786966 ps |
| CPU time | 194.55 seconds |
| Started | Jul 13 07:54:37 PM PDT 24 |
| Finished | Jul 13 07:57:53 PM PDT 24 |
| Peak memory | 608692 kb |
| Host | smart-a8574b26-2e20-47c6-ad1b-8afc05a6f744 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009231338 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.4009231338 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.997237504 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 4549819822 ps |
| CPU time | 529.76 seconds |
| Started | Jul 13 07:53:12 PM PDT 24 |
| Finished | Jul 13 08:02:03 PM PDT 24 |
| Peak memory | 608452 kb |
| Host | smart-fbfc3a8a-7e11-4258-9ef3-51b3d97ff1fa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997237504 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.997237504 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2217839117 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 5464759286 ps |
| CPU time | 625.86 seconds |
| Started | Jul 13 07:52:32 PM PDT 24 |
| Finished | Jul 13 08:02:59 PM PDT 24 |
| Peak memory | 609508 kb |
| Host | smart-8fba3c86-7d0c-4150-8e47-26884ab96512 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217839117 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.2217839117 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.815549887 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 4997503972 ps |
| CPU time | 553.54 seconds |
| Started | Jul 13 07:53:30 PM PDT 24 |
| Finished | Jul 13 08:02:44 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-65614955-124c-4774-9062-47bf0de8d6f0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815549887 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.815549887 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2342146730 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 4857683464 ps |
| CPU time | 532.15 seconds |
| Started | Jul 13 07:53:55 PM PDT 24 |
| Finished | Jul 13 08:02:48 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-0124f477-2c33-4ef3-a924-37c0693367b2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342146730 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.2342146730 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.14386574 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 11899254832 ps |
| CPU time | 1046.44 seconds |
| Started | Jul 13 07:51:08 PM PDT 24 |
| Finished | Jul 13 08:08:36 PM PDT 24 |
| Peak memory | 609924 kb |
| Host | smart-71d1398f-ccba-482d-84b7-b72264d4675f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14386574 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.14386574 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.4234290414 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 3908636804 ps |
| CPU time | 541.43 seconds |
| Started | Jul 13 08:00:13 PM PDT 24 |
| Finished | Jul 13 08:09:15 PM PDT 24 |
| Peak memory | 609204 kb |
| Host | smart-3fb69606-279d-4edb-b014-02a82daad993 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234290414 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.4234290414 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2520293725 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 4253860872 ps |
| CPU time | 715 seconds |
| Started | Jul 13 07:53:21 PM PDT 24 |
| Finished | Jul 13 08:05:17 PM PDT 24 |
| Peak memory | 609072 kb |
| Host | smart-e117afa2-e5ac-4d46-9afa-1c2cc9a2999a |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520293725 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.2520293725 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3492609864 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 2694030996 ps |
| CPU time | 307.59 seconds |
| Started | Jul 13 07:58:33 PM PDT 24 |
| Finished | Jul 13 08:03:42 PM PDT 24 |
| Peak memory | 609084 kb |
| Host | smart-6cfb2862-5dd3-4e1b-af5f-e2505e47c76a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492609864 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.3492609864 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3861764043 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 15194560168 ps |
| CPU time | 3996.87 seconds |
| Started | Jul 13 07:51:03 PM PDT 24 |
| Finished | Jul 13 08:57:44 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-bd250281-c811-47aa-94c5-c2088656dde0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861764043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.3861764043 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3786256118 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 21778289775 ps |
| CPU time | 4388.04 seconds |
| Started | Jul 13 07:56:19 PM PDT 24 |
| Finished | Jul 13 09:09:28 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-5882c5cf-d06a-4935-a3a6-edccc1e738f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3786256118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.3786256118 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.529866447 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 5211708744 ps |
| CPU time | 431.45 seconds |
| Started | Jul 13 07:49:58 PM PDT 24 |
| Finished | Jul 13 07:57:10 PM PDT 24 |
| Peak memory | 608800 kb |
| Host | smart-9244d7b8-ebed-474f-8aaf-ad10212d2755 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52986 6447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.529866447 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.2624646869 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 3044623300 ps |
| CPU time | 326.14 seconds |
| Started | Jul 13 07:49:20 PM PDT 24 |
| Finished | Jul 13 07:54:47 PM PDT 24 |
| Peak memory | 608624 kb |
| Host | smart-9faf251d-9bed-4679-b4aa-169493199129 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624646869 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.2624646869 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3919774099 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 5393054288 ps |
| CPU time | 530.02 seconds |
| Started | Jul 13 07:47:21 PM PDT 24 |
| Finished | Jul 13 07:56:11 PM PDT 24 |
| Peak memory | 610800 kb |
| Host | smart-7192ccb0-e818-4921-b0e1-eea336101102 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919774099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.3919774099 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.2174354551 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 2385135936 ps |
| CPU time | 196.19 seconds |
| Started | Jul 13 07:57:55 PM PDT 24 |
| Finished | Jul 13 08:01:14 PM PDT 24 |
| Peak memory | 609128 kb |
| Host | smart-95cd2410-6202-496c-ac5d-579293fc70aa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174354551 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.2174354551 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.1773966222 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 4957061720 ps |
| CPU time | 867.26 seconds |
| Started | Jul 13 07:44:43 PM PDT 24 |
| Finished | Jul 13 07:59:14 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-9eb0b75e-b4fb-4e15-bb59-f53223794d40 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1773966222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.1773966222 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.3343031502 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 6198037768 ps |
| CPU time | 1541.88 seconds |
| Started | Jul 13 07:49:30 PM PDT 24 |
| Finished | Jul 13 08:15:13 PM PDT 24 |
| Peak memory | 610004 kb |
| Host | smart-683956b5-ee8e-4835-8b6e-c61ae16756fa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343031502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.3343031502 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.1180383681 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 3467888388 ps |
| CPU time | 614.36 seconds |
| Started | Jul 13 07:55:23 PM PDT 24 |
| Finished | Jul 13 08:05:38 PM PDT 24 |
| Peak memory | 609788 kb |
| Host | smart-685a8128-9fc0-4ec6-a1fa-51079d69cca8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180383681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ boot_mode.1180383681 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3623212781 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 6878105205 ps |
| CPU time | 1462.2 seconds |
| Started | Jul 13 07:54:29 PM PDT 24 |
| Finished | Jul 13 08:18:52 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-672b8495-25fe-4000-ae24-943a2ae0ea8a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623212781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.3623212781 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.1017246774 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 3700003440 ps |
| CPU time | 583.71 seconds |
| Started | Jul 13 07:49:23 PM PDT 24 |
| Finished | Jul 13 07:59:07 PM PDT 24 |
| Peak memory | 616012 kb |
| Host | smart-a31478ce-1100-4e34-a454-15ad7a60014d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017246774 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.1017246774 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.2432776017 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 6859462724 ps |
| CPU time | 1739.06 seconds |
| Started | Jul 13 07:49:36 PM PDT 24 |
| Finished | Jul 13 08:18:36 PM PDT 24 |
| Peak memory | 608676 kb |
| Host | smart-b0d3931e-0582-46b5-8824-479f60199512 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432776017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.2432776017 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.61739930 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 2852029304 ps |
| CPU time | 259.89 seconds |
| Started | Jul 13 07:49:03 PM PDT 24 |
| Finished | Jul 13 07:53:25 PM PDT 24 |
| Peak memory | 608684 kb |
| Host | smart-c7649fb6-9a2c-490e-a17e-43bdf5ba9520 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61 739930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.61739930 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.1399711410 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 7120516940 ps |
| CPU time | 1803.7 seconds |
| Started | Jul 13 07:50:16 PM PDT 24 |
| Finished | Jul 13 08:20:22 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-d3ef255a-d4e8-4dbd-91a6-6ad7fa5ace00 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1399711410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.1399711410 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2031576795 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 2584641400 ps |
| CPU time | 233.71 seconds |
| Started | Jul 13 07:48:01 PM PDT 24 |
| Finished | Jul 13 07:51:56 PM PDT 24 |
| Peak memory | 608124 kb |
| Host | smart-9d2da844-e32e-413b-aa4b-c7b1d4493fe0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031576795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.2031576795 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1458518236 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 3268236028 ps |
| CPU time | 528 seconds |
| Started | Jul 13 07:57:23 PM PDT 24 |
| Finished | Jul 13 08:06:12 PM PDT 24 |
| Peak memory | 608916 kb |
| Host | smart-0cabc696-45b9-4533-ba21-d4f38e46cc89 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1458518236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.1458518236 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.2324529789 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 2662442968 ps |
| CPU time | 274.78 seconds |
| Started | Jul 13 07:46:30 PM PDT 24 |
| Finished | Jul 13 07:51:06 PM PDT 24 |
| Peak memory | 609124 kb |
| Host | smart-b2fd4d3e-5d54-4269-b1c7-5519f00f537d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324529789 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.2324529789 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.1719503109 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 3376267932 ps |
| CPU time | 298.37 seconds |
| Started | Jul 13 07:47:57 PM PDT 24 |
| Finished | Jul 13 07:52:57 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-5565245d-015f-433f-bd8b-811881852a82 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719503109 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.1719503109 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.1696072745 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 2528668814 ps |
| CPU time | 319.55 seconds |
| Started | Jul 13 07:52:55 PM PDT 24 |
| Finished | Jul 13 07:58:16 PM PDT 24 |
| Peak memory | 608804 kb |
| Host | smart-5f270a3f-dffd-4527-a6a8-c33f5bcf64fe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696072745 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.1696072745 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.1258146833 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 2205717684 ps |
| CPU time | 100.52 seconds |
| Started | Jul 13 07:44:33 PM PDT 24 |
| Finished | Jul 13 07:46:18 PM PDT 24 |
| Peak memory | 608832 kb |
| Host | smart-c0471be4-b9ea-471d-a35f-87a7b45edf23 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258146833 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.1258146833 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.336556798 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 58940753806 ps |
| CPU time | 11156.4 seconds |
| Started | Jul 13 07:46:56 PM PDT 24 |
| Finished | Jul 13 10:52:54 PM PDT 24 |
| Peak memory | 624220 kb |
| Host | smart-75052108-5414-46c8-aa02-c554cc3c2946 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=336556798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.336556798 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.230301665 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 4736694908 ps |
| CPU time | 622.2 seconds |
| Started | Jul 13 07:54:00 PM PDT 24 |
| Finished | Jul 13 08:04:23 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-716d5cfc-bebb-4e55-b4ee-4d1d214201ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=230301665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.230301665 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.2800113442 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 5962195720 ps |
| CPU time | 1142.2 seconds |
| Started | Jul 13 07:50:07 PM PDT 24 |
| Finished | Jul 13 08:09:11 PM PDT 24 |
| Peak memory | 609444 kb |
| Host | smart-37778f3d-9562-433c-8245-70a6a1cb187f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800113442 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.2800113442 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.3635819527 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 6256186200 ps |
| CPU time | 1321.65 seconds |
| Started | Jul 13 07:50:42 PM PDT 24 |
| Finished | Jul 13 08:12:45 PM PDT 24 |
| Peak memory | 608656 kb |
| Host | smart-ff662d08-0add-40c0-9df3-aec6b1f9fde1 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635819527 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.3635819527 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2270181327 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 7210139811 ps |
| CPU time | 939.18 seconds |
| Started | Jul 13 07:57:37 PM PDT 24 |
| Finished | Jul 13 08:13:18 PM PDT 24 |
| Peak memory | 608708 kb |
| Host | smart-507bad2b-68cd-4717-a457-ceb452a268c6 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270181327 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2270181327 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2894363922 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 6496885046 ps |
| CPU time | 1223.14 seconds |
| Started | Jul 13 07:46:25 PM PDT 24 |
| Finished | Jul 13 08:06:49 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-42e45e6a-1bd2-46be-a567-893d67fa34f7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894363922 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.2894363922 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3975216231 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 3034073200 ps |
| CPU time | 376.85 seconds |
| Started | Jul 13 07:48:21 PM PDT 24 |
| Finished | Jul 13 07:54:40 PM PDT 24 |
| Peak memory | 609104 kb |
| Host | smart-e0168c60-6989-4511-a825-0f28e29fcb24 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975216231 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.3975216231 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2123784825 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 5813209440 ps |
| CPU time | 1236.75 seconds |
| Started | Jul 13 07:56:36 PM PDT 24 |
| Finished | Jul 13 08:17:13 PM PDT 24 |
| Peak memory | 609356 kb |
| Host | smart-ec0021a7-c138-47c2-948b-4dc6f1a743b6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123784825 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.2123784825 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3064906573 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 4047829416 ps |
| CPU time | 502.23 seconds |
| Started | Jul 13 07:47:30 PM PDT 24 |
| Finished | Jul 13 07:55:53 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-1b7cf93d-c0ab-4a18-8abe-363f9ab000d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064906573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.3064906573 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.361556363 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 3938685764 ps |
| CPU time | 559.14 seconds |
| Started | Jul 13 07:47:14 PM PDT 24 |
| Finished | Jul 13 07:56:34 PM PDT 24 |
| Peak memory | 609524 kb |
| Host | smart-89cca744-c846-48dd-80b9-1c7ad4a4b0a2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=361556363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.361556363 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.687794352 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 4773523309 ps |
| CPU time | 666.85 seconds |
| Started | Jul 13 07:54:47 PM PDT 24 |
| Finished | Jul 13 08:05:54 PM PDT 24 |
| Peak memory | 609596 kb |
| Host | smart-d8deadec-6a87-401a-8bdc-832c8da107f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=687794352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.687794352 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1848297671 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 3296151680 ps |
| CPU time | 394.14 seconds |
| Started | Jul 13 07:57:43 PM PDT 24 |
| Finished | Jul 13 08:04:18 PM PDT 24 |
| Peak memory | 609120 kb |
| Host | smart-b94f38ce-b489-4987-b7ec-ac5380af9bec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848297 671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.1848297671 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.4024556038 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 23909787650 ps |
| CPU time | 2099.27 seconds |
| Started | Jul 13 07:45:39 PM PDT 24 |
| Finished | Jul 13 08:20:39 PM PDT 24 |
| Peak memory | 612192 kb |
| Host | smart-8577a31f-117c-464c-8239-03a51a337b63 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024556038 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.4024556038 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1471415169 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 22539377644 ps |
| CPU time | 2361.02 seconds |
| Started | Jul 13 07:54:37 PM PDT 24 |
| Finished | Jul 13 08:33:59 PM PDT 24 |
| Peak memory | 614040 kb |
| Host | smart-9dcd97a2-2a99-40cb-9296-443fbdfbce26 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1471415169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.1471415169 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1737002151 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 2458509708 ps |
| CPU time | 277.74 seconds |
| Started | Jul 13 07:59:05 PM PDT 24 |
| Finished | Jul 13 08:03:44 PM PDT 24 |
| Peak memory | 609108 kb |
| Host | smart-fdfc7bb6-c633-4d0a-87db-0cb637f27ddf |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1737002151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.1737002151 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.3749364417 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 2894415024 ps |
| CPU time | 226.17 seconds |
| Started | Jul 13 07:58:05 PM PDT 24 |
| Finished | Jul 13 08:01:52 PM PDT 24 |
| Peak memory | 609600 kb |
| Host | smart-9684be9d-34d9-46ae-9c2f-ad2b6ccfd49d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749364417 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.3749364417 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.909195705 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 3303123670 ps |
| CPU time | 253.67 seconds |
| Started | Jul 13 07:54:45 PM PDT 24 |
| Finished | Jul 13 07:58:59 PM PDT 24 |
| Peak memory | 609152 kb |
| Host | smart-653a2ee9-7638-40c9-98ed-d497a8eb3df8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909195705 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.909195705 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.4097650155 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2584814932 ps |
| CPU time | 250.34 seconds |
| Started | Jul 13 07:50:52 PM PDT 24 |
| Finished | Jul 13 07:55:07 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-dfea5598-ae68-49d4-8c12-1b90a6fe1a6a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097650155 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.4097650155 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1629397492 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 3589742581 ps |
| CPU time | 228.5 seconds |
| Started | Jul 13 07:52:24 PM PDT 24 |
| Finished | Jul 13 07:56:14 PM PDT 24 |
| Peak memory | 608692 kb |
| Host | smart-afa521e0-7acc-42ed-996b-3dea9f49994d |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629397492 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.1629397492 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.773166568 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 3641653929 ps |
| CPU time | 291.76 seconds |
| Started | Jul 13 07:55:26 PM PDT 24 |
| Finished | Jul 13 08:00:18 PM PDT 24 |
| Peak memory | 608716 kb |
| Host | smart-31e891af-ad6d-43c5-872f-429432b9cfa8 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773166568 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.773166568 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.4263862310 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 6406596248 ps |
| CPU time | 1599.75 seconds |
| Started | Jul 13 07:50:37 PM PDT 24 |
| Finished | Jul 13 08:17:18 PM PDT 24 |
| Peak memory | 609608 kb |
| Host | smart-3f676ea5-7df5-48c3-b6fd-97d93c6d6ec8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263862310 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_multistream.4263862310 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.2843581611 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 2765373800 ps |
| CPU time | 421.25 seconds |
| Started | Jul 13 07:49:53 PM PDT 24 |
| Finished | Jul 13 07:56:55 PM PDT 24 |
| Peak memory | 609084 kb |
| Host | smart-62346a01-55ec-491f-9e3a-dd6f5ea1492c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843581611 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.2843581611 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.1302817153 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 3605499480 ps |
| CPU time | 358.13 seconds |
| Started | Jul 13 07:57:41 PM PDT 24 |
| Finished | Jul 13 08:03:39 PM PDT 24 |
| Peak memory | 609044 kb |
| Host | smart-15fd6593-4516-4d9a-b9a3-492d2ad5d611 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302817153 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.1302817153 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.4231775977 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 4024289154 ps |
| CPU time | 503.53 seconds |
| Started | Jul 13 07:44:13 PM PDT 24 |
| Finished | Jul 13 07:52:40 PM PDT 24 |
| Peak memory | 609000 kb |
| Host | smart-ebd539d4-73b4-4df0-9f37-3cb8a3a90044 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231775977 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.4231775977 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2721516146 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 4665300624 ps |
| CPU time | 1023.99 seconds |
| Started | Jul 13 07:50:03 PM PDT 24 |
| Finished | Jul 13 08:07:08 PM PDT 24 |
| Peak memory | 608612 kb |
| Host | smart-b1672be5-99c6-4e34-a256-367514095a70 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721516146 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.2721516146 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2425469264 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 4743806078 ps |
| CPU time | 940.79 seconds |
| Started | Jul 13 07:48:29 PM PDT 24 |
| Finished | Jul 13 08:04:12 PM PDT 24 |
| Peak memory | 608628 kb |
| Host | smart-73ce4bc3-c7fd-42bb-a639-707f916fb6c5 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425469264 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.2425469264 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.614411381 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 4826873960 ps |
| CPU time | 951.28 seconds |
| Started | Jul 13 07:48:14 PM PDT 24 |
| Finished | Jul 13 08:04:07 PM PDT 24 |
| Peak memory | 608604 kb |
| Host | smart-a8b35442-e50f-46fe-95f0-5b54172c9769 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614411381 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.614411381 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.217609086 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 64511177105 ps |
| CPU time | 12662.1 seconds |
| Started | Jul 13 07:45:12 PM PDT 24 |
| Finished | Jul 13 11:16:16 PM PDT 24 |
| Peak memory | 624216 kb |
| Host | smart-f5da3cb5-fbaf-4b71-8c7c-7c51a8736310 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=217609086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.217609086 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1297685495 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 8520815360 ps |
| CPU time | 1715.83 seconds |
| Started | Jul 13 07:49:52 PM PDT 24 |
| Finished | Jul 13 08:18:29 PM PDT 24 |
| Peak memory | 616184 kb |
| Host | smart-8173fe2d-d1b7-4016-82f5-78058c8ff219 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297 685495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.1297685495 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.777753571 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 9245153822 ps |
| CPU time | 1769.87 seconds |
| Started | Jul 13 07:49:32 PM PDT 24 |
| Finished | Jul 13 08:19:03 PM PDT 24 |
| Peak memory | 617220 kb |
| Host | smart-c46e5f3b-870c-4a67-b0d6-ae8071eb3a2e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=777753571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.777753571 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3262434958 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 12029548363 ps |
| CPU time | 1690.41 seconds |
| Started | Jul 13 07:57:15 PM PDT 24 |
| Finished | Jul 13 08:25:26 PM PDT 24 |
| Peak memory | 616204 kb |
| Host | smart-0bc0820e-b667-4c1f-85aa-74eb46c1403a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3262434958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.3262434958 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2305114255 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 8055120250 ps |
| CPU time | 1419.11 seconds |
| Started | Jul 13 07:53:35 PM PDT 24 |
| Finished | Jul 13 08:17:15 PM PDT 24 |
| Peak memory | 617216 kb |
| Host | smart-b0d3cd26-c705-4e49-a9d5-1b8cdf585376 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2305114255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.2305114255 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.910760407 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 10482694460 ps |
| CPU time | 2172.6 seconds |
| Started | Jul 13 07:50:50 PM PDT 24 |
| Finished | Jul 13 08:27:07 PM PDT 24 |
| Peak memory | 610556 kb |
| Host | smart-59d09695-741e-4ce3-b648-ae8b3b1915f1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910760 407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.910760407 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1348145690 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 12791109720 ps |
| CPU time | 2681.58 seconds |
| Started | Jul 13 07:51:38 PM PDT 24 |
| Finished | Jul 13 08:36:20 PM PDT 24 |
| Peak memory | 609436 kb |
| Host | smart-218ee835-d5e7-4ebf-90f9-85618e5698a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13481 45690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.1348145690 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1491407075 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 12020015924 ps |
| CPU time | 3657.46 seconds |
| Started | Jul 13 07:52:36 PM PDT 24 |
| Finished | Jul 13 08:53:35 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-ff20c36b-1d6f-4fa5-89c9-8ad0387bf2dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14914 07075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.1491407075 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.1763020876 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 3451109808 ps |
| CPU time | 262.7 seconds |
| Started | Jul 13 07:51:07 PM PDT 24 |
| Finished | Jul 13 07:55:32 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-1122e9f4-fb7d-4c02-804c-7cbdc8130173 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763020876 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.1763020876 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.3070476689 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 2895090680 ps |
| CPU time | 253.39 seconds |
| Started | Jul 13 07:50:12 PM PDT 24 |
| Finished | Jul 13 07:54:27 PM PDT 24 |
| Peak memory | 609256 kb |
| Host | smart-520122ca-9f2d-4242-a257-36f2bae9ef3d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070476689 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.3070476689 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.283351349 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 2661080220 ps |
| CPU time | 265.52 seconds |
| Started | Jul 13 07:50:02 PM PDT 24 |
| Finished | Jul 13 07:54:28 PM PDT 24 |
| Peak memory | 609048 kb |
| Host | smart-60aec991-7aed-427a-88cb-df249ce013af |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283351349 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_idle.283351349 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.37007366 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 2850330904 ps |
| CPU time | 199.06 seconds |
| Started | Jul 13 07:50:26 PM PDT 24 |
| Finished | Jul 13 07:53:46 PM PDT 24 |
| Peak memory | 609116 kb |
| Host | smart-aed11976-2395-4985-a656-db991cd118c7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37007366 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_cshake.37007366 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2492352656 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 2366350970 ps |
| CPU time | 326.87 seconds |
| Started | Jul 13 07:51:02 PM PDT 24 |
| Finished | Jul 13 07:56:33 PM PDT 24 |
| Peak memory | 609088 kb |
| Host | smart-76191dfb-c6e6-4aca-84e4-028e9d50e926 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492352656 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.2492352656 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1172812126 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 3434957743 ps |
| CPU time | 313.75 seconds |
| Started | Jul 13 07:51:41 PM PDT 24 |
| Finished | Jul 13 07:56:55 PM PDT 24 |
| Peak memory | 608664 kb |
| Host | smart-7330e883-e2a1-4531-a1f9-cb521522faa1 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172812126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.1172812126 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3040486907 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 3065835299 ps |
| CPU time | 271.45 seconds |
| Started | Jul 13 07:56:14 PM PDT 24 |
| Finished | Jul 13 08:00:46 PM PDT 24 |
| Peak memory | 608684 kb |
| Host | smart-a1502a92-01b8-4daa-99a2-aa1e6199bd00 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30404869 07 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3040486907 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.1412736744 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 3083533074 ps |
| CPU time | 325.37 seconds |
| Started | Jul 13 07:57:08 PM PDT 24 |
| Finished | Jul 13 08:02:34 PM PDT 24 |
| Peak memory | 609068 kb |
| Host | smart-8b1853e9-7b9b-4a9f-8a5d-cab1825faf84 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412736744 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.1412736744 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2685193839 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 3740619960 ps |
| CPU time | 367.46 seconds |
| Started | Jul 13 07:49:50 PM PDT 24 |
| Finished | Jul 13 07:56:00 PM PDT 24 |
| Peak memory | 609040 kb |
| Host | smart-a84fa566-25be-43c7-b35c-a03dadca8ebd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685193839 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.2685193839 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.2014257478 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 5768962730 ps |
| CPU time | 785.63 seconds |
| Started | Jul 13 07:58:33 PM PDT 24 |
| Finished | Jul 13 08:11:40 PM PDT 24 |
| Peak memory | 608784 kb |
| Host | smart-68693e8e-b5b0-4420-aa65-432cfeca27bf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2014257478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.2014257478 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.271238288 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 2527798287 ps |
| CPU time | 186.2 seconds |
| Started | Jul 13 07:46:49 PM PDT 24 |
| Finished | Jul 13 07:49:56 PM PDT 24 |
| Peak memory | 620384 kb |
| Host | smart-09cd2dae-5e13-491c-826a-62a898064c7a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27123828 8 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.271238288 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1279720656 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 5087341500 ps |
| CPU time | 552.83 seconds |
| Started | Jul 13 07:52:50 PM PDT 24 |
| Finished | Jul 13 08:02:04 PM PDT 24 |
| Peak memory | 620860 kb |
| Host | smart-7ff7d0e9-52dd-4423-aa63-66a5c2a7abda |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279720656 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.1279720656 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1569052415 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 2042386965 ps |
| CPU time | 131.04 seconds |
| Started | Jul 13 07:51:33 PM PDT 24 |
| Finished | Jul 13 07:53:45 PM PDT 24 |
| Peak memory | 617132 kb |
| Host | smart-84bc242a-3b5d-416f-9730-51bec11317ef |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569052415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1569052415 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2088856976 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 47394245666 ps |
| CPU time | 5408.25 seconds |
| Started | Jul 13 07:50:29 PM PDT 24 |
| Finished | Jul 13 09:20:40 PM PDT 24 |
| Peak memory | 618388 kb |
| Host | smart-3873b054-4c77-45d3-bd29-eb0b261c9b5b |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088856976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_dev.2088856976 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1440171631 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 47958271787 ps |
| CPU time | 6178.24 seconds |
| Started | Jul 13 07:49:17 PM PDT 24 |
| Finished | Jul 13 09:32:17 PM PDT 24 |
| Peak memory | 618640 kb |
| Host | smart-f2c4c86f-2a21-42a9-a495-6fa25515ea03 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440171631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_lc_walkthrough_prod.1440171631 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1825327965 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 10248463905 ps |
| CPU time | 730.03 seconds |
| Started | Jul 13 07:47:29 PM PDT 24 |
| Finished | Jul 13 07:59:40 PM PDT 24 |
| Peak memory | 619356 kb |
| Host | smart-03e9a137-7518-41ab-b934-9f840b35f931 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825327965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.1825327965 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.80887880 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 48992087425 ps |
| CPU time | 5407.01 seconds |
| Started | Jul 13 07:46:52 PM PDT 24 |
| Finished | Jul 13 09:17:00 PM PDT 24 |
| Peak memory | 619556 kb |
| Host | smart-a9277691-8560-4273-9520-1201273d3636 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80887880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_lc_walkthrough_rma.80887880 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.96478544 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 27173511238 ps |
| CPU time | 2079.69 seconds |
| Started | Jul 13 07:48:49 PM PDT 24 |
| Finished | Jul 13 08:23:30 PM PDT 24 |
| Peak memory | 620504 kb |
| Host | smart-883c5d10-5ec2-4910-8e71-3fd9b66324c1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=96478544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testunlocks.96478544 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3324032969 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 17419248896 ps |
| CPU time | 3437.76 seconds |
| Started | Jul 13 07:47:15 PM PDT 24 |
| Finished | Jul 13 08:44:33 PM PDT 24 |
| Peak memory | 609648 kb |
| Host | smart-6042ee3c-25e1-4347-b558-35065b8d7b9d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3324032969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.3324032969 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1070118837 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 19169915053 ps |
| CPU time | 3945.06 seconds |
| Started | Jul 13 07:49:09 PM PDT 24 |
| Finished | Jul 13 08:54:56 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-8e92b072-262a-4af9-9170-6bc3c8d07d5f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1070118837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1070118837 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.235138643 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 24527370473 ps |
| CPU time | 3904.55 seconds |
| Started | Jul 13 07:54:53 PM PDT 24 |
| Finished | Jul 13 08:59:58 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-26f5f517-bc30-4057-9027-be05ac28d6a6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235138643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.235138643 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.4270753373 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 3171135750 ps |
| CPU time | 463.94 seconds |
| Started | Jul 13 07:47:53 PM PDT 24 |
| Finished | Jul 13 07:55:37 PM PDT 24 |
| Peak memory | 608700 kb |
| Host | smart-ca6cb94a-6681-4d0e-89de-e9d1e688843a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270753373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.4270753373 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.4210004797 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 6147818140 ps |
| CPU time | 654.6 seconds |
| Started | Jul 13 07:46:25 PM PDT 24 |
| Finished | Jul 13 07:57:20 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-9cc79f43-cb4f-4d80-bda4-f3d5f1ba74f8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4210004797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.4210004797 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.3006586047 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 11368527520 ps |
| CPU time | 2564.61 seconds |
| Started | Jul 13 07:56:47 PM PDT 24 |
| Finished | Jul 13 08:39:32 PM PDT 24 |
| Peak memory | 608804 kb |
| Host | smart-f4308b55-3f05-4f57-81ff-31872689d889 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006586047 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.3006586047 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.1023831386 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 3367517106 ps |
| CPU time | 297.1 seconds |
| Started | Jul 13 07:47:38 PM PDT 24 |
| Finished | Jul 13 07:52:36 PM PDT 24 |
| Peak memory | 609608 kb |
| Host | smart-0ba1ce27-b3f6-4ccc-b670-b4baf88555fd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023831386 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.1023831386 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.199945408 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 7204395840 ps |
| CPU time | 1170.3 seconds |
| Started | Jul 13 07:49:55 PM PDT 24 |
| Finished | Jul 13 08:09:26 PM PDT 24 |
| Peak memory | 609676 kb |
| Host | smart-337b4a68-9947-468b-9cf3-8569d78104d5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=199945408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.199945408 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1503521048 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 8864125880 ps |
| CPU time | 1433.65 seconds |
| Started | Jul 13 07:48:50 PM PDT 24 |
| Finished | Jul 13 08:12:45 PM PDT 24 |
| Peak memory | 609952 kb |
| Host | smart-02bd3fc8-301a-4689-9473-38a62a080866 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1503521048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.1503521048 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3049397637 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 8172968900 ps |
| CPU time | 1486.67 seconds |
| Started | Jul 13 07:47:09 PM PDT 24 |
| Finished | Jul 13 08:11:57 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-6f6d7dc1-47ba-40f6-9f57-e991ff666d11 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3049397637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.3049397637 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1201176334 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 4633228480 ps |
| CPU time | 699.24 seconds |
| Started | Jul 13 07:49:07 PM PDT 24 |
| Finished | Jul 13 08:00:48 PM PDT 24 |
| Peak memory | 608704 kb |
| Host | smart-bf2a9993-d621-419d-81e2-7c0436781e93 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1201176334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1201176334 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1448498671 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 3305437194 ps |
| CPU time | 306.86 seconds |
| Started | Jul 13 07:56:53 PM PDT 24 |
| Finished | Jul 13 08:02:01 PM PDT 24 |
| Peak memory | 607940 kb |
| Host | smart-3a08c7ae-1236-475c-9aa4-507d1cf3a692 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448498671 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.1448498671 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.1190455685 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 2960450976 ps |
| CPU time | 335.71 seconds |
| Started | Jul 13 07:51:02 PM PDT 24 |
| Finished | Jul 13 07:56:41 PM PDT 24 |
| Peak memory | 608660 kb |
| Host | smart-0002c94f-e4dc-499a-b998-b53544e790fc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190455685 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.1190455685 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.2985601475 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 3979823320 ps |
| CPU time | 647.13 seconds |
| Started | Jul 13 07:56:28 PM PDT 24 |
| Finished | Jul 13 08:07:17 PM PDT 24 |
| Peak memory | 609388 kb |
| Host | smart-d48e62e1-3b7d-4ea1-9dc3-cc78f5a21161 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985601475 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.2985601475 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.234324124 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 4348535810 ps |
| CPU time | 445.1 seconds |
| Started | Jul 13 07:55:46 PM PDT 24 |
| Finished | Jul 13 08:03:12 PM PDT 24 |
| Peak memory | 608732 kb |
| Host | smart-bbf8ddc8-b73b-411f-a52f-783a78ea31ed |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234324124 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.234324124 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2452147067 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 8374584712 ps |
| CPU time | 1675.86 seconds |
| Started | Jul 13 07:52:15 PM PDT 24 |
| Finished | Jul 13 08:20:12 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-91b9107a-df1d-4279-9ac9-d1780f724511 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452 147067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.2452147067 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1364163132 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 20948415721 ps |
| CPU time | 2587.32 seconds |
| Started | Jul 13 07:50:11 PM PDT 24 |
| Finished | Jul 13 08:33:20 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-7089e8d9-3b04-4f86-afd1-6261c3d82533 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136 4163132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.1364163132 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.930094111 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 16835095161 ps |
| CPU time | 1289.8 seconds |
| Started | Jul 13 07:48:20 PM PDT 24 |
| Finished | Jul 13 08:09:51 PM PDT 24 |
| Peak memory | 610676 kb |
| Host | smart-2f815ec0-8c6b-4937-ac39-8f09ef5ac92f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=930094111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.930094111 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.800614913 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 26386359520 ps |
| CPU time | 1723.75 seconds |
| Started | Jul 13 07:53:20 PM PDT 24 |
| Finished | Jul 13 08:22:04 PM PDT 24 |
| Peak memory | 610232 kb |
| Host | smart-eb614a9d-3b3b-4d23-a02b-07ffcfe809c7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 800614913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.800614913 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3152363585 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 7511761360 ps |
| CPU time | 664.12 seconds |
| Started | Jul 13 07:50:08 PM PDT 24 |
| Finished | Jul 13 08:01:14 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-95390b13-8f24-4719-acef-1e325b1ad2ff |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152363585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.3152363585 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.809462221 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 5870222192 ps |
| CPU time | 434.12 seconds |
| Started | Jul 13 07:48:52 PM PDT 24 |
| Finished | Jul 13 07:56:07 PM PDT 24 |
| Peak memory | 616268 kb |
| Host | smart-4c9bb02b-6fc8-40ab-b2c0-aaa60d203bc3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=809462221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.809462221 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2268691993 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 8873698563 ps |
| CPU time | 575.42 seconds |
| Started | Jul 13 07:48:16 PM PDT 24 |
| Finished | Jul 13 07:57:52 PM PDT 24 |
| Peak memory | 608968 kb |
| Host | smart-5475ec75-cccd-48bd-bfbf-eb9c2500a739 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268691993 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.2268691993 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.997166209 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 3496754000 ps |
| CPU time | 472.01 seconds |
| Started | Jul 13 07:52:55 PM PDT 24 |
| Finished | Jul 13 08:00:48 PM PDT 24 |
| Peak memory | 609124 kb |
| Host | smart-a6c661b0-6674-486d-8c50-76d8c79580de |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997166209 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.997166209 |
| Directory | /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2888496944 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 4533810653 ps |
| CPU time | 516.67 seconds |
| Started | Jul 13 07:47:53 PM PDT 24 |
| Finished | Jul 13 07:56:31 PM PDT 24 |
| Peak memory | 615528 kb |
| Host | smart-18e48f5d-8b1e-4163-a155-bc0f146709ca |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2888496944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.2888496944 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1588255669 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 12431031200 ps |
| CPU time | 1632.88 seconds |
| Started | Jul 13 07:52:04 PM PDT 24 |
| Finished | Jul 13 08:19:19 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-13b4c892-4f09-4c49-a928-07fed1229458 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588255669 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1588255669 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3883951559 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6956898760 ps |
| CPU time | 544.25 seconds |
| Started | Jul 13 07:52:34 PM PDT 24 |
| Finished | Jul 13 08:01:39 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-c5d68211-b765-4adf-ae7e-8df767e872e7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883951559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3883951559 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3563471951 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 5679509076 ps |
| CPU time | 407.01 seconds |
| Started | Jul 13 07:45:24 PM PDT 24 |
| Finished | Jul 13 07:52:12 PM PDT 24 |
| Peak memory | 608816 kb |
| Host | smart-5bdd830a-3502-45ba-8911-141ee0257265 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563471951 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.3563471951 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1345769157 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 25458617847 ps |
| CPU time | 2418.25 seconds |
| Started | Jul 13 07:47:53 PM PDT 24 |
| Finished | Jul 13 08:28:12 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-293e79a8-219c-49aa-a964-447be3531b2e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1345769157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1345769157 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1241669082 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 22461739648 ps |
| CPU time | 1930.53 seconds |
| Started | Jul 13 07:53:07 PM PDT 24 |
| Finished | Jul 13 08:25:18 PM PDT 24 |
| Peak memory | 610240 kb |
| Host | smart-ab4c7788-3432-4bc7-8756-1b8773eca323 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1241669082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1241669082 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1449171557 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 34402733976 ps |
| CPU time | 3074.6 seconds |
| Started | Jul 13 07:50:48 PM PDT 24 |
| Finished | Jul 13 08:42:04 PM PDT 24 |
| Peak memory | 610516 kb |
| Host | smart-64cc347a-7573-4149-b739-db57977ada35 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449171557 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s leep_power_glitch_reset.1449171557 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.383041916 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 4531365148 ps |
| CPU time | 471.65 seconds |
| Started | Jul 13 07:54:09 PM PDT 24 |
| Finished | Jul 13 08:02:02 PM PDT 24 |
| Peak memory | 610472 kb |
| Host | smart-588889ff-3933-470c-8b40-23dc0c96df9a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=383041916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_sl eep_wake_up.383041916 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2424510906 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 2339345580 ps |
| CPU time | 211.95 seconds |
| Started | Jul 13 07:54:29 PM PDT 24 |
| Finished | Jul 13 07:58:02 PM PDT 24 |
| Peak memory | 608000 kb |
| Host | smart-955751bf-46b3-452d-8a7d-7915237d0a0d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424510906 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.2424510906 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1694571634 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 5653819797 ps |
| CPU time | 424.93 seconds |
| Started | Jul 13 07:46:55 PM PDT 24 |
| Finished | Jul 13 07:54:01 PM PDT 24 |
| Peak memory | 616948 kb |
| Host | smart-0574cdeb-cd2a-4310-91eb-b2a8c1396c7f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1694571634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.1694571634 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2140630680 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 7293979280 ps |
| CPU time | 610.49 seconds |
| Started | Jul 13 07:54:16 PM PDT 24 |
| Finished | Jul 13 08:04:27 PM PDT 24 |
| Peak memory | 610164 kb |
| Host | smart-89b89d86-f3af-4314-83af-62a00eabc9b9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2140630680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.2140630680 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2668120909 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 6160050074 ps |
| CPU time | 472.06 seconds |
| Started | Jul 13 07:58:27 PM PDT 24 |
| Finished | Jul 13 08:06:19 PM PDT 24 |
| Peak memory | 608708 kb |
| Host | smart-25437f32-993c-4427-89d1-1740cacb2bfa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668120909 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.2668120909 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3344441488 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 8051020599 ps |
| CPU time | 1116.47 seconds |
| Started | Jul 13 07:47:57 PM PDT 24 |
| Finished | Jul 13 08:06:34 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-b0317fa8-12c6-422d-a2d8-03e755a75ab5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344441488 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.3344441488 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.4019453700 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 4917654596 ps |
| CPU time | 411.12 seconds |
| Started | Jul 13 07:48:26 PM PDT 24 |
| Finished | Jul 13 07:55:18 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-237a91f6-84b0-4b9b-bae4-cb6d7f3a574a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019453700 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.4019453700 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3242298971 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 6397618036 ps |
| CPU time | 545.76 seconds |
| Started | Jul 13 07:57:46 PM PDT 24 |
| Finished | Jul 13 08:06:52 PM PDT 24 |
| Peak memory | 609756 kb |
| Host | smart-90743e75-e701-4f51-afe9-f7288ed2959d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242298971 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.3242298971 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.4250333735 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 5341300220 ps |
| CPU time | 602.17 seconds |
| Started | Jul 13 07:54:18 PM PDT 24 |
| Finished | Jul 13 08:04:21 PM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-660f49b2-a434-46d7-8808-93e124fc6bd2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425 0333735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.4250333735 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1779682904 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 9525425343 ps |
| CPU time | 452.84 seconds |
| Started | Jul 13 07:50:49 PM PDT 24 |
| Finished | Jul 13 07:58:28 PM PDT 24 |
| Peak memory | 624144 kb |
| Host | smart-a89d3973-e486-40ef-b06a-6a9d3189c10a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779682904 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.1779682904 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3608561986 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 7099437400 ps |
| CPU time | 838.02 seconds |
| Started | Jul 13 07:49:52 PM PDT 24 |
| Finished | Jul 13 08:03:52 PM PDT 24 |
| Peak memory | 609876 kb |
| Host | smart-ce730430-7f2b-49fd-a289-81a33fb78e8e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608561986 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.3608561986 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.406275329 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 5707078160 ps |
| CPU time | 604 seconds |
| Started | Jul 13 07:52:38 PM PDT 24 |
| Finished | Jul 13 08:02:43 PM PDT 24 |
| Peak memory | 640532 kb |
| Host | smart-9a0e9b28-b7d5-4d06-a8a9-fce3f97f1f8e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 406275329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.406275329 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3453689437 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 3175616078 ps |
| CPU time | 312.24 seconds |
| Started | Jul 13 07:58:28 PM PDT 24 |
| Finished | Jul 13 08:03:41 PM PDT 24 |
| Peak memory | 609052 kb |
| Host | smart-dd5fd452-fb69-4995-b0fd-6448f61ea645 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453689437 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.3453689437 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1310128341 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 4306829700 ps |
| CPU time | 384.53 seconds |
| Started | Jul 13 07:51:17 PM PDT 24 |
| Finished | Jul 13 07:57:43 PM PDT 24 |
| Peak memory | 609764 kb |
| Host | smart-f344a0d2-ab89-4ff3-9968-8dd2fe5686e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310128341 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.1310128341 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2708874926 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 2386790388 ps |
| CPU time | 240.67 seconds |
| Started | Jul 13 07:50:53 PM PDT 24 |
| Finished | Jul 13 07:54:59 PM PDT 24 |
| Peak memory | 608028 kb |
| Host | smart-07e393b5-62a4-4cd2-b88b-c4fb10970123 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708874926 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.2708874926 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3130476051 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2415265844 ps |
| CPU time | 284.8 seconds |
| Started | Jul 13 07:56:27 PM PDT 24 |
| Finished | Jul 13 08:01:12 PM PDT 24 |
| Peak memory | 609220 kb |
| Host | smart-e62b56f3-825c-4b70-b5aa-66086dc693bc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3130476051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.3130476051 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.4105063983 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 2526953982 ps |
| CPU time | 223.52 seconds |
| Started | Jul 13 07:56:30 PM PDT 24 |
| Finished | Jul 13 08:00:14 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-c2471b29-483d-4963-9045-a84aff4816ed |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105063983 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.4105063983 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1817215814 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 2355913032 ps |
| CPU time | 310.95 seconds |
| Started | Jul 13 07:57:47 PM PDT 24 |
| Finished | Jul 13 08:02:59 PM PDT 24 |
| Peak memory | 646128 kb |
| Host | smart-2475448a-15e8-4f23-b6e2-421238f749ed |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817215814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.1817215814 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.819061136 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 4931905250 ps |
| CPU time | 827.86 seconds |
| Started | Jul 13 07:48:06 PM PDT 24 |
| Finished | Jul 13 08:01:54 PM PDT 24 |
| Peak memory | 608688 kb |
| Host | smart-31987c52-82d5-4dc9-93b3-e4b46e3869eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81906 1136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.819061136 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2161523325 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 5520189220 ps |
| CPU time | 1057.07 seconds |
| Started | Jul 13 07:47:21 PM PDT 24 |
| Finished | Jul 13 08:04:59 PM PDT 24 |
| Peak memory | 608676 kb |
| Host | smart-e8d7b527-674b-411e-9177-1a34e0208d09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2161523325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.2161523325 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1677198066 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 5081672902 ps |
| CPU time | 490.28 seconds |
| Started | Jul 13 07:53:45 PM PDT 24 |
| Finished | Jul 13 08:01:56 PM PDT 24 |
| Peak memory | 623132 kb |
| Host | smart-40e89fe2-620c-40df-be6e-f8001ee0a6f3 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677198066 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.1677198066 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3324345633 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 5751050080 ps |
| CPU time | 366.3 seconds |
| Started | Jul 13 07:52:50 PM PDT 24 |
| Finished | Jul 13 07:58:57 PM PDT 24 |
| Peak memory | 619620 kb |
| Host | smart-9262c5fa-a8a1-4f63-a282-d6d49b5357bc |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324345633 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.3324345633 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.967975825 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4692500150 ps |
| CPU time | 383.09 seconds |
| Started | Jul 13 07:55:10 PM PDT 24 |
| Finished | Jul 13 08:01:33 PM PDT 24 |
| Peak memory | 618508 kb |
| Host | smart-dd131aa6-57f3-4fb2-ab94-69335014455e |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967975 825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.967975825 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2901126897 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 3082400624 ps |
| CPU time | 312.17 seconds |
| Started | Jul 13 07:58:02 PM PDT 24 |
| Finished | Jul 13 08:03:15 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-9162717d-0b45-4554-97b9-ae20087207a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901126897 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.2901126897 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.627238447 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 3123525560 ps |
| CPU time | 308.94 seconds |
| Started | Jul 13 07:52:18 PM PDT 24 |
| Finished | Jul 13 07:57:28 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-b70e0a1b-1292-4502-bb24-65e9143e0246 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627238447 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_timer_irq.627238447 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.312498723 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 3449090296 ps |
| CPU time | 358.62 seconds |
| Started | Jul 13 07:57:57 PM PDT 24 |
| Finished | Jul 13 08:03:56 PM PDT 24 |
| Peak memory | 609244 kb |
| Host | smart-dc68817b-ffae-4d7f-b285-3683a1e95d47 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312498723 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_timer_smoketest.312498723 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.270972924 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 2998723802 ps |
| CPU time | 224.52 seconds |
| Started | Jul 13 07:52:12 PM PDT 24 |
| Finished | Jul 13 07:55:57 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-f9871726-2edc-4523-bef5-3ed7d19be897 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709729 24 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.270972924 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2578327888 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 8285695128 ps |
| CPU time | 1282.25 seconds |
| Started | Jul 13 07:46:08 PM PDT 24 |
| Finished | Jul 13 08:07:32 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-145cc8f0-1ce8-4816-a7f6-23f84eb7490a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578327888 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.2578327888 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3275319305 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 8344653904 ps |
| CPU time | 873.67 seconds |
| Started | Jul 13 07:50:45 PM PDT 24 |
| Finished | Jul 13 08:05:19 PM PDT 24 |
| Peak memory | 609868 kb |
| Host | smart-b343b660-681f-42c0-8b83-f2317f484536 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275319305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl eep_sram_ret_contents_no_scramble.3275319305 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1382213492 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 8473246680 ps |
| CPU time | 814.92 seconds |
| Started | Jul 13 07:51:30 PM PDT 24 |
| Finished | Jul 13 08:05:05 PM PDT 24 |
| Peak memory | 609808 kb |
| Host | smart-b5837663-a1b9-453b-9707-6f71ffb2863c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382213492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.1382213492 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3075984458 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 6615576489 ps |
| CPU time | 799.45 seconds |
| Started | Jul 13 07:48:59 PM PDT 24 |
| Finished | Jul 13 08:02:19 PM PDT 24 |
| Peak memory | 624308 kb |
| Host | smart-94069d35-bbe6-4efb-9beb-536edbf5ce99 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075984458 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.3075984458 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2414318175 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 5205884419 ps |
| CPU time | 805.25 seconds |
| Started | Jul 13 07:48:41 PM PDT 24 |
| Finished | Jul 13 08:02:08 PM PDT 24 |
| Peak memory | 624312 kb |
| Host | smart-0e13956a-817f-4e0a-891c-73e7696b6927 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414318175 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.2414318175 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.1333854292 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3239192294 ps |
| CPU time | 383.72 seconds |
| Started | Jul 13 07:46:20 PM PDT 24 |
| Finished | Jul 13 07:52:44 PM PDT 24 |
| Peak memory | 617740 kb |
| Host | smart-accc5abc-ad4f-4102-84a6-49c88c422ddc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333854292 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.1333854292 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3155090009 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2696815208 ps |
| CPU time | 258.71 seconds |
| Started | Jul 13 07:47:11 PM PDT 24 |
| Finished | Jul 13 07:51:30 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-d160fda1-c7c9-4299-ba83-9772c0e6e929 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155090009 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.3155090009 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.84334017 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 7919188436 ps |
| CPU time | 722.31 seconds |
| Started | Jul 13 07:55:21 PM PDT 24 |
| Finished | Jul 13 08:07:23 PM PDT 24 |
| Peak memory | 609808 kb |
| Host | smart-80145c78-96fc-4349-b8eb-e1e1e008d7f8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84334017 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.84334017 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.412984537 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 4642807740 ps |
| CPU time | 564.53 seconds |
| Started | Jul 13 07:52:11 PM PDT 24 |
| Finished | Jul 13 08:01:36 PM PDT 24 |
| Peak memory | 610308 kb |
| Host | smart-fb76ddfa-2aa8-432e-80b7-531f9ef85956 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412984537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ sram_ctrl_scrambled_access.412984537 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.68030518 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 5203663946 ps |
| CPU time | 486.24 seconds |
| Started | Jul 13 07:51:13 PM PDT 24 |
| Finished | Jul 13 07:59:20 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-f545bac4-16d5-48b0-8d8c-c9df5a6aebb5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68030518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.68030518 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3260687084 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 4224576431 ps |
| CPU time | 488.7 seconds |
| Started | Jul 13 07:55:47 PM PDT 24 |
| Finished | Jul 13 08:03:57 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-497713e7-e000-4205-a2ea-65af5aae4565 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260687084 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3260687084 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.4157123069 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 2968291152 ps |
| CPU time | 161.34 seconds |
| Started | Jul 13 07:57:46 PM PDT 24 |
| Finished | Jul 13 08:00:28 PM PDT 24 |
| Peak memory | 609056 kb |
| Host | smart-c509492e-2864-4fd8-9e9d-b77a3dd52ec5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157123069 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.4157123069 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3379409987 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 20738243051 ps |
| CPU time | 4062.76 seconds |
| Started | Jul 13 07:54:32 PM PDT 24 |
| Finished | Jul 13 09:02:16 PM PDT 24 |
| Peak memory | 609952 kb |
| Host | smart-bd888d98-79b9-4bae-9a9b-53725d2c4c31 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379409987 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.3379409987 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2191963501 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 4807118404 ps |
| CPU time | 658.3 seconds |
| Started | Jul 13 07:46:16 PM PDT 24 |
| Finished | Jul 13 07:57:18 PM PDT 24 |
| Peak memory | 613024 kb |
| Host | smart-da091588-7f76-49b4-a389-1d9bc4b6110a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191963501 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.2191963501 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3714944162 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 3115938180 ps |
| CPU time | 368.12 seconds |
| Started | Jul 13 07:47:15 PM PDT 24 |
| Finished | Jul 13 07:53:25 PM PDT 24 |
| Peak memory | 612488 kb |
| Host | smart-0434083c-e3cd-47ec-acc4-61eb9061b46d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714944162 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.3714944162 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1643563725 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 3782986575 ps |
| CPU time | 342.26 seconds |
| Started | Jul 13 07:48:20 PM PDT 24 |
| Finished | Jul 13 07:54:04 PM PDT 24 |
| Peak memory | 608700 kb |
| Host | smart-2327e6bf-c967-479c-9483-e74d303c395f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643563725 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.1643563725 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.4122129562 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 22148135728 ps |
| CPU time | 1929.69 seconds |
| Started | Jul 13 07:49:31 PM PDT 24 |
| Finished | Jul 13 08:21:42 PM PDT 24 |
| Peak memory | 614004 kb |
| Host | smart-d77530ae-021b-4658-bcf0-f1f57c8bc4b9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41221295 62 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.4122129562 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.697149651 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 5962069928 ps |
| CPU time | 418.9 seconds |
| Started | Jul 13 07:47:57 PM PDT 24 |
| Finished | Jul 13 07:54:57 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-908a43b0-689d-4ecc-a563-6dd1ac649ac5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697149651 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.697149651 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.658713374 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 4057581960 ps |
| CPU time | 619.18 seconds |
| Started | Jul 13 07:46:07 PM PDT 24 |
| Finished | Jul 13 07:56:28 PM PDT 24 |
| Peak memory | 617872 kb |
| Host | smart-a9fe19de-bfd4-49c2-a947-278df7f52b14 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=658713374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.658713374 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.374405771 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 2840726322 ps |
| CPU time | 247.67 seconds |
| Started | Jul 13 07:57:14 PM PDT 24 |
| Finished | Jul 13 08:01:22 PM PDT 24 |
| Peak memory | 615192 kb |
| Host | smart-a87bdd74-a169-4ab7-a0b7-aaecf4f83044 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374405771 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_uart_smoketest.374405771 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.685944295 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 4604926906 ps |
| CPU time | 605.27 seconds |
| Started | Jul 13 07:47:48 PM PDT 24 |
| Finished | Jul 13 07:57:55 PM PDT 24 |
| Peak memory | 623520 kb |
| Host | smart-004754c5-70d6-4e24-8fdc-941cc9f4452f |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685944295 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.685944295 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3508527160 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 3939837780 ps |
| CPU time | 578.4 seconds |
| Started | Jul 13 07:46:28 PM PDT 24 |
| Finished | Jul 13 07:56:08 PM PDT 24 |
| Peak memory | 623228 kb |
| Host | smart-dd16509a-0d67-41f8-b015-58fa5eec6d54 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508527160 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.3508527160 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1207410129 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 3930638312 ps |
| CPU time | 676.05 seconds |
| Started | Jul 13 07:48:51 PM PDT 24 |
| Finished | Jul 13 08:00:08 PM PDT 24 |
| Peak memory | 623164 kb |
| Host | smart-f4fa7f5f-dbb4-4211-90e5-82ddad5e27c1 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207410129 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.1207410129 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1301973730 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 3618781428 ps |
| CPU time | 771.61 seconds |
| Started | Jul 13 07:47:17 PM PDT 24 |
| Finished | Jul 13 08:00:10 PM PDT 24 |
| Peak memory | 623200 kb |
| Host | smart-139c28f1-ea0b-45a7-b0a8-6dc32ff50ea5 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301973730 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.1301973730 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.882445016 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 7667485470 ps |
| CPU time | 789.16 seconds |
| Started | Jul 13 07:52:38 PM PDT 24 |
| Finished | Jul 13 08:05:48 PM PDT 24 |
| Peak memory | 620220 kb |
| Host | smart-a8a4cf36-4f9a-4908-bbb1-2e363da30edc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=882445016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.882445016 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.2177718056 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 1974358460 ps |
| CPU time | 144.38 seconds |
| Started | Jul 13 07:53:33 PM PDT 24 |
| Finished | Jul 13 07:55:58 PM PDT 24 |
| Peak memory | 619416 kb |
| Host | smart-3f440829-f5ab-4a62-8401-2a089acdc04f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177718056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.2177718056 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_rma.1329318724 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 7567018845 ps |
| CPU time | 820.45 seconds |
| Started | Jul 13 07:54:15 PM PDT 24 |
| Finished | Jul 13 08:07:56 PM PDT 24 |
| Peak memory | 620308 kb |
| Host | smart-589a5511-1d56-49a1-a119-00c861d52538 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329318724 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.1329318724 |
| Directory | /workspace/1.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_testunlock0.4246977146 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 7465432889 ps |
| CPU time | 926.05 seconds |
| Started | Jul 13 07:52:49 PM PDT 24 |
| Finished | Jul 13 08:08:15 PM PDT 24 |
| Peak memory | 620356 kb |
| Host | smart-eaf9a171-235c-4c21-b6a1-fd75c7895183 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4246977146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.4246977146 |
| Directory | /workspace/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.590603757 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 15131351911 ps |
| CPU time | 4193.03 seconds |
| Started | Jul 13 08:01:06 PM PDT 24 |
| Finished | Jul 13 09:11:00 PM PDT 24 |
| Peak memory | 610516 kb |
| Host | smart-1c1bda77-f749-4ca2-a4ac-036ed15b4e2e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590603757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .rom_e2e_asm_init_dev.590603757 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.244585517 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 15438600629 ps |
| CPU time | 4031.29 seconds |
| Started | Jul 13 08:02:58 PM PDT 24 |
| Finished | Jul 13 09:10:10 PM PDT 24 |
| Peak memory | 610512 kb |
| Host | smart-85caa7c0-8e5e-42e6-b782-453c6868997f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244585517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.244585517 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3931855252 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 14897951304 ps |
| CPU time | 3644.52 seconds |
| Started | Jul 13 07:59:58 PM PDT 24 |
| Finished | Jul 13 09:00:44 PM PDT 24 |
| Peak memory | 609584 kb |
| Host | smart-7179401b-8316-48c0-8586-09fbd38a748a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931855252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.3931855252 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.2296593708 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 14993765988 ps |
| CPU time | 3614.9 seconds |
| Started | Jul 13 08:06:17 PM PDT 24 |
| Finished | Jul 13 09:06:33 PM PDT 24 |
| Peak memory | 609524 kb |
| Host | smart-f7b76a9c-a0a7-42bc-9a8b-95558d75c631 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296593708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.2296593708 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2487370623 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 11231370328 ps |
| CPU time | 2831.16 seconds |
| Started | Jul 13 08:01:06 PM PDT 24 |
| Finished | Jul 13 08:48:18 PM PDT 24 |
| Peak memory | 609740 kb |
| Host | smart-44be5179-a06d-4a65-acb3-7b51dbc79b2e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487370623 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_test_unlocked0.2487370623 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3054801166 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 14472674060 ps |
| CPU time | 3996.18 seconds |
| Started | Jul 13 08:00:46 PM PDT 24 |
| Finished | Jul 13 09:07:23 PM PDT 24 |
| Peak memory | 609816 kb |
| Host | smart-66b0cd1c-40aa-4225-9250-35eb525c408e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054801166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3054801166 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2154572507 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 15236681456 ps |
| CPU time | 3989.96 seconds |
| Started | Jul 13 08:06:06 PM PDT 24 |
| Finished | Jul 13 09:12:37 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-7631bf0a-71da-4b47-8bee-474e5a3cf9ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154572507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext _no_meas.2154572507 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3224275869 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 14161197184 ps |
| CPU time | 3441.02 seconds |
| Started | Jul 13 08:02:48 PM PDT 24 |
| Finished | Jul 13 09:00:09 PM PDT 24 |
| Peak memory | 609528 kb |
| Host | smart-4ad03250-5707-4af9-b5ba-89b1ac9d01da |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224275869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.3224275869 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.732629061 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 28352432339 ps |
| CPU time | 3911.34 seconds |
| Started | Jul 13 08:00:28 PM PDT 24 |
| Finished | Jul 13 09:05:41 PM PDT 24 |
| Peak memory | 612708 kb |
| Host | smart-ddda25c5-dc3a-4d77-a747-f4f878082b40 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732629061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.732629061 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.2058627783 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 15022505400 ps |
| CPU time | 3932.91 seconds |
| Started | Jul 13 08:00:22 PM PDT 24 |
| Finished | Jul 13 09:05:56 PM PDT 24 |
| Peak memory | 610788 kb |
| Host | smart-ff51cbc3-f31d-4ce9-ba98-f06f5db9acc4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=2058627783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.2058627783 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.3604458872 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 17564853012 ps |
| CPU time | 4446.24 seconds |
| Started | Jul 13 08:00:06 PM PDT 24 |
| Finished | Jul 13 09:14:13 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-99ebe152-aa5a-45d6-b447-b904efc3060a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604458872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.3604458872 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.3075120594 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 5845007688 ps |
| CPU time | 547.36 seconds |
| Started | Jul 13 07:59:53 PM PDT 24 |
| Finished | Jul 13 08:09:00 PM PDT 24 |
| Peak memory | 609624 kb |
| Host | smart-0bac155b-2647-469a-bfff-5e4fb2f6ec62 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075120594 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.3075120594 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.2389654980 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 2474384066 ps |
| CPU time | 128.54 seconds |
| Started | Jul 13 07:58:49 PM PDT 24 |
| Finished | Jul 13 08:00:58 PM PDT 24 |
| Peak memory | 615980 kb |
| Host | smart-aa86d7af-aad2-42fe-86d9-8c2ff7c673ae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389654980 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.2389654980 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3785613567 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 8376311934 ps |
| CPU time | 642.55 seconds |
| Started | Jul 13 08:10:57 PM PDT 24 |
| Finished | Jul 13 08:21:40 PM PDT 24 |
| Peak memory | 622476 kb |
| Host | smart-d318194d-8efd-407c-9023-1d77ee788db3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785613567 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.3785613567 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3672670376 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 8706760800 ps |
| CPU time | 1760.97 seconds |
| Started | Jul 13 08:09:52 PM PDT 24 |
| Finished | Jul 13 08:39:14 PM PDT 24 |
| Peak memory | 618248 kb |
| Host | smart-11e0dacd-d2cf-4041-8aac-05b297e4376c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3672670376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.3672670376 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.681078965 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 10003958059 ps |
| CPU time | 1147.28 seconds |
| Started | Jul 13 08:11:07 PM PDT 24 |
| Finished | Jul 13 08:30:15 PM PDT 24 |
| Peak memory | 622108 kb |
| Host | smart-8af9fb79-604a-492c-9847-02c6effeaf0d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681078965 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.681078965 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3520966682 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 3927496240 ps |
| CPU time | 669.32 seconds |
| Started | Jul 13 08:11:06 PM PDT 24 |
| Finished | Jul 13 08:22:17 PM PDT 24 |
| Peak memory | 617028 kb |
| Host | smart-e34c4ce0-c8eb-46cd-832f-0812f6494fbb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3520966682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.3520966682 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.2086808783 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 4829829368 ps |
| CPU time | 625.58 seconds |
| Started | Jul 13 08:11:24 PM PDT 24 |
| Finished | Jul 13 08:21:51 PM PDT 24 |
| Peak memory | 616232 kb |
| Host | smart-b5c44d9c-32b9-40a8-9046-c8dc4c5c5ec0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2086808783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.2086808783 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.4063953215 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 5842246856 ps |
| CPU time | 589.45 seconds |
| Started | Jul 13 08:10:23 PM PDT 24 |
| Finished | Jul 13 08:20:16 PM PDT 24 |
| Peak memory | 620792 kb |
| Host | smart-caf0f436-041b-4754-a205-db3923a8b3e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063953215 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.4063953215 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3974118587 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 8206955404 ps |
| CPU time | 1584.88 seconds |
| Started | Jul 13 08:11:15 PM PDT 24 |
| Finished | Jul 13 08:37:40 PM PDT 24 |
| Peak memory | 618524 kb |
| Host | smart-e99674a4-65f4-4f3a-a966-baa3d17ea19e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3974118587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.3974118587 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2679792224 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 3728659636 ps |
| CPU time | 433.61 seconds |
| Started | Jul 13 08:10:36 PM PDT 24 |
| Finished | Jul 13 08:17:50 PM PDT 24 |
| Peak memory | 648116 kb |
| Host | smart-55ad6085-5413-4202-873d-8624a053b5ed |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679792224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2679792224 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2090547813 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 6582366298 ps |
| CPU time | 504.75 seconds |
| Started | Jul 13 08:11:37 PM PDT 24 |
| Finished | Jul 13 08:20:03 PM PDT 24 |
| Peak memory | 620548 kb |
| Host | smart-938f713c-34b6-40b0-aff5-834ae23ac0ae |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090547813 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.2090547813 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.312270620 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 3910697192 ps |
| CPU time | 686.21 seconds |
| Started | Jul 13 08:10:20 PM PDT 24 |
| Finished | Jul 13 08:21:48 PM PDT 24 |
| Peak memory | 618052 kb |
| Host | smart-2a6749f2-376f-4a19-8164-b101a0c0c589 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=312270620 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.312270620 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2962801218 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 7531606743 ps |
| CPU time | 545.18 seconds |
| Started | Jul 13 08:10:21 PM PDT 24 |
| Finished | Jul 13 08:19:30 PM PDT 24 |
| Peak memory | 620556 kb |
| Host | smart-c94ef3f2-384d-4bee-857a-4ec769aa3f54 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962801218 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.2962801218 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1050751022 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 4307324132 ps |
| CPU time | 483.4 seconds |
| Started | Jul 13 08:11:24 PM PDT 24 |
| Finished | Jul 13 08:19:28 PM PDT 24 |
| Peak memory | 617540 kb |
| Host | smart-2ff5c256-7c08-44ff-ab49-387a882b5cb5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1050751022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.1050751022 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1581306194 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 3521144144 ps |
| CPU time | 451.91 seconds |
| Started | Jul 13 08:11:05 PM PDT 24 |
| Finished | Jul 13 08:18:38 PM PDT 24 |
| Peak memory | 648300 kb |
| Host | smart-b7b51d9f-642f-4a69-9c48-302871e62873 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581306194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1581306194 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3892581583 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 3928696848 ps |
| CPU time | 510.61 seconds |
| Started | Jul 13 08:10:45 PM PDT 24 |
| Finished | Jul 13 08:19:16 PM PDT 24 |
| Peak memory | 618304 kb |
| Host | smart-68e069cc-d0da-4419-aa9e-17e9888bd16f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3892581583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.3892581583 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2950606059 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 3964308450 ps |
| CPU time | 405.69 seconds |
| Started | Jul 13 08:11:31 PM PDT 24 |
| Finished | Jul 13 08:18:17 PM PDT 24 |
| Peak memory | 618540 kb |
| Host | smart-4c643202-5b23-4afb-9bbf-8e86b56c08eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2950606059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.2950606059 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.560806637 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 8523273792 ps |
| CPU time | 1550.82 seconds |
| Started | Jul 13 08:11:52 PM PDT 24 |
| Finished | Jul 13 08:37:43 PM PDT 24 |
| Peak memory | 617952 kb |
| Host | smart-a26cd431-7c33-4dd1-9cfd-892ee0428f59 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=560806637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.560806637 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.1681719278 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 12885689920 ps |
| CPU time | 2601.15 seconds |
| Started | Jul 13 08:12:36 PM PDT 24 |
| Finished | Jul 13 08:55:58 PM PDT 24 |
| Peak memory | 617968 kb |
| Host | smart-c7da9821-eb35-42ee-b39c-397276ad68d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1681719278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.1681719278 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1450189825 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 3707123684 ps |
| CPU time | 435.45 seconds |
| Started | Jul 13 08:11:35 PM PDT 24 |
| Finished | Jul 13 08:18:51 PM PDT 24 |
| Peak memory | 618228 kb |
| Host | smart-bca05701-b1c9-4cfa-a739-e456db083fb7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1450189825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.1450189825 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.2244817693 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 13267246900 ps |
| CPU time | 1549.24 seconds |
| Started | Jul 13 07:57:22 PM PDT 24 |
| Finished | Jul 13 08:23:13 PM PDT 24 |
| Peak memory | 606952 kb |
| Host | smart-f20a0989-6a08-4852-873f-3347541f0826 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244817693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.2 244817693 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.980350705 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 5501254406 ps |
| CPU time | 575.62 seconds |
| Started | Jul 13 08:04:33 PM PDT 24 |
| Finished | Jul 13 08:14:09 PM PDT 24 |
| Peak memory | 619472 kb |
| Host | smart-732cec8c-b4bb-454b-a081-b025a4c396cd |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9 80350705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.980350705 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.1523977608 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 3421488008 ps |
| CPU time | 319.27 seconds |
| Started | Jul 13 07:58:26 PM PDT 24 |
| Finished | Jul 13 08:03:46 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-4331c788-fe92-4ccf-9bb1-3bf00721f96f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1523977608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.1523977608 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.558313527 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 18910008644 ps |
| CPU time | 738.27 seconds |
| Started | Jul 13 08:01:17 PM PDT 24 |
| Finished | Jul 13 08:13:36 PM PDT 24 |
| Peak memory | 618532 kb |
| Host | smart-8e9c14fa-63e7-44d4-9e83-eabf04f746cc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=558313527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.558313527 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.1192237892 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 3130311618 ps |
| CPU time | 302.85 seconds |
| Started | Jul 13 08:01:58 PM PDT 24 |
| Finished | Jul 13 08:07:01 PM PDT 24 |
| Peak memory | 608688 kb |
| Host | smart-4d6783d8-397c-42a5-8443-0faf6e1186d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192237892 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.1192237892 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1070299549 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3233985453 ps |
| CPU time | 240.97 seconds |
| Started | Jul 13 08:01:08 PM PDT 24 |
| Finished | Jul 13 08:05:10 PM PDT 24 |
| Peak memory | 608688 kb |
| Host | smart-750b54cc-3413-4adb-8185-c0650d938c4c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070 299549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.1070299549 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1020958889 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 2650546052 ps |
| CPU time | 268.27 seconds |
| Started | Jul 13 08:05:17 PM PDT 24 |
| Finished | Jul 13 08:09:46 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-07566682-cb89-4fd5-8bf1-617d17e0922d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020958889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.1020958889 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.4247838740 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 2625967424 ps |
| CPU time | 251.13 seconds |
| Started | Jul 13 08:01:56 PM PDT 24 |
| Finished | Jul 13 08:06:08 PM PDT 24 |
| Peak memory | 608676 kb |
| Host | smart-b27df02a-dd5e-41e5-bd2b-f6255bdc0be5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247838740 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.4247838740 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.1685013622 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 2777567904 ps |
| CPU time | 298.32 seconds |
| Started | Jul 13 08:01:54 PM PDT 24 |
| Finished | Jul 13 08:06:53 PM PDT 24 |
| Peak memory | 608624 kb |
| Host | smart-2c611227-c102-4172-a515-4f2b9a1d0e7e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685013622 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.1685013622 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.1057810404 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 3567413425 ps |
| CPU time | 392.77 seconds |
| Started | Jul 13 08:03:20 PM PDT 24 |
| Finished | Jul 13 08:09:53 PM PDT 24 |
| Peak memory | 608732 kb |
| Host | smart-f641dbb2-986d-4c99-81fd-742928ef2357 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057810404 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.1057810404 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.938292317 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 3350916444 ps |
| CPU time | 302.65 seconds |
| Started | Jul 13 08:06:24 PM PDT 24 |
| Finished | Jul 13 08:11:28 PM PDT 24 |
| Peak memory | 609120 kb |
| Host | smart-73447682-2111-4b45-8664-be3ef874f062 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938292317 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.938292317 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.1539345009 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 4096107506 ps |
| CPU time | 451.06 seconds |
| Started | Jul 13 08:01:57 PM PDT 24 |
| Finished | Jul 13 08:09:28 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-f029b162-b5ab-4343-89f2-abb83e8e6b90 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1539345009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.1539345009 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.692265929 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 5602094530 ps |
| CPU time | 549.37 seconds |
| Started | Jul 13 08:03:44 PM PDT 24 |
| Finished | Jul 13 08:12:54 PM PDT 24 |
| Peak memory | 618804 kb |
| Host | smart-29f2d4ff-6035-4fcc-93b0-8f5edb55d9e2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=692265929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.692265929 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.579859542 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 8033655668 ps |
| CPU time | 1755.76 seconds |
| Started | Jul 13 08:02:28 PM PDT 24 |
| Finished | Jul 13 08:31:44 PM PDT 24 |
| Peak memory | 609636 kb |
| Host | smart-3d3529b1-67aa-4815-ae7f-a20260a18db1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=579859542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.579859542 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.4070888106 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 6870519472 ps |
| CPU time | 1864.46 seconds |
| Started | Jul 13 08:02:31 PM PDT 24 |
| Finished | Jul 13 08:33:36 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-77e7a5db-470a-4493-a43e-1963e09cf391 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070888106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.4070888106 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2846898520 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 3559528904 ps |
| CPU time | 400.4 seconds |
| Started | Jul 13 08:03:31 PM PDT 24 |
| Finished | Jul 13 08:10:12 PM PDT 24 |
| Peak memory | 648264 kb |
| Host | smart-9fa98bb0-dbf2-4cc8-967c-d4b0f5f2a7c0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846898520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_alert_handler_lpg_sleep_mode_alerts.2846898520 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1497392305 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 11215611180 ps |
| CPU time | 1498.06 seconds |
| Started | Jul 13 08:10:07 PM PDT 24 |
| Finished | Jul 13 08:35:06 PM PDT 24 |
| Peak memory | 610356 kb |
| Host | smart-d5619435-79d9-4903-9bc9-209c13774ad5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497392305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.1497392305 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.255473234 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 8292418080 ps |
| CPU time | 1438.93 seconds |
| Started | Jul 13 08:02:24 PM PDT 24 |
| Finished | Jul 13 08:26:23 PM PDT 24 |
| Peak memory | 609748 kb |
| Host | smart-9a2f5437-619b-46e2-8217-e1f4aa3eb36a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=255473234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.255473234 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.46752485 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 4043299822 ps |
| CPU time | 399.99 seconds |
| Started | Jul 13 08:01:35 PM PDT 24 |
| Finished | Jul 13 08:08:16 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-9cc2fdb4-9dad-4ace-ae56-4891de79f94e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=46752485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.46752485 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.115986997 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 255823788306 ps |
| CPU time | 13201.9 seconds |
| Started | Jul 13 08:02:21 PM PDT 24 |
| Finished | Jul 13 11:42:24 PM PDT 24 |
| Peak memory | 609952 kb |
| Host | smart-5c0f7f20-d7cb-4d94-8e60-8d09be411578 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=115986997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.115986997 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.3037331470 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 3233717144 ps |
| CPU time | 312.27 seconds |
| Started | Jul 13 08:02:25 PM PDT 24 |
| Finished | Jul 13 08:07:38 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-c336a270-a9de-44ec-b8ed-a9416fad4c47 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037331470 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.3037331470 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.2323291042 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 3294651948 ps |
| CPU time | 390.86 seconds |
| Started | Jul 13 08:01:29 PM PDT 24 |
| Finished | Jul 13 08:08:00 PM PDT 24 |
| Peak memory | 609348 kb |
| Host | smart-7261f5e3-d8e5-4ae3-93c2-3f4387c21edd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323291042 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.2323291042 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2992675696 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 7421230200 ps |
| CPU time | 455.21 seconds |
| Started | Jul 13 08:03:19 PM PDT 24 |
| Finished | Jul 13 08:10:55 PM PDT 24 |
| Peak memory | 608912 kb |
| Host | smart-3b8d5b02-6c5b-4d8d-b8b5-a21da750258c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2992675696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2992675696 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3874614845 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 2638277640 ps |
| CPU time | 323.28 seconds |
| Started | Jul 13 08:07:14 PM PDT 24 |
| Finished | Jul 13 08:12:38 PM PDT 24 |
| Peak memory | 608008 kb |
| Host | smart-a5ce8182-1894-4005-a661-b898979e1241 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874614845 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.3874614845 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2424939883 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 7716964786 ps |
| CPU time | 689.38 seconds |
| Started | Jul 13 08:00:55 PM PDT 24 |
| Finished | Jul 13 08:12:25 PM PDT 24 |
| Peak memory | 609964 kb |
| Host | smart-2a609696-1541-410f-8d79-902de28db334 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2424939883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.2424939883 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3091859397 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 5702770668 ps |
| CPU time | 749.37 seconds |
| Started | Jul 13 08:02:15 PM PDT 24 |
| Finished | Jul 13 08:14:45 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-22cd54b0-526b-446c-986d-d61f085d15df |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3091859397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.3091859397 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.3843313909 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 8139819720 ps |
| CPU time | 1189.63 seconds |
| Started | Jul 13 08:05:24 PM PDT 24 |
| Finished | Jul 13 08:25:14 PM PDT 24 |
| Peak memory | 616496 kb |
| Host | smart-2040f584-f719-425f-bfb2-2385bf90c587 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843313909 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.3843313909 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2319603427 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 17439514198 ps |
| CPU time | 2373.67 seconds |
| Started | Jul 13 08:05:30 PM PDT 24 |
| Finished | Jul 13 08:45:05 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-ab84be3c-585f-44d6-b6d1-1caa370f46ed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319603427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.2319603427 |
| Directory | /workspace/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3217724718 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 14149435884 ps |
| CPU time | 1239.4 seconds |
| Started | Jul 13 08:03:53 PM PDT 24 |
| Finished | Jul 13 08:24:33 PM PDT 24 |
| Peak memory | 622672 kb |
| Host | smart-53e8a504-6ff8-4620-aecb-a20810808d77 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3217724718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.3217724718 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.290761332 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 3867611704 ps |
| CPU time | 638.86 seconds |
| Started | Jul 13 08:03:29 PM PDT 24 |
| Finished | Jul 13 08:14:09 PM PDT 24 |
| Peak memory | 612376 kb |
| Host | smart-3ed3d29c-3c01-407e-8ac5-944792622854 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290761332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.290761332 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.47043952 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 4174760536 ps |
| CPU time | 612.23 seconds |
| Started | Jul 13 08:05:31 PM PDT 24 |
| Finished | Jul 13 08:15:43 PM PDT 24 |
| Peak memory | 612376 kb |
| Host | smart-4098da1f-91af-42f4-be88-04afe36fa635 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47043952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clk mgr_external_clk_src_for_sw_fast_rma.47043952 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.492894156 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 4483818568 ps |
| CPU time | 731.49 seconds |
| Started | Jul 13 08:04:47 PM PDT 24 |
| Finished | Jul 13 08:16:59 PM PDT 24 |
| Peak memory | 612084 kb |
| Host | smart-767b123f-5a96-49f9-85b5-d30939668a3d |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492894156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.492894156 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3174186252 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 4703910710 ps |
| CPU time | 596.58 seconds |
| Started | Jul 13 08:03:21 PM PDT 24 |
| Finished | Jul 13 08:13:19 PM PDT 24 |
| Peak memory | 612136 kb |
| Host | smart-92cd49d6-6ab5-42f7-8cf9-f7c38302018d |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174186252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.3174186252 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2384607277 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 4609752404 ps |
| CPU time | 667.94 seconds |
| Started | Jul 13 08:06:51 PM PDT 24 |
| Finished | Jul 13 08:18:00 PM PDT 24 |
| Peak memory | 611332 kb |
| Host | smart-26cbba81-c381-4290-958f-8074debf6874 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384607277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2384607277 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.711325053 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 4685843368 ps |
| CPU time | 654.19 seconds |
| Started | Jul 13 08:03:48 PM PDT 24 |
| Finished | Jul 13 08:14:43 PM PDT 24 |
| Peak memory | 612344 kb |
| Host | smart-a65e0eda-819c-426a-913a-8ee52b8d6960 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711325053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.711325053 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2114559353 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 2324605923 ps |
| CPU time | 371.48 seconds |
| Started | Jul 13 08:07:24 PM PDT 24 |
| Finished | Jul 13 08:13:36 PM PDT 24 |
| Peak memory | 607940 kb |
| Host | smart-cc7d6fd6-3803-4840-8680-423f0ae9b310 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114559353 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.2114559353 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3410068937 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 3545379980 ps |
| CPU time | 643.38 seconds |
| Started | Jul 13 08:04:06 PM PDT 24 |
| Finished | Jul 13 08:14:50 PM PDT 24 |
| Peak memory | 609220 kb |
| Host | smart-847395b1-f44b-49c0-b242-1732c468d495 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410068937 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.3410068937 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3436016606 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 2832819464 ps |
| CPU time | 254.43 seconds |
| Started | Jul 13 08:04:57 PM PDT 24 |
| Finished | Jul 13 08:09:12 PM PDT 24 |
| Peak memory | 608676 kb |
| Host | smart-db68fb3f-667a-4241-9765-cf33b97a604d |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436016606 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.3436016606 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2454457979 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 5300155782 ps |
| CPU time | 439.58 seconds |
| Started | Jul 13 08:04:23 PM PDT 24 |
| Finished | Jul 13 08:11:43 PM PDT 24 |
| Peak memory | 608492 kb |
| Host | smart-52fe046f-5aac-47de-a73f-f48540a9cdea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454457979 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.2454457979 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3049996350 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 4473107732 ps |
| CPU time | 531.73 seconds |
| Started | Jul 13 08:03:29 PM PDT 24 |
| Finished | Jul 13 08:12:21 PM PDT 24 |
| Peak memory | 609432 kb |
| Host | smart-a799e2e9-cd82-43d2-b687-318e16f35286 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049996350 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.3049996350 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2631663415 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 4500857182 ps |
| CPU time | 556.48 seconds |
| Started | Jul 13 08:04:08 PM PDT 24 |
| Finished | Jul 13 08:13:25 PM PDT 24 |
| Peak memory | 609504 kb |
| Host | smart-60b4d886-6b69-4360-b351-3df6de3969be |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631663415 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.2631663415 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.4027240697 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 4735447320 ps |
| CPU time | 424.71 seconds |
| Started | Jul 13 08:04:31 PM PDT 24 |
| Finished | Jul 13 08:11:37 PM PDT 24 |
| Peak memory | 609748 kb |
| Host | smart-7484c7c7-396e-45f4-92b3-6b580968f2e2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027240697 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.4027240697 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3071853157 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 9919167420 ps |
| CPU time | 1405.03 seconds |
| Started | Jul 13 08:03:52 PM PDT 24 |
| Finished | Jul 13 08:27:17 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-3c54f297-4445-4f0e-b68d-23fea97972c3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071853157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.3071853157 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3812343725 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 3605646562 ps |
| CPU time | 402.36 seconds |
| Started | Jul 13 08:06:59 PM PDT 24 |
| Finished | Jul 13 08:13:42 PM PDT 24 |
| Peak memory | 608748 kb |
| Host | smart-93c2f8bf-a5aa-4e93-9c36-d7d1957cccf0 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812343725 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.3812343725 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1016921842 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 4580498216 ps |
| CPU time | 728.39 seconds |
| Started | Jul 13 08:05:31 PM PDT 24 |
| Finished | Jul 13 08:17:40 PM PDT 24 |
| Peak memory | 609540 kb |
| Host | smart-ae458562-14d8-4276-affe-013ffa447f82 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016921842 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.1016921842 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2748712904 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 2905385104 ps |
| CPU time | 327.96 seconds |
| Started | Jul 13 08:06:59 PM PDT 24 |
| Finished | Jul 13 08:12:27 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-4235a0b1-cc03-420d-a303-b3f6e70e34b9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748712904 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.2748712904 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1167338461 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 20052444710 ps |
| CPU time | 5388.57 seconds |
| Started | Jul 13 08:02:29 PM PDT 24 |
| Finished | Jul 13 09:32:19 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-724eff0a-86b5-400e-b892-1bb538474d6a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167338461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.1167338461 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2127909277 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 113780638058 ps |
| CPU time | 17214 seconds |
| Started | Jul 13 08:05:27 PM PDT 24 |
| Finished | Jul 14 12:52:23 AM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-69e633d4-7451-4d60-90b7-58350bc42fd6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2127909277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.2127909277 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3696937169 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 5509513800 ps |
| CPU time | 437.39 seconds |
| Started | Jul 13 08:01:48 PM PDT 24 |
| Finished | Jul 13 08:09:06 PM PDT 24 |
| Peak memory | 609004 kb |
| Host | smart-ea665643-40a4-48b2-80e2-662036bd4369 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36969 37169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.3696937169 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.108112945 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 3152254312 ps |
| CPU time | 306.31 seconds |
| Started | Jul 13 08:02:54 PM PDT 24 |
| Finished | Jul 13 08:08:01 PM PDT 24 |
| Peak memory | 608692 kb |
| Host | smart-8756710f-8cd1-4c65-aab0-4709da55f26f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108112945 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.108112945 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.757290059 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 6012325035 ps |
| CPU time | 721.2 seconds |
| Started | Jul 13 08:02:37 PM PDT 24 |
| Finished | Jul 13 08:14:39 PM PDT 24 |
| Peak memory | 610708 kb |
| Host | smart-2f6ed871-92d7-429c-9c28-767d2a98cb56 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757290059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrn g_lc_hw_debug_en_test.757290059 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.2107580109 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 2851294104 ps |
| CPU time | 234.94 seconds |
| Started | Jul 13 08:07:49 PM PDT 24 |
| Finished | Jul 13 08:11:45 PM PDT 24 |
| Peak memory | 608528 kb |
| Host | smart-c9921759-ea4a-4f5a-81a7-c75946c8e003 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107580109 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.2107580109 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.2886774821 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 3400298964 ps |
| CPU time | 743.14 seconds |
| Started | Jul 13 08:01:38 PM PDT 24 |
| Finished | Jul 13 08:14:01 PM PDT 24 |
| Peak memory | 608368 kb |
| Host | smart-719efe8c-5b51-4f52-8910-1c3cbda1dd0c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886774821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ boot_mode.2886774821 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3744373172 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 7020565554 ps |
| CPU time | 1399.41 seconds |
| Started | Jul 13 08:02:05 PM PDT 24 |
| Finished | Jul 13 08:25:25 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-6171a1bf-c00f-4703-a045-5f9d606dea61 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3744373172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.3744373172 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2304558000 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 6134030589 ps |
| CPU time | 859.54 seconds |
| Started | Jul 13 08:03:04 PM PDT 24 |
| Finished | Jul 13 08:17:24 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-3500155d-17bb-4682-95a3-accbf0b8255a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304558000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.2304558000 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.994482509 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 3475524166 ps |
| CPU time | 622.5 seconds |
| Started | Jul 13 08:02:38 PM PDT 24 |
| Finished | Jul 13 08:13:01 PM PDT 24 |
| Peak memory | 616000 kb |
| Host | smart-53efed86-1001-48b8-981a-3ab57a16fe0e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994482509 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_edn_kat.994482509 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.1471424083 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 10306990424 ps |
| CPU time | 2360.63 seconds |
| Started | Jul 13 08:02:12 PM PDT 24 |
| Finished | Jul 13 08:41:34 PM PDT 24 |
| Peak memory | 608704 kb |
| Host | smart-8a91a581-5ca5-43be-83db-7fb3cfd3a480 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471424083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.1471424083 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.886726745 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 3108691352 ps |
| CPU time | 254.89 seconds |
| Started | Jul 13 08:01:33 PM PDT 24 |
| Finished | Jul 13 08:05:48 PM PDT 24 |
| Peak memory | 608692 kb |
| Host | smart-79557f87-1bba-456b-98c6-264b6c6287e3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88 6726745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.886726745 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.484480052 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 6470704580 ps |
| CPU time | 1349.11 seconds |
| Started | Jul 13 08:02:57 PM PDT 24 |
| Finished | Jul 13 08:25:27 PM PDT 24 |
| Peak memory | 608848 kb |
| Host | smart-8951d58a-fe5d-4382-86a5-fc7bab8dbad1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=484480052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.484480052 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2787225452 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 2629667300 ps |
| CPU time | 206.24 seconds |
| Started | Jul 13 08:10:28 PM PDT 24 |
| Finished | Jul 13 08:13:55 PM PDT 24 |
| Peak memory | 608644 kb |
| Host | smart-642aaf8d-f41b-4dc3-9194-7add7e1337ac |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787225452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.2787225452 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2735975519 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 4173295840 ps |
| CPU time | 590.37 seconds |
| Started | Jul 13 08:05:55 PM PDT 24 |
| Finished | Jul 13 08:15:46 PM PDT 24 |
| Peak memory | 608696 kb |
| Host | smart-6932c7dd-235e-4887-8dcc-b84f755182f4 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2735975519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.2735975519 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.1786592563 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 3394929880 ps |
| CPU time | 315.67 seconds |
| Started | Jul 13 07:58:50 PM PDT 24 |
| Finished | Jul 13 08:04:06 PM PDT 24 |
| Peak memory | 609052 kb |
| Host | smart-41aea040-9f64-4e7c-be22-a449a38c5c38 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786592563 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.1786592563 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.4272657630 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 3252056528 ps |
| CPU time | 236.35 seconds |
| Started | Jul 13 07:57:29 PM PDT 24 |
| Finished | Jul 13 08:01:26 PM PDT 24 |
| Peak memory | 607880 kb |
| Host | smart-60bd890f-a6fe-4360-820f-4d43faf7483e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272657630 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.4272657630 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.3474269579 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 2278670048 ps |
| CPU time | 214.5 seconds |
| Started | Jul 13 07:59:01 PM PDT 24 |
| Finished | Jul 13 08:02:36 PM PDT 24 |
| Peak memory | 608696 kb |
| Host | smart-9c7821a5-924f-4857-b1dc-f3361f0d7271 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474269579 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.3474269579 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.2030470310 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 2960874858 ps |
| CPU time | 133.86 seconds |
| Started | Jul 13 07:56:43 PM PDT 24 |
| Finished | Jul 13 07:58:58 PM PDT 24 |
| Peak memory | 609340 kb |
| Host | smart-39ac17a3-6981-4b1a-a956-b5f80f6a0081 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030470310 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.2030470310 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1241588156 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 58565676703 ps |
| CPU time | 10012.5 seconds |
| Started | Jul 13 07:59:26 PM PDT 24 |
| Finished | Jul 13 10:46:20 PM PDT 24 |
| Peak memory | 624188 kb |
| Host | smart-2349216c-0ffc-498f-9516-6ecc2d922d28 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1241588156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.1241588156 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.2112381636 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 4610933992 ps |
| CPU time | 788.49 seconds |
| Started | Jul 13 08:05:06 PM PDT 24 |
| Finished | Jul 13 08:18:15 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-531b93db-a77b-4baa-bc72-f28daa9da753 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2112381636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.2112381636 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.1591414589 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 5296209180 ps |
| CPU time | 1006.21 seconds |
| Started | Jul 13 08:00:29 PM PDT 24 |
| Finished | Jul 13 08:17:16 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-2021c9be-9be9-4b0c-9fd9-088765c7cb40 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591414589 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.1591414589 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2601919621 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 5689438572 ps |
| CPU time | 1010.5 seconds |
| Started | Jul 13 08:02:45 PM PDT 24 |
| Finished | Jul 13 08:19:36 PM PDT 24 |
| Peak memory | 608676 kb |
| Host | smart-7f7f3163-6951-4bb8-a9ae-40adf8da4cca |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601919621 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.2601919621 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4291634901 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 7574324666 ps |
| CPU time | 1287.69 seconds |
| Started | Jul 13 08:07:53 PM PDT 24 |
| Finished | Jul 13 08:29:22 PM PDT 24 |
| Peak memory | 608704 kb |
| Host | smart-35f134c1-2679-4842-806d-7cac5d6ce930 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291634901 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4291634901 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2245080529 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 6121353165 ps |
| CPU time | 1349.65 seconds |
| Started | Jul 13 08:00:59 PM PDT 24 |
| Finished | Jul 13 08:23:30 PM PDT 24 |
| Peak memory | 609432 kb |
| Host | smart-7989fbe9-ef57-4db8-99f0-dcf00aa9b228 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245080529 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.2245080529 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.634566691 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 4141184072 ps |
| CPU time | 412.05 seconds |
| Started | Jul 13 08:02:50 PM PDT 24 |
| Finished | Jul 13 08:09:43 PM PDT 24 |
| Peak memory | 609148 kb |
| Host | smart-6eeb5707-c587-4d3b-9c0c-bb7a1640de73 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634566691 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.634566691 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2142402031 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 3843896994 ps |
| CPU time | 463.58 seconds |
| Started | Jul 13 08:00:02 PM PDT 24 |
| Finished | Jul 13 08:07:46 PM PDT 24 |
| Peak memory | 608820 kb |
| Host | smart-c29fae55-bbfe-4036-93c8-cf5cedb07df1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21 42402031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.2142402031 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1497984838 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 5261559662 ps |
| CPU time | 1193 seconds |
| Started | Jul 13 08:07:14 PM PDT 24 |
| Finished | Jul 13 08:27:08 PM PDT 24 |
| Peak memory | 609460 kb |
| Host | smart-fde19303-9676-4c9e-befe-28bb9dc65a38 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497984838 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.1497984838 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.530642830 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 3871229782 ps |
| CPU time | 667.24 seconds |
| Started | Jul 13 08:00:47 PM PDT 24 |
| Finished | Jul 13 08:11:55 PM PDT 24 |
| Peak memory | 609540 kb |
| Host | smart-de8c91b3-fb40-4637-826c-69c421ae0cc2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530642830 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.530642830 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.578928673 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 4176975669 ps |
| CPU time | 687.52 seconds |
| Started | Jul 13 07:59:31 PM PDT 24 |
| Finished | Jul 13 08:11:00 PM PDT 24 |
| Peak memory | 609520 kb |
| Host | smart-512d30cf-bf2d-41bf-8697-99f045f3b7b6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=578928673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.578928673 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3836589672 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 5005671913 ps |
| CPU time | 908.29 seconds |
| Started | Jul 13 08:05:41 PM PDT 24 |
| Finished | Jul 13 08:20:49 PM PDT 24 |
| Peak memory | 608640 kb |
| Host | smart-8bf85b1d-4d10-46b0-ade3-a11cb63ea4f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3836589672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3836589672 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.601793084 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 3082368874 ps |
| CPU time | 331.08 seconds |
| Started | Jul 13 08:04:39 PM PDT 24 |
| Finished | Jul 13 08:10:10 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-e2cdc1fa-2780-4c36-bbc6-c794b1265d85 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6017930 84 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.601793084 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.1046890906 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 18134953472 ps |
| CPU time | 2080.38 seconds |
| Started | Jul 13 08:01:25 PM PDT 24 |
| Finished | Jul 13 08:36:08 PM PDT 24 |
| Peak memory | 611724 kb |
| Host | smart-60d5be22-6463-4654-af1c-481d2b94a0f9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046890906 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.1046890906 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.131462342 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 26474658437 ps |
| CPU time | 1811.68 seconds |
| Started | Jul 13 08:04:38 PM PDT 24 |
| Finished | Jul 13 08:34:50 PM PDT 24 |
| Peak memory | 612996 kb |
| Host | smart-ee5a511e-3597-4ace-a6b6-3c7bbd2aff4d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=131462342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.131462342 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1707376933 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 3016464248 ps |
| CPU time | 262.66 seconds |
| Started | Jul 13 08:09:07 PM PDT 24 |
| Finished | Jul 13 08:13:30 PM PDT 24 |
| Peak memory | 609044 kb |
| Host | smart-69be0cc4-80ee-4824-8779-c480fa92f2f5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1707376933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.1707376933 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.1687912440 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 2802909784 ps |
| CPU time | 311.79 seconds |
| Started | Jul 13 08:03:13 PM PDT 24 |
| Finished | Jul 13 08:08:25 PM PDT 24 |
| Peak memory | 608628 kb |
| Host | smart-8a1f30fb-d244-4cfc-8b67-5e6b235861a4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687912440 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.1687912440 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.2159409409 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 3607706454 ps |
| CPU time | 282.41 seconds |
| Started | Jul 13 08:02:30 PM PDT 24 |
| Finished | Jul 13 08:07:13 PM PDT 24 |
| Peak memory | 609148 kb |
| Host | smart-8613bdcb-9986-4ea6-a117-b4a8da8cfb8e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159409409 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.2159409409 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.2074043002 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 2272247276 ps |
| CPU time | 228.58 seconds |
| Started | Jul 13 08:02:44 PM PDT 24 |
| Finished | Jul 13 08:06:34 PM PDT 24 |
| Peak memory | 608956 kb |
| Host | smart-66743953-fd00-494c-b4b4-3cc693f5be6f |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074043002 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.2074043002 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3787727890 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 3179814113 ps |
| CPU time | 328.51 seconds |
| Started | Jul 13 08:07:06 PM PDT 24 |
| Finished | Jul 13 08:12:35 PM PDT 24 |
| Peak memory | 608696 kb |
| Host | smart-fc29ec33-9ad6-45a2-b27e-280ec73693be |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787727890 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.3787727890 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.1282221226 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 8188095148 ps |
| CPU time | 2209.57 seconds |
| Started | Jul 13 08:03:16 PM PDT 24 |
| Finished | Jul 13 08:40:06 PM PDT 24 |
| Peak memory | 609576 kb |
| Host | smart-808c1e07-d1d6-40de-ac03-dd09610722fd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282221226 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_multistream.1282221226 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.303669058 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 3487778840 ps |
| CPU time | 349.57 seconds |
| Started | Jul 13 08:02:58 PM PDT 24 |
| Finished | Jul 13 08:08:48 PM PDT 24 |
| Peak memory | 609072 kb |
| Host | smart-d8f9bab2-feb3-4bd2-931f-04e44e2dc062 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303669058 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.303669058 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.2120407952 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 3505757476 ps |
| CPU time | 356.91 seconds |
| Started | Jul 13 08:07:02 PM PDT 24 |
| Finished | Jul 13 08:12:59 PM PDT 24 |
| Peak memory | 609088 kb |
| Host | smart-c9a8198a-80cf-4888-856b-2b6faaab50fc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120407952 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.2120407952 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3056800667 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 3839118730 ps |
| CPU time | 642.45 seconds |
| Started | Jul 13 08:02:13 PM PDT 24 |
| Finished | Jul 13 08:12:57 PM PDT 24 |
| Peak memory | 609260 kb |
| Host | smart-f09b0a9a-5500-4208-9f85-754f69358ff1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056800667 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.3056800667 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1642632194 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 4879407440 ps |
| CPU time | 1077.31 seconds |
| Started | Jul 13 08:01:19 PM PDT 24 |
| Finished | Jul 13 08:19:19 PM PDT 24 |
| Peak memory | 608808 kb |
| Host | smart-b367e6af-b709-4dbf-8ba8-88685679c855 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642632194 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.1642632194 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.270087718 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 5405593194 ps |
| CPU time | 925.38 seconds |
| Started | Jul 13 07:59:42 PM PDT 24 |
| Finished | Jul 13 08:15:08 PM PDT 24 |
| Peak memory | 608604 kb |
| Host | smart-4a269bd4-ceab-4a25-8d8d-199a08d02679 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270087718 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.270087718 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.2014377868 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 65431796908 ps |
| CPU time | 11346.9 seconds |
| Started | Jul 13 07:58:55 PM PDT 24 |
| Finished | Jul 13 11:08:03 PM PDT 24 |
| Peak memory | 624192 kb |
| Host | smart-d9a79132-a290-4389-ac13-5b28d6b1479c |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2014377868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.2014377868 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.820133223 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 8725532568 ps |
| CPU time | 1726.8 seconds |
| Started | Jul 13 08:03:46 PM PDT 24 |
| Finished | Jul 13 08:32:34 PM PDT 24 |
| Peak memory | 615928 kb |
| Host | smart-0efa46c3-51c2-485f-b837-c4658f170a25 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8201 33223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.820133223 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3484335934 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 8237947829 ps |
| CPU time | 1563.1 seconds |
| Started | Jul 13 08:03:28 PM PDT 24 |
| Finished | Jul 13 08:29:32 PM PDT 24 |
| Peak memory | 617228 kb |
| Host | smart-efc7af91-d617-4112-a460-8490923ad2b7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3484335934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.3484335934 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4141287913 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 11501896051 ps |
| CPU time | 1831.58 seconds |
| Started | Jul 13 08:05:04 PM PDT 24 |
| Finished | Jul 13 08:35:36 PM PDT 24 |
| Peak memory | 617276 kb |
| Host | smart-7e2360a2-8d82-4f8a-b807-43a18cb58ad2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4141287913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.4141287913 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2727461480 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 13458516000 ps |
| CPU time | 2509.34 seconds |
| Started | Jul 13 08:04:19 PM PDT 24 |
| Finished | Jul 13 08:46:09 PM PDT 24 |
| Peak memory | 617036 kb |
| Host | smart-ed64c9b0-d453-44c5-af1e-4d6d2734784a |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2727461480 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.2727461480 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1303279779 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 11135258560 ps |
| CPU time | 2813 seconds |
| Started | Jul 13 08:04:05 PM PDT 24 |
| Finished | Jul 13 08:51:00 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-46150675-0778-4f7d-81b2-6a7fce9dda16 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130327 9779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.1303279779 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.866616319 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 18177707364 ps |
| CPU time | 4630.74 seconds |
| Started | Jul 13 08:04:07 PM PDT 24 |
| Finished | Jul 13 09:21:20 PM PDT 24 |
| Peak memory | 610412 kb |
| Host | smart-16a358d0-1da1-40e2-baa5-c2f4bbd1b4df |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86661 6319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.866616319 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.112626018 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 2995428676 ps |
| CPU time | 281.17 seconds |
| Started | Jul 13 08:04:42 PM PDT 24 |
| Finished | Jul 13 08:09:24 PM PDT 24 |
| Peak memory | 609292 kb |
| Host | smart-7efc43bc-a267-4040-b4bc-8ce31820892c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112626018 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_kmac_app_rom.112626018 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.3036961571 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 2110355922 ps |
| CPU time | 199.71 seconds |
| Started | Jul 13 07:59:34 PM PDT 24 |
| Finished | Jul 13 08:02:54 PM PDT 24 |
| Peak memory | 609152 kb |
| Host | smart-4b05d867-a616-41f7-9b79-4a3c6a346d35 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036961571 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.3036961571 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.3222275037 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 2517320608 ps |
| CPU time | 244.86 seconds |
| Started | Jul 13 08:03:31 PM PDT 24 |
| Finished | Jul 13 08:07:36 PM PDT 24 |
| Peak memory | 609112 kb |
| Host | smart-1b418d0a-2ddb-4407-a62d-1e62abe7bbfe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222275037 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.3222275037 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.902516780 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 2906315566 ps |
| CPU time | 278.06 seconds |
| Started | Jul 13 08:02:55 PM PDT 24 |
| Finished | Jul 13 08:07:34 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-a0633853-019b-4260-a134-e4600e38654d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902516780 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_kmac_mode_cshake.902516780 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.4162091399 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 3239482016 ps |
| CPU time | 311.15 seconds |
| Started | Jul 13 08:04:32 PM PDT 24 |
| Finished | Jul 13 08:09:44 PM PDT 24 |
| Peak memory | 607944 kb |
| Host | smart-ed844b44-67ac-448d-a49d-256eebdf54d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162091399 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.4162091399 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.891272185 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 3464790106 ps |
| CPU time | 365.46 seconds |
| Started | Jul 13 08:02:50 PM PDT 24 |
| Finished | Jul 13 08:08:56 PM PDT 24 |
| Peak memory | 609124 kb |
| Host | smart-7a35879d-22b4-433a-8200-cce788fb9deb |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891272185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.891272185 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1154407856 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 3795023125 ps |
| CPU time | 290.27 seconds |
| Started | Jul 13 08:05:08 PM PDT 24 |
| Finished | Jul 13 08:09:59 PM PDT 24 |
| Peak memory | 608692 kb |
| Host | smart-a615a5c7-34c1-4968-b8f4-9a462fab2b14 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11544078 56 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1154407856 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.2681420888 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 3676242548 ps |
| CPU time | 346.21 seconds |
| Started | Jul 13 08:09:05 PM PDT 24 |
| Finished | Jul 13 08:14:52 PM PDT 24 |
| Peak memory | 609124 kb |
| Host | smart-7023896d-ef68-40f3-a6d5-7e07baa80936 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681420888 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.2681420888 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.224435043 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 2632465560 ps |
| CPU time | 311.75 seconds |
| Started | Jul 13 08:00:08 PM PDT 24 |
| Finished | Jul 13 08:05:21 PM PDT 24 |
| Peak memory | 609220 kb |
| Host | smart-d293f7e5-19d2-4e0b-a242-1d0596488a34 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224435043 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.224435043 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1341545375 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 4470432490 ps |
| CPU time | 536.82 seconds |
| Started | Jul 13 08:06:25 PM PDT 24 |
| Finished | Jul 13 08:15:22 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-03de6758-e46d-4eb7-b88c-29481704e333 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1341545375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.1341545375 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.423890903 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 3533041773 ps |
| CPU time | 240.17 seconds |
| Started | Jul 13 07:59:35 PM PDT 24 |
| Finished | Jul 13 08:03:36 PM PDT 24 |
| Peak memory | 620940 kb |
| Host | smart-ac48cb83-6c3b-4d07-87d2-a8e5fb6bbb18 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42389090 3 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.423890903 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2469574060 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 5799178494 ps |
| CPU time | 412.79 seconds |
| Started | Jul 13 08:00:31 PM PDT 24 |
| Finished | Jul 13 08:07:25 PM PDT 24 |
| Peak memory | 620880 kb |
| Host | smart-3c293381-894a-42d8-8096-b7171f7fcdb7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469574060 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.2469574060 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.811838429 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 2449746975 ps |
| CPU time | 110.68 seconds |
| Started | Jul 13 08:00:01 PM PDT 24 |
| Finished | Jul 13 08:01:52 PM PDT 24 |
| Peak memory | 617020 kb |
| Host | smart-7d28aee3-25d8-440e-bc29-7f169569582c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=811838429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.811838429 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2978112265 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 2893260779 ps |
| CPU time | 114.79 seconds |
| Started | Jul 13 08:01:53 PM PDT 24 |
| Finished | Jul 13 08:03:48 PM PDT 24 |
| Peak memory | 616440 kb |
| Host | smart-2cec2388-2f1f-4628-8679-621520a606df |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978112265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2978112265 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.28827209 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 50865603935 ps |
| CPU time | 5663.64 seconds |
| Started | Jul 13 08:01:36 PM PDT 24 |
| Finished | Jul 13 09:36:01 PM PDT 24 |
| Peak memory | 619696 kb |
| Host | smart-81edb32b-6e54-4d90-9fe1-f74eb8f860e5 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28827209 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_lc_walkthrough_prod.28827209 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.167980752 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 9523798840 ps |
| CPU time | 963.94 seconds |
| Started | Jul 13 08:01:07 PM PDT 24 |
| Finished | Jul 13 08:17:12 PM PDT 24 |
| Peak memory | 619148 kb |
| Host | smart-75dd648e-c1c5-442f-a8e4-666fc1bbe0a9 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=167980752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.167980752 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.708978313 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 29608237684 ps |
| CPU time | 2045.79 seconds |
| Started | Jul 13 08:01:44 PM PDT 24 |
| Finished | Jul 13 08:35:50 PM PDT 24 |
| Peak memory | 619492 kb |
| Host | smart-9abdd7c6-c6de-4d97-adba-9f444bf5a5c4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=708978313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testunl ocks.708978313 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1566321015 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 16564300256 ps |
| CPU time | 3949.91 seconds |
| Started | Jul 13 08:03:00 PM PDT 24 |
| Finished | Jul 13 09:08:51 PM PDT 24 |
| Peak memory | 609856 kb |
| Host | smart-eb08d324-d462-4ead-a589-7a081633df67 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1566321015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.1566321015 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.783867318 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 18733637528 ps |
| CPU time | 4051.28 seconds |
| Started | Jul 13 08:00:59 PM PDT 24 |
| Finished | Jul 13 09:08:31 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-0a8c1637-1a6c-44da-bc20-5440db7d4c80 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=783867318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.783867318 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.419932459 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 24798006729 ps |
| CPU time | 3930.39 seconds |
| Started | Jul 13 08:05:36 PM PDT 24 |
| Finished | Jul 13 09:11:07 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-6f094c50-6bf9-4404-b4ff-39d166af9df0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419932459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.419932459 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1605302892 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 3364451028 ps |
| CPU time | 609.04 seconds |
| Started | Jul 13 08:03:03 PM PDT 24 |
| Finished | Jul 13 08:13:14 PM PDT 24 |
| Peak memory | 609348 kb |
| Host | smart-862470d7-067e-4e0e-9066-10067109b7f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605302892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.1605302892 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.546345453 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 5269765504 ps |
| CPU time | 1038.95 seconds |
| Started | Jul 13 08:09:22 PM PDT 24 |
| Finished | Jul 13 08:26:41 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-a4727926-46e6-48dc-a9f7-17bdd9371dbf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=546345453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.546345453 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.1987619298 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 9348518152 ps |
| CPU time | 2100.79 seconds |
| Started | Jul 13 08:07:01 PM PDT 24 |
| Finished | Jul 13 08:42:03 PM PDT 24 |
| Peak memory | 609548 kb |
| Host | smart-7a1516ce-57f4-4a99-ac4e-272a068b5529 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987619298 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.1987619298 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.4252601385 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 3381587521 ps |
| CPU time | 293.12 seconds |
| Started | Jul 13 08:02:28 PM PDT 24 |
| Finished | Jul 13 08:07:21 PM PDT 24 |
| Peak memory | 608680 kb |
| Host | smart-7c1a0056-8472-4037-9b28-08c94817d457 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252601385 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.4252601385 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.895536664 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 6528259560 ps |
| CPU time | 1104.37 seconds |
| Started | Jul 13 08:01:22 PM PDT 24 |
| Finished | Jul 13 08:19:47 PM PDT 24 |
| Peak memory | 609688 kb |
| Host | smart-56668765-e569-41e4-b6c2-e3534fbfe76f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=895536664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.895536664 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2409755917 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 8824470434 ps |
| CPU time | 1387.46 seconds |
| Started | Jul 13 08:00:26 PM PDT 24 |
| Finished | Jul 13 08:23:34 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-4181b450-41a1-4edc-ac48-6195cdf6cfbe |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2409755917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.2409755917 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3582524329 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 6751184368 ps |
| CPU time | 1453.81 seconds |
| Started | Jul 13 08:00:11 PM PDT 24 |
| Finished | Jul 13 08:24:26 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-83acd707-6a2a-4edf-bb1f-fbb066e37084 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3582524329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.3582524329 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2960005371 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 4213171640 ps |
| CPU time | 666.06 seconds |
| Started | Jul 13 08:00:02 PM PDT 24 |
| Finished | Jul 13 08:11:08 PM PDT 24 |
| Peak memory | 608696 kb |
| Host | smart-0063f9a3-48e0-43a9-89d7-75f15fa357e6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2960005371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2960005371 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1963599004 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 2946733442 ps |
| CPU time | 244.14 seconds |
| Started | Jul 13 08:05:47 PM PDT 24 |
| Finished | Jul 13 08:09:51 PM PDT 24 |
| Peak memory | 609056 kb |
| Host | smart-dc73aeb4-66df-429e-916c-dd1c44ce0bf4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963599004 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.1963599004 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.2559872059 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2679857826 ps |
| CPU time | 260.82 seconds |
| Started | Jul 13 08:04:56 PM PDT 24 |
| Finished | Jul 13 08:09:21 PM PDT 24 |
| Peak memory | 612372 kb |
| Host | smart-8b808f5a-873a-4799-bf27-bb9a6399317f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559872059 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.2559872059 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.3193988836 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 3114610746 ps |
| CPU time | 420.08 seconds |
| Started | Jul 13 08:04:38 PM PDT 24 |
| Finished | Jul 13 08:11:39 PM PDT 24 |
| Peak memory | 609064 kb |
| Host | smart-f6bac070-ab8f-4b1a-8afa-56d658d4e553 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193988836 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.3193988836 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.2674078068 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 4261643230 ps |
| CPU time | 746.67 seconds |
| Started | Jul 13 08:04:37 PM PDT 24 |
| Finished | Jul 13 08:17:04 PM PDT 24 |
| Peak memory | 609400 kb |
| Host | smart-edd33efb-4351-4309-81ce-271da7dea0d5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674078068 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.2674078068 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.3051028271 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 10338168200 ps |
| CPU time | 620.91 seconds |
| Started | Jul 13 08:08:34 PM PDT 24 |
| Finished | Jul 13 08:18:56 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-07022d3e-82c4-4b4d-a7c1-8ff1fe2661d1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051028271 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.3051028271 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3611596048 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 9828734745 ps |
| CPU time | 1894.21 seconds |
| Started | Jul 13 08:02:24 PM PDT 24 |
| Finished | Jul 13 08:33:59 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-9cd8ffd2-d359-4f9d-9a97-f411b30f3585 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611 596048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.3611596048 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2901123822 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 29384072519 ps |
| CPU time | 2364.04 seconds |
| Started | Jul 13 08:05:14 PM PDT 24 |
| Finished | Jul 13 08:44:40 PM PDT 24 |
| Peak memory | 609512 kb |
| Host | smart-b08bce5b-89c7-44ed-b23f-a39ee6e9d852 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290 1123822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.2901123822 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3189991654 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 18775653156 ps |
| CPU time | 1743.25 seconds |
| Started | Jul 13 08:00:52 PM PDT 24 |
| Finished | Jul 13 08:29:56 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-e9c55f1c-a597-40bf-84b6-2a83f2e168d0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3189991654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3189991654 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1755163923 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 25083651566 ps |
| CPU time | 2160.42 seconds |
| Started | Jul 13 08:05:25 PM PDT 24 |
| Finished | Jul 13 08:41:26 PM PDT 24 |
| Peak memory | 610240 kb |
| Host | smart-c97976cb-44ea-4df7-a7c2-7cc8041c072a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1755163923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1755163923 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1620429941 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 10007196260 ps |
| CPU time | 585.56 seconds |
| Started | Jul 13 08:01:34 PM PDT 24 |
| Finished | Jul 13 08:11:20 PM PDT 24 |
| Peak memory | 609128 kb |
| Host | smart-1dbcd15d-1c95-4294-ae5c-20004876f48a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620429941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.1620429941 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2702494588 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 7704738088 ps |
| CPU time | 516.34 seconds |
| Started | Jul 13 08:07:47 PM PDT 24 |
| Finished | Jul 13 08:16:24 PM PDT 24 |
| Peak memory | 616764 kb |
| Host | smart-f2bcee99-7816-4747-b3da-13bfaed24ec0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2702494588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2702494588 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.192551147 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 7203175570 ps |
| CPU time | 389.83 seconds |
| Started | Jul 13 08:02:19 PM PDT 24 |
| Finished | Jul 13 08:08:49 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-682032dc-9ea1-43f1-bc93-d006bca61562 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192551147 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.192551147 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.4188064197 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 4129852770 ps |
| CPU time | 578.45 seconds |
| Started | Jul 13 08:01:11 PM PDT 24 |
| Finished | Jul 13 08:10:50 PM PDT 24 |
| Peak memory | 616204 kb |
| Host | smart-0984fca4-3761-42b3-9530-0721bef2dd9f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4188064197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.4188064197 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1278017044 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 13043079401 ps |
| CPU time | 1476.49 seconds |
| Started | Jul 13 08:01:58 PM PDT 24 |
| Finished | Jul 13 08:26:35 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-e590de21-9a3f-46b1-bc38-7f0dbaa4f7c0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278017044 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1278017044 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3812669046 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 6851538930 ps |
| CPU time | 405.08 seconds |
| Started | Jul 13 08:06:31 PM PDT 24 |
| Finished | Jul 13 08:13:17 PM PDT 24 |
| Peak memory | 609896 kb |
| Host | smart-72c5e8cc-a81f-4ba1-8a2f-497156ccc11f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812669046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3812669046 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3390820878 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 6681825500 ps |
| CPU time | 639.53 seconds |
| Started | Jul 13 08:02:05 PM PDT 24 |
| Finished | Jul 13 08:12:45 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-21eed765-a9b9-40de-b87c-48e6ed63cb46 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390820878 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.3390820878 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3542711612 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 29756399007 ps |
| CPU time | 2779.98 seconds |
| Started | Jul 13 08:00:09 PM PDT 24 |
| Finished | Jul 13 08:46:30 PM PDT 24 |
| Peak memory | 609664 kb |
| Host | smart-71aa9832-77b4-44cb-9bf8-4aee956897e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3542711612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3542711612 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2924498749 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 20517001940 ps |
| CPU time | 1373.98 seconds |
| Started | Jul 13 08:07:36 PM PDT 24 |
| Finished | Jul 13 08:30:31 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-b7252c70-e40c-4f67-9c4b-00771ff716c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2924498749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2924498749 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.695666635 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 29898163878 ps |
| CPU time | 2884.29 seconds |
| Started | Jul 13 08:07:37 PM PDT 24 |
| Finished | Jul 13 08:55:42 PM PDT 24 |
| Peak memory | 611120 kb |
| Host | smart-2714e9ba-dcaf-4af6-9b6c-8addbd5b5cdb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695666635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.695666635 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3801152592 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 6968244170 ps |
| CPU time | 599.49 seconds |
| Started | Jul 13 08:05:19 PM PDT 24 |
| Finished | Jul 13 08:15:20 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-4df4c8d3-1696-4613-b8e0-dd403db37ea2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3801152592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3801152592 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2318778911 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 3034099780 ps |
| CPU time | 221.57 seconds |
| Started | Jul 13 08:01:39 PM PDT 24 |
| Finished | Jul 13 08:05:21 PM PDT 24 |
| Peak memory | 609056 kb |
| Host | smart-3bb6490c-5ce9-4a16-8243-a2ec33c32818 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318778911 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.2318778911 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1958773649 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 4555760004 ps |
| CPU time | 472.07 seconds |
| Started | Jul 13 08:00:42 PM PDT 24 |
| Finished | Jul 13 08:08:34 PM PDT 24 |
| Peak memory | 615936 kb |
| Host | smart-b502219b-abbf-4068-a4f4-d7c8f464191d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1958773649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.1958773649 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1703471252 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 4983227376 ps |
| CPU time | 456.85 seconds |
| Started | Jul 13 08:04:17 PM PDT 24 |
| Finished | Jul 13 08:11:55 PM PDT 24 |
| Peak memory | 608692 kb |
| Host | smart-1c55e21b-e9de-4631-add8-952503ef6e79 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17034712 52 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1703471252 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1733856532 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 5913318836 ps |
| CPU time | 659.34 seconds |
| Started | Jul 13 08:04:24 PM PDT 24 |
| Finished | Jul 13 08:15:24 PM PDT 24 |
| Peak memory | 609944 kb |
| Host | smart-df24c5b9-623b-481f-a905-e88e16ece560 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1733856532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.1733856532 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1039445050 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 5528182024 ps |
| CPU time | 394.24 seconds |
| Started | Jul 13 08:05:59 PM PDT 24 |
| Finished | Jul 13 08:12:34 PM PDT 24 |
| Peak memory | 608784 kb |
| Host | smart-b854a53c-be3d-4892-91d1-bd2630006a39 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039445050 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.1039445050 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.359091346 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 7182353880 ps |
| CPU time | 908.14 seconds |
| Started | Jul 13 08:02:02 PM PDT 24 |
| Finished | Jul 13 08:17:11 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-152b178e-e430-4d15-8b25-9cb84a21d95f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359091346 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.359091346 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3173075696 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 4622629448 ps |
| CPU time | 551.85 seconds |
| Started | Jul 13 08:00:50 PM PDT 24 |
| Finished | Jul 13 08:10:03 PM PDT 24 |
| Peak memory | 609408 kb |
| Host | smart-13f495a8-a8f1-4a5f-984f-5bfdc619ee95 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173075696 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3173075696 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1128125798 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5897174880 ps |
| CPU time | 397.53 seconds |
| Started | Jul 13 08:09:38 PM PDT 24 |
| Finished | Jul 13 08:16:16 PM PDT 24 |
| Peak memory | 609620 kb |
| Host | smart-d9188eed-220f-4e76-a0c1-5785c92b9bd2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128125798 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.1128125798 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.457441815 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 4286575590 ps |
| CPU time | 504.54 seconds |
| Started | Jul 13 08:01:48 PM PDT 24 |
| Finished | Jul 13 08:10:13 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-b1ed816f-d37f-40ce-b50c-07849b8ff1c7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457 441815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.457441815 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1967277919 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 8355265566 ps |
| CPU time | 663.18 seconds |
| Started | Jul 13 08:03:35 PM PDT 24 |
| Finished | Jul 13 08:14:39 PM PDT 24 |
| Peak memory | 624104 kb |
| Host | smart-7e84374a-3b63-4a08-a2c1-891cc057ab8e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967277919 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.1967277919 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2418746253 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 12817774796 ps |
| CPU time | 1660 seconds |
| Started | Jul 13 08:00:30 PM PDT 24 |
| Finished | Jul 13 08:28:11 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-bf919cac-ad38-4226-a14b-2d3024b891ef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2418746253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.2418746253 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.966411694 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 4889343400 ps |
| CPU time | 771.3 seconds |
| Started | Jul 13 08:01:46 PM PDT 24 |
| Finished | Jul 13 08:14:38 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-bb2166c2-60a9-4c73-adbf-9e25d5b6252f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966411694 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_rstmgr_cpu_info.966411694 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2353722211 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 5784499090 ps |
| CPU time | 686.94 seconds |
| Started | Jul 13 07:57:44 PM PDT 24 |
| Finished | Jul 13 08:09:12 PM PDT 24 |
| Peak memory | 640684 kb |
| Host | smart-b882c76a-525d-4307-a87c-1a73c5eeb794 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2353722211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.2353722211 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2458604555 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 2125117290 ps |
| CPU time | 167.55 seconds |
| Started | Jul 13 08:05:57 PM PDT 24 |
| Finished | Jul 13 08:08:45 PM PDT 24 |
| Peak memory | 609028 kb |
| Host | smart-208815c1-98dc-4f64-887d-428bdf6a1368 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458604555 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.2458604555 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2822130964 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 3857031072 ps |
| CPU time | 389.74 seconds |
| Started | Jul 13 07:59:57 PM PDT 24 |
| Finished | Jul 13 08:06:27 PM PDT 24 |
| Peak memory | 609508 kb |
| Host | smart-56151310-7ad6-421e-9799-06f5f71cc709 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822130964 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.2822130964 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2446861037 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 3015041380 ps |
| CPU time | 246.97 seconds |
| Started | Jul 13 08:01:21 PM PDT 24 |
| Finished | Jul 13 08:05:30 PM PDT 24 |
| Peak memory | 609124 kb |
| Host | smart-378bd4ca-be86-43ad-aef2-bc09072a5c43 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446861037 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.2446861037 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.528661680 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 3709200040 ps |
| CPU time | 375.8 seconds |
| Started | Jul 13 08:04:36 PM PDT 24 |
| Finished | Jul 13 08:10:52 PM PDT 24 |
| Peak memory | 608704 kb |
| Host | smart-45cc676e-204c-4c87-aca5-579a6310021d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=528661680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.528661680 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1061241951 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2984805020 ps |
| CPU time | 244.21 seconds |
| Started | Jul 13 08:04:29 PM PDT 24 |
| Finished | Jul 13 08:08:34 PM PDT 24 |
| Peak memory | 609632 kb |
| Host | smart-63b26709-5cb1-48c1-b0e7-6db0f22c1ee7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061241951 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.1061241951 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3157042007 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 4623226660 ps |
| CPU time | 799.48 seconds |
| Started | Jul 13 08:01:25 PM PDT 24 |
| Finished | Jul 13 08:14:47 PM PDT 24 |
| Peak memory | 608200 kb |
| Host | smart-e7da017e-69e7-4b28-b406-e53f53c2b269 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31570 42007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.3157042007 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2819034836 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 5504392824 ps |
| CPU time | 1251.33 seconds |
| Started | Jul 13 08:03:29 PM PDT 24 |
| Finished | Jul 13 08:24:21 PM PDT 24 |
| Peak memory | 608684 kb |
| Host | smart-e0d2d9eb-b166-44b7-9629-686acb8fc375 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2819034836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.2819034836 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2770804565 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 6396897561 ps |
| CPU time | 734.04 seconds |
| Started | Jul 13 08:07:06 PM PDT 24 |
| Finished | Jul 13 08:19:21 PM PDT 24 |
| Peak memory | 623480 kb |
| Host | smart-13198d78-37fb-468b-b8dd-d60e13ec485b |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770804565 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.2770804565 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.401038393 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 5393413200 ps |
| CPU time | 463.12 seconds |
| Started | Jul 13 08:07:11 PM PDT 24 |
| Finished | Jul 13 08:14:54 PM PDT 24 |
| Peak memory | 619608 kb |
| Host | smart-3c493681-d099-4706-8309-4ed7cdb468a6 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401038393 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.401038393 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4009091792 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 4275669104 ps |
| CPU time | 401.12 seconds |
| Started | Jul 13 08:05:35 PM PDT 24 |
| Finished | Jul 13 08:12:17 PM PDT 24 |
| Peak memory | 619476 kb |
| Host | smart-a171ab74-bf1a-47fa-8fe9-7ef17b083182 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400909 1792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4009091792 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.94312805 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 3085882560 ps |
| CPU time | 285.84 seconds |
| Started | Jul 13 08:06:04 PM PDT 24 |
| Finished | Jul 13 08:10:50 PM PDT 24 |
| Peak memory | 609220 kb |
| Host | smart-9a125c49-8944-4915-ade9-ef44b7959447 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94312805 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_rv_plic_smoketest.94312805 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.1308948497 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 3008708280 ps |
| CPU time | 346.68 seconds |
| Started | Jul 13 08:00:50 PM PDT 24 |
| Finished | Jul 13 08:06:37 PM PDT 24 |
| Peak memory | 609084 kb |
| Host | smart-0dc8a710-2c3c-49b1-8386-276ccccb9c08 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308948497 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.1308948497 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.83163348 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 3740041062 ps |
| CPU time | 385.04 seconds |
| Started | Jul 13 08:08:48 PM PDT 24 |
| Finished | Jul 13 08:15:14 PM PDT 24 |
| Peak memory | 609208 kb |
| Host | smart-03202783-4aa1-4e1f-8c9c-7bac34ba76dc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83163348 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rv_timer_smoketest.83163348 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2420393806 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 3341890795 ps |
| CPU time | 297.74 seconds |
| Started | Jul 13 08:04:38 PM PDT 24 |
| Finished | Jul 13 08:09:37 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-d22f6a7a-4c06-4a2e-918b-7ef1370ef059 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420393 806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.2420393806 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.858351584 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5150672422 ps |
| CPU time | 491.43 seconds |
| Started | Jul 13 08:05:25 PM PDT 24 |
| Finished | Jul 13 08:13:38 PM PDT 24 |
| Peak memory | 609820 kb |
| Host | smart-83642a73-cacd-4abb-a62f-2208a88adaf6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858351584 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.858351584 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3221901551 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 8418681216 ps |
| CPU time | 1291.35 seconds |
| Started | Jul 13 07:58:55 PM PDT 24 |
| Finished | Jul 13 08:20:27 PM PDT 24 |
| Peak memory | 610044 kb |
| Host | smart-74a9e4da-dcba-420c-b3b1-4e5f16b5e0d2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221901551 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.3221901551 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.4077020614 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 7038726448 ps |
| CPU time | 713.23 seconds |
| Started | Jul 13 08:05:52 PM PDT 24 |
| Finished | Jul 13 08:17:46 PM PDT 24 |
| Peak memory | 609864 kb |
| Host | smart-5c771d76-73cf-4185-84fc-9d62f286a0fd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077020614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.4077020614 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.275384584 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 8886542830 ps |
| CPU time | 906.43 seconds |
| Started | Jul 13 08:03:09 PM PDT 24 |
| Finished | Jul 13 08:18:16 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-fa556369-29bd-4c53-a392-752129460485 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275384584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_ sram_ret_contents_scramble.275384584 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.1383763557 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 6303971520 ps |
| CPU time | 847.44 seconds |
| Started | Jul 13 08:00:36 PM PDT 24 |
| Finished | Jul 13 08:14:44 PM PDT 24 |
| Peak memory | 624312 kb |
| Host | smart-d1b7d3f7-cb08-4593-9221-166e83559b9c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383763557 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.1383763557 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2779606712 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4727420418 ps |
| CPU time | 501.68 seconds |
| Started | Jul 13 08:00:26 PM PDT 24 |
| Finished | Jul 13 08:08:48 PM PDT 24 |
| Peak memory | 624288 kb |
| Host | smart-b4529f9d-16fd-449d-9e17-5e2a598953ce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779606712 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.2779606712 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.770872986 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3543454975 ps |
| CPU time | 334.64 seconds |
| Started | Jul 13 07:59:22 PM PDT 24 |
| Finished | Jul 13 08:04:57 PM PDT 24 |
| Peak memory | 618788 kb |
| Host | smart-c5ab75ba-a42e-483e-9355-fa50dee7fc57 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770872986 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.770872986 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1248038361 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 6942546795 ps |
| CPU time | 884.4 seconds |
| Started | Jul 13 08:03:22 PM PDT 24 |
| Finished | Jul 13 08:18:07 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-07c176d4-235b-4ba6-9403-16a178db375c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248038361 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.1248038361 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3540201942 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 4254249120 ps |
| CPU time | 750.58 seconds |
| Started | Jul 13 08:03:50 PM PDT 24 |
| Finished | Jul 13 08:16:21 PM PDT 24 |
| Peak memory | 609728 kb |
| Host | smart-49de2006-8690-428c-8751-f1d78ac7e3a1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540201942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _sram_ctrl_scrambled_access.3540201942 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2012798358 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 4755206886 ps |
| CPU time | 620.88 seconds |
| Started | Jul 13 08:07:21 PM PDT 24 |
| Finished | Jul 13 08:17:42 PM PDT 24 |
| Peak memory | 610028 kb |
| Host | smart-c5cca621-c22f-4f89-8f09-02b6e5974659 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012798358 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2012798358 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2479993217 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 3160428914 ps |
| CPU time | 280.67 seconds |
| Started | Jul 13 08:07:46 PM PDT 24 |
| Finished | Jul 13 08:12:28 PM PDT 24 |
| Peak memory | 609120 kb |
| Host | smart-ff6d1e11-4710-4d15-b871-3f86799cd013 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479993217 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.2479993217 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3256883779 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 20733897586 ps |
| CPU time | 4472.42 seconds |
| Started | Jul 13 08:04:07 PM PDT 24 |
| Finished | Jul 13 09:18:41 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-8faa5986-32b6-4b84-bc4c-c4c7dd4fdc9e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256883779 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.3256883779 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1099126853 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 4232620110 ps |
| CPU time | 623.1 seconds |
| Started | Jul 13 08:01:05 PM PDT 24 |
| Finished | Jul 13 08:11:31 PM PDT 24 |
| Peak memory | 612856 kb |
| Host | smart-bc2a9eda-ec72-434b-9517-0b462c8028b4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099126853 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.1099126853 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.482579395 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 3414787684 ps |
| CPU time | 274.82 seconds |
| Started | Jul 13 08:01:03 PM PDT 24 |
| Finished | Jul 13 08:05:39 PM PDT 24 |
| Peak memory | 612432 kb |
| Host | smart-5c2753a1-3977-4c1f-b363-6a5226ded06e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482579395 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.482579395 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3112708879 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 3940437122 ps |
| CPU time | 453.9 seconds |
| Started | Jul 13 08:02:39 PM PDT 24 |
| Finished | Jul 13 08:10:15 PM PDT 24 |
| Peak memory | 608716 kb |
| Host | smart-4298ff7a-ca56-4f28-ac72-4541d6cd5155 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112708879 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.3112708879 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.820921547 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 6248070754 ps |
| CPU time | 566.95 seconds |
| Started | Jul 13 08:00:34 PM PDT 24 |
| Finished | Jul 13 08:10:02 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-995ab40d-931d-44e2-bdfb-cd627776de86 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820921547 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.820921547 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3304306025 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 12929938736 ps |
| CPU time | 3187.72 seconds |
| Started | Jul 13 08:00:07 PM PDT 24 |
| Finished | Jul 13 08:53:17 PM PDT 24 |
| Peak memory | 618264 kb |
| Host | smart-bd7a36a9-1dd1-4f50-a015-9abd9dc6b1a0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3304306025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.3304306025 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.4139982165 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 2738733864 ps |
| CPU time | 280.42 seconds |
| Started | Jul 13 08:06:07 PM PDT 24 |
| Finished | Jul 13 08:10:47 PM PDT 24 |
| Peak memory | 615184 kb |
| Host | smart-1bb92229-df84-496f-be59-8eb65b208069 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139982165 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.4139982165 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.3720842846 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 4547310792 ps |
| CPU time | 647.79 seconds |
| Started | Jul 13 07:58:46 PM PDT 24 |
| Finished | Jul 13 08:09:35 PM PDT 24 |
| Peak memory | 622196 kb |
| Host | smart-43716eaf-aecb-482f-9af7-6d0bafdfe91a |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720842846 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.3720842846 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.186380167 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 3998141828 ps |
| CPU time | 758.05 seconds |
| Started | Jul 13 07:59:17 PM PDT 24 |
| Finished | Jul 13 08:11:56 PM PDT 24 |
| Peak memory | 621616 kb |
| Host | smart-b5a5fcba-5291-4d50-80e8-f875ea7a9d09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186380167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_ alt_clk_freq.186380167 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3428410625 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 3853419380 ps |
| CPU time | 445.55 seconds |
| Started | Jul 13 07:59:03 PM PDT 24 |
| Finished | Jul 13 08:06:30 PM PDT 24 |
| Peak memory | 624152 kb |
| Host | smart-38d4a498-c737-4fc3-8a37-3ffd375606da |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428410625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3428410625 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3170674692 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 79058258776 ps |
| CPU time | 14471.3 seconds |
| Started | Jul 13 07:59:02 PM PDT 24 |
| Finished | Jul 14 12:00:16 AM PDT 24 |
| Peak memory | 634568 kb |
| Host | smart-9f919be6-f7ff-47c3-865a-ef4720ca820a |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3170674692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.3170674692 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2506381884 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 4928068622 ps |
| CPU time | 791.26 seconds |
| Started | Jul 13 07:59:08 PM PDT 24 |
| Finished | Jul 13 08:12:21 PM PDT 24 |
| Peak memory | 623520 kb |
| Host | smart-31b25d70-d669-4d71-bfb8-8e18dcae36c6 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506381884 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.2506381884 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1591540152 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 4477583860 ps |
| CPU time | 703.17 seconds |
| Started | Jul 13 07:58:07 PM PDT 24 |
| Finished | Jul 13 08:09:51 PM PDT 24 |
| Peak memory | 622064 kb |
| Host | smart-349dff02-2b82-4d39-a05a-12e275545c67 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591540152 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.1591540152 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.4065554171 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 4214931488 ps |
| CPU time | 648.64 seconds |
| Started | Jul 13 07:59:58 PM PDT 24 |
| Finished | Jul 13 08:10:48 PM PDT 24 |
| Peak memory | 623188 kb |
| Host | smart-2ca01abf-1a93-44f4-b8f2-01d0a6c88f99 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065554171 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.4065554171 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.2207186794 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 2251525110 ps |
| CPU time | 144 seconds |
| Started | Jul 13 08:04:17 PM PDT 24 |
| Finished | Jul 13 08:06:42 PM PDT 24 |
| Peak memory | 619844 kb |
| Host | smart-02a742e2-d9a7-44cf-a9eb-1c648cae30e7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2207186794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.2207186794 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.2970113208 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2354570986 ps |
| CPU time | 135.79 seconds |
| Started | Jul 13 08:05:16 PM PDT 24 |
| Finished | Jul 13 08:07:32 PM PDT 24 |
| Peak memory | 619436 kb |
| Host | smart-641f844c-bf36-48d8-8a66-8cefc4dfdbe1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970113208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.2970113208 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_rma.1883139744 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 8166798828 ps |
| CPU time | 822.01 seconds |
| Started | Jul 13 08:05:26 PM PDT 24 |
| Finished | Jul 13 08:19:08 PM PDT 24 |
| Peak memory | 620360 kb |
| Host | smart-a0753e88-5fcd-4da4-bdbe-8ff813f3cf5c |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883139744 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.1883139744 |
| Directory | /workspace/2.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_testunlock0.2172707840 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 6538062057 ps |
| CPU time | 628.64 seconds |
| Started | Jul 13 08:05:01 PM PDT 24 |
| Finished | Jul 13 08:15:30 PM PDT 24 |
| Peak memory | 620356 kb |
| Host | smart-d0b86cc4-aa71-4f42-bb1f-b12261028206 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2172707840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.2172707840 |
| Directory | /workspace/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.789990436 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 15793377960 ps |
| CPU time | 3643.76 seconds |
| Started | Jul 13 08:09:23 PM PDT 24 |
| Finished | Jul 13 09:10:07 PM PDT 24 |
| Peak memory | 610528 kb |
| Host | smart-a8208d09-7647-46a9-b192-ad5491333860 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789990436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rom_e2e_asm_init_dev.789990436 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.46406137 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 15191505618 ps |
| CPU time | 3776.7 seconds |
| Started | Jul 13 08:13:18 PM PDT 24 |
| Finished | Jul 13 09:16:15 PM PDT 24 |
| Peak memory | 609752 kb |
| Host | smart-9f100b46-7c8f-4920-918d-f7cb929962d8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46406137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rom_e2e_asm_init_prod.46406137 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2539277841 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 15430661792 ps |
| CPU time | 5196.57 seconds |
| Started | Jul 13 08:11:55 PM PDT 24 |
| Finished | Jul 13 09:38:33 PM PDT 24 |
| Peak memory | 610532 kb |
| Host | smart-2bbe22be-ffeb-4d62-8818-285dff1c2a27 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539277841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.2539277841 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.318771190 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 14993772336 ps |
| CPU time | 4148.51 seconds |
| Started | Jul 13 08:10:06 PM PDT 24 |
| Finished | Jul 13 09:19:16 PM PDT 24 |
| Peak memory | 609708 kb |
| Host | smart-102b2d04-b2d8-4c08-bced-b8d75652c4b3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318771190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rom_e2e_asm_init_rma.318771190 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.429836153 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 11499417107 ps |
| CPU time | 3034.05 seconds |
| Started | Jul 13 08:09:31 PM PDT 24 |
| Finished | Jul 13 09:00:05 PM PDT 24 |
| Peak memory | 609588 kb |
| Host | smart-80eb996a-4fe3-402e-9bfc-c330f93a220d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429836153 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.rom_e2e_asm_init_test_unlocked0.429836153 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1140698254 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 15380173066 ps |
| CPU time | 4084.02 seconds |
| Started | Jul 13 08:13:25 PM PDT 24 |
| Finished | Jul 13 09:21:30 PM PDT 24 |
| Peak memory | 609704 kb |
| Host | smart-d30b1bee-6621-4be0-ba3f-b2c290c4b4bf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140698254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in it_rom_ext_invalid_meas.1140698254 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.4223474772 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 14924047800 ps |
| CPU time | 3328.25 seconds |
| Started | Jul 13 08:10:37 PM PDT 24 |
| Finished | Jul 13 09:06:06 PM PDT 24 |
| Peak memory | 609876 kb |
| Host | smart-040dd9c1-fba8-45be-b2a3-0761010e173c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223474772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.4223474772 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1205499743 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 15597186376 ps |
| CPU time | 3646.23 seconds |
| Started | Jul 13 08:11:17 PM PDT 24 |
| Finished | Jul 13 09:12:04 PM PDT 24 |
| Peak memory | 609844 kb |
| Host | smart-d55808da-ea3e-4396-b81e-a4f48af62e16 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205499743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.1205499743 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2692556891 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 14231456304 ps |
| CPU time | 3383.91 seconds |
| Started | Jul 13 08:12:18 PM PDT 24 |
| Finished | Jul 13 09:08:42 PM PDT 24 |
| Peak memory | 610516 kb |
| Host | smart-8e101164-e4b2-43ac-9662-e59b3a3304fa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692556891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_ shutdown_exception_c.2692556891 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.1326311444 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 15025555120 ps |
| CPU time | 3677.81 seconds |
| Started | Jul 13 08:09:11 PM PDT 24 |
| Finished | Jul 13 09:10:30 PM PDT 24 |
| Peak memory | 609816 kb |
| Host | smart-8559585e-9514-4bfa-958e-33c319813d2a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1326311444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.1326311444 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.2028025667 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 17310578512 ps |
| CPU time | 4848 seconds |
| Started | Jul 13 08:13:19 PM PDT 24 |
| Finished | Jul 13 09:34:08 PM PDT 24 |
| Peak memory | 609832 kb |
| Host | smart-ad7d760d-d230-41df-996b-7463e8339afa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028025667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.2028025667 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.650906396 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 4875311500 ps |
| CPU time | 467.46 seconds |
| Started | Jul 13 08:05:50 PM PDT 24 |
| Finished | Jul 13 08:13:38 PM PDT 24 |
| Peak memory | 609896 kb |
| Host | smart-980440b3-8c3b-44ee-89e8-b86b46e12dd8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650906396 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.650906396 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_raw_unlock.2837934475 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 5818506120 ps |
| CPU time | 242.2 seconds |
| Started | Jul 13 08:06:12 PM PDT 24 |
| Finished | Jul 13 08:10:15 PM PDT 24 |
| Peak memory | 623176 kb |
| Host | smart-7de9c70d-c0af-468a-81ac-1a47b7715861 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2837934475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.2837934475 |
| Directory | /workspace/2.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.4241844468 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 2795620829 ps |
| CPU time | 150.68 seconds |
| Started | Jul 13 08:06:02 PM PDT 24 |
| Finished | Jul 13 08:08:34 PM PDT 24 |
| Peak memory | 617240 kb |
| Host | smart-68e35b6b-f1d7-4296-b045-f9b69e82c953 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241844468 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.4241844468 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3312478988 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 4406211728 ps |
| CPU time | 351.11 seconds |
| Started | Jul 13 08:11:47 PM PDT 24 |
| Finished | Jul 13 08:17:39 PM PDT 24 |
| Peak memory | 648400 kb |
| Host | smart-b286468b-387e-49f2-8b40-7b701c24d450 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312478988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3312478988 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.2532665132 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 5705246552 ps |
| CPU time | 639.67 seconds |
| Started | Jul 13 08:12:55 PM PDT 24 |
| Finished | Jul 13 08:23:35 PM PDT 24 |
| Peak memory | 649268 kb |
| Host | smart-913f4f75-3092-45a3-9eae-923fe90439af |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2532665132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.2532665132 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.1523227083 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 5797940360 ps |
| CPU time | 671.81 seconds |
| Started | Jul 13 08:12:54 PM PDT 24 |
| Finished | Jul 13 08:24:06 PM PDT 24 |
| Peak memory | 616260 kb |
| Host | smart-b771c699-c18f-4e05-ace6-9dd4ce4fed24 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1523227083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.1523227083 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.69367926 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 4546764480 ps |
| CPU time | 582.81 seconds |
| Started | Jul 13 08:11:52 PM PDT 24 |
| Finished | Jul 13 08:21:35 PM PDT 24 |
| Peak memory | 649496 kb |
| Host | smart-a3c15416-54b4-4af5-9fde-24f98857755d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 69367926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.69367926 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.4015862991 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 4312462056 ps |
| CPU time | 368.18 seconds |
| Started | Jul 13 08:12:42 PM PDT 24 |
| Finished | Jul 13 08:18:51 PM PDT 24 |
| Peak memory | 648228 kb |
| Host | smart-ee4f3de7-118b-429d-9a1d-369eb73a7c2d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015862991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4015862991 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.4177209072 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 4187507560 ps |
| CPU time | 601.31 seconds |
| Started | Jul 13 08:13:17 PM PDT 24 |
| Finished | Jul 13 08:23:19 PM PDT 24 |
| Peak memory | 649280 kb |
| Host | smart-b80bbfc7-6d9d-4280-8900-c7543966771e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4177209072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.4177209072 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.1133572614 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 4833790564 ps |
| CPU time | 604.49 seconds |
| Started | Jul 13 08:15:48 PM PDT 24 |
| Finished | Jul 13 08:25:53 PM PDT 24 |
| Peak memory | 649772 kb |
| Host | smart-18fdf578-6839-4603-af86-724893477edf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1133572614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.1133572614 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2919216960 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 3690044020 ps |
| CPU time | 453.18 seconds |
| Started | Jul 13 08:08:00 PM PDT 24 |
| Finished | Jul 13 08:15:34 PM PDT 24 |
| Peak memory | 648172 kb |
| Host | smart-0ac8d3ec-7929-4f87-95a7-86ce3548c18d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919216960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.2919216960 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.1687920245 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 6149517268 ps |
| CPU time | 767.95 seconds |
| Started | Jul 13 08:09:55 PM PDT 24 |
| Finished | Jul 13 08:22:44 PM PDT 24 |
| Peak memory | 649504 kb |
| Host | smart-a2fcc16d-60e7-4425-82d5-bd8f655fce80 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1687920245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.1687920245 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3245898102 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 7856262792 ps |
| CPU time | 555.13 seconds |
| Started | Jul 13 08:07:37 PM PDT 24 |
| Finished | Jul 13 08:16:53 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-51d93909-5116-47f4-b83e-83af07a0a938 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3245898102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3245898102 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.3622029359 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 18394125400 ps |
| CPU time | 5204.48 seconds |
| Started | Jul 13 08:07:16 PM PDT 24 |
| Finished | Jul 13 09:34:02 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-9eff1a73-ad3d-4258-adc6-f734311b02e6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622029359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.3622029359 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.225369456 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 5938591700 ps |
| CPU time | 581.12 seconds |
| Started | Jul 13 08:06:26 PM PDT 24 |
| Finished | Jul 13 08:16:08 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-8b99e73b-013f-4c92-bf79-78954580551f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=225369456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.225369456 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2049485414 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 10831288140 ps |
| CPU time | 1227.58 seconds |
| Started | Jul 13 08:06:51 PM PDT 24 |
| Finished | Jul 13 08:27:19 PM PDT 24 |
| Peak memory | 622628 kb |
| Host | smart-19c3e9ee-6fb1-4d2f-b872-9b6cdacc8ccb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049485414 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.2049485414 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3339774236 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 8746548200 ps |
| CPU time | 1286.03 seconds |
| Started | Jul 13 08:07:47 PM PDT 24 |
| Finished | Jul 13 08:29:14 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-9560558e-3ee4-4e54-8d8f-f9f27de534e3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33397742 36 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.3339774236 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.894597805 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 8189153134 ps |
| CPU time | 1590.88 seconds |
| Started | Jul 13 08:06:46 PM PDT 24 |
| Finished | Jul 13 08:33:18 PM PDT 24 |
| Peak memory | 618192 kb |
| Host | smart-1c805541-e183-4ccd-b89e-07db397f6b9b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=894597805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.894597805 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.1379908588 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 4340272932 ps |
| CPU time | 653.01 seconds |
| Started | Jul 13 08:06:24 PM PDT 24 |
| Finished | Jul 13 08:17:18 PM PDT 24 |
| Peak memory | 623180 kb |
| Host | smart-b3bbb255-89f4-46fc-b0a1-5922579333e1 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379908588 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.1379908588 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.73296645 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 3884308396 ps |
| CPU time | 630.52 seconds |
| Started | Jul 13 08:09:17 PM PDT 24 |
| Finished | Jul 13 08:19:48 PM PDT 24 |
| Peak memory | 621760 kb |
| Host | smart-1e7291b3-bae1-4073-b9f1-86aa870c236e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73296645 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_bau drate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_a lt_clk_freq.73296645 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.851994883 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 8194232544 ps |
| CPU time | 974.42 seconds |
| Started | Jul 13 08:07:10 PM PDT 24 |
| Finished | Jul 13 08:23:25 PM PDT 24 |
| Peak memory | 622716 kb |
| Host | smart-d510f143-019b-4ffb-82a2-d5c7708a2ab5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851994883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.851994883 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.381869817 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 3847450580 ps |
| CPU time | 533.94 seconds |
| Started | Jul 13 08:06:16 PM PDT 24 |
| Finished | Jul 13 08:15:11 PM PDT 24 |
| Peak memory | 623240 kb |
| Host | smart-a3a54aa5-4018-46f4-a076-96538b3e3119 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381869817 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.381869817 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3396585711 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 3705162752 ps |
| CPU time | 642.68 seconds |
| Started | Jul 13 08:06:35 PM PDT 24 |
| Finished | Jul 13 08:17:18 PM PDT 24 |
| Peak memory | 623316 kb |
| Host | smart-50630f65-aca8-43c5-9bd4-4ada77b9d275 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396585711 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.3396585711 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.549115190 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 4777102384 ps |
| CPU time | 590.71 seconds |
| Started | Jul 13 08:06:21 PM PDT 24 |
| Finished | Jul 13 08:16:13 PM PDT 24 |
| Peak memory | 623512 kb |
| Host | smart-82aaf03d-8bea-4d75-b02f-9f89ca8b436c |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549115190 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.549115190 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.1659669994 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 11934040602 ps |
| CPU time | 1418.95 seconds |
| Started | Jul 13 08:07:37 PM PDT 24 |
| Finished | Jul 13 08:31:17 PM PDT 24 |
| Peak memory | 620388 kb |
| Host | smart-10ad6fc5-9c3f-4291-a222-02f632e3d1b0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1659669994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.1659669994 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.2750057376 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 2891621315 ps |
| CPU time | 168.17 seconds |
| Started | Jul 13 08:06:24 PM PDT 24 |
| Finished | Jul 13 08:09:13 PM PDT 24 |
| Peak memory | 619852 kb |
| Host | smart-838ff6aa-e6a5-48c4-bff4-1b9ef17af1de |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750057376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.2750057376 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_testunlock0.2451410809 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 2399729855 ps |
| CPU time | 145.24 seconds |
| Started | Jul 13 08:06:22 PM PDT 24 |
| Finished | Jul 13 08:08:47 PM PDT 24 |
| Peak memory | 620008 kb |
| Host | smart-97491640-62f2-465b-a739-1ecf15f0b977 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2451410809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.2451410809 |
| Directory | /workspace/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3589718118 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 3623185900 ps |
| CPU time | 493.14 seconds |
| Started | Jul 13 08:12:26 PM PDT 24 |
| Finished | Jul 13 08:20:39 PM PDT 24 |
| Peak memory | 648244 kb |
| Host | smart-515bfa3c-a4cd-4835-b169-ab57da00e7b4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589718118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3589718118 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2407860021 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 4382473200 ps |
| CPU time | 428.4 seconds |
| Started | Jul 13 08:12:09 PM PDT 24 |
| Finished | Jul 13 08:19:18 PM PDT 24 |
| Peak memory | 648272 kb |
| Host | smart-493014d0-118a-40a2-9007-bff780c1705b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407860021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2407860021 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.892866470 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 3320320486 ps |
| CPU time | 466.38 seconds |
| Started | Jul 13 08:12:08 PM PDT 24 |
| Finished | Jul 13 08:19:55 PM PDT 24 |
| Peak memory | 647948 kb |
| Host | smart-1fbc7cde-87de-4f73-b944-06a3a4134648 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892866470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_s w_alert_handler_lpg_sleep_mode_alerts.892866470 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.393399238 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 5988588680 ps |
| CPU time | 671.84 seconds |
| Started | Jul 13 08:15:51 PM PDT 24 |
| Finished | Jul 13 08:27:04 PM PDT 24 |
| Peak memory | 649264 kb |
| Host | smart-006dfa15-d195-4a7e-b1ca-ccbc168e9fe2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 393399238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.393399238 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3606052604 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 4166222148 ps |
| CPU time | 404.26 seconds |
| Started | Jul 13 08:12:43 PM PDT 24 |
| Finished | Jul 13 08:19:27 PM PDT 24 |
| Peak memory | 647880 kb |
| Host | smart-43adbd47-68a9-45bc-aec2-f8a9959e923c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606052604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3606052604 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.115527434 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 4014065090 ps |
| CPU time | 447.67 seconds |
| Started | Jul 13 08:13:30 PM PDT 24 |
| Finished | Jul 13 08:20:58 PM PDT 24 |
| Peak memory | 648348 kb |
| Host | smart-26c8c08b-762c-4a00-951b-40320aced7d5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115527434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_s w_alert_handler_lpg_sleep_mode_alerts.115527434 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.969091766 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 4901620280 ps |
| CPU time | 580.35 seconds |
| Started | Jul 13 08:12:11 PM PDT 24 |
| Finished | Jul 13 08:21:51 PM PDT 24 |
| Peak memory | 616260 kb |
| Host | smart-fc5ed80b-747c-448e-acbc-fea30a3d0136 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 969091766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.969091766 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1290689302 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 4113101874 ps |
| CPU time | 376.42 seconds |
| Started | Jul 13 08:13:31 PM PDT 24 |
| Finished | Jul 13 08:19:47 PM PDT 24 |
| Peak memory | 648300 kb |
| Host | smart-6616896f-9a95-4a64-8cbb-0e5d0ed494c1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290689302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1290689302 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2349763287 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 4545403072 ps |
| CPU time | 467.8 seconds |
| Started | Jul 13 08:12:38 PM PDT 24 |
| Finished | Jul 13 08:20:27 PM PDT 24 |
| Peak memory | 648492 kb |
| Host | smart-57a9dd73-c7d9-4446-a87b-b03f36d55b7c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349763287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2349763287 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2986356765 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 3385558718 ps |
| CPU time | 470.66 seconds |
| Started | Jul 13 08:12:34 PM PDT 24 |
| Finished | Jul 13 08:20:25 PM PDT 24 |
| Peak memory | 648228 kb |
| Host | smart-89dc3f6b-f1ef-4069-a11e-783315a0a583 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986356765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2986356765 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.994247021 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 5990244786 ps |
| CPU time | 711.5 seconds |
| Started | Jul 13 08:12:48 PM PDT 24 |
| Finished | Jul 13 08:24:40 PM PDT 24 |
| Peak memory | 649500 kb |
| Host | smart-1ecd762d-0c5b-44eb-a81c-59f22e43fbad |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 994247021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.994247021 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2985164652 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 5988195900 ps |
| CPU time | 488.97 seconds |
| Started | Jul 13 08:10:10 PM PDT 24 |
| Finished | Jul 13 08:18:20 PM PDT 24 |
| Peak memory | 608716 kb |
| Host | smart-615b4adb-0fd1-42f4-8fba-9249f454a1be |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2985164652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2985164652 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.228238667 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 17087632280 ps |
| CPU time | 4634.17 seconds |
| Started | Jul 13 08:12:27 PM PDT 24 |
| Finished | Jul 13 09:29:42 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-e413aaed-9bdd-46d3-8ec5-10224c7239c8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228238667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.228238667 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2636386787 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 5604559712 ps |
| CPU time | 741.04 seconds |
| Started | Jul 13 08:07:24 PM PDT 24 |
| Finished | Jul 13 08:19:45 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-2150a7b0-0203-4565-9a61-3277c856bb10 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2636386787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.2636386787 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1339419039 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 12960085486 ps |
| CPU time | 963.75 seconds |
| Started | Jul 13 08:11:34 PM PDT 24 |
| Finished | Jul 13 08:27:39 PM PDT 24 |
| Peak memory | 623428 kb |
| Host | smart-316faf59-7a1d-4b69-8a31-01e0d773d636 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339419039 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.1339419039 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2582990819 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 4276856984 ps |
| CPU time | 359.86 seconds |
| Started | Jul 13 08:11:52 PM PDT 24 |
| Finished | Jul 13 08:17:52 PM PDT 24 |
| Peak memory | 608464 kb |
| Host | smart-39270c9f-8f37-4299-ae18-9e90d6bda23d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25829908 19 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.2582990819 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2188916478 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 8692596184 ps |
| CPU time | 1634.38 seconds |
| Started | Jul 13 08:08:39 PM PDT 24 |
| Finished | Jul 13 08:35:54 PM PDT 24 |
| Peak memory | 617956 kb |
| Host | smart-68b4155d-bae7-45e2-9e74-b8e92126283a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2188916478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.2188916478 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.3538904538 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 4571354488 ps |
| CPU time | 738.4 seconds |
| Started | Jul 13 08:07:30 PM PDT 24 |
| Finished | Jul 13 08:19:49 PM PDT 24 |
| Peak memory | 622164 kb |
| Host | smart-3989356c-d31b-4f86-9170-342d2ad94695 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538904538 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.3538904538 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3312201443 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 8425051638 ps |
| CPU time | 1719.88 seconds |
| Started | Jul 13 08:07:30 PM PDT 24 |
| Finished | Jul 13 08:36:10 PM PDT 24 |
| Peak memory | 624204 kb |
| Host | smart-5ac1c294-29fe-4cb5-b2be-c92246dc4a23 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312201443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.3312201443 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3779527800 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 13703080128 ps |
| CPU time | 1677.33 seconds |
| Started | Jul 13 08:07:19 PM PDT 24 |
| Finished | Jul 13 08:35:18 PM PDT 24 |
| Peak memory | 622748 kb |
| Host | smart-cfe69fcb-4991-46b1-be51-49b3baa95fd3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779527800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3779527800 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3172992973 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 4307230600 ps |
| CPU time | 592.94 seconds |
| Started | Jul 13 08:08:42 PM PDT 24 |
| Finished | Jul 13 08:18:35 PM PDT 24 |
| Peak memory | 623504 kb |
| Host | smart-f16e47b8-631f-4988-9b04-0a5e133b585b |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172992973 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.3172992973 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.459445391 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 4916184516 ps |
| CPU time | 721.42 seconds |
| Started | Jul 13 08:07:43 PM PDT 24 |
| Finished | Jul 13 08:19:44 PM PDT 24 |
| Peak memory | 623476 kb |
| Host | smart-58f7c23e-3625-46d5-99fd-f53bd2c2f9d3 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459445391 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.459445391 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1047447058 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 3850134872 ps |
| CPU time | 746.6 seconds |
| Started | Jul 13 08:10:11 PM PDT 24 |
| Finished | Jul 13 08:22:39 PM PDT 24 |
| Peak memory | 623192 kb |
| Host | smart-00c1a7a6-32c0-476e-a55d-f262857b163c |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047447058 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.1047447058 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.972313030 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 13086540642 ps |
| CPU time | 1518.6 seconds |
| Started | Jul 13 08:07:31 PM PDT 24 |
| Finished | Jul 13 08:32:50 PM PDT 24 |
| Peak memory | 620408 kb |
| Host | smart-164f47ff-c730-4d81-ac62-ce3401d4b0d0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972313030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.972313030 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.2133975793 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 4202162353 ps |
| CPU time | 483.56 seconds |
| Started | Jul 13 08:07:38 PM PDT 24 |
| Finished | Jul 13 08:15:42 PM PDT 24 |
| Peak memory | 620308 kb |
| Host | smart-c016b8fd-e2ff-460b-915e-03edfdc6b1ab |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133975793 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.2133975793 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2964084162 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 3375129360 ps |
| CPU time | 469.26 seconds |
| Started | Jul 13 08:13:33 PM PDT 24 |
| Finished | Jul 13 08:21:23 PM PDT 24 |
| Peak memory | 648456 kb |
| Host | smart-7e071684-a6b1-4956-bd73-a2c7dbb3cbfa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964084162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2964084162 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1615617172 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 3642474226 ps |
| CPU time | 491.42 seconds |
| Started | Jul 13 08:12:35 PM PDT 24 |
| Finished | Jul 13 08:20:47 PM PDT 24 |
| Peak memory | 647928 kb |
| Host | smart-4769dc46-70e9-4a20-bd86-56968801dcc0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615617172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1615617172 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.994254736 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 5364992488 ps |
| CPU time | 726.87 seconds |
| Started | Jul 13 08:12:43 PM PDT 24 |
| Finished | Jul 13 08:24:52 PM PDT 24 |
| Peak memory | 649536 kb |
| Host | smart-5d525ebe-521e-4f1d-bacc-ec766eeb412b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 994254736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.994254736 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3208478525 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 4218384848 ps |
| CPU time | 404.18 seconds |
| Started | Jul 13 08:13:59 PM PDT 24 |
| Finished | Jul 13 08:20:44 PM PDT 24 |
| Peak memory | 647944 kb |
| Host | smart-d08d1d29-95a1-4b7d-8ff0-1ebd804e5a8e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208478525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3208478525 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2535434295 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 3815759400 ps |
| CPU time | 403.39 seconds |
| Started | Jul 13 08:12:55 PM PDT 24 |
| Finished | Jul 13 08:19:39 PM PDT 24 |
| Peak memory | 647960 kb |
| Host | smart-96a5c95d-40dc-4a7b-b8f3-387b5eb24f61 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535434295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2535434295 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.1677282267 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 6269084064 ps |
| CPU time | 788.92 seconds |
| Started | Jul 13 08:14:19 PM PDT 24 |
| Finished | Jul 13 08:27:29 PM PDT 24 |
| Peak memory | 649300 kb |
| Host | smart-9bcca36d-fa27-490a-8aac-792a500ddf6b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1677282267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.1677282267 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2984481179 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 3395138054 ps |
| CPU time | 451.49 seconds |
| Started | Jul 13 08:13:53 PM PDT 24 |
| Finished | Jul 13 08:21:24 PM PDT 24 |
| Peak memory | 648188 kb |
| Host | smart-14ee26bb-e10c-42c0-8d5e-32504f869b2d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984481179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2984481179 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.1790380952 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 4632787480 ps |
| CPU time | 728.65 seconds |
| Started | Jul 13 08:13:16 PM PDT 24 |
| Finished | Jul 13 08:25:25 PM PDT 24 |
| Peak memory | 649696 kb |
| Host | smart-c9748b01-01c1-461c-b5d7-791bdd47d757 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1790380952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.1790380952 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.229624168 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 3593736500 ps |
| CPU time | 405.87 seconds |
| Started | Jul 13 08:13:48 PM PDT 24 |
| Finished | Jul 13 08:20:34 PM PDT 24 |
| Peak memory | 648020 kb |
| Host | smart-49e0778d-0a42-4373-b028-090d1d0cdb16 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229624168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_s w_alert_handler_lpg_sleep_mode_alerts.229624168 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.916434893 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 4864860794 ps |
| CPU time | 542.95 seconds |
| Started | Jul 13 08:13:35 PM PDT 24 |
| Finished | Jul 13 08:22:39 PM PDT 24 |
| Peak memory | 649712 kb |
| Host | smart-58dbe38a-b8d6-4039-ad46-9bb74c0ac930 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 916434893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.916434893 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3202191656 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 3800414600 ps |
| CPU time | 422.64 seconds |
| Started | Jul 13 08:18:12 PM PDT 24 |
| Finished | Jul 13 08:25:15 PM PDT 24 |
| Peak memory | 648156 kb |
| Host | smart-c1ee5f4d-aedf-47c9-abd2-45c2ba53aa43 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202191656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3202191656 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.1490166882 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 4700129960 ps |
| CPU time | 484.15 seconds |
| Started | Jul 13 08:14:37 PM PDT 24 |
| Finished | Jul 13 08:22:42 PM PDT 24 |
| Peak memory | 649716 kb |
| Host | smart-f7dfe458-e2f1-4780-a7bb-ab9235831fea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1490166882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.1490166882 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3326173453 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3650220344 ps |
| CPU time | 492.22 seconds |
| Started | Jul 13 08:14:02 PM PDT 24 |
| Finished | Jul 13 08:22:15 PM PDT 24 |
| Peak memory | 648192 kb |
| Host | smart-f551a587-4d95-48d7-b15b-550c5fa37e66 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326173453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3326173453 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.657096230 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 5311963470 ps |
| CPU time | 696.71 seconds |
| Started | Jul 13 08:14:14 PM PDT 24 |
| Finished | Jul 13 08:25:51 PM PDT 24 |
| Peak memory | 649508 kb |
| Host | smart-fe685858-00bd-4272-a697-c174b21e73b4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 657096230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.657096230 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.3559660200 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 5227040864 ps |
| CPU time | 765.71 seconds |
| Started | Jul 13 08:14:53 PM PDT 24 |
| Finished | Jul 13 08:27:40 PM PDT 24 |
| Peak memory | 649572 kb |
| Host | smart-4b5c3ca6-28ad-4dec-ac63-911a91dd940a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3559660200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.3559660200 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2799514481 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 4190662636 ps |
| CPU time | 366.58 seconds |
| Started | Jul 13 08:08:40 PM PDT 24 |
| Finished | Jul 13 08:14:47 PM PDT 24 |
| Peak memory | 648232 kb |
| Host | smart-2208a48f-25f4-45f8-bf57-5453fdc24161 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799514481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s w_alert_handler_lpg_sleep_mode_alerts.2799514481 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3853300479 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 11762386216 ps |
| CPU time | 2834.53 seconds |
| Started | Jul 13 08:10:58 PM PDT 24 |
| Finished | Jul 13 08:58:14 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-f2055bf6-34b1-42ce-a97b-06ecf489e9c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853300479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.3853300479 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2780797804 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 5162251384 ps |
| CPU time | 818.96 seconds |
| Started | Jul 13 08:08:32 PM PDT 24 |
| Finished | Jul 13 08:22:11 PM PDT 24 |
| Peak memory | 610304 kb |
| Host | smart-1748db24-ec32-472e-822f-b50e8e5ad30d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2780797804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.2780797804 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1717348594 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 12069893174 ps |
| CPU time | 1281.27 seconds |
| Started | Jul 13 08:09:58 PM PDT 24 |
| Finished | Jul 13 08:31:20 PM PDT 24 |
| Peak memory | 622924 kb |
| Host | smart-08edb6d4-8191-406e-a5e2-6fc2014cfd13 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717348594 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.1717348594 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3910694978 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 4044412808 ps |
| CPU time | 665.53 seconds |
| Started | Jul 13 08:08:57 PM PDT 24 |
| Finished | Jul 13 08:20:03 PM PDT 24 |
| Peak memory | 618056 kb |
| Host | smart-f6a8b4e7-86e1-47e7-8862-b652882a3738 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3910694978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.3910694978 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.226112724 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 3625644660 ps |
| CPU time | 365.02 seconds |
| Started | Jul 13 08:13:26 PM PDT 24 |
| Finished | Jul 13 08:19:31 PM PDT 24 |
| Peak memory | 648408 kb |
| Host | smart-14050d15-56dd-4a56-a986-7cb4b106381e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226112724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_s w_alert_handler_lpg_sleep_mode_alerts.226112724 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.3251764519 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 4869520020 ps |
| CPU time | 588.96 seconds |
| Started | Jul 13 08:14:33 PM PDT 24 |
| Finished | Jul 13 08:24:23 PM PDT 24 |
| Peak memory | 649908 kb |
| Host | smart-e158ad08-29f6-438a-938d-d7a38e40391e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3251764519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.3251764519 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1760238471 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 3595088704 ps |
| CPU time | 515.04 seconds |
| Started | Jul 13 08:14:09 PM PDT 24 |
| Finished | Jul 13 08:22:44 PM PDT 24 |
| Peak memory | 647936 kb |
| Host | smart-ed64c5cd-0ab2-4bcf-809f-9e1c2a19d5b0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760238471 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1760238471 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.3296213964 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 5966003838 ps |
| CPU time | 550.66 seconds |
| Started | Jul 13 08:15:23 PM PDT 24 |
| Finished | Jul 13 08:24:34 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-aa0d0354-d99e-494f-ac38-be92175d51ee |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3296213964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.3296213964 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.1659879291 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 5754884800 ps |
| CPU time | 517.33 seconds |
| Started | Jul 13 08:15:49 PM PDT 24 |
| Finished | Jul 13 08:24:27 PM PDT 24 |
| Peak memory | 649528 kb |
| Host | smart-8a5ce8cb-e218-4046-90fd-4f84cd787ba0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1659879291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.1659879291 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3468495443 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 3532793444 ps |
| CPU time | 344.97 seconds |
| Started | Jul 13 08:16:08 PM PDT 24 |
| Finished | Jul 13 08:21:53 PM PDT 24 |
| Peak memory | 648292 kb |
| Host | smart-3930a2ec-41d7-495f-b706-a5a1eb3847ef |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468495443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3468495443 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.740862356 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 5701350692 ps |
| CPU time | 743.24 seconds |
| Started | Jul 13 08:14:52 PM PDT 24 |
| Finished | Jul 13 08:27:16 PM PDT 24 |
| Peak memory | 616256 kb |
| Host | smart-5914a878-c227-48c0-ac12-4ff0e2593927 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 740862356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.740862356 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.764130074 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 3374519994 ps |
| CPU time | 381.59 seconds |
| Started | Jul 13 08:15:33 PM PDT 24 |
| Finished | Jul 13 08:21:55 PM PDT 24 |
| Peak memory | 648192 kb |
| Host | smart-ebe3845c-a9e0-4946-b11a-7da3134d1732 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764130074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_s w_alert_handler_lpg_sleep_mode_alerts.764130074 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.3627017736 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 5074514000 ps |
| CPU time | 676.51 seconds |
| Started | Jul 13 08:15:11 PM PDT 24 |
| Finished | Jul 13 08:26:28 PM PDT 24 |
| Peak memory | 649288 kb |
| Host | smart-f67c436d-2327-49c8-b0f0-03885e9d1a1a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3627017736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.3627017736 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.2927874884 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 4584966142 ps |
| CPU time | 663.82 seconds |
| Started | Jul 13 08:15:22 PM PDT 24 |
| Finished | Jul 13 08:26:26 PM PDT 24 |
| Peak memory | 649744 kb |
| Host | smart-6234e254-23f5-4bdc-bb2e-60c5e96ca411 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2927874884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.2927874884 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.16762255 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 5191462284 ps |
| CPU time | 579.33 seconds |
| Started | Jul 13 08:15:23 PM PDT 24 |
| Finished | Jul 13 08:25:03 PM PDT 24 |
| Peak memory | 649276 kb |
| Host | smart-036f8303-70f0-424c-8ef0-7bb7c13d1441 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 16762255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.16762255 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.531760966 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 6135483000 ps |
| CPU time | 696.36 seconds |
| Started | Jul 13 08:14:37 PM PDT 24 |
| Finished | Jul 13 08:26:14 PM PDT 24 |
| Peak memory | 649580 kb |
| Host | smart-76783e71-c76c-4dc3-8de6-2445a6537fb5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 531760966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.531760966 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3443845616 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 3782155368 ps |
| CPU time | 452.33 seconds |
| Started | Jul 13 08:15:04 PM PDT 24 |
| Finished | Jul 13 08:22:37 PM PDT 24 |
| Peak memory | 648116 kb |
| Host | smart-e6737650-7548-4044-bd34-62443eb6a847 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443845616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3443845616 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.689083258 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 3673800728 ps |
| CPU time | 448.9 seconds |
| Started | Jul 13 08:09:05 PM PDT 24 |
| Finished | Jul 13 08:16:34 PM PDT 24 |
| Peak memory | 648012 kb |
| Host | smart-ab539710-fa96-4f4c-9263-d2781b86e44a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689083258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw _alert_handler_lpg_sleep_mode_alerts.689083258 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.2280978865 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 5516443200 ps |
| CPU time | 663.2 seconds |
| Started | Jul 13 08:12:08 PM PDT 24 |
| Finished | Jul 13 08:23:12 PM PDT 24 |
| Peak memory | 649724 kb |
| Host | smart-6031faf3-6295-427f-a22c-5afea54cb96a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2280978865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.2280978865 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1714935210 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 34927869912 ps |
| CPU time | 7983.06 seconds |
| Started | Jul 13 08:10:22 PM PDT 24 |
| Finished | Jul 13 10:23:29 PM PDT 24 |
| Peak memory | 609924 kb |
| Host | smart-65cad4fd-184f-4b3e-8e9f-069bf5d62ecd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714935210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.1714935210 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1736657342 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 6917345484 ps |
| CPU time | 738 seconds |
| Started | Jul 13 08:08:34 PM PDT 24 |
| Finished | Jul 13 08:20:52 PM PDT 24 |
| Peak memory | 620660 kb |
| Host | smart-788fff11-251b-4470-b94c-94110ea0c49d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736657342 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.1736657342 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3715620133 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 3436662350 ps |
| CPU time | 457.69 seconds |
| Started | Jul 13 08:15:39 PM PDT 24 |
| Finished | Jul 13 08:23:17 PM PDT 24 |
| Peak memory | 648344 kb |
| Host | smart-543df4cd-50ab-45c5-a54f-141390a7031d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715620133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3715620133 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.2252986421 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 6195101004 ps |
| CPU time | 765.87 seconds |
| Started | Jul 13 08:15:08 PM PDT 24 |
| Finished | Jul 13 08:27:55 PM PDT 24 |
| Peak memory | 649700 kb |
| Host | smart-928f7f7b-a80a-4c4b-98e4-bfd42b66f692 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2252986421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.2252986421 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1389964273 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 3573605690 ps |
| CPU time | 436.02 seconds |
| Started | Jul 13 08:16:03 PM PDT 24 |
| Finished | Jul 13 08:23:19 PM PDT 24 |
| Peak memory | 648240 kb |
| Host | smart-86e893c7-fc1c-4af8-9cd2-659edeb474b0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389964273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1389964273 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.1153512244 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 5230085354 ps |
| CPU time | 571.88 seconds |
| Started | Jul 13 08:15:23 PM PDT 24 |
| Finished | Jul 13 08:24:55 PM PDT 24 |
| Peak memory | 649624 kb |
| Host | smart-237eab2f-b33b-42ec-a6f3-6b938e2f32e3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1153512244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.1153512244 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2740306854 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 3762382404 ps |
| CPU time | 368.52 seconds |
| Started | Jul 13 08:16:19 PM PDT 24 |
| Finished | Jul 13 08:22:28 PM PDT 24 |
| Peak memory | 647912 kb |
| Host | smart-23d2f3c0-3b59-4c2b-9b52-3648a4f6599d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740306854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2740306854 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.2732638405 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 5611185608 ps |
| CPU time | 661.53 seconds |
| Started | Jul 13 08:17:17 PM PDT 24 |
| Finished | Jul 13 08:28:19 PM PDT 24 |
| Peak memory | 649268 kb |
| Host | smart-be65cb19-e1e6-4655-8eea-1a30ac83a671 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2732638405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.2732638405 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2658015613 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 3459453664 ps |
| CPU time | 348.89 seconds |
| Started | Jul 13 08:15:55 PM PDT 24 |
| Finished | Jul 13 08:21:45 PM PDT 24 |
| Peak memory | 648208 kb |
| Host | smart-9b3a1147-c9ab-47a2-9422-8619fd14c6b6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658015613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2658015613 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.3441315287 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 4941161232 ps |
| CPU time | 588.31 seconds |
| Started | Jul 13 08:15:12 PM PDT 24 |
| Finished | Jul 13 08:25:01 PM PDT 24 |
| Peak memory | 649676 kb |
| Host | smart-d56a9141-60d1-45b7-9047-8b38b021e3dd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3441315287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.3441315287 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.3095716515 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 4913978270 ps |
| CPU time | 654.66 seconds |
| Started | Jul 13 08:16:28 PM PDT 24 |
| Finished | Jul 13 08:27:23 PM PDT 24 |
| Peak memory | 649296 kb |
| Host | smart-76e8b339-4c9c-4665-b980-8756ef7beae3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3095716515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.3095716515 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3926606306 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 3544529960 ps |
| CPU time | 383.98 seconds |
| Started | Jul 13 08:16:51 PM PDT 24 |
| Finished | Jul 13 08:23:15 PM PDT 24 |
| Peak memory | 648272 kb |
| Host | smart-43976438-991c-451c-8ee2-bc6a7bd18b40 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926606306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3926606306 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.28894805 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 5751955996 ps |
| CPU time | 610.93 seconds |
| Started | Jul 13 08:15:49 PM PDT 24 |
| Finished | Jul 13 08:26:01 PM PDT 24 |
| Peak memory | 649624 kb |
| Host | smart-b5cf348b-9691-4ca9-8052-cde6570b93c7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 28894805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.28894805 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2362578449 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 3834729652 ps |
| CPU time | 432.05 seconds |
| Started | Jul 13 08:16:26 PM PDT 24 |
| Finished | Jul 13 08:23:39 PM PDT 24 |
| Peak memory | 648068 kb |
| Host | smart-f07816f7-68e1-4743-88b8-cc5b0c49b38a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362578449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2362578449 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.349467477 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 4579585440 ps |
| CPU time | 641.66 seconds |
| Started | Jul 13 08:16:33 PM PDT 24 |
| Finished | Jul 13 08:27:15 PM PDT 24 |
| Peak memory | 649852 kb |
| Host | smart-4642c4b3-1a74-4180-9d5a-fb6a8e596e4e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 349467477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.349467477 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.417196007 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 5088729970 ps |
| CPU time | 572.62 seconds |
| Started | Jul 13 08:14:49 PM PDT 24 |
| Finished | Jul 13 08:24:22 PM PDT 24 |
| Peak memory | 649712 kb |
| Host | smart-1d9cd488-ce2a-4691-8a9b-bc3a87c60bb6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 417196007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.417196007 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.989171996 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 17772388060 ps |
| CPU time | 5583.52 seconds |
| Started | Jul 13 08:15:08 PM PDT 24 |
| Finished | Jul 13 09:48:13 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-2c344797-b594-4c10-a2a0-66257d3979f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989171996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.989171996 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2318224212 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 10953006047 ps |
| CPU time | 1224.28 seconds |
| Started | Jul 13 08:09:14 PM PDT 24 |
| Finished | Jul 13 08:29:39 PM PDT 24 |
| Peak memory | 622996 kb |
| Host | smart-51fbf634-512c-43c1-a7c7-fa383b1efdc2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318224212 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.2318224212 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1259345022 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 4362433640 ps |
| CPU time | 665.89 seconds |
| Started | Jul 13 08:09:52 PM PDT 24 |
| Finished | Jul 13 08:20:58 PM PDT 24 |
| Peak memory | 618216 kb |
| Host | smart-e35d5cc1-41cb-459a-8f6b-18279e417310 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1259345022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.1259345022 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.762322562 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 5499788934 ps |
| CPU time | 608.2 seconds |
| Started | Jul 13 08:17:33 PM PDT 24 |
| Finished | Jul 13 08:27:42 PM PDT 24 |
| Peak memory | 649184 kb |
| Host | smart-c6c6ed98-6d30-439e-86de-bf8a2531ac8a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 762322562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.762322562 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2200399807 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 3151669670 ps |
| CPU time | 322.23 seconds |
| Started | Jul 13 08:15:46 PM PDT 24 |
| Finished | Jul 13 08:21:08 PM PDT 24 |
| Peak memory | 617948 kb |
| Host | smart-49101fc8-b3e9-4a32-b8eb-10abe905c796 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200399807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2200399807 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.2113293600 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 4715680612 ps |
| CPU time | 913.54 seconds |
| Started | Jul 13 08:15:45 PM PDT 24 |
| Finished | Jul 13 08:30:59 PM PDT 24 |
| Peak memory | 649536 kb |
| Host | smart-fc897af3-6b22-4379-95f2-c3587532eb85 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2113293600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.2113293600 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2740219860 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 4167757664 ps |
| CPU time | 437 seconds |
| Started | Jul 13 08:16:50 PM PDT 24 |
| Finished | Jul 13 08:24:08 PM PDT 24 |
| Peak memory | 648312 kb |
| Host | smart-11552862-99f5-49d3-b1bc-1ff3b82a33c8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740219860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2740219860 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.4211426228 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 3907936086 ps |
| CPU time | 382.2 seconds |
| Started | Jul 13 08:16:29 PM PDT 24 |
| Finished | Jul 13 08:22:51 PM PDT 24 |
| Peak memory | 648196 kb |
| Host | smart-fb8467c9-615d-4bc4-915f-ea8430b03f05 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211426228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4211426228 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.1401333267 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 4815599480 ps |
| CPU time | 658.73 seconds |
| Started | Jul 13 08:17:25 PM PDT 24 |
| Finished | Jul 13 08:28:25 PM PDT 24 |
| Peak memory | 649684 kb |
| Host | smart-db3e9960-d115-4b7d-99ee-d3a35d235d39 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1401333267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.1401333267 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3612034155 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 3858959756 ps |
| CPU time | 365.42 seconds |
| Started | Jul 13 08:15:42 PM PDT 24 |
| Finished | Jul 13 08:21:48 PM PDT 24 |
| Peak memory | 648472 kb |
| Host | smart-e57f4674-6d28-4167-a3f3-bfc1cc6ad870 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612034155 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3612034155 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2029407608 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 3201444250 ps |
| CPU time | 377.47 seconds |
| Started | Jul 13 08:16:54 PM PDT 24 |
| Finished | Jul 13 08:23:12 PM PDT 24 |
| Peak memory | 647984 kb |
| Host | smart-03ef880f-14f0-48d6-950e-b8f1b83a5402 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029407608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2029407608 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.2758966959 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 4887032392 ps |
| CPU time | 645.42 seconds |
| Started | Jul 13 08:15:46 PM PDT 24 |
| Finished | Jul 13 08:26:31 PM PDT 24 |
| Peak memory | 649496 kb |
| Host | smart-90197d9c-6d5e-4012-9ba0-f9f5cb21bcd8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2758966959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.2758966959 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.947128312 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 4171779012 ps |
| CPU time | 392.92 seconds |
| Started | Jul 13 08:15:47 PM PDT 24 |
| Finished | Jul 13 08:22:21 PM PDT 24 |
| Peak memory | 647956 kb |
| Host | smart-a27e8261-8cea-4429-950c-65c278ce864a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947128312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_s w_alert_handler_lpg_sleep_mode_alerts.947128312 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.2400727488 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 4663010092 ps |
| CPU time | 702.18 seconds |
| Started | Jul 13 08:17:09 PM PDT 24 |
| Finished | Jul 13 08:28:52 PM PDT 24 |
| Peak memory | 649848 kb |
| Host | smart-fae0543a-c099-43a1-89a3-57c87a70ea6a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2400727488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.2400727488 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.4249265896 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 3211028760 ps |
| CPU time | 382.3 seconds |
| Started | Jul 13 08:17:17 PM PDT 24 |
| Finished | Jul 13 08:23:40 PM PDT 24 |
| Peak memory | 648144 kb |
| Host | smart-5d5c5fe0-d875-457a-b2e4-84ffae36ec3f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249265896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4249265896 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.3102944819 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 4562510140 ps |
| CPU time | 578.68 seconds |
| Started | Jul 13 08:16:59 PM PDT 24 |
| Finished | Jul 13 08:26:39 PM PDT 24 |
| Peak memory | 649532 kb |
| Host | smart-b239c38b-b02c-4db2-a4f2-2c1a5399331d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3102944819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.3102944819 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2984487829 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 3591748056 ps |
| CPU time | 384.54 seconds |
| Started | Jul 13 08:16:50 PM PDT 24 |
| Finished | Jul 13 08:23:16 PM PDT 24 |
| Peak memory | 648180 kb |
| Host | smart-6935e1c0-36ad-4be0-9038-6a8e86ab7746 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984487829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2984487829 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.595232883 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 4768441434 ps |
| CPU time | 919.37 seconds |
| Started | Jul 13 08:16:27 PM PDT 24 |
| Finished | Jul 13 08:31:47 PM PDT 24 |
| Peak memory | 649160 kb |
| Host | smart-f9b4cd4d-721f-4373-bb5a-7d94aa9d7b49 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 595232883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.595232883 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.500880978 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 3370313720 ps |
| CPU time | 405.45 seconds |
| Started | Jul 13 08:17:55 PM PDT 24 |
| Finished | Jul 13 08:24:41 PM PDT 24 |
| Peak memory | 647940 kb |
| Host | smart-538e7293-641b-424e-8051-b81e71a3bd83 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500880978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_s w_alert_handler_lpg_sleep_mode_alerts.500880978 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.233926948 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 4172898052 ps |
| CPU time | 541.66 seconds |
| Started | Jul 13 08:18:14 PM PDT 24 |
| Finished | Jul 13 08:27:16 PM PDT 24 |
| Peak memory | 649256 kb |
| Host | smart-7757e768-e038-4da8-aba3-54f8ebe26e2d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 233926948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.233926948 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2485711866 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 3262989528 ps |
| CPU time | 358.98 seconds |
| Started | Jul 13 08:09:34 PM PDT 24 |
| Finished | Jul 13 08:15:34 PM PDT 24 |
| Peak memory | 648328 kb |
| Host | smart-aac7a0ac-b6f7-4ab9-8357-4c173db92ce4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485711866 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.2485711866 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.3305492666 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 6093803392 ps |
| CPU time | 623.19 seconds |
| Started | Jul 13 08:11:16 PM PDT 24 |
| Finished | Jul 13 08:21:40 PM PDT 24 |
| Peak memory | 649840 kb |
| Host | smart-7201e7ff-8f48-4a1c-b58c-90be877183a3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3305492666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.3305492666 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2147556691 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 7194359728 ps |
| CPU time | 510.29 seconds |
| Started | Jul 13 08:14:41 PM PDT 24 |
| Finished | Jul 13 08:23:13 PM PDT 24 |
| Peak memory | 620736 kb |
| Host | smart-e7b2e1b5-0411-47a8-a014-df4b629e283c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147556691 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.2147556691 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1006202371 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 4344575770 ps |
| CPU time | 629.45 seconds |
| Started | Jul 13 08:12:58 PM PDT 24 |
| Finished | Jul 13 08:23:28 PM PDT 24 |
| Peak memory | 618524 kb |
| Host | smart-2803f88a-845d-4e96-a5c2-389b89d13e83 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1006202371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.1006202371 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3713563634 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 3212537100 ps |
| CPU time | 390.04 seconds |
| Started | Jul 13 08:16:54 PM PDT 24 |
| Finished | Jul 13 08:23:25 PM PDT 24 |
| Peak memory | 648268 kb |
| Host | smart-14608576-2e6f-417a-af09-520ba3d6f766 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713563634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3713563634 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.1106114847 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 5160985510 ps |
| CPU time | 640.26 seconds |
| Started | Jul 13 08:16:44 PM PDT 24 |
| Finished | Jul 13 08:27:24 PM PDT 24 |
| Peak memory | 649808 kb |
| Host | smart-68be40bd-454a-4a77-a466-2351a2491e0f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1106114847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.1106114847 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3518978951 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 3675483146 ps |
| CPU time | 343.77 seconds |
| Started | Jul 13 08:17:06 PM PDT 24 |
| Finished | Jul 13 08:22:51 PM PDT 24 |
| Peak memory | 648076 kb |
| Host | smart-cf64d9bd-0d8f-4f43-990b-03e0de79ae63 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518978951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3518978951 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.968883585 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 6089221480 ps |
| CPU time | 637.16 seconds |
| Started | Jul 13 08:16:56 PM PDT 24 |
| Finished | Jul 13 08:27:34 PM PDT 24 |
| Peak memory | 649436 kb |
| Host | smart-62a159b1-8ea1-4c8e-a4bc-c2e00d97405f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 968883585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.968883585 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.414324327 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 4251467416 ps |
| CPU time | 353.45 seconds |
| Started | Jul 13 08:16:25 PM PDT 24 |
| Finished | Jul 13 08:22:18 PM PDT 24 |
| Peak memory | 648232 kb |
| Host | smart-c7d6a4eb-9440-4c20-909e-706b8fdbd042 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414324327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_s w_alert_handler_lpg_sleep_mode_alerts.414324327 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.3405998221 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 4873241022 ps |
| CPU time | 732.81 seconds |
| Started | Jul 13 08:17:41 PM PDT 24 |
| Finished | Jul 13 08:29:54 PM PDT 24 |
| Peak memory | 649716 kb |
| Host | smart-b59b517e-9a35-4868-899e-7c8d4d94fac3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3405998221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.3405998221 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2955293970 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 3324802612 ps |
| CPU time | 428.51 seconds |
| Started | Jul 13 08:17:07 PM PDT 24 |
| Finished | Jul 13 08:24:17 PM PDT 24 |
| Peak memory | 648604 kb |
| Host | smart-ccf4622f-d0fa-409a-9050-d7d3206030e3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955293970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2955293970 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.918911326 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 3904074800 ps |
| CPU time | 328.89 seconds |
| Started | Jul 13 08:17:49 PM PDT 24 |
| Finished | Jul 13 08:23:19 PM PDT 24 |
| Peak memory | 648176 kb |
| Host | smart-bdb1b7c7-7cd2-44b6-8f19-cc1136206917 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918911326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_s w_alert_handler_lpg_sleep_mode_alerts.918911326 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.2395908281 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 4421737540 ps |
| CPU time | 669.95 seconds |
| Started | Jul 13 08:16:20 PM PDT 24 |
| Finished | Jul 13 08:27:30 PM PDT 24 |
| Peak memory | 649340 kb |
| Host | smart-eebd955e-219c-4ffb-b466-c7a1b6a62261 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2395908281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.2395908281 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.2754562037 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 5495437764 ps |
| CPU time | 816.98 seconds |
| Started | Jul 13 08:19:19 PM PDT 24 |
| Finished | Jul 13 08:32:56 PM PDT 24 |
| Peak memory | 649320 kb |
| Host | smart-f8cfe542-b396-4aed-8c76-961a51c03696 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2754562037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.2754562037 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.76607212 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3060995160 ps |
| CPU time | 367.95 seconds |
| Started | Jul 13 08:17:59 PM PDT 24 |
| Finished | Jul 13 08:24:07 PM PDT 24 |
| Peak memory | 648764 kb |
| Host | smart-df706bda-1d30-434b-adc7-a3c79d2830f0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76607212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw _alert_handler_lpg_sleep_mode_alerts.76607212 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.1847240614 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 5609278984 ps |
| CPU time | 644.43 seconds |
| Started | Jul 13 08:19:15 PM PDT 24 |
| Finished | Jul 13 08:30:00 PM PDT 24 |
| Peak memory | 649712 kb |
| Host | smart-bd2c669e-2cbc-4430-8f50-e4c5efe54c72 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1847240614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.1847240614 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.2605482744 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 4961791352 ps |
| CPU time | 545.26 seconds |
| Started | Jul 13 08:17:24 PM PDT 24 |
| Finished | Jul 13 08:26:29 PM PDT 24 |
| Peak memory | 649672 kb |
| Host | smart-b9b1532a-0d7f-479c-94bb-b7d5a0bc598b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2605482744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.2605482744 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.475027293 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3257552104 ps |
| CPU time | 352.96 seconds |
| Started | Jul 13 08:17:37 PM PDT 24 |
| Finished | Jul 13 08:23:31 PM PDT 24 |
| Peak memory | 648244 kb |
| Host | smart-a4db88c8-7f24-4ab1-b428-259b2ce32472 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475027293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_s w_alert_handler_lpg_sleep_mode_alerts.475027293 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.577719386 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 5825221310 ps |
| CPU time | 620.59 seconds |
| Started | Jul 13 08:17:52 PM PDT 24 |
| Finished | Jul 13 08:28:13 PM PDT 24 |
| Peak memory | 649300 kb |
| Host | smart-1cc544d3-43b7-4914-8f27-e6370b245eaa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 577719386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.577719386 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.952591757 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 3356214616 ps |
| CPU time | 317.94 seconds |
| Started | Jul 13 08:18:23 PM PDT 24 |
| Finished | Jul 13 08:23:41 PM PDT 24 |
| Peak memory | 648128 kb |
| Host | smart-f71d4786-3f20-4906-9058-670f7a047e71 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952591757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_s w_alert_handler_lpg_sleep_mode_alerts.952591757 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.483848971 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 4119394592 ps |
| CPU time | 482.98 seconds |
| Started | Jul 13 08:09:46 PM PDT 24 |
| Finished | Jul 13 08:17:49 PM PDT 24 |
| Peak memory | 647804 kb |
| Host | smart-8131e77a-2847-4b15-9021-d4a74be7b294 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483848971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw _alert_handler_lpg_sleep_mode_alerts.483848971 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.1145521171 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 5086814160 ps |
| CPU time | 531.71 seconds |
| Started | Jul 13 08:10:16 PM PDT 24 |
| Finished | Jul 13 08:19:08 PM PDT 24 |
| Peak memory | 616192 kb |
| Host | smart-d77380de-b395-44e5-83e0-57ecd4c46d48 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1145521171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.1145521171 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3775586502 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 21834826270 ps |
| CPU time | 4859.68 seconds |
| Started | Jul 13 08:09:59 PM PDT 24 |
| Finished | Jul 13 09:31:00 PM PDT 24 |
| Peak memory | 610028 kb |
| Host | smart-6d1ddce2-9efa-4d3e-a1fb-f32307a429c7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775586502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.3775586502 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3299323025 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 10272809820 ps |
| CPU time | 823.95 seconds |
| Started | Jul 13 08:10:06 PM PDT 24 |
| Finished | Jul 13 08:23:50 PM PDT 24 |
| Peak memory | 621724 kb |
| Host | smart-0dcac415-d70e-496c-b15c-593f8a807cbb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299323025 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.3299323025 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3958202158 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 3773386172 ps |
| CPU time | 497.99 seconds |
| Started | Jul 13 08:09:17 PM PDT 24 |
| Finished | Jul 13 08:17:36 PM PDT 24 |
| Peak memory | 618260 kb |
| Host | smart-da14acf9-7e7e-4fd3-94b5-6a19a920e4c3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3958202158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.3958202158 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.697960434 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 4654416476 ps |
| CPU time | 638.75 seconds |
| Started | Jul 13 08:18:42 PM PDT 24 |
| Finished | Jul 13 08:29:22 PM PDT 24 |
| Peak memory | 616292 kb |
| Host | smart-6fae3b8a-a524-4d92-a200-d7abaf4867b2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 697960434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.697960434 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.2835128267 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 4297055614 ps |
| CPU time | 601.57 seconds |
| Started | Jul 13 08:17:54 PM PDT 24 |
| Finished | Jul 13 08:27:56 PM PDT 24 |
| Peak memory | 649276 kb |
| Host | smart-b7008eca-5108-4dba-9b1d-f75122f0f949 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2835128267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.2835128267 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.2119179117 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 4864696040 ps |
| CPU time | 600.43 seconds |
| Started | Jul 13 08:16:52 PM PDT 24 |
| Finished | Jul 13 08:26:53 PM PDT 24 |
| Peak memory | 649316 kb |
| Host | smart-8df640fd-3030-49ec-9c35-a2c68e5f1916 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2119179117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.2119179117 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.363117336 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 6130528926 ps |
| CPU time | 777.61 seconds |
| Started | Jul 13 08:18:13 PM PDT 24 |
| Finished | Jul 13 08:31:11 PM PDT 24 |
| Peak memory | 649240 kb |
| Host | smart-9b029f08-72c1-45af-a4d0-06a9af324d3b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 363117336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.363117336 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.2109058199 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 5606337350 ps |
| CPU time | 696.76 seconds |
| Started | Jul 13 08:18:07 PM PDT 24 |
| Finished | Jul 13 08:29:44 PM PDT 24 |
| Peak memory | 649576 kb |
| Host | smart-312ba7b5-449f-4986-84cf-52d19f676244 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2109058199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.2109058199 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.4221828968 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 5385507990 ps |
| CPU time | 787.55 seconds |
| Started | Jul 13 08:17:28 PM PDT 24 |
| Finished | Jul 13 08:30:37 PM PDT 24 |
| Peak memory | 649572 kb |
| Host | smart-d5f6d15f-9e8a-4fdd-8622-71363640b37b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4221828968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.4221828968 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.222724743 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 5079326042 ps |
| CPU time | 635.41 seconds |
| Started | Jul 13 08:17:41 PM PDT 24 |
| Finished | Jul 13 08:28:17 PM PDT 24 |
| Peak memory | 649456 kb |
| Host | smart-49ef9394-06cb-4bf3-b283-87c9198f11d3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 222724743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.222724743 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.854981553 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 5498865288 ps |
| CPU time | 714.95 seconds |
| Started | Jul 13 08:18:09 PM PDT 24 |
| Finished | Jul 13 08:30:05 PM PDT 24 |
| Peak memory | 649684 kb |
| Host | smart-c8be98e6-4f68-4f52-bfb1-246d60620e8d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 854981553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.854981553 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.580650830 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 5303598720 ps |
| CPU time | 314.13 seconds |
| Started | Jul 13 08:10:56 PM PDT 24 |
| Finished | Jul 13 08:16:11 PM PDT 24 |
| Peak memory | 649008 kb |
| Host | smart-b90af1c9-eb19-4d7a-a04e-4d97d021d923 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580650830 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 0.chip_padctrl_attributes.580650830 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1687046331 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 4716582165 ps |
| CPU time | 286.35 seconds |
| Started | Jul 13 08:11:09 PM PDT 24 |
| Finished | Jul 13 08:15:56 PM PDT 24 |
| Peak memory | 640292 kb |
| Host | smart-8a823c80-58b6-4cb9-8e0d-07293b3a035a |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687046331 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.1687046331 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1850617548 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4592205556 ps |
| CPU time | 358.16 seconds |
| Started | Jul 13 08:11:10 PM PDT 24 |
| Finished | Jul 13 08:17:09 PM PDT 24 |
| Peak memory | 654844 kb |
| Host | smart-260a2b3c-ef52-45e8-af98-422834509851 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850617548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.1850617548 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1878469081 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 5065631710 ps |
| CPU time | 283.96 seconds |
| Started | Jul 13 08:11:03 PM PDT 24 |
| Finished | Jul 13 08:15:47 PM PDT 24 |
| Peak memory | 656664 kb |
| Host | smart-6e3d1b10-30ce-48f4-baca-05b0a76ee783 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878469081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.1878469081 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1345741436 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 5083824413 ps |
| CPU time | 411.95 seconds |
| Started | Jul 13 08:11:08 PM PDT 24 |
| Finished | Jul 13 08:18:00 PM PDT 24 |
| Peak memory | 656700 kb |
| Host | smart-283cb564-645c-4dec-acf8-c95cec1506eb |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345741436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.1345741436 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.4206061303 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 4796493426 ps |
| CPU time | 375.45 seconds |
| Started | Jul 13 08:11:26 PM PDT 24 |
| Finished | Jul 13 08:17:43 PM PDT 24 |
| Peak memory | 656708 kb |
| Host | smart-4967793a-2f10-4fbd-b861-0b6fce1ef54e |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206061303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.4206061303 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3395312030 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5244618860 ps |
| CPU time | 292.85 seconds |
| Started | Jul 13 08:11:21 PM PDT 24 |
| Finished | Jul 13 08:16:14 PM PDT 24 |
| Peak memory | 648516 kb |
| Host | smart-84aed040-0acf-4c6e-9ff8-42f2299a7a5d |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395312030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.3395312030 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1955547992 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 6037456004 ps |
| CPU time | 332.46 seconds |
| Started | Jul 13 08:11:08 PM PDT 24 |
| Finished | Jul 13 08:16:41 PM PDT 24 |
| Peak memory | 641912 kb |
| Host | smart-b8272736-ab7e-42fb-81b7-39339659df14 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955547992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.1955547992 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
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