| T1200 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.44463187 |
|
|
Jul 13 07:50:08 PM PDT 24 |
Jul 13 08:05:23 PM PDT 24 |
9866937151 ps |
| T1201 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.68030518 |
|
|
Jul 13 07:51:13 PM PDT 24 |
Jul 13 07:59:20 PM PDT 24 |
5203663946 ps |
| T230 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1303279779 |
|
|
Jul 13 08:04:05 PM PDT 24 |
Jul 13 08:51:00 PM PDT 24 |
11135258560 ps |
| T1202 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3473872408 |
|
|
Jul 13 07:53:14 PM PDT 24 |
Jul 13 09:06:46 PM PDT 24 |
15715239816 ps |
| T1203 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1777820171 |
|
|
Jul 13 07:48:14 PM PDT 24 |
Jul 13 07:52:11 PM PDT 24 |
2539497623 ps |
| T1204 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1779682904 |
|
|
Jul 13 07:50:49 PM PDT 24 |
Jul 13 07:58:28 PM PDT 24 |
9525425343 ps |
| T244 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3608561986 |
|
|
Jul 13 07:49:52 PM PDT 24 |
Jul 13 08:03:52 PM PDT 24 |
7099437400 ps |
| T1205 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1736657342 |
|
|
Jul 13 08:08:34 PM PDT 24 |
Jul 13 08:20:52 PM PDT 24 |
6917345484 ps |
| T256 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2939937229 |
|
|
Jul 13 07:46:02 PM PDT 24 |
Jul 13 08:22:28 PM PDT 24 |
10120948090 ps |
| T1206 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3428410625 |
|
|
Jul 13 07:59:03 PM PDT 24 |
Jul 13 08:06:30 PM PDT 24 |
3853419380 ps |
| T1207 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1569052415 |
|
|
Jul 13 07:51:33 PM PDT 24 |
Jul 13 07:53:45 PM PDT 24 |
2042386965 ps |
| T286 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1061241951 |
|
|
Jul 13 08:04:29 PM PDT 24 |
Jul 13 08:08:34 PM PDT 24 |
2984805020 ps |
| T1208 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.177572915 |
|
|
Jul 13 07:47:43 PM PDT 24 |
Jul 13 08:00:02 PM PDT 24 |
5726371368 ps |
| T794 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2524999047 |
|
|
Jul 13 08:10:53 PM PDT 24 |
Jul 13 08:17:35 PM PDT 24 |
4186192784 ps |
| T764 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.657096230 |
|
|
Jul 13 08:14:14 PM PDT 24 |
Jul 13 08:25:51 PM PDT 24 |
5311963470 ps |
| T1209 |
/workspace/coverage/default/0.rom_e2e_smoke.2588053913 |
|
|
Jul 13 07:54:48 PM PDT 24 |
Jul 13 09:14:34 PM PDT 24 |
14740974198 ps |
| T1210 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2741799285 |
|
|
Jul 13 07:45:56 PM PDT 24 |
Jul 13 07:52:57 PM PDT 24 |
3353050632 ps |
| T1211 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.2120407952 |
|
|
Jul 13 08:07:02 PM PDT 24 |
Jul 13 08:12:59 PM PDT 24 |
3505757476 ps |
| T267 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.4222142840 |
|
|
Jul 13 07:45:35 PM PDT 24 |
Jul 13 07:49:35 PM PDT 24 |
2610572280 ps |
| T161 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.2086808783 |
|
|
Jul 13 08:11:24 PM PDT 24 |
Jul 13 08:21:51 PM PDT 24 |
4829829368 ps |
| T112 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.275695356 |
|
|
Jul 13 07:58:23 PM PDT 24 |
Jul 13 08:53:30 PM PDT 24 |
20869395134 ps |
| T1212 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.740862356 |
|
|
Jul 13 08:14:52 PM PDT 24 |
Jul 13 08:27:16 PM PDT 24 |
5701350692 ps |
| T1213 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.2532665132 |
|
|
Jul 13 08:12:55 PM PDT 24 |
Jul 13 08:23:35 PM PDT 24 |
5705246552 ps |
| T1214 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.210957343 |
|
|
Jul 13 07:43:45 PM PDT 24 |
Jul 13 08:19:44 PM PDT 24 |
13425331956 ps |
| T1215 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3312201443 |
|
|
Jul 13 08:07:30 PM PDT 24 |
Jul 13 08:36:10 PM PDT 24 |
8425051638 ps |
| T232 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1491407075 |
|
|
Jul 13 07:52:36 PM PDT 24 |
Jul 13 08:53:35 PM PDT 24 |
12020015924 ps |
| T705 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1992431561 |
|
|
Jul 13 07:49:01 PM PDT 24 |
Jul 13 07:58:39 PM PDT 24 |
4480339774 ps |
| T1216 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.4057600907 |
|
|
Jul 13 07:59:57 PM PDT 24 |
Jul 13 09:18:54 PM PDT 24 |
15013984960 ps |
| T1217 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.3095716515 |
|
|
Jul 13 08:16:28 PM PDT 24 |
Jul 13 08:27:23 PM PDT 24 |
4913978270 ps |
| T1218 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.2389654980 |
|
|
Jul 13 07:58:49 PM PDT 24 |
Jul 13 08:00:58 PM PDT 24 |
2474384066 ps |
| T786 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2109058199 |
|
|
Jul 13 08:18:07 PM PDT 24 |
Jul 13 08:29:44 PM PDT 24 |
5606337350 ps |
| T1219 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3910694978 |
|
|
Jul 13 08:08:57 PM PDT 24 |
Jul 13 08:20:03 PM PDT 24 |
4044412808 ps |
| T776 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3589718118 |
|
|
Jul 13 08:12:26 PM PDT 24 |
Jul 13 08:20:39 PM PDT 24 |
3623185900 ps |
| T1220 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.764130074 |
|
|
Jul 13 08:15:33 PM PDT 24 |
Jul 13 08:21:55 PM PDT 24 |
3374519994 ps |
| T725 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.234324124 |
|
|
Jul 13 07:55:46 PM PDT 24 |
Jul 13 08:03:12 PM PDT 24 |
4348535810 ps |
| T1221 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.770554685 |
|
|
Jul 13 07:46:18 PM PDT 24 |
Jul 13 07:58:01 PM PDT 24 |
4241149284 ps |
| T1222 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.816042413 |
|
|
Jul 13 07:44:23 PM PDT 24 |
Jul 13 10:50:11 PM PDT 24 |
58970058170 ps |
| T1223 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3999252661 |
|
|
Jul 13 07:46:28 PM PDT 24 |
Jul 13 07:49:05 PM PDT 24 |
3253655916 ps |
| T1224 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.695666635 |
|
|
Jul 13 08:07:37 PM PDT 24 |
Jul 13 08:55:42 PM PDT 24 |
29898163878 ps |
| T833 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.121593652 |
|
|
Jul 13 08:12:58 PM PDT 24 |
Jul 13 08:20:37 PM PDT 24 |
4441261270 ps |
| T1225 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.4250333735 |
|
|
Jul 13 07:54:18 PM PDT 24 |
Jul 13 08:04:21 PM PDT 24 |
5341300220 ps |
| T1226 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3172992973 |
|
|
Jul 13 08:08:42 PM PDT 24 |
Jul 13 08:18:35 PM PDT 24 |
4307230600 ps |
| T1227 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.186380167 |
|
|
Jul 13 07:59:17 PM PDT 24 |
Jul 13 08:11:56 PM PDT 24 |
3998141828 ps |
| T1228 |
/workspace/coverage/default/2.chip_sw_example_concurrency.1786592563 |
|
|
Jul 13 07:58:50 PM PDT 24 |
Jul 13 08:04:06 PM PDT 24 |
3394929880 ps |
| T22 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2595782020 |
|
|
Jul 13 07:45:36 PM PDT 24 |
Jul 13 07:51:24 PM PDT 24 |
3156018817 ps |
| T197 |
/workspace/coverage/default/0.chip_jtag_csr_rw.1520684233 |
|
|
Jul 13 07:36:04 PM PDT 24 |
Jul 13 08:01:16 PM PDT 24 |
10366413690 ps |
| T1229 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1825327965 |
|
|
Jul 13 07:47:29 PM PDT 24 |
Jul 13 07:59:40 PM PDT 24 |
10248463905 ps |
| T363 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.383041916 |
|
|
Jul 13 07:54:09 PM PDT 24 |
Jul 13 08:02:02 PM PDT 24 |
4531365148 ps |
| T313 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.2052883821 |
|
|
Jul 13 07:52:21 PM PDT 24 |
Jul 13 08:13:56 PM PDT 24 |
5860659488 ps |
| T162 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3800723563 |
|
|
Jul 13 07:46:13 PM PDT 24 |
Jul 13 07:57:40 PM PDT 24 |
6165222708 ps |
| T326 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.4107319299 |
|
|
Jul 13 07:48:10 PM PDT 24 |
Jul 13 08:01:37 PM PDT 24 |
4859838114 ps |
| T113 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.551518812 |
|
|
Jul 13 07:45:46 PM PDT 24 |
Jul 13 09:07:38 PM PDT 24 |
23107944483 ps |
| T1230 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2279327163 |
|
|
Jul 13 07:45:47 PM PDT 24 |
Jul 13 07:53:51 PM PDT 24 |
5018182392 ps |
| T1231 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2859165637 |
|
|
Jul 13 07:51:22 PM PDT 24 |
Jul 13 09:34:20 PM PDT 24 |
23464499044 ps |
| T1232 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.457441815 |
|
|
Jul 13 08:01:48 PM PDT 24 |
Jul 13 08:10:13 PM PDT 24 |
4286575590 ps |
| T260 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.966411694 |
|
|
Jul 13 08:01:46 PM PDT 24 |
Jul 13 08:14:38 PM PDT 24 |
4889343400 ps |
| T1233 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3981516230 |
|
|
Jul 13 07:49:51 PM PDT 24 |
Jul 13 08:57:58 PM PDT 24 |
14974826094 ps |
| T712 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.3296213964 |
|
|
Jul 13 08:15:23 PM PDT 24 |
Jul 13 08:24:34 PM PDT 24 |
5966003838 ps |
| T1234 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2304558000 |
|
|
Jul 13 08:03:04 PM PDT 24 |
Jul 13 08:17:24 PM PDT 24 |
6134030589 ps |
| T1235 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.2621133435 |
|
|
Jul 13 07:43:10 PM PDT 24 |
Jul 13 07:54:40 PM PDT 24 |
4138809212 ps |
| T1236 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.2310428352 |
|
|
Jul 13 07:52:22 PM PDT 24 |
Jul 13 09:08:50 PM PDT 24 |
14928871149 ps |
| T1237 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3960389475 |
|
|
Jul 13 07:47:52 PM PDT 24 |
Jul 13 08:07:34 PM PDT 24 |
8063191077 ps |
| T1238 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.969091766 |
|
|
Jul 13 08:12:11 PM PDT 24 |
Jul 13 08:21:51 PM PDT 24 |
4901620280 ps |
| T1239 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1787487068 |
|
|
Jul 13 08:11:43 PM PDT 24 |
Jul 13 08:19:55 PM PDT 24 |
4013312652 ps |
| T445 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2919216960 |
|
|
Jul 13 08:08:00 PM PDT 24 |
Jul 13 08:15:34 PM PDT 24 |
3690044020 ps |
| T1240 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3582524329 |
|
|
Jul 13 08:00:11 PM PDT 24 |
Jul 13 08:24:26 PM PDT 24 |
6751184368 ps |
| T777 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.3693784832 |
|
|
Jul 13 08:12:31 PM PDT 24 |
Jul 13 08:23:10 PM PDT 24 |
5679312608 ps |
| T1241 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1029444508 |
|
|
Jul 13 07:47:55 PM PDT 24 |
Jul 13 07:55:07 PM PDT 24 |
5164843800 ps |
| T1242 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1401333267 |
|
|
Jul 13 08:17:25 PM PDT 24 |
Jul 13 08:28:25 PM PDT 24 |
4815599480 ps |
| T1243 |
/workspace/coverage/default/2.chip_sival_flash_info_access.1523977608 |
|
|
Jul 13 07:58:26 PM PDT 24 |
Jul 13 08:03:46 PM PDT 24 |
3421488008 ps |
| T1244 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.4248889763 |
|
|
Jul 13 07:46:50 PM PDT 24 |
Jul 13 07:52:27 PM PDT 24 |
3046852768 ps |
| T90 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.3557546567 |
|
|
Jul 13 08:11:22 PM PDT 24 |
Jul 13 08:21:49 PM PDT 24 |
5143206696 ps |
| T1245 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2692556891 |
|
|
Jul 13 08:12:18 PM PDT 24 |
Jul 13 09:08:42 PM PDT 24 |
14231456304 ps |
| T1246 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1047447058 |
|
|
Jul 13 08:10:11 PM PDT 24 |
Jul 13 08:22:39 PM PDT 24 |
3850134872 ps |
| T1247 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.4021072659 |
|
|
Jul 13 07:47:00 PM PDT 24 |
Jul 13 08:14:07 PM PDT 24 |
10679541944 ps |
| T754 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.952591757 |
|
|
Jul 13 08:18:23 PM PDT 24 |
Jul 13 08:23:41 PM PDT 24 |
3356214616 ps |
| T181 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3622840927 |
|
|
Jul 13 07:45:32 PM PDT 24 |
Jul 13 09:15:50 PM PDT 24 |
44369062485 ps |
| T1248 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.3474269579 |
|
|
Jul 13 07:59:01 PM PDT 24 |
Jul 13 08:02:36 PM PDT 24 |
2278670048 ps |
| T1249 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.2193020695 |
|
|
Jul 13 07:47:23 PM PDT 24 |
Jul 13 07:55:29 PM PDT 24 |
3326442792 ps |
| T208 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1118133354 |
|
|
Jul 13 07:44:19 PM PDT 24 |
Jul 13 07:55:29 PM PDT 24 |
5016835520 ps |
| T772 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.2029929238 |
|
|
Jul 13 08:18:02 PM PDT 24 |
Jul 13 08:27:13 PM PDT 24 |
3963383412 ps |
| T1250 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3258043408 |
|
|
Jul 13 07:44:55 PM PDT 24 |
Jul 13 07:54:51 PM PDT 24 |
5341642056 ps |
| T1251 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.916434893 |
|
|
Jul 13 08:13:35 PM PDT 24 |
Jul 13 08:22:39 PM PDT 24 |
4864860794 ps |
| T1252 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.732629061 |
|
|
Jul 13 08:00:28 PM PDT 24 |
Jul 13 09:05:41 PM PDT 24 |
28352432339 ps |
| T1253 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.807374469 |
|
|
Jul 13 07:46:16 PM PDT 24 |
Jul 13 07:51:21 PM PDT 24 |
2795040602 ps |
| T1254 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.2827688856 |
|
|
Jul 13 07:58:43 PM PDT 24 |
Jul 13 08:12:51 PM PDT 24 |
5883221100 ps |
| T1255 |
/workspace/coverage/default/1.chip_sw_power_idle_load.2985601475 |
|
|
Jul 13 07:56:28 PM PDT 24 |
Jul 13 08:07:17 PM PDT 24 |
3979823320 ps |
| T1256 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.3006586047 |
|
|
Jul 13 07:56:47 PM PDT 24 |
Jul 13 08:39:32 PM PDT 24 |
11368527520 ps |
| T1257 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1339419039 |
|
|
Jul 13 08:11:34 PM PDT 24 |
Jul 13 08:27:39 PM PDT 24 |
12960085486 ps |
| T318 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1988520761 |
|
|
Jul 13 07:48:31 PM PDT 24 |
Jul 13 08:19:37 PM PDT 24 |
11077052520 ps |
| T1258 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.2611971852 |
|
|
Jul 13 07:48:43 PM PDT 24 |
Jul 13 08:29:26 PM PDT 24 |
10010252930 ps |
| T1259 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2837538706 |
|
|
Jul 13 07:49:08 PM PDT 24 |
Jul 13 08:42:45 PM PDT 24 |
11229787287 ps |
| T1260 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3102944819 |
|
|
Jul 13 08:16:59 PM PDT 24 |
Jul 13 08:26:39 PM PDT 24 |
4562510140 ps |
| T14 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.856652404 |
|
|
Jul 13 07:44:24 PM PDT 24 |
Jul 13 07:53:20 PM PDT 24 |
4955356440 ps |
| T1261 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.3431073356 |
|
|
Jul 13 07:42:38 PM PDT 24 |
Jul 13 07:47:08 PM PDT 24 |
2920106044 ps |
| T1262 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.199945408 |
|
|
Jul 13 07:49:55 PM PDT 24 |
Jul 13 08:09:26 PM PDT 24 |
7204395840 ps |
| T1263 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.336556798 |
|
|
Jul 13 07:46:56 PM PDT 24 |
Jul 13 10:52:54 PM PDT 24 |
58940753806 ps |
| T1264 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2822130964 |
|
|
Jul 13 07:59:57 PM PDT 24 |
Jul 13 08:06:27 PM PDT 24 |
3857031072 ps |
| T1265 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2095075591 |
|
|
Jul 13 07:53:34 PM PDT 24 |
Jul 13 09:04:58 PM PDT 24 |
14364204890 ps |
| T1266 |
/workspace/coverage/default/2.chip_tap_straps_dev.2207186794 |
|
|
Jul 13 08:04:17 PM PDT 24 |
Jul 13 08:06:42 PM PDT 24 |
2251525110 ps |
| T164 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.955282956 |
|
|
Jul 13 07:46:57 PM PDT 24 |
Jul 13 07:57:49 PM PDT 24 |
5196633560 ps |
| T1267 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.1677282267 |
|
|
Jul 13 08:14:19 PM PDT 24 |
Jul 13 08:27:29 PM PDT 24 |
6269084064 ps |
| T1268 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.924159500 |
|
|
Jul 13 07:44:08 PM PDT 24 |
Jul 13 07:53:43 PM PDT 24 |
17932307240 ps |
| T1269 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2992675696 |
|
|
Jul 13 08:03:19 PM PDT 24 |
Jul 13 08:10:55 PM PDT 24 |
7421230200 ps |
| T1270 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.69266634 |
|
|
Jul 13 07:47:38 PM PDT 24 |
Jul 13 08:15:34 PM PDT 24 |
15067102609 ps |
| T158 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1240741964 |
|
|
Jul 13 07:51:07 PM PDT 24 |
Jul 13 07:53:11 PM PDT 24 |
2913256932 ps |
| T194 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.1383763557 |
|
|
Jul 13 08:00:36 PM PDT 24 |
Jul 13 08:14:44 PM PDT 24 |
6303971520 ps |
| T804 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.16762255 |
|
|
Jul 13 08:15:23 PM PDT 24 |
Jul 13 08:25:03 PM PDT 24 |
5191462284 ps |
| T805 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3257123212 |
|
|
Jul 13 08:13:06 PM PDT 24 |
Jul 13 08:19:18 PM PDT 24 |
3460931824 ps |
| T403 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1924197137 |
|
|
Jul 13 07:44:51 PM PDT 24 |
Jul 13 07:52:16 PM PDT 24 |
3312232027 ps |
| T424 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2924498749 |
|
|
Jul 13 08:07:36 PM PDT 24 |
Jul 13 08:30:31 PM PDT 24 |
20517001940 ps |
| T1271 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.4157123069 |
|
|
Jul 13 07:57:46 PM PDT 24 |
Jul 13 08:00:28 PM PDT 24 |
2968291152 ps |
| T1272 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.244585517 |
|
|
Jul 13 08:02:58 PM PDT 24 |
Jul 13 09:10:10 PM PDT 24 |
15438600629 ps |
| T811 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.1676801260 |
|
|
Jul 13 08:11:01 PM PDT 24 |
Jul 13 08:23:16 PM PDT 24 |
5522310830 ps |
| T1273 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1249817283 |
|
|
Jul 13 07:47:33 PM PDT 24 |
Jul 13 07:54:33 PM PDT 24 |
3184504872 ps |
| T1274 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.4065554171 |
|
|
Jul 13 07:59:58 PM PDT 24 |
Jul 13 08:10:48 PM PDT 24 |
4214931488 ps |
| T1275 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1817215814 |
|
|
Jul 13 07:57:47 PM PDT 24 |
Jul 13 08:02:59 PM PDT 24 |
2355913032 ps |
| T195 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.3075984458 |
|
|
Jul 13 07:48:59 PM PDT 24 |
Jul 13 08:02:19 PM PDT 24 |
6615576489 ps |
| T1276 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3917311001 |
|
|
Jul 13 07:53:35 PM PDT 24 |
Jul 13 08:41:29 PM PDT 24 |
11229398189 ps |
| T1277 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3948821723 |
|
|
Jul 13 07:43:41 PM PDT 24 |
Jul 13 08:07:34 PM PDT 24 |
8562168152 ps |
| T1278 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1518425994 |
|
|
Jul 13 07:47:59 PM PDT 24 |
Jul 13 07:54:13 PM PDT 24 |
3133209361 ps |
| T1279 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2030295800 |
|
|
Jul 13 07:48:08 PM PDT 24 |
Jul 13 08:09:22 PM PDT 24 |
11479484842 ps |
| T1280 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.279696729 |
|
|
Jul 13 07:42:46 PM PDT 24 |
Jul 13 07:46:58 PM PDT 24 |
2995118376 ps |
| T1281 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.882515580 |
|
|
Jul 13 07:43:36 PM PDT 24 |
Jul 13 08:15:02 PM PDT 24 |
20854663067 ps |
| T1282 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3174186252 |
|
|
Jul 13 08:03:21 PM PDT 24 |
Jul 13 08:13:19 PM PDT 24 |
4703910710 ps |
| T1283 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.2112381636 |
|
|
Jul 13 08:05:06 PM PDT 24 |
Jul 13 08:18:15 PM PDT 24 |
4610933992 ps |
| T261 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.3251764519 |
|
|
Jul 13 08:14:33 PM PDT 24 |
Jul 13 08:24:23 PM PDT 24 |
4869520020 ps |
| T327 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.1840486184 |
|
|
Jul 13 08:03:50 PM PDT 24 |
Jul 13 08:16:20 PM PDT 24 |
4339784172 ps |
| T1284 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.3766573817 |
|
|
Jul 13 08:11:59 PM PDT 24 |
Jul 13 08:27:35 PM PDT 24 |
5244303670 ps |
| T1285 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3112708879 |
|
|
Jul 13 08:02:39 PM PDT 24 |
Jul 13 08:10:15 PM PDT 24 |
3940437122 ps |
| T1286 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.4172447214 |
|
|
Jul 13 07:46:26 PM PDT 24 |
Jul 13 08:11:38 PM PDT 24 |
8086984096 ps |
| T23 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.965562946 |
|
|
Jul 13 07:44:00 PM PDT 24 |
Jul 13 07:49:00 PM PDT 24 |
3346922831 ps |
| T446 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.253750724 |
|
|
Jul 13 08:10:35 PM PDT 24 |
Jul 13 08:22:30 PM PDT 24 |
5458608520 ps |
| T788 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.947128312 |
|
|
Jul 13 08:15:47 PM PDT 24 |
Jul 13 08:22:21 PM PDT 24 |
4171779012 ps |
| T1287 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.1659879291 |
|
|
Jul 13 08:15:49 PM PDT 24 |
Jul 13 08:24:27 PM PDT 24 |
5754884800 ps |
| T1288 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.4246977146 |
|
|
Jul 13 07:52:49 PM PDT 24 |
Jul 13 08:08:15 PM PDT 24 |
7465432889 ps |
| T1289 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3375920645 |
|
|
Jul 13 07:52:59 PM PDT 24 |
Jul 13 09:50:28 PM PDT 24 |
22516091530 ps |
| T238 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.4084489466 |
|
|
Jul 13 07:46:52 PM PDT 24 |
Jul 13 09:42:17 PM PDT 24 |
49129256500 ps |
| T1290 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1064730131 |
|
|
Jul 13 07:41:59 PM PDT 24 |
Jul 13 07:53:41 PM PDT 24 |
9211589137 ps |
| T129 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1703471252 |
|
|
Jul 13 08:04:17 PM PDT 24 |
Jul 13 08:11:55 PM PDT 24 |
4983227376 ps |
| T1291 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1348145690 |
|
|
Jul 13 07:51:38 PM PDT 24 |
Jul 13 08:36:20 PM PDT 24 |
12791109720 ps |
| T1292 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.131462342 |
|
|
Jul 13 08:04:38 PM PDT 24 |
Jul 13 08:34:50 PM PDT 24 |
26474658437 ps |
| T370 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.1298606215 |
|
|
Jul 13 08:11:20 PM PDT 24 |
Jul 13 08:23:19 PM PDT 24 |
5599185980 ps |
| T1293 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2200399807 |
|
|
Jul 13 08:15:46 PM PDT 24 |
Jul 13 08:21:08 PM PDT 24 |
3151669670 ps |
| T1294 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.620243985 |
|
|
Jul 13 08:12:44 PM PDT 24 |
Jul 13 08:19:10 PM PDT 24 |
3817430956 ps |
| T51 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.770872986 |
|
|
Jul 13 07:59:22 PM PDT 24 |
Jul 13 08:04:57 PM PDT 24 |
3543454975 ps |
| T11 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.858351584 |
|
|
Jul 13 08:05:25 PM PDT 24 |
Jul 13 08:13:38 PM PDT 24 |
5150672422 ps |
| T1295 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1808312833 |
|
|
Jul 13 07:43:30 PM PDT 24 |
Jul 13 07:46:33 PM PDT 24 |
2933699970 ps |
| T1296 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3582413881 |
|
|
Jul 13 07:49:44 PM PDT 24 |
Jul 13 07:59:15 PM PDT 24 |
7408992732 ps |
| T1297 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1629397492 |
|
|
Jul 13 07:52:24 PM PDT 24 |
Jul 13 07:56:14 PM PDT 24 |
3589742581 ps |
| T1298 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.312270620 |
|
|
Jul 13 08:10:20 PM PDT 24 |
Jul 13 08:21:48 PM PDT 24 |
3910697192 ps |
| T533 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2012798358 |
|
|
Jul 13 08:07:21 PM PDT 24 |
Jul 13 08:17:42 PM PDT 24 |
4755206886 ps |
| T1299 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.406275329 |
|
|
Jul 13 07:52:38 PM PDT 24 |
Jul 13 08:02:43 PM PDT 24 |
5707078160 ps |
| T1300 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.911249414 |
|
|
Jul 13 07:41:54 PM PDT 24 |
Jul 13 07:46:07 PM PDT 24 |
3464390470 ps |
| T1301 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1290689302 |
|
|
Jul 13 08:13:31 PM PDT 24 |
Jul 13 08:19:47 PM PDT 24 |
4113101874 ps |
| T1302 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3000858459 |
|
|
Jul 13 07:52:31 PM PDT 24 |
Jul 13 08:04:37 PM PDT 24 |
4566039226 ps |
| T1303 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3691342740 |
|
|
Jul 13 07:43:43 PM PDT 24 |
Jul 13 07:48:33 PM PDT 24 |
3225561204 ps |
| T1304 |
/workspace/coverage/default/0.chip_tap_straps_dev.703302788 |
|
|
Jul 13 07:43:03 PM PDT 24 |
Jul 13 08:07:53 PM PDT 24 |
14366934535 ps |
| T1305 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.2765360260 |
|
|
Jul 13 07:44:57 PM PDT 24 |
Jul 13 09:11:44 PM PDT 24 |
18405040176 ps |
| T1306 |
/workspace/coverage/default/1.chip_sw_example_flash.1719503109 |
|
|
Jul 13 07:47:57 PM PDT 24 |
Jul 13 07:52:57 PM PDT 24 |
3376267932 ps |
| T1307 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2708874926 |
|
|
Jul 13 07:50:53 PM PDT 24 |
Jul 13 07:54:59 PM PDT 24 |
2386790388 ps |
| T1308 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2434291291 |
|
|
Jul 13 07:46:29 PM PDT 24 |
Jul 13 07:58:26 PM PDT 24 |
5419130828 ps |
| T663 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.51187004 |
|
|
Jul 13 07:45:21 PM PDT 24 |
Jul 13 07:54:15 PM PDT 24 |
5168770575 ps |
| T1309 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1050751022 |
|
|
Jul 13 08:11:24 PM PDT 24 |
Jul 13 08:19:28 PM PDT 24 |
4307324132 ps |
| T1310 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3861764043 |
|
|
Jul 13 07:51:03 PM PDT 24 |
Jul 13 08:57:44 PM PDT 24 |
15194560168 ps |
| T1311 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1195849981 |
|
|
Jul 13 07:45:14 PM PDT 24 |
Jul 13 07:50:35 PM PDT 24 |
3103797625 ps |
| T1312 |
/workspace/coverage/default/1.chip_tap_straps_prod.2177718056 |
|
|
Jul 13 07:53:33 PM PDT 24 |
Jul 13 07:55:58 PM PDT 24 |
1974358460 ps |
| T1313 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.708978313 |
|
|
Jul 13 08:01:44 PM PDT 24 |
Jul 13 08:35:50 PM PDT 24 |
29608237684 ps |
| T1314 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.558313527 |
|
|
Jul 13 08:01:17 PM PDT 24 |
Jul 13 08:13:36 PM PDT 24 |
18910008644 ps |
| T364 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3116951332 |
|
|
Jul 13 07:43:56 PM PDT 24 |
Jul 13 07:53:31 PM PDT 24 |
7166336700 ps |
| T48 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1483824633 |
|
|
Jul 13 07:46:17 PM PDT 24 |
Jul 13 07:55:00 PM PDT 24 |
5850419558 ps |
| T796 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.556699836 |
|
|
Jul 13 08:11:12 PM PDT 24 |
Jul 13 08:21:54 PM PDT 24 |
5582377250 ps |
| T1315 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.2174354551 |
|
|
Jul 13 07:57:55 PM PDT 24 |
Jul 13 08:01:14 PM PDT 24 |
2385135936 ps |
| T1316 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1301973730 |
|
|
Jul 13 07:47:17 PM PDT 24 |
Jul 13 08:00:10 PM PDT 24 |
3618781428 ps |
| T233 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.866616319 |
|
|
Jul 13 08:04:07 PM PDT 24 |
Jul 13 09:21:20 PM PDT 24 |
18177707364 ps |
| T787 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.994254736 |
|
|
Jul 13 08:12:43 PM PDT 24 |
Jul 13 08:24:52 PM PDT 24 |
5364992488 ps |
| T1317 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.809462221 |
|
|
Jul 13 07:48:52 PM PDT 24 |
Jul 13 07:56:07 PM PDT 24 |
5870222192 ps |
| T1318 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3040486907 |
|
|
Jul 13 07:56:14 PM PDT 24 |
Jul 13 08:00:46 PM PDT 24 |
3065835299 ps |
| T1319 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1448498671 |
|
|
Jul 13 07:56:53 PM PDT 24 |
Jul 13 08:02:01 PM PDT 24 |
3305437194 ps |
| T1320 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.417760374 |
|
|
Jul 13 07:43:33 PM PDT 24 |
Jul 13 08:01:29 PM PDT 24 |
5466501256 ps |
| T1321 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2127909277 |
|
|
Jul 13 08:05:27 PM PDT 24 |
Jul 14 12:52:23 AM PDT 24 |
113780638058 ps |
| T287 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.529333765 |
|
|
Jul 13 07:46:05 PM PDT 24 |
Jul 13 07:51:44 PM PDT 24 |
3658276828 ps |
| T1322 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.1190455685 |
|
|
Jul 13 07:51:02 PM PDT 24 |
Jul 13 07:56:41 PM PDT 24 |
2960450976 ps |
| T406 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.980350705 |
|
|
Jul 13 08:04:33 PM PDT 24 |
Jul 13 08:14:09 PM PDT 24 |
5501254406 ps |
| T381 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.660997739 |
|
|
Jul 13 07:43:34 PM PDT 24 |
Jul 13 07:57:12 PM PDT 24 |
5868721974 ps |
| T1323 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1733856532 |
|
|
Jul 13 08:04:24 PM PDT 24 |
Jul 13 08:15:24 PM PDT 24 |
5913318836 ps |
| T1324 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.2224108204 |
|
|
Jul 13 07:45:34 PM PDT 24 |
Jul 13 08:10:43 PM PDT 24 |
8403428836 ps |
| T779 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.500880978 |
|
|
Jul 13 08:17:55 PM PDT 24 |
Jul 13 08:24:41 PM PDT 24 |
3370313720 ps |
| T1325 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2979314096 |
|
|
Jul 13 07:45:12 PM PDT 24 |
Jul 13 08:13:42 PM PDT 24 |
10881339262 ps |
| T1326 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.3070476689 |
|
|
Jul 13 07:50:12 PM PDT 24 |
Jul 13 07:54:27 PM PDT 24 |
2895090680 ps |
| T322 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2904332279 |
|
|
Jul 13 07:50:31 PM PDT 24 |
Jul 13 08:16:01 PM PDT 24 |
6841667920 ps |
| T1327 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2960005371 |
|
|
Jul 13 08:00:02 PM PDT 24 |
Jul 13 08:11:08 PM PDT 24 |
4213171640 ps |
| T1328 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.3720842846 |
|
|
Jul 13 07:58:46 PM PDT 24 |
Jul 13 08:09:35 PM PDT 24 |
4547310792 ps |
| T1329 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3436016606 |
|
|
Jul 13 08:04:57 PM PDT 24 |
Jul 13 08:09:12 PM PDT 24 |
2832819464 ps |
| T165 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1341545375 |
|
|
Jul 13 08:06:25 PM PDT 24 |
Jul 13 08:15:22 PM PDT 24 |
4470432490 ps |
| T1330 |
/workspace/coverage/default/4.chip_tap_straps_prod.972313030 |
|
|
Jul 13 08:07:31 PM PDT 24 |
Jul 13 08:32:50 PM PDT 24 |
13086540642 ps |
| T1331 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3299129128 |
|
|
Jul 13 07:48:52 PM PDT 24 |
Jul 13 07:53:07 PM PDT 24 |
3276697512 ps |
| T797 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3468495443 |
|
|
Jul 13 08:16:08 PM PDT 24 |
Jul 13 08:21:53 PM PDT 24 |
3532793444 ps |
| T1332 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.991628650 |
|
|
Jul 13 07:48:53 PM PDT 24 |
Jul 13 08:07:48 PM PDT 24 |
4755664724 ps |
| T336 |
/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.203514528 |
|
|
Jul 13 07:44:27 PM PDT 24 |
Jul 13 07:50:25 PM PDT 24 |
3497956362 ps |
| T1333 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.4070555791 |
|
|
Jul 13 07:46:07 PM PDT 24 |
Jul 13 07:50:07 PM PDT 24 |
2847146088 ps |
| T824 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.2758966959 |
|
|
Jul 13 08:15:46 PM PDT 24 |
Jul 13 08:26:31 PM PDT 24 |
4887032392 ps |
| T1334 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3508527160 |
|
|
Jul 13 07:46:28 PM PDT 24 |
Jul 13 07:56:08 PM PDT 24 |
3939837780 ps |
| T193 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2878088433 |
|
|
Jul 13 07:44:23 PM PDT 24 |
Jul 13 07:55:31 PM PDT 24 |
5056791948 ps |
| T1335 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.29515062 |
|
|
Jul 13 08:13:33 PM PDT 24 |
Jul 13 08:21:28 PM PDT 24 |
4050360880 ps |
| T1336 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3242298971 |
|
|
Jul 13 07:57:46 PM PDT 24 |
Jul 13 08:06:52 PM PDT 24 |
6397618036 ps |
| T832 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.762322562 |
|
|
Jul 13 08:17:33 PM PDT 24 |
Jul 13 08:27:42 PM PDT 24 |
5499788934 ps |
| T818 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.689083258 |
|
|
Jul 13 08:09:05 PM PDT 24 |
Jul 13 08:16:34 PM PDT 24 |
3673800728 ps |
| T1337 |
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.3622029359 |
|
|
Jul 13 08:07:16 PM PDT 24 |
Jul 13 09:34:02 PM PDT 24 |
18394125400 ps |
| T813 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1919596757 |
|
|
Jul 13 08:11:04 PM PDT 24 |
Jul 13 08:17:26 PM PDT 24 |
3949759246 ps |
| T751 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.122413838 |
|
|
Jul 13 08:13:54 PM PDT 24 |
Jul 13 08:23:31 PM PDT 24 |
5708158632 ps |
| T44 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1734405815 |
|
|
Jul 13 07:42:06 PM PDT 24 |
Jul 13 07:48:24 PM PDT 24 |
3472263928 ps |
| T1338 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.1059564671 |
|
|
Jul 13 07:48:31 PM PDT 24 |
Jul 13 07:53:57 PM PDT 24 |
3395685752 ps |
| T1339 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1480390573 |
|
|
Jul 13 07:46:31 PM PDT 24 |
Jul 13 07:57:17 PM PDT 24 |
6520744140 ps |
| T1340 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.275384584 |
|
|
Jul 13 08:03:09 PM PDT 24 |
Jul 13 08:18:16 PM PDT 24 |
8886542830 ps |
| T138 |
/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2319603427 |
|
|
Jul 13 08:05:30 PM PDT 24 |
Jul 13 08:45:05 PM PDT 24 |
17439514198 ps |
| T407 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.960119414 |
|
|
Jul 13 07:54:47 PM PDT 24 |
Jul 13 08:03:14 PM PDT 24 |
4469923460 ps |
| T758 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.115527434 |
|
|
Jul 13 08:13:30 PM PDT 24 |
Jul 13 08:20:58 PM PDT 24 |
4014065090 ps |
| T1341 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.390373744 |
|
|
Jul 13 07:47:59 PM PDT 24 |
Jul 13 07:52:29 PM PDT 24 |
2882998600 ps |
| T198 |
/workspace/coverage/default/1.chip_jtag_mem_access.3051630492 |
|
|
Jul 13 07:45:33 PM PDT 24 |
Jul 13 08:13:27 PM PDT 24 |
13733609364 ps |
| T1342 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.617114740 |
|
|
Jul 13 07:45:01 PM PDT 24 |
Jul 13 07:53:12 PM PDT 24 |
5719177840 ps |
| T1343 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3919774099 |
|
|
Jul 13 07:47:21 PM PDT 24 |
Jul 13 07:56:11 PM PDT 24 |
5393054288 ps |
| T1344 |
/workspace/coverage/default/3.chip_tap_straps_dev.1659669994 |
|
|
Jul 13 08:07:37 PM PDT 24 |
Jul 13 08:31:17 PM PDT 24 |
11934040602 ps |
| T1345 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.14386574 |
|
|
Jul 13 07:51:08 PM PDT 24 |
Jul 13 08:08:36 PM PDT 24 |
11899254832 ps |
| T1346 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.2825506853 |
|
|
Jul 13 07:46:21 PM PDT 24 |
Jul 13 07:55:25 PM PDT 24 |
10483696976 ps |
| T1347 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1020958889 |
|
|
Jul 13 08:05:17 PM PDT 24 |
Jul 13 08:09:46 PM PDT 24 |
2650546052 ps |
| T1348 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.167980752 |
|
|
Jul 13 08:01:07 PM PDT 24 |
Jul 13 08:17:12 PM PDT 24 |
9523798840 ps |
| T1349 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1620429941 |
|
|
Jul 13 08:01:34 PM PDT 24 |
Jul 13 08:11:20 PM PDT 24 |
10007196260 ps |
| T1350 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.579859542 |
|
|
Jul 13 08:02:28 PM PDT 24 |
Jul 13 08:31:44 PM PDT 24 |
8033655668 ps |
| T1351 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2642177272 |
|
|
Jul 13 07:44:30 PM PDT 24 |
Jul 13 07:48:32 PM PDT 24 |
2281915261 ps |
| T1352 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.55391835 |
|
|
Jul 13 07:47:46 PM PDT 24 |
Jul 13 08:08:51 PM PDT 24 |
6584719920 ps |
| T262 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.568449795 |
|
|
Jul 13 08:14:52 PM PDT 24 |
Jul 13 08:29:44 PM PDT 24 |
5162005648 ps |
| T1353 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.757290059 |
|
|
Jul 13 08:02:37 PM PDT 24 |
Jul 13 08:14:39 PM PDT 24 |
6012325035 ps |
| T1354 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.549115190 |
|
|
Jul 13 08:06:21 PM PDT 24 |
Jul 13 08:16:13 PM PDT 24 |
4777102384 ps |
| T1355 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1796086300 |
|
|
Jul 13 07:43:45 PM PDT 24 |
Jul 13 08:24:46 PM PDT 24 |
13374586791 ps |
| T1356 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.28827209 |
|
|
Jul 13 08:01:36 PM PDT 24 |
Jul 13 09:36:01 PM PDT 24 |
50865603935 ps |
| T1357 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.2432776017 |
|
|
Jul 13 07:49:36 PM PDT 24 |
Jul 13 08:18:36 PM PDT 24 |
6859462724 ps |
| T1358 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2846898520 |
|
|
Jul 13 08:03:31 PM PDT 24 |
Jul 13 08:10:12 PM PDT 24 |
3559528904 ps |
| T678 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.412984537 |
|
|
Jul 13 07:52:11 PM PDT 24 |
Jul 13 08:01:36 PM PDT 24 |
4642807740 ps |
| T1359 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3520966682 |
|
|
Jul 13 08:11:06 PM PDT 24 |
Jul 13 08:22:17 PM PDT 24 |
3927496240 ps |
| T667 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.844101613 |
|
|
Jul 13 07:50:12 PM PDT 24 |
Jul 13 08:00:22 PM PDT 24 |
3694863720 ps |
| T801 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2984481179 |
|
|
Jul 13 08:13:53 PM PDT 24 |
Jul 13 08:21:24 PM PDT 24 |
3395138054 ps |
| T349 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2420393806 |
|
|
Jul 13 08:04:38 PM PDT 24 |
Jul 13 08:09:37 PM PDT 24 |
3341890795 ps |
| T1360 |
/workspace/coverage/default/0.chip_sw_hmac_oneshot.3922833113 |
|
|
Jul 13 07:48:34 PM PDT 24 |
Jul 13 07:53:45 PM PDT 24 |
3020786612 ps |
| T1361 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1357974650 |
|
|
Jul 13 07:44:44 PM PDT 24 |
Jul 13 07:56:51 PM PDT 24 |
9480961416 ps |
| T791 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2913812703 |
|
|
Jul 13 08:14:15 PM PDT 24 |
Jul 13 08:20:33 PM PDT 24 |
3732796600 ps |
| T1362 |
/workspace/coverage/default/2.chip_sw_power_idle_load.2674078068 |
|
|
Jul 13 08:04:37 PM PDT 24 |
Jul 13 08:17:04 PM PDT 24 |
4261643230 ps |
| T1363 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2217839117 |
|
|
Jul 13 07:52:32 PM PDT 24 |
Jul 13 08:02:59 PM PDT 24 |
5464759286 ps |
| T1364 |
/workspace/coverage/default/0.chip_sw_hmac_multistream.1490913515 |
|
|
Jul 13 07:44:28 PM PDT 24 |
Jul 13 08:18:23 PM PDT 24 |
7578999376 ps |
| T1365 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.1539345009 |
|
|
Jul 13 08:01:57 PM PDT 24 |
Jul 13 08:09:28 PM PDT 24 |
4096107506 ps |