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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.01 95.41 93.61 95.49 94.41 97.53 99.60


Total test records in report: 2907
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T2763 /workspace/coverage/cover_reg_top/46.xbar_stress_all.2919588568 Jul 14 07:36:10 PM PDT 24 Jul 14 07:39:32 PM PDT 24 5697456129 ps
T2764 /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2052098084 Jul 14 07:41:13 PM PDT 24 Jul 14 07:43:21 PM PDT 24 355994010 ps
T2765 /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.482939279 Jul 14 07:28:31 PM PDT 24 Jul 14 07:28:39 PM PDT 24 49492609 ps
T2766 /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2706874611 Jul 14 07:29:49 PM PDT 24 Jul 14 07:30:18 PM PDT 24 295604259 ps
T2767 /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.139552606 Jul 14 07:30:58 PM PDT 24 Jul 14 07:35:06 PM PDT 24 21848807802 ps
T2768 /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.2204856417 Jul 14 07:44:25 PM PDT 24 Jul 14 07:50:05 PM PDT 24 21526061010 ps
T2769 /workspace/coverage/cover_reg_top/19.xbar_stress_all.3073816121 Jul 14 07:31:16 PM PDT 24 Jul 14 07:39:39 PM PDT 24 12914714311 ps
T2770 /workspace/coverage/cover_reg_top/92.xbar_same_source.478769118 Jul 14 07:43:17 PM PDT 24 Jul 14 07:44:30 PM PDT 24 2633454568 ps
T2771 /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.1146406051 Jul 14 07:30:21 PM PDT 24 Jul 14 07:38:10 PM PDT 24 43255496525 ps
T2772 /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.3706306825 Jul 14 07:27:13 PM PDT 24 Jul 14 07:27:34 PM PDT 24 215886704 ps
T2773 /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.3040591770 Jul 14 07:41:21 PM PDT 24 Jul 14 08:00:29 PM PDT 24 56325033777 ps
T2774 /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.4067557551 Jul 14 07:36:11 PM PDT 24 Jul 14 07:36:33 PM PDT 24 517106129 ps
T2775 /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.4198191051 Jul 14 07:39:49 PM PDT 24 Jul 14 07:53:28 PM PDT 24 46186134550 ps
T476 /workspace/coverage/cover_reg_top/14.chip_csr_rw.2960683450 Jul 14 07:30:15 PM PDT 24 Jul 14 07:35:06 PM PDT 24 3854381368 ps
T2776 /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.2186193876 Jul 14 07:42:59 PM PDT 24 Jul 14 07:45:35 PM PDT 24 498196235 ps
T2777 /workspace/coverage/cover_reg_top/6.xbar_error_random.159120440 Jul 14 07:28:27 PM PDT 24 Jul 14 07:28:52 PM PDT 24 231139875 ps
T2778 /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.4250457395 Jul 14 07:42:18 PM PDT 24 Jul 14 07:42:55 PM PDT 24 90670067 ps
T630 /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.2103197107 Jul 14 07:33:20 PM PDT 24 Jul 14 07:41:30 PM PDT 24 13915935571 ps
T2779 /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.2181766509 Jul 14 07:41:56 PM PDT 24 Jul 14 07:44:12 PM PDT 24 7629906131 ps
T2780 /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.1566934170 Jul 14 07:43:10 PM PDT 24 Jul 14 07:43:16 PM PDT 24 59210147 ps
T2781 /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.1967977154 Jul 14 07:27:20 PM PDT 24 Jul 14 07:42:49 PM PDT 24 83200260165 ps
T2782 /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1207110774 Jul 14 07:27:01 PM PDT 24 Jul 14 07:32:58 PM PDT 24 8862518404 ps
T2783 /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.2330338895 Jul 14 07:32:43 PM PDT 24 Jul 14 07:38:13 PM PDT 24 3577421422 ps
T2784 /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.223897001 Jul 14 07:36:46 PM PDT 24 Jul 14 07:37:20 PM PDT 24 62852358 ps
T2785 /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.3963636941 Jul 14 07:34:22 PM PDT 24 Jul 14 07:35:54 PM PDT 24 8455035282 ps
T2786 /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.2440472592 Jul 14 07:43:51 PM PDT 24 Jul 14 07:44:03 PM PDT 24 120144193 ps
T2787 /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.2429345999 Jul 14 07:28:10 PM PDT 24 Jul 14 07:28:18 PM PDT 24 36638906 ps
T2788 /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.2647189128 Jul 14 07:33:53 PM PDT 24 Jul 14 07:34:05 PM PDT 24 96912153 ps
T2789 /workspace/coverage/cover_reg_top/30.xbar_same_source.1181054990 Jul 14 07:33:13 PM PDT 24 Jul 14 07:34:38 PM PDT 24 2548451008 ps
T2790 /workspace/coverage/cover_reg_top/58.xbar_same_source.2896459878 Jul 14 07:38:12 PM PDT 24 Jul 14 07:38:57 PM PDT 24 523241521 ps
T2791 /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.1149015777 Jul 14 07:32:12 PM PDT 24 Jul 14 07:33:47 PM PDT 24 455925078 ps
T2792 /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.4067255095 Jul 14 07:35:20 PM PDT 24 Jul 14 07:38:18 PM PDT 24 427243608 ps
T2793 /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.2589030504 Jul 14 07:31:21 PM PDT 24 Jul 14 07:40:39 PM PDT 24 49808794270 ps
T2794 /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.3234924635 Jul 14 07:30:43 PM PDT 24 Jul 14 08:07:02 PM PDT 24 14809445415 ps
T2795 /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.919593029 Jul 14 07:33:34 PM PDT 24 Jul 14 07:34:08 PM PDT 24 373478148 ps
T2796 /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3420453795 Jul 14 07:42:38 PM PDT 24 Jul 14 07:43:37 PM PDT 24 356187949 ps
T2797 /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.52458892 Jul 14 07:42:23 PM PDT 24 Jul 14 07:44:09 PM PDT 24 9621750245 ps
T2798 /workspace/coverage/cover_reg_top/85.xbar_random.162044116 Jul 14 07:42:23 PM PDT 24 Jul 14 07:42:59 PM PDT 24 1020761447 ps
T2799 /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.36389284 Jul 14 07:32:21 PM PDT 24 Jul 14 07:37:53 PM PDT 24 20066260737 ps
T2800 /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.2083363640 Jul 14 07:36:40 PM PDT 24 Jul 14 07:46:48 PM PDT 24 61163523600 ps
T2801 /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.2728654224 Jul 14 07:37:04 PM PDT 24 Jul 14 07:39:41 PM PDT 24 4548566877 ps
T2802 /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.4232500183 Jul 14 07:43:23 PM PDT 24 Jul 14 07:44:13 PM PDT 24 1130307883 ps
T2803 /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3510393302 Jul 14 07:29:39 PM PDT 24 Jul 14 07:35:23 PM PDT 24 19552839746 ps
T2804 /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.3141453731 Jul 14 07:27:17 PM PDT 24 Jul 14 07:28:09 PM PDT 24 1311366263 ps
T2805 /workspace/coverage/cover_reg_top/73.xbar_access_same_device.1729307195 Jul 14 07:40:31 PM PDT 24 Jul 14 07:41:14 PM PDT 24 818702348 ps
T2806 /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.3987040998 Jul 14 07:37:47 PM PDT 24 Jul 14 07:49:11 PM PDT 24 59466388963 ps
T2807 /workspace/coverage/cover_reg_top/23.xbar_random.2248641893 Jul 14 07:31:56 PM PDT 24 Jul 14 07:32:18 PM PDT 24 213838063 ps
T2808 /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.1733394252 Jul 14 07:33:09 PM PDT 24 Jul 14 07:34:55 PM PDT 24 9651129621 ps
T2809 /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.2853869522 Jul 14 07:39:57 PM PDT 24 Jul 14 07:46:19 PM PDT 24 21481713863 ps
T2810 /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.3300345738 Jul 14 07:42:58 PM PDT 24 Jul 14 07:43:49 PM PDT 24 1282774550 ps
T2811 /workspace/coverage/cover_reg_top/32.xbar_access_same_device.2750615031 Jul 14 07:33:33 PM PDT 24 Jul 14 07:34:31 PM PDT 24 1636110945 ps
T2812 /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3151333383 Jul 14 07:38:58 PM PDT 24 Jul 14 07:42:08 PM PDT 24 988141677 ps
T2813 /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.815268690 Jul 14 07:43:55 PM PDT 24 Jul 14 07:44:01 PM PDT 24 18046876 ps
T2814 /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.879014308 Jul 14 07:34:01 PM PDT 24 Jul 14 07:34:29 PM PDT 24 630810418 ps
T2815 /workspace/coverage/cover_reg_top/96.xbar_random.1458230547 Jul 14 07:43:51 PM PDT 24 Jul 14 07:44:34 PM PDT 24 513063516 ps
T2816 /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.1189040331 Jul 14 07:33:46 PM PDT 24 Jul 14 07:42:37 PM PDT 24 31537326454 ps
T2817 /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.854528931 Jul 14 07:44:02 PM PDT 24 Jul 14 07:45:38 PM PDT 24 277058186 ps
T2818 /workspace/coverage/cover_reg_top/96.xbar_same_source.756033522 Jul 14 07:43:55 PM PDT 24 Jul 14 07:44:21 PM PDT 24 778354413 ps
T2819 /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1030994116 Jul 14 07:30:18 PM PDT 24 Jul 14 07:44:00 PM PDT 24 9369330840 ps
T2820 /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3035089154 Jul 14 07:30:58 PM PDT 24 Jul 14 07:32:33 PM PDT 24 5330279442 ps
T2821 /workspace/coverage/cover_reg_top/9.xbar_same_source.4138214959 Jul 14 07:29:14 PM PDT 24 Jul 14 07:29:42 PM PDT 24 806632627 ps
T2822 /workspace/coverage/cover_reg_top/79.xbar_access_same_device.554711421 Jul 14 07:41:24 PM PDT 24 Jul 14 07:42:46 PM PDT 24 2081736797 ps
T2823 /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.2760992231 Jul 14 07:42:16 PM PDT 24 Jul 14 07:43:53 PM PDT 24 5869335129 ps
T2824 /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.3107187848 Jul 14 07:39:04 PM PDT 24 Jul 14 07:57:24 PM PDT 24 92174544087 ps
T2825 /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.2358133676 Jul 14 07:39:31 PM PDT 24 Jul 14 07:58:35 PM PDT 24 65914612412 ps
T2826 /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.1483441908 Jul 14 07:41:40 PM PDT 24 Jul 14 07:42:40 PM PDT 24 1371901924 ps
T2827 /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.1349612662 Jul 14 07:35:34 PM PDT 24 Jul 14 07:37:31 PM PDT 24 6164419573 ps
T2828 /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.1564474781 Jul 14 07:36:31 PM PDT 24 Jul 14 07:37:09 PM PDT 24 895467361 ps
T2829 /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.4058124036 Jul 14 07:30:24 PM PDT 24 Jul 14 07:43:55 PM PDT 24 17488287801 ps
T2830 /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.4064997073 Jul 14 07:35:42 PM PDT 24 Jul 14 07:37:28 PM PDT 24 6109910667 ps
T2831 /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.4038688149 Jul 14 07:29:45 PM PDT 24 Jul 14 07:30:52 PM PDT 24 5661997535 ps
T2832 /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.4105882292 Jul 14 07:33:06 PM PDT 24 Jul 14 07:33:23 PM PDT 24 355471111 ps
T2833 /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.1129687435 Jul 14 07:31:34 PM PDT 24 Jul 14 07:31:41 PM PDT 24 51462422 ps
T2834 /workspace/coverage/cover_reg_top/33.xbar_access_same_device.4251027871 Jul 14 07:33:45 PM PDT 24 Jul 14 07:35:22 PM PDT 24 2567433741 ps
T2835 /workspace/coverage/cover_reg_top/43.xbar_smoke.184187502 Jul 14 07:35:26 PM PDT 24 Jul 14 07:35:35 PM PDT 24 173770156 ps
T2836 /workspace/coverage/cover_reg_top/40.xbar_random.2644347121 Jul 14 07:34:59 PM PDT 24 Jul 14 07:35:11 PM PDT 24 194607186 ps
T2837 /workspace/coverage/cover_reg_top/65.xbar_smoke.4140345252 Jul 14 07:39:12 PM PDT 24 Jul 14 07:39:18 PM PDT 24 39723992 ps
T2838 /workspace/coverage/cover_reg_top/75.xbar_random.826517671 Jul 14 07:40:45 PM PDT 24 Jul 14 07:41:16 PM PDT 24 874873914 ps
T2839 /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.3703801978 Jul 14 07:27:16 PM PDT 24 Jul 14 07:28:32 PM PDT 24 2189901086 ps
T2840 /workspace/coverage/cover_reg_top/41.xbar_error_random.3408680539 Jul 14 07:35:20 PM PDT 24 Jul 14 07:36:34 PM PDT 24 2162743338 ps
T2841 /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.4275130573 Jul 14 07:32:27 PM PDT 24 Jul 14 07:32:34 PM PDT 24 35656439 ps
T2842 /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.1477186247 Jul 14 07:32:48 PM PDT 24 Jul 14 07:45:58 PM PDT 24 45256043832 ps
T2843 /workspace/coverage/cover_reg_top/3.xbar_smoke.439381786 Jul 14 07:27:27 PM PDT 24 Jul 14 07:27:38 PM PDT 24 224130274 ps
T2844 /workspace/coverage/cover_reg_top/27.xbar_error_random.3011313474 Jul 14 07:32:51 PM PDT 24 Jul 14 07:33:53 PM PDT 24 1783161541 ps
T2845 /workspace/coverage/cover_reg_top/39.xbar_access_same_device.2858984830 Jul 14 07:34:50 PM PDT 24 Jul 14 07:36:45 PM PDT 24 2668903017 ps
T2846 /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.357757369 Jul 14 07:43:11 PM PDT 24 Jul 14 07:43:47 PM PDT 24 804670862 ps
T2847 /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.712946721 Jul 14 07:40:29 PM PDT 24 Jul 14 07:40:44 PM PDT 24 128809037 ps
T2848 /workspace/coverage/cover_reg_top/7.xbar_smoke.1328861442 Jul 14 07:28:31 PM PDT 24 Jul 14 07:28:37 PM PDT 24 38272357 ps
T2849 /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.3698486678 Jul 14 07:32:46 PM PDT 24 Jul 14 07:44:05 PM PDT 24 59108389475 ps
T2850 /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.3264033603 Jul 14 07:31:17 PM PDT 24 Jul 14 07:31:39 PM PDT 24 22329653 ps
T2851 /workspace/coverage/cover_reg_top/54.xbar_stress_all.3401765692 Jul 14 07:37:39 PM PDT 24 Jul 14 07:38:02 PM PDT 24 274269720 ps
T2852 /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.684502701 Jul 14 07:38:19 PM PDT 24 Jul 14 07:55:23 PM PDT 24 55162875705 ps
T2853 /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.2149208337 Jul 14 07:31:57 PM PDT 24 Jul 14 07:33:10 PM PDT 24 6634720772 ps
T2854 /workspace/coverage/cover_reg_top/77.xbar_smoke.1476711068 Jul 14 07:40:55 PM PDT 24 Jul 14 07:41:04 PM PDT 24 194926313 ps
T2855 /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.1556108432 Jul 14 07:42:04 PM PDT 24 Jul 14 07:43:46 PM PDT 24 9345339030 ps
T2856 /workspace/coverage/cover_reg_top/85.xbar_stress_all.2600800971 Jul 14 07:42:25 PM PDT 24 Jul 14 07:45:21 PM PDT 24 2256785505 ps
T2857 /workspace/coverage/cover_reg_top/80.xbar_smoke.1254995802 Jul 14 07:41:34 PM PDT 24 Jul 14 07:41:41 PM PDT 24 55167660 ps
T2858 /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.1221807597 Jul 14 07:40:45 PM PDT 24 Jul 14 07:42:12 PM PDT 24 4929832995 ps
T2859 /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.4237653310 Jul 14 07:42:58 PM PDT 24 Jul 14 07:48:40 PM PDT 24 10104314853 ps
T2860 /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2940509377 Jul 14 07:33:21 PM PDT 24 Jul 14 07:33:28 PM PDT 24 51693052 ps
T2861 /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.556438077 Jul 14 07:30:19 PM PDT 24 Jul 14 07:30:26 PM PDT 24 68730159 ps
T2862 /workspace/coverage/cover_reg_top/80.xbar_stress_all.3893644973 Jul 14 07:41:35 PM PDT 24 Jul 14 07:44:14 PM PDT 24 1847158825 ps
T2863 /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.965572239 Jul 14 07:29:42 PM PDT 24 Jul 14 07:31:24 PM PDT 24 5434320637 ps
T2864 /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.4083249084 Jul 14 07:32:12 PM PDT 24 Jul 14 07:33:24 PM PDT 24 2435655301 ps
T2865 /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.1838791383 Jul 14 07:42:52 PM PDT 24 Jul 14 07:47:01 PM PDT 24 15422281947 ps
T2866 /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1074301375 Jul 14 07:27:03 PM PDT 24 Jul 14 07:33:51 PM PDT 24 23409190735 ps
T2867 /workspace/coverage/cover_reg_top/17.xbar_access_same_device.3281046518 Jul 14 07:30:53 PM PDT 24 Jul 14 07:31:46 PM PDT 24 668042960 ps
T2868 /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.575858382 Jul 14 07:28:45 PM PDT 24 Jul 14 07:29:48 PM PDT 24 869126934 ps
T2869 /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.663072360 Jul 14 07:39:25 PM PDT 24 Jul 14 07:52:51 PM PDT 24 72263461753 ps
T2870 /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.859601501 Jul 14 07:28:01 PM PDT 24 Jul 14 07:28:50 PM PDT 24 569131979 ps
T2871 /workspace/coverage/cover_reg_top/17.chip_csr_rw.3809297704 Jul 14 07:30:57 PM PDT 24 Jul 14 07:40:01 PM PDT 24 6416698600 ps
T2872 /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.3891228308 Jul 14 07:42:38 PM PDT 24 Jul 14 07:45:39 PM PDT 24 1560984259 ps
T2873 /workspace/coverage/cover_reg_top/36.xbar_smoke.1905763212 Jul 14 07:34:23 PM PDT 24 Jul 14 07:34:32 PM PDT 24 171195438 ps
T2874 /workspace/coverage/cover_reg_top/6.xbar_access_same_device.2032426183 Jul 14 07:28:17 PM PDT 24 Jul 14 07:29:00 PM PDT 24 899238091 ps
T2875 /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.2074546126 Jul 14 07:42:03 PM PDT 24 Jul 14 07:42:25 PM PDT 24 216980730 ps
T2876 /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.1196737395 Jul 14 07:41:28 PM PDT 24 Jul 14 07:44:42 PM PDT 24 666056976 ps
T2877 /workspace/coverage/cover_reg_top/18.xbar_stress_all.4230404981 Jul 14 07:31:05 PM PDT 24 Jul 14 07:42:57 PM PDT 24 17677128226 ps
T2878 /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.4241231356 Jul 14 07:28:52 PM PDT 24 Jul 14 07:30:04 PM PDT 24 4182459406 ps
T2879 /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.3453134674 Jul 14 07:39:09 PM PDT 24 Jul 14 07:40:31 PM PDT 24 7516670538 ps
T2880 /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.2418213089 Jul 14 07:27:31 PM PDT 24 Jul 14 07:45:05 PM PDT 24 91713923738 ps
T2881 /workspace/coverage/cover_reg_top/10.xbar_smoke.3454327361 Jul 14 07:29:20 PM PDT 24 Jul 14 07:29:27 PM PDT 24 46791361 ps
T2882 /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.516549548 Jul 14 07:39:25 PM PDT 24 Jul 14 07:45:44 PM PDT 24 7059822130 ps
T2883 /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.4210982415 Jul 14 07:41:49 PM PDT 24 Jul 14 07:58:10 PM PDT 24 82738565332 ps
T2884 /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.106084513 Jul 14 07:31:00 PM PDT 24 Jul 14 07:31:23 PM PDT 24 77720553 ps
T2885 /workspace/coverage/cover_reg_top/2.chip_csr_rw.2691800541 Jul 14 07:27:26 PM PDT 24 Jul 14 07:36:23 PM PDT 24 5630752759 ps
T2886 /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.1405042980 Jul 14 07:39:24 PM PDT 24 Jul 14 07:39:46 PM PDT 24 499471989 ps
T2887 /workspace/coverage/cover_reg_top/45.xbar_stress_all.1015422269 Jul 14 07:36:02 PM PDT 24 Jul 14 07:36:46 PM PDT 24 544963403 ps
T2888 /workspace/coverage/cover_reg_top/28.xbar_same_source.2026897548 Jul 14 07:32:58 PM PDT 24 Jul 14 07:33:17 PM PDT 24 239725878 ps
T2889 /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1934311799 Jul 14 07:29:28 PM PDT 24 Jul 14 07:31:20 PM PDT 24 10110353114 ps
T2890 /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3100276255 Jul 14 07:30:15 PM PDT 24 Jul 14 07:30:38 PM PDT 24 23399049 ps
T2891 /workspace/coverage/cover_reg_top/88.xbar_access_same_device.3140989921 Jul 14 07:42:44 PM PDT 24 Jul 14 07:44:41 PM PDT 24 2888344574 ps
T2892 /workspace/coverage/cover_reg_top/91.xbar_random.3123713048 Jul 14 07:43:06 PM PDT 24 Jul 14 07:43:36 PM PDT 24 344276498 ps
T2893 /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.2925136364 Jul 14 07:33:53 PM PDT 24 Jul 14 07:35:06 PM PDT 24 4073624957 ps
T2894 /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.913781550 Jul 14 07:29:55 PM PDT 24 Jul 14 07:35:18 PM PDT 24 9400547717 ps
T2895 /workspace/coverage/cover_reg_top/44.xbar_same_source.2996733796 Jul 14 07:35:47 PM PDT 24 Jul 14 07:36:23 PM PDT 24 444740720 ps
T2896 /workspace/coverage/cover_reg_top/13.xbar_same_source.1582526555 Jul 14 07:30:05 PM PDT 24 Jul 14 07:30:14 PM PDT 24 68811725 ps
T2897 /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.4048734551 Jul 14 07:39:17 PM PDT 24 Jul 14 08:13:32 PM PDT 24 102734752981 ps
T2898 /workspace/coverage/cover_reg_top/56.xbar_error_random.377117942 Jul 14 07:37:48 PM PDT 24 Jul 14 07:37:57 PM PDT 24 130719549 ps
T2899 /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.2466140641 Jul 14 07:31:00 PM PDT 24 Jul 14 07:31:06 PM PDT 24 37929135 ps
T2900 /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.3012811786 Jul 14 07:42:31 PM PDT 24 Jul 14 07:51:14 PM PDT 24 12873399604 ps
T2901 /workspace/coverage/cover_reg_top/71.xbar_smoke.2117280396 Jul 14 07:40:02 PM PDT 24 Jul 14 07:40:11 PM PDT 24 206332344 ps
T2902 /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.729884160 Jul 14 07:40:18 PM PDT 24 Jul 14 07:41:46 PM PDT 24 4603656751 ps
T2903 /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.3285801526 Jul 14 07:40:45 PM PDT 24 Jul 14 07:54:16 PM PDT 24 74902475216 ps
T2904 /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.2718073337 Jul 14 07:36:00 PM PDT 24 Jul 14 07:36:31 PM PDT 24 301135624 ps
T2905 /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.3340826278 Jul 14 07:39:41 PM PDT 24 Jul 14 08:10:46 PM PDT 24 103071856734 ps
T2906 /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.1979746041 Jul 14 07:43:54 PM PDT 24 Jul 14 07:44:08 PM PDT 24 269786125 ps
T2907 /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.1470251175 Jul 14 07:30:34 PM PDT 24 Jul 14 08:09:24 PM PDT 24 15210619317 ps
T39 /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3221052529 Jul 14 08:19:32 PM PDT 24 Jul 14 08:24:34 PM PDT 24 5618918640 ps
T40 /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2475144409 Jul 14 08:19:30 PM PDT 24 Jul 14 08:22:58 PM PDT 24 4516365711 ps
T41 /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.217865062 Jul 14 08:19:23 PM PDT 24 Jul 14 08:22:48 PM PDT 24 3845012625 ps
T187 /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.856632003 Jul 14 08:19:43 PM PDT 24 Jul 14 08:23:54 PM PDT 24 5169645608 ps
T188 /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.320414827 Jul 14 08:19:35 PM PDT 24 Jul 14 08:24:57 PM PDT 24 4433394030 ps
T189 /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2556779911 Jul 14 08:19:50 PM PDT 24 Jul 14 08:24:05 PM PDT 24 3738328250 ps
T190 /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1692315846 Jul 14 08:19:24 PM PDT 24 Jul 14 08:23:36 PM PDT 24 4340450778 ps
T194 /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1164335796 Jul 14 08:19:24 PM PDT 24 Jul 14 08:25:03 PM PDT 24 4758585585 ps
T191 /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1814822430 Jul 14 08:19:27 PM PDT 24 Jul 14 08:23:43 PM PDT 24 4433036970 ps
T195 /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.562520973 Jul 14 08:19:29 PM PDT 24 Jul 14 08:22:59 PM PDT 24 4617881576 ps

Test location /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1194275139
Short name T71
Test name
Test status
Simulation time 21959589877 ps
CPU time 2879.66 seconds
Started Jul 14 08:13:28 PM PDT 24
Finished Jul 14 09:01:29 PM PDT 24
Peak memory 609932 kb
Host smart-58bddff4-326e-426d-9303-cd5f4044673d
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194275139
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.1194275139
Directory /workspace/2.chip_sw_ast_clk_rst_inputs/latest

Test location /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.2558148662
Short name T380
Test name
Test status
Simulation time 16194613800 ps
CPU time 2048.45 seconds
Started Jul 14 07:28:46 PM PDT 24
Finished Jul 14 08:02:55 PM PDT 24
Peak memory 593272 kb
Host smart-63714786-8d81-4411-a8e7-e1d200b2d7dd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558148662 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.2558148662
Directory /workspace/8.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all.2817473740
Short name T486
Test name
Test status
Simulation time 15577500321 ps
CPU time 596.7 seconds
Started Jul 14 07:43:33 PM PDT 24
Finished Jul 14 07:53:30 PM PDT 24
Peak memory 575604 kb
Host smart-063e08aa-cbd6-42f1-88c6-60e20ba844c1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817473740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.2817473740
Directory /workspace/93.xbar_stress_all/latest

Test location /workspace/coverage/default/1.chip_plic_all_irqs_0.43434633
Short name T321
Test name
Test status
Simulation time 6649248880 ps
CPU time 1428.49 seconds
Started Jul 14 08:02:35 PM PDT 24
Finished Jul 14 08:26:24 PM PDT 24
Peak memory 608232 kb
Host smart-02acbaa5-1863-4383-8190-ab1d1192ed92
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43434633 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_plic_all_irqs_0.43434633
Directory /workspace/1.chip_plic_all_irqs_0/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1834119023
Short name T87
Test name
Test status
Simulation time 100178152397 ps
CPU time 1925.26 seconds
Started Jul 14 07:35:33 PM PDT 24
Finished Jul 14 08:07:39 PM PDT 24
Peak memory 575500 kb
Host smart-d2760d3a-c495-47fe-95d7-6ae30ac4bf6e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834119023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_
device_slow_rsp.1834119023
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1066642283
Short name T488
Test name
Test status
Simulation time 121670753509 ps
CPU time 2303.91 seconds
Started Jul 14 07:30:51 PM PDT 24
Finished Jul 14 08:09:16 PM PDT 24
Peak memory 575544 kb
Host smart-c2f2cb39-4416-4b09-a2d7-f31a0f74b95f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066642283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_
device_slow_rsp.1066642283
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3221052529
Short name T39
Test name
Test status
Simulation time 5618918640 ps
CPU time 300.9 seconds
Started Jul 14 08:19:32 PM PDT 24
Finished Jul 14 08:24:34 PM PDT 24
Peak memory 649104 kb
Host smart-91606a9c-8fb3-4f7d-95be-4490f233276d
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221052529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 8.chip_padctrl_attributes.3221052529
Directory /workspace/8.chip_padctrl_attributes/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3555013652
Short name T153
Test name
Test status
Simulation time 12411960276 ps
CPU time 3428.53 seconds
Started Jul 14 07:54:48 PM PDT 24
Finished Jul 14 08:51:58 PM PDT 24
Peak memory 610364 kb
Host smart-8eb15ab1-9c01-4f0a-b81b-cec7f8ed0bf9
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35550
13652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.3555013652
Directory /workspace/0.chip_sw_keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.4056693713
Short name T6
Test name
Test status
Simulation time 11192843286 ps
CPU time 2418.83 seconds
Started Jul 14 08:21:03 PM PDT 24
Finished Jul 14 09:01:23 PM PDT 24
Peak memory 610016 kb
Host smart-bd283d89-4fb1-4506-ad47-f5703f441841
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056693713 -assert nopostproc +UVM_TESTNAME=chip_base_te
st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.rom_e2e_asm_init_test_unlocked0.4056693713
Directory /workspace/2.rom_e2e_asm_init_test_unlocked0/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.2271108260
Short name T823
Test name
Test status
Simulation time 141725285257 ps
CPU time 2544.18 seconds
Started Jul 14 07:43:30 PM PDT 24
Finished Jul 14 08:25:55 PM PDT 24
Peak memory 575500 kb
Host smart-8434761f-250a-4d95-b393-b156c723c9a0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271108260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_
device_slow_rsp.2271108260
Directory /workspace/93.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.3608663129
Short name T551
Test name
Test status
Simulation time 92560612907 ps
CPU time 1835.48 seconds
Started Jul 14 07:28:23 PM PDT 24
Finished Jul 14 07:59:00 PM PDT 24
Peak memory 575564 kb
Host smart-0d8698bb-d1d8-4553-833c-7c511c30065d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608663129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d
evice_slow_rsp.3608663129
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2833892275
Short name T21
Test name
Test status
Simulation time 2524503402 ps
CPU time 248.54 seconds
Started Jul 14 07:51:57 PM PDT 24
Finished Jul 14 07:56:07 PM PDT 24
Peak memory 608660 kb
Host smart-fc1da7a0-a550-4f87-ad72-09ee94aca2ca
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833
892275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.2833892275
Directory /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2061202962
Short name T166
Test name
Test status
Simulation time 48534160184 ps
CPU time 5079.31 seconds
Started Jul 14 07:59:51 PM PDT 24
Finished Jul 14 09:24:32 PM PDT 24
Peak memory 619888 kb
Host smart-94ff3524-63fc-4954-adbc-7f21fe80b199
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d
evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061202962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi
p_sw_lc_walkthrough_prod.2061202962
Directory /workspace/1.chip_sw_lc_walkthrough_prod/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3861261542
Short name T19
Test name
Test status
Simulation time 78651775924 ps
CPU time 13874.4 seconds
Started Jul 14 07:52:51 PM PDT 24
Finished Jul 14 11:44:09 PM PDT 24
Peak memory 635572 kb
Host smart-3f899701-97c3-4487-95b3-53bb0fe4191c
User root
Command /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3861261542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.3861261542
Directory /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest

Test location /workspace/coverage/default/2.chip_jtag_csr_rw.2655452295
Short name T64
Test name
Test status
Simulation time 8995005670 ps
CPU time 953.58 seconds
Started Jul 14 08:05:14 PM PDT 24
Finished Jul 14 08:21:08 PM PDT 24
Peak memory 607312 kb
Host smart-ccb086ab-f2be-40e8-aa80-dd89b2cd8210
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655452295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c
hip_jtag_csr_rw.2655452295
Directory /workspace/2.chip_jtag_csr_rw/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3566440537
Short name T183
Test name
Test status
Simulation time 3715665040 ps
CPU time 413.93 seconds
Started Jul 14 07:56:57 PM PDT 24
Finished Jul 14 08:03:52 PM PDT 24
Peak memory 608668 kb
Host smart-a5af689a-b0ab-4795-9aaa-f3aec305aa5a
User root
Command /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3566440537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.3566440537
Directory /workspace/0.chip_sw_rv_core_ibex_address_translation/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4111518400
Short name T1
Test name
Test status
Simulation time 7194112572 ps
CPU time 389.6 seconds
Started Jul 14 08:02:45 PM PDT 24
Finished Jul 14 08:09:15 PM PDT 24
Peak memory 609680 kb
Host smart-e3ac181c-904e-4799-ac66-1949bf90ae47
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111518400 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4111518400
Directory /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/0.chip_plic_all_irqs_20.2724990830
Short name T322
Test name
Test status
Simulation time 5194529720 ps
CPU time 1074.87 seconds
Started Jul 14 07:57:47 PM PDT 24
Finished Jul 14 08:15:43 PM PDT 24
Peak memory 608692 kb
Host smart-99619429-e84d-4c64-ac3c-df2df3f8142f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724990830 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.chip_plic_all_irqs_20.2724990830
Directory /workspace/0.chip_plic_all_irqs_20/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.1331367063
Short name T545
Test name
Test status
Simulation time 49102615859 ps
CPU time 956.51 seconds
Started Jul 14 07:40:50 PM PDT 24
Finished Jul 14 07:56:47 PM PDT 24
Peak memory 575556 kb
Host smart-be42dda6-d2f3-4c14-aa9f-91f463eea6f8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331367063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_
device_slow_rsp.1331367063
Directory /workspace/75.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1911399206
Short name T4
Test name
Test status
Simulation time 4886310856 ps
CPU time 445.06 seconds
Started Jul 14 08:04:26 PM PDT 24
Finished Jul 14 08:11:51 PM PDT 24
Peak memory 609128 kb
Host smart-136d1c12-0f93-4211-8a01-2ecb2c6d3edf
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1911399206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.1911399206
Directory /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.74717502
Short name T134
Test name
Test status
Simulation time 6559526475 ps
CPU time 442.71 seconds
Started Jul 14 07:27:35 PM PDT 24
Finished Jul 14 07:34:59 PM PDT 24
Peak memory 660840 kb
Host smart-eb15dbf3-6c15-4a11-8288-b111f5090575
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74717502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_res
et.74717502
Directory /workspace/3.chip_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_error_random.2784455555
Short name T85
Test name
Test status
Simulation time 2371723144 ps
CPU time 85.54 seconds
Started Jul 14 07:34:17 PM PDT 24
Finished Jul 14 07:35:43 PM PDT 24
Peak memory 575332 kb
Host smart-45f5b8e5-2ed7-444f-a012-019ccef0ae62
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784455555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2784455555
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3439747470
Short name T92
Test name
Test status
Simulation time 9945365068 ps
CPU time 1287.89 seconds
Started Jul 14 07:56:37 PM PDT 24
Finished Jul 14 08:18:06 PM PDT 24
Peak memory 610292 kb
Host smart-75df9b2e-e5d7-4d7f-b253-8ec96e3a29c9
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler
_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439747470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han
dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.chip_sw_alert_handler_lpg_sleep_mode_pings.3439747470
Directory /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_access_same_device.1451172724
Short name T836
Test name
Test status
Simulation time 2615561098 ps
CPU time 100.92 seconds
Started Jul 14 07:42:50 PM PDT 24
Finished Jul 14 07:44:32 PM PDT 24
Peak memory 575404 kb
Host smart-eed7b590-656f-4c4f-bb58-0235b70e3ce5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451172724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device
.1451172724
Directory /workspace/89.xbar_access_same_device/latest

Test location /workspace/coverage/default/2.chip_sw_gpio.3014484173
Short name T36
Test name
Test status
Simulation time 4158990781 ps
CPU time 516.09 seconds
Started Jul 14 08:07:58 PM PDT 24
Finished Jul 14 08:16:35 PM PDT 24
Peak memory 608684 kb
Host smart-5ac7c0fe-6e7a-4000-bd6c-e4256ba69ff9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014484173 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.chip_sw_gpio.3014484173
Directory /workspace/2.chip_sw_gpio/latest

Test location /workspace/coverage/default/0.chip_plic_all_irqs_10.3164581107
Short name T154
Test name
Test status
Simulation time 3703937084 ps
CPU time 410.35 seconds
Started Jul 14 07:52:09 PM PDT 24
Finished Jul 14 07:59:00 PM PDT 24
Peak memory 609220 kb
Host smart-f560f51b-c141-41dd-a37d-40fb7bf3234b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164581107 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.chip_plic_all_irqs_10.3164581107
Directory /workspace/0.chip_plic_all_irqs_10/latest

Test location /workspace/coverage/cover_reg_top/15.chip_tl_errors.1811795831
Short name T552
Test name
Test status
Simulation time 4082142249 ps
CPU time 384.13 seconds
Started Jul 14 07:30:20 PM PDT 24
Finished Jul 14 07:36:45 PM PDT 24
Peak memory 603888 kb
Host smart-9eb41035-1182-47a4-83ad-be61658c7b8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811795831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.1811795831
Directory /workspace/15.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.1929778747
Short name T448
Test name
Test status
Simulation time 151286670377 ps
CPU time 2983.57 seconds
Started Jul 14 07:39:44 PM PDT 24
Finished Jul 14 08:29:29 PM PDT 24
Peak memory 575592 kb
Host smart-7f69ed30-1603-418b-8b72-156f9b5e565d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929778747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_
device_slow_rsp.1929778747
Directory /workspace/68.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.868374718
Short name T451
Test name
Test status
Simulation time 2047820132 ps
CPU time 379.66 seconds
Started Jul 14 07:37:41 PM PDT 24
Finished Jul 14 07:44:02 PM PDT 24
Peak memory 575500 kb
Host smart-5be5322e-392b-4781-95b4-53bc0caaa663
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868374718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_
with_rand_reset.868374718
Directory /workspace/55.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.982957484
Short name T832
Test name
Test status
Simulation time 73648065635 ps
CPU time 1336.66 seconds
Started Jul 14 07:42:31 PM PDT 24
Finished Jul 14 08:04:49 PM PDT 24
Peak memory 575568 kb
Host smart-46b50f25-8cf7-4e1c-a822-d1dd0e5e8a83
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982957484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_d
evice_slow_rsp.982957484
Directory /workspace/86.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/0.chip_sw_edn_auto_mode.194897474
Short name T119
Test name
Test status
Simulation time 5064203882 ps
CPU time 1219.01 seconds
Started Jul 14 07:54:48 PM PDT 24
Finished Jul 14 08:15:09 PM PDT 24
Peak memory 608808 kb
Host smart-1c09fd9c-d104-4aef-8117-c9a196d58b37
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc
elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194897474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_a
uto_mode.194897474
Directory /workspace/0.chip_sw_edn_auto_mode/latest

Test location /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.172699660
Short name T169
Test name
Test status
Simulation time 44322650440 ps
CPU time 4885.81 seconds
Started Jul 14 07:55:32 PM PDT 24
Finished Jul 14 09:16:59 PM PDT 24
Peak memory 622020 kb
Host smart-3d96d227-df2d-4586-a2ca-9c0b3f0f0152
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_
rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=172699660 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.172699660
Directory /workspace/1.chip_sw_flash_rma_unlocked/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.33503415
Short name T22
Test name
Test status
Simulation time 3307683202 ps
CPU time 369.62 seconds
Started Jul 14 07:57:43 PM PDT 24
Finished Jul 14 08:03:53 PM PDT 24
Peak memory 608656 kb
Host smart-ab741a3f-2841-4357-80b7-239f9b43d321
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350
3415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.33503415
Directory /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest

Test location /workspace/coverage/default/1.chip_sw_alert_test.1683264292
Short name T66
Test name
Test status
Simulation time 3572200120 ps
CPU time 360.91 seconds
Started Jul 14 08:00:10 PM PDT 24
Finished Jul 14 08:06:12 PM PDT 24
Peak memory 609208 kb
Host smart-aa65555e-d7d3-42b6-8d7e-a798adfdebe2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683264292 -assert nopostproc +UVM_TESTNAME=chip_ba
se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.chip_sw_alert_test.1683264292
Directory /workspace/1.chip_sw_alert_test/latest

Test location /workspace/coverage/default/51.chip_sw_all_escalation_resets.1360355363
Short name T100
Test name
Test status
Simulation time 5006866152 ps
CPU time 712.3 seconds
Started Jul 14 08:22:47 PM PDT 24
Finished Jul 14 08:34:40 PM PDT 24
Peak memory 616212 kb
Host smart-13b2a5b8-aaee-46b7-8e54-ca4f30a49f92
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1360355363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.1360355363
Directory /workspace/51.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3221489933
Short name T90
Test name
Test status
Simulation time 3938636680 ps
CPU time 406.5 seconds
Started Jul 14 08:26:44 PM PDT 24
Finished Jul 14 08:33:31 PM PDT 24
Peak memory 648772 kb
Host smart-0136e5cc-01ff-4aa4-a478-7f5b56f6c61a
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221489933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3221489933
Directory /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/0.rom_e2e_shutdown_output.3335521682
Short name T55
Test name
Test status
Simulation time 25062146072 ps
CPU time 3292.41 seconds
Started Jul 14 07:57:29 PM PDT 24
Finished Jul 14 08:52:22 PM PDT 24
Peak memory 611112 kb
Host smart-f99f96f6-d95a-42bd-bca7-0c63b555c71d
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f
lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335521682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rom_e2e_shutdown_output.3335521682
Directory /workspace/0.rom_e2e_shutdown_output/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.1101213079
Short name T86
Test name
Test status
Simulation time 53282440942 ps
CPU time 584.88 seconds
Started Jul 14 07:34:52 PM PDT 24
Finished Jul 14 07:44:38 PM PDT 24
Peak memory 575460 kb
Host smart-e0f3c507-4704-4403-9282-9e9009107624
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101213079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1101213079
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.871021089
Short name T45
Test name
Test status
Simulation time 3090505840 ps
CPU time 280.76 seconds
Started Jul 14 07:58:06 PM PDT 24
Finished Jul 14 08:02:47 PM PDT 24
Peak memory 608820 kb
Host smart-8f4f2e10-ee75-4be8-a6b5-cb28798829fc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871021089 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.871021089
Directory /workspace/1.chip_sw_spi_host_tx_rx/latest

Test location /workspace/coverage/cover_reg_top/25.chip_tl_errors.2021726901
Short name T559
Test name
Test status
Simulation time 4204755538 ps
CPU time 383.19 seconds
Started Jul 14 07:32:10 PM PDT 24
Finished Jul 14 07:38:33 PM PDT 24
Peak memory 603880 kb
Host smart-ba06b1b5-b67c-48db-a2de-f42c9822290e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021726901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.2021726901
Directory /workspace/25.chip_tl_errors/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3452877499
Short name T127
Test name
Test status
Simulation time 5031252294 ps
CPU time 450.8 seconds
Started Jul 14 07:54:39 PM PDT 24
Finished Jul 14 08:02:10 PM PDT 24
Peak memory 608660 kb
Host smart-e014b341-9766-402e-abd4-4acf07a4e854
User root
Command /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34528774
99 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3452877499
Directory /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.35825406
Short name T23
Test name
Test status
Simulation time 3313024380 ps
CPU time 274.58 seconds
Started Jul 14 08:06:50 PM PDT 24
Finished Jul 14 08:11:25 PM PDT 24
Peak memory 608440 kb
Host smart-647007fd-84cd-44e4-bed4-4eec2a398106
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582
5406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.35825406
Directory /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.939137310
Short name T18
Test name
Test status
Simulation time 8237358510 ps
CPU time 626.91 seconds
Started Jul 14 08:12:53 PM PDT 24
Finished Jul 14 08:23:21 PM PDT 24
Peak memory 609956 kb
Host smart-1af63870-a032-4015-82f4-e72cfd8f8c1e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939137310 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.939137310
Directory /workspace/2.chip_sw_sram_ctrl_execution_main/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pin_retention.3671360134
Short name T3
Test name
Test status
Simulation time 3860713260 ps
CPU time 324.16 seconds
Started Jul 14 08:00:16 PM PDT 24
Finished Jul 14 08:05:42 PM PDT 24
Peak memory 608656 kb
Host smart-10fc275d-ae77-4362-90be-3d6dbde7f597
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671360134 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.3671360134
Directory /workspace/1.chip_sw_sleep_pin_retention/latest

Test location /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2238006685
Short name T275
Test name
Test status
Simulation time 6246972480 ps
CPU time 1106.55 seconds
Started Jul 14 08:16:07 PM PDT 24
Finished Jul 14 08:34:35 PM PDT 24
Peak memory 610272 kb
Host smart-63628d87-8815-4474-81d1-92a2b32aeb6c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2238006685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.2238006685
Directory /workspace/5.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/cover_reg_top/23.chip_tl_errors.2874920862
Short name T639
Test name
Test status
Simulation time 4392515838 ps
CPU time 324.95 seconds
Started Jul 14 07:31:57 PM PDT 24
Finished Jul 14 07:37:22 PM PDT 24
Peak memory 603904 kb
Host smart-c897a09a-b1e0-4cf1-93f4-02cc647f93ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874920862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.2874920862
Directory /workspace/23.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.chip_csr_rw.679197630
Short name T416
Test name
Test status
Simulation time 4761791070 ps
CPU time 444.21 seconds
Started Jul 14 07:30:19 PM PDT 24
Finished Jul 14 07:37:45 PM PDT 24
Peak memory 599052 kb
Host smart-32306e64-3dfd-4259-a343-66269b0b1b1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679197630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.679197630
Directory /workspace/13.chip_csr_rw/latest

Test location /workspace/coverage/default/10.chip_sw_all_escalation_resets.1749683516
Short name T247
Test name
Test status
Simulation time 6017337572 ps
CPU time 751.15 seconds
Started Jul 14 08:20:39 PM PDT 24
Finished Jul 14 08:33:12 PM PDT 24
Peak memory 649496 kb
Host smart-12662171-d5f9-4cce-9fa9-6fecba9726de
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1749683516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.1749683516
Directory /workspace/10.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2829968987
Short name T58
Test name
Test status
Simulation time 11953597575 ps
CPU time 1065.43 seconds
Started Jul 14 08:19:22 PM PDT 24
Finished Jul 14 08:37:08 PM PDT 24
Peak memory 623136 kb
Host smart-bcdec511-63af-41d2-adc7-ebfb0e040881
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829968987 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.2829968987
Directory /workspace/10.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/56.chip_sw_all_escalation_resets.2249518514
Short name T366
Test name
Test status
Simulation time 4972885470 ps
CPU time 586.92 seconds
Started Jul 14 08:24:22 PM PDT 24
Finished Jul 14 08:34:10 PM PDT 24
Peak memory 649288 kb
Host smart-b7d0b27b-43d5-4ad0-a667-5dd084d6abb3
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2249518514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.2249518514
Directory /workspace/56.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3453810491
Short name T115
Test name
Test status
Simulation time 4192221881 ps
CPU time 736.93 seconds
Started Jul 14 08:12:22 PM PDT 24
Finished Jul 14 08:24:40 PM PDT 24
Peak memory 609792 kb
Host smart-6253a95d-9dbf-492d-b1b5-5d70c6bd47a7
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s
w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453810491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3453810491
Directory /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3102925166
Short name T238
Test name
Test status
Simulation time 4233921512 ps
CPU time 415.3 seconds
Started Jul 14 07:57:54 PM PDT 24
Finished Jul 14 08:04:51 PM PDT 24
Peak memory 608804 kb
Host smart-95436eb2-0b69-4f68-9385-c46376f7b9f7
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31
02925166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.3102925166
Directory /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest

Test location /workspace/coverage/default/23.chip_sw_all_escalation_resets.960567894
Short name T264
Test name
Test status
Simulation time 4294099930 ps
CPU time 513.3 seconds
Started Jul 14 08:20:57 PM PDT 24
Finished Jul 14 08:29:31 PM PDT 24
Peak memory 649816 kb
Host smart-82a6019b-9b48-4b97-aa4c-836983acf526
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
960567894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.960567894
Directory /workspace/23.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.63203712
Short name T309
Test name
Test status
Simulation time 4111250852 ps
CPU time 390.07 seconds
Started Jul 14 08:12:04 PM PDT 24
Finished Jul 14 08:18:35 PM PDT 24
Peak memory 648348 kb
Host smart-d890c894-7c90-4f9a-bed8-119e2e3c115f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63203712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_
escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_
alert_handler_lpg_sleep_mode_alerts.63203712
Directory /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1715073901
Short name T177
Test name
Test status
Simulation time 3108533537 ps
CPU time 314.65 seconds
Started Jul 14 08:13:40 PM PDT 24
Finished Jul 14 08:18:56 PM PDT 24
Peak memory 612760 kb
Host smart-1268975c-03e3-41d0-a703-c9bdc45ded9e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715073901 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.1715073901
Directory /workspace/2.chip_sw_sysrst_ctrl_inputs/latest

Test location /workspace/coverage/default/0.chip_plic_all_irqs_0.3941327911
Short name T326
Test name
Test status
Simulation time 5710116680 ps
CPU time 1265.1 seconds
Started Jul 14 07:54:27 PM PDT 24
Finished Jul 14 08:15:33 PM PDT 24
Peak memory 609408 kb
Host smart-26a32b2b-72d2-467f-bb53-e200558651d5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941327911 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_plic_all_irqs_0.3941327911
Directory /workspace/0.chip_plic_all_irqs_0/latest

Test location /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1872239428
Short name T114
Test name
Test status
Simulation time 6964049660 ps
CPU time 1031.53 seconds
Started Jul 14 07:53:35 PM PDT 24
Finished Jul 14 08:10:47 PM PDT 24
Peak memory 610408 kb
Host smart-2d7f984b-efc2-48e5-b8fd-0e030b0fd34d
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e
ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872239428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.1872239428
Directory /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2153820160
Short name T173
Test name
Test status
Simulation time 3504556842 ps
CPU time 138.38 seconds
Started Jul 14 08:00:25 PM PDT 24
Finished Jul 14 08:02:44 PM PDT 24
Peak memory 619460 kb
Host smart-581a4a29-84bd-4b1f-bd28-931074597422
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153820160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.2153820160
Directory /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest

Test location /workspace/coverage/default/2.chip_tap_straps_testunlock0.2101997097
Short name T75
Test name
Test status
Simulation time 3562297287 ps
CPU time 298.25 seconds
Started Jul 14 08:13:09 PM PDT 24
Finished Jul 14 08:18:07 PM PDT 24
Peak memory 620292 kb
Host smart-103b49ec-4932-4f30-b3d4-da5fd91c4ea4
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101997097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.2101997097
Directory /workspace/2.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.1535810101
Short name T713
Test name
Test status
Simulation time 4091184290 ps
CPU time 309.84 seconds
Started Jul 14 07:33:27 PM PDT 24
Finished Jul 14 07:38:37 PM PDT 24
Peak memory 575248 kb
Host smart-53c8feb8-f285-4242-9ab1-293d342a2eca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535810101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al
l_with_reset_error.1535810101
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.522386303
Short name T126
Test name
Test status
Simulation time 7437940920 ps
CPU time 816.47 seconds
Started Jul 14 08:19:51 PM PDT 24
Finished Jul 14 08:33:28 PM PDT 24
Peak memory 610088 kb
Host smart-7ca0c420-b77a-469a-a8b5-7e82f651b911
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52238630
3 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.522386303
Directory /workspace/3.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/cover_reg_top/21.chip_tl_errors.2119412153
Short name T564
Test name
Test status
Simulation time 4868167084 ps
CPU time 354.29 seconds
Started Jul 14 07:31:35 PM PDT 24
Finished Jul 14 07:37:30 PM PDT 24
Peak memory 603924 kb
Host smart-d7440a9f-9797-4fbe-903d-f16e78f39731
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119412153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.2119412153
Directory /workspace/21.chip_tl_errors/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pin_wake.853646589
Short name T9
Test name
Test status
Simulation time 3780472058 ps
CPU time 302.41 seconds
Started Jul 14 07:53:09 PM PDT 24
Finished Jul 14 07:58:12 PM PDT 24
Peak memory 608448 kb
Host smart-9a3e7598-801e-4120-a78e-196b82bdffc8
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853646589 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.853646589
Directory /workspace/0.chip_sw_sleep_pin_wake/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_access_same_device.1875870219
Short name T429
Test name
Test status
Simulation time 3053594452 ps
CPU time 140.43 seconds
Started Jul 14 07:32:04 PM PDT 24
Finished Jul 14 07:34:25 PM PDT 24
Peak memory 575504 kb
Host smart-db6dae74-4b38-4394-9593-87089c365f65
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875870219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device
.1875870219
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/default/3.chip_sw_all_escalation_resets.401492279
Short name T74
Test name
Test status
Simulation time 4931728440 ps
CPU time 684.97 seconds
Started Jul 14 08:19:02 PM PDT 24
Finished Jul 14 08:30:28 PM PDT 24
Peak memory 649324 kb
Host smart-b98ed46f-8041-4050-a3de-efd2b8460a65
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
401492279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.401492279
Directory /workspace/3.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2348011128
Short name T25
Test name
Test status
Simulation time 4376829602 ps
CPU time 504.52 seconds
Started Jul 14 07:52:35 PM PDT 24
Finished Jul 14 08:01:00 PM PDT 24
Peak memory 624316 kb
Host smart-27f8c180-4f56-4853-afb7-b28289a370a7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348011128 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.2348011128
Directory /workspace/0.chip_sw_spi_device_pass_through_collision/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pin_wake.2823628024
Short name T12
Test name
Test status
Simulation time 3365270732 ps
CPU time 229.07 seconds
Started Jul 14 07:55:09 PM PDT 24
Finished Jul 14 07:58:59 PM PDT 24
Peak memory 608404 kb
Host smart-6e25411c-f9bc-4506-ad3c-bcd8ec07303c
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823628024
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.2823628024
Directory /workspace/1.chip_sw_sleep_pin_wake/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_config_host.2060012522
Short name T34
Test name
Test status
Simulation time 7617839704 ps
CPU time 1863.24 seconds
Started Jul 14 07:51:49 PM PDT 24
Finished Jul 14 08:22:53 PM PDT 24
Peak memory 609260 kb
Host smart-7fc4c6e6-b5a3-49aa-9c1c-4a0e29f82841
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20600
12522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.2060012522
Directory /workspace/0.chip_sw_usbdev_config_host/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.2885969828
Short name T1811
Test name
Test status
Simulation time 3007127401 ps
CPU time 399.23 seconds
Started Jul 14 07:39:40 PM PDT 24
Finished Jul 14 07:46:20 PM PDT 24
Peak memory 575536 kb
Host smart-329063ba-ae68-4ea5-af60-ba0221f29925
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885969828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all
_with_rand_reset.2885969828
Directory /workspace/67.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3652466295
Short name T334
Test name
Test status
Simulation time 9067088479 ps
CPU time 1202.11 seconds
Started Jul 14 07:58:35 PM PDT 24
Finished Jul 14 08:18:39 PM PDT 24
Peak memory 622728 kb
Host smart-99604a4b-28bb-4a6c-a9aa-52d22386c9f6
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652466295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.3652466295
Directory /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.1291560022
Short name T673
Test name
Test status
Simulation time 8482058028 ps
CPU time 485.4 seconds
Started Jul 14 07:34:16 PM PDT 24
Finished Jul 14 07:42:22 PM PDT 24
Peak memory 575600 kb
Host smart-ed41b968-a628-4383-9d7c-b99e16133387
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291560022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al
l_with_reset_error.1291560022
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1348617628
Short name T185
Test name
Test status
Simulation time 43075446502 ps
CPU time 5608.7 seconds
Started Jul 14 07:52:22 PM PDT 24
Finished Jul 14 09:25:52 PM PDT 24
Peak memory 621632 kb
Host smart-f7968af2-c6b3-4a40-8ace-e24dcf396573
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_
rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1348617628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.1348617628
Directory /workspace/0.chip_sw_flash_rma_unlocked/latest

Test location /workspace/coverage/default/2.chip_plic_all_irqs_20.698780404
Short name T325
Test name
Test status
Simulation time 4529788080 ps
CPU time 930.91 seconds
Started Jul 14 08:12:16 PM PDT 24
Finished Jul 14 08:27:48 PM PDT 24
Peak memory 609584 kb
Host smart-04edd958-23aa-4995-8b29-274cb4037280
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698780404 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_plic_all_irqs_20.698780404
Directory /workspace/2.chip_plic_all_irqs_20/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.615501026
Short name T130
Test name
Test status
Simulation time 7969673424 ps
CPU time 436.06 seconds
Started Jul 14 07:27:51 PM PDT 24
Finished Jul 14 07:35:08 PM PDT 24
Peak memory 664468 kb
Host smart-54fdbac0-9147-4b70-b9e3-5830f8c883d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615501026 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_re
set.615501026
Directory /workspace/4.chip_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.309096239
Short name T593
Test name
Test status
Simulation time 4961346037 ps
CPU time 434 seconds
Started Jul 14 07:29:16 PM PDT 24
Finished Jul 14 07:36:31 PM PDT 24
Peak memory 575596 kb
Host smart-55a8fc5e-12e7-475c-ba4f-3cfa11d2ef9a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309096239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_w
ith_rand_reset.309096239
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.chip_tl_errors.1657704458
Short name T695
Test name
Test status
Simulation time 4994875100 ps
CPU time 378.32 seconds
Started Jul 14 07:30:56 PM PDT 24
Finished Jul 14 07:37:15 PM PDT 24
Peak memory 603952 kb
Host smart-84669b36-8e95-4b57-811c-e4bbc34c674c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657704458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.1657704458
Directory /workspace/18.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.1277641845
Short name T2241
Test name
Test status
Simulation time 8055013787 ps
CPU time 482.71 seconds
Started Jul 14 07:40:03 PM PDT 24
Finished Jul 14 07:48:07 PM PDT 24
Peak memory 575552 kb
Host smart-e269491d-a529-4ebc-857b-cf6c68396e39
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277641845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all
_with_rand_reset.1277641845
Directory /workspace/70.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.chip_sw_all_escalation_resets.3592042
Short name T1293
Test name
Test status
Simulation time 4554928704 ps
CPU time 633.81 seconds
Started Jul 14 08:19:05 PM PDT 24
Finished Jul 14 08:29:40 PM PDT 24
Peak memory 649872 kb
Host smart-17049678-91dc-47ce-bf67-22884a11f3a4
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3592042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.3592042
Directory /workspace/15.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/2.chip_sw_power_sleep_load.3389888959
Short name T250
Test name
Test status
Simulation time 3785125476 ps
CPU time 341.41 seconds
Started Jul 14 08:13:03 PM PDT 24
Finished Jul 14 08:18:46 PM PDT 24
Peak memory 608456 kb
Host smart-15735404-5a90-46b6-bc76-925565a21ce2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389888959 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.3389888959
Directory /workspace/2.chip_sw_power_sleep_load/latest

Test location /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2195432389
Short name T106
Test name
Test status
Simulation time 7943588300 ps
CPU time 1227.5 seconds
Started Jul 14 08:19:18 PM PDT 24
Finished Jul 14 08:39:46 PM PDT 24
Peak memory 617848 kb
Host smart-76e3a6f9-e837-4366-86da-230ac4ac8127
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2195432389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.2195432389
Directory /workspace/14.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.225539835
Short name T717
Test name
Test status
Simulation time 2855280534 ps
CPU time 361.53 seconds
Started Jul 14 07:41:09 PM PDT 24
Finished Jul 14 07:47:11 PM PDT 24
Peak memory 575552 kb
Host smart-160f5198-c5b4-4ffb-a4f6-2ded887fd152
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225539835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all
_with_reset_error.225539835
Directory /workspace/77.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1502949836
Short name T8
Test name
Test status
Simulation time 3258332730 ps
CPU time 300.75 seconds
Started Jul 14 07:55:22 PM PDT 24
Finished Jul 14 08:00:24 PM PDT 24
Peak memory 619160 kb
Host smart-a03c8ae9-7c19-4997-8631-dd31377d74c5
User root
Command /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1
502949836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.1502949836
Directory /workspace/0.chip_rv_dm_ndm_reset_req/latest

Test location /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.110428399
Short name T132
Test name
Test status
Simulation time 4660731280 ps
CPU time 574.25 seconds
Started Jul 14 08:02:56 PM PDT 24
Finished Jul 14 08:12:31 PM PDT 24
Peak memory 610028 kb
Host smart-0a56b62c-2af0-4c0a-b9bd-fa0ab57993b2
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11042839
9 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.110428399
Directory /workspace/1.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1731500071
Short name T129
Test name
Test status
Simulation time 6080127620 ps
CPU time 653.1 seconds
Started Jul 14 08:12:35 PM PDT 24
Finished Jul 14 08:23:29 PM PDT 24
Peak memory 609712 kb
Host smart-177e3744-0850-45cd-9957-b81cba2e4794
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17315000
71 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.1731500071
Directory /workspace/2.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.431293967
Short name T235
Test name
Test status
Simulation time 23460510063 ps
CPU time 2111.66 seconds
Started Jul 14 07:54:55 PM PDT 24
Finished Jul 14 08:30:08 PM PDT 24
Peak memory 612812 kb
Host smart-e00859be-140b-4c44-bc6d-183b0ebeddcf
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=431293967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.431293967
Directory /workspace/0.chip_sw_flash_init_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1103548072
Short name T137
Test name
Test status
Simulation time 3289976564 ps
CPU time 363.13 seconds
Started Jul 14 07:53:26 PM PDT 24
Finished Jul 14 07:59:29 PM PDT 24
Peak memory 608800 kb
Host smart-2e329f31-7a6e-41b3-ad9f-42b5ae885e28
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11035480
72 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.1103548072
Directory /workspace/0.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.4030558955
Short name T497
Test name
Test status
Simulation time 6366226959 ps
CPU time 862.55 seconds
Started Jul 14 07:37:52 PM PDT 24
Finished Jul 14 07:52:15 PM PDT 24
Peak memory 575560 kb
Host smart-5e7c91f4-f344-4346-a899-f87f43d2f6a0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030558955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all
_with_rand_reset.4030558955
Directory /workspace/56.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2619321115
Short name T69
Test name
Test status
Simulation time 3272600620 ps
CPU time 417.86 seconds
Started Jul 14 07:51:50 PM PDT 24
Finished Jul 14 07:58:49 PM PDT 24
Peak memory 608656 kb
Host smart-0fae2641-6c2e-4bef-bac4-0091b292ea10
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261932
1115 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.2619321115
Directory /workspace/0.chip_sw_usbdev_aon_pullup/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3761247802
Short name T31
Test name
Test status
Simulation time 20221366397 ps
CPU time 3134.48 seconds
Started Jul 14 08:09:24 PM PDT 24
Finished Jul 14 09:01:39 PM PDT 24
Peak memory 610104 kb
Host smart-a44234d1-1175-4773-9310-e7159ea39df7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761247802 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.3761247802
Directory /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.2062447449
Short name T382
Test name
Test status
Simulation time 14621199294 ps
CPU time 1909.69 seconds
Started Jul 14 07:31:00 PM PDT 24
Finished Jul 14 08:02:51 PM PDT 24
Peak memory 593256 kb
Host smart-f434f0e9-0cb6-406c-8b6f-cfaec754a2ae
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062447449 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.2062447449
Directory /workspace/18.chip_same_csr_outstanding/latest

Test location /workspace/coverage/default/2.chip_plic_all_irqs_0.3017350543
Short name T323
Test name
Test status
Simulation time 6217001576 ps
CPU time 1152.59 seconds
Started Jul 14 08:11:38 PM PDT 24
Finished Jul 14 08:30:51 PM PDT 24
Peak memory 609224 kb
Host smart-13bafdb5-0343-49ba-90d3-b5cce4cf10bb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017350543 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_plic_all_irqs_0.3017350543
Directory /workspace/2.chip_plic_all_irqs_0/latest

Test location /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2475144409
Short name T40
Test name
Test status
Simulation time 4516365711 ps
CPU time 207.65 seconds
Started Jul 14 08:19:30 PM PDT 24
Finished Jul 14 08:22:58 PM PDT 24
Peak memory 640332 kb
Host smart-b82f3f28-8244-4ad0-927b-83fd02f18e47
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475144409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 0.chip_padctrl_attributes.2475144409
Directory /workspace/0.chip_padctrl_attributes/latest

Test location /workspace/coverage/default/1.chip_plic_all_irqs_20.2273431764
Short name T324
Test name
Test status
Simulation time 4844302886 ps
CPU time 927.73 seconds
Started Jul 14 08:01:30 PM PDT 24
Finished Jul 14 08:16:58 PM PDT 24
Peak memory 609572 kb
Host smart-5d29a1e1-e7b5-484f-9b33-b8c087bcfbf5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273431764 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.chip_plic_all_irqs_20.2273431764
Directory /workspace/1.chip_plic_all_irqs_20/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3876987738
Short name T61
Test name
Test status
Simulation time 3782611160 ps
CPU time 702.19 seconds
Started Jul 14 07:55:42 PM PDT 24
Finished Jul 14 08:07:26 PM PDT 24
Peak memory 612372 kb
Host smart-b534bb01-9a2b-4031-9cff-1ec9705ddcbd
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876987738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_rma.3876987738
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.4181111476
Short name T347
Test name
Test status
Simulation time 3848902544 ps
CPU time 602.61 seconds
Started Jul 14 08:00:32 PM PDT 24
Finished Jul 14 08:10:35 PM PDT 24
Peak memory 609200 kb
Host smart-6e509a0b-8578-474d-9731-d5f3f0052704
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181111476
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.4181111476
Directory /workspace/1.chip_sw_flash_ctrl_ops/latest

Test location /workspace/coverage/default/2.chip_plic_all_irqs_10.3056672218
Short name T155
Test name
Test status
Simulation time 3690614556 ps
CPU time 525.15 seconds
Started Jul 14 08:12:39 PM PDT 24
Finished Jul 14 08:21:25 PM PDT 24
Peak memory 607996 kb
Host smart-0e2ddb44-182c-473f-97dd-f694a09c975d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056672218 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.chip_plic_all_irqs_10.3056672218
Directory /workspace/2.chip_plic_all_irqs_10/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.2969794837
Short name T846
Test name
Test status
Simulation time 486702685 ps
CPU time 243.49 seconds
Started Jul 14 07:34:42 PM PDT 24
Finished Jul 14 07:38:47 PM PDT 24
Peak memory 575456 kb
Host smart-3968bc83-c649-4425-a438-ab5e1e0006e6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969794837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all
_with_rand_reset.2969794837
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.3162033591
Short name T825
Test name
Test status
Simulation time 145769540573 ps
CPU time 2843.59 seconds
Started Jul 14 07:38:19 PM PDT 24
Finished Jul 14 08:25:43 PM PDT 24
Peak memory 575536 kb
Host smart-251eec4e-b821-4f8d-b986-48a72179d3d1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162033591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_
device_slow_rsp.3162033591
Directory /workspace/59.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3745607424
Short name T162
Test name
Test status
Simulation time 2640089796 ps
CPU time 101.5 seconds
Started Jul 14 07:58:22 PM PDT 24
Finished Jul 14 08:00:05 PM PDT 24
Peak memory 621244 kb
Host smart-480922a2-cfb5-4fef-b016-f5cc0920213a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745607424 -assert nopost
proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.3745607424
Directory /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.929938249
Short name T852
Test name
Test status
Simulation time 9764875599 ps
CPU time 565.29 seconds
Started Jul 14 07:32:00 PM PDT 24
Finished Jul 14 07:41:26 PM PDT 24
Peak memory 575604 kb
Host smart-2e73a006-9f65-4902-8c2f-1f513633a595
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929938249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_
with_rand_reset.929938249
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.4184772773
Short name T257
Test name
Test status
Simulation time 11803963616 ps
CPU time 2341.71 seconds
Started Jul 14 07:56:16 PM PDT 24
Finished Jul 14 08:35:20 PM PDT 24
Peak memory 623156 kb
Host smart-0c3eb0f8-4f94-4a3e-ae24-278f563645b9
User root
Command /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41847
72773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.4184772773
Directory /workspace/0.rom_e2e_jtag_debug_dev/latest

Test location /workspace/coverage/cover_reg_top/14.chip_tl_errors.3652924313
Short name T555
Test name
Test status
Simulation time 3800983594 ps
CPU time 238.31 seconds
Started Jul 14 07:30:04 PM PDT 24
Finished Jul 14 07:34:02 PM PDT 24
Peak memory 603792 kb
Host smart-77a4071a-0569-4bb1-8a2f-86cce0e88041
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652924313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.3652924313
Directory /workspace/14.chip_tl_errors/latest

Test location /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.442799867
Short name T1133
Test name
Test status
Simulation time 42668123800 ps
CPU time 4593.3 seconds
Started Jul 14 08:09:24 PM PDT 24
Finished Jul 14 09:25:59 PM PDT 24
Peak memory 621220 kb
Host smart-5fb64c19-da9d-471a-b9fb-df4c8a00878a
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_
rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=442799867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.442799867
Directory /workspace/2.chip_sw_flash_rma_unlocked/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.4107375797
Short name T231
Test name
Test status
Simulation time 49779211720 ps
CPU time 5342.08 seconds
Started Jul 14 08:10:48 PM PDT 24
Finished Jul 14 09:39:53 PM PDT 24
Peak memory 618860 kb
Host smart-5ee2fa7a-b5cd-4603-830b-5aab1484c02d
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d
evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107375797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi
p_sw_lc_walkthrough_prod.4107375797
Directory /workspace/2.chip_sw_lc_walkthrough_prod/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.164692657
Short name T2279
Test name
Test status
Simulation time 7219658357 ps
CPU time 833.5 seconds
Started Jul 14 07:34:57 PM PDT 24
Finished Jul 14 07:48:51 PM PDT 24
Peak memory 575516 kb
Host smart-1573a394-3b45-4526-b701-45629c65b344
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164692657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_
with_rand_reset.164692657
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.933425358
Short name T308
Test name
Test status
Simulation time 8845169388 ps
CPU time 1783.99 seconds
Started Jul 14 08:19:17 PM PDT 24
Finished Jul 14 08:49:02 PM PDT 24
Peak memory 618516 kb
Host smart-35869c4f-b31e-440e-b9a6-163e66cec8af
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=933425358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.933425358
Directory /workspace/15.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.2052798234
Short name T2497
Test name
Test status
Simulation time 814330716 ps
CPU time 216.54 seconds
Started Jul 14 07:34:37 PM PDT 24
Finished Jul 14 07:38:14 PM PDT 24
Peak memory 575412 kb
Host smart-9284ce79-faa2-43bc-bf32-09eb97b68859
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052798234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al
l_with_reset_error.2052798234
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.516549548
Short name T2882
Test name
Test status
Simulation time 7059822130 ps
CPU time 379.08 seconds
Started Jul 14 07:39:25 PM PDT 24
Finished Jul 14 07:45:44 PM PDT 24
Peak memory 575548 kb
Host smart-5e478e97-ba0e-46fb-8f59-d24b90bd5a50
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516549548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_
with_rand_reset.516549548
Directory /workspace/66.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2343193112
Short name T306
Test name
Test status
Simulation time 3803428866 ps
CPU time 349.29 seconds
Started Jul 14 08:20:33 PM PDT 24
Finished Jul 14 08:26:23 PM PDT 24
Peak memory 648228 kb
Host smart-c239d375-eb4c-4b97-8944-87e9e460ed02
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343193112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2343193112
Directory /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3774540056
Short name T60
Test name
Test status
Simulation time 5597214702 ps
CPU time 498.49 seconds
Started Jul 14 07:51:52 PM PDT 24
Finished Jul 14 08:00:12 PM PDT 24
Peak memory 620748 kb
Host smart-d70d22a7-17ec-4d35-b06f-0316eeb98c5d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774540056 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.3774540056
Directory /workspace/0.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3765462881
Short name T160
Test name
Test status
Simulation time 1945429547 ps
CPU time 88.41 seconds
Started Jul 14 08:10:19 PM PDT 24
Finished Jul 14 08:11:48 PM PDT 24
Peak memory 621232 kb
Host smart-ac5d42fb-b5d8-4f3c-a5f3-32dec16422c3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765462881 -assert nopost
proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.3765462881
Directory /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_csrng.3109778778
Short name T120
Test name
Test status
Simulation time 6628057208 ps
CPU time 1117.46 seconds
Started Jul 14 08:12:20 PM PDT 24
Finished Jul 14 08:30:58 PM PDT 24
Peak memory 608788 kb
Host smart-20b3a714-b5f2-4703-b647-e7b8a4fdf126
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_
csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3109778778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.3109778778
Directory /workspace/2.chip_sw_entropy_src_csrng/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.441479922
Short name T215
Test name
Test status
Simulation time 5288497000 ps
CPU time 892.11 seconds
Started Jul 14 07:53:16 PM PDT 24
Finished Jul 14 08:08:10 PM PDT 24
Peak memory 608604 kb
Host smart-7ee311fc-cef8-4b34-b5fc-ab03b1d18000
User root
Command /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441479922 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.441479922
Directory /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest

Test location /workspace/coverage/default/20.chip_sw_all_escalation_resets.1045683705
Short name T761
Test name
Test status
Simulation time 5858342930 ps
CPU time 573.42 seconds
Started Jul 14 08:19:37 PM PDT 24
Finished Jul 14 08:29:11 PM PDT 24
Peak memory 649520 kb
Host smart-c8716288-95ac-4e2a-bb91-75cf2360bb04
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1045683705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.1045683705
Directory /workspace/20.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_idle.2394559549
Short name T896
Test name
Test status
Simulation time 2830775912 ps
CPU time 311.18 seconds
Started Jul 14 07:55:33 PM PDT 24
Finished Jul 14 08:00:46 PM PDT 24
Peak memory 609128 kb
Host smart-d26cb366-9e13-4f38-b35b-c60c5b698573
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394559549 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.chip_sw_kmac_idle.2394559549
Directory /workspace/0.chip_sw_kmac_idle/latest

Test location /workspace/coverage/cover_reg_top/1.chip_tl_errors.3781411080
Short name T562
Test name
Test status
Simulation time 3417246220 ps
CPU time 237.34 seconds
Started Jul 14 07:26:59 PM PDT 24
Finished Jul 14 07:30:57 PM PDT 24
Peak memory 598876 kb
Host smart-3772c47d-5875-49e3-abbd-59ce43a989cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781411080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.3781411080
Directory /workspace/1.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.1254339998
Short name T537
Test name
Test status
Simulation time 111758371788 ps
CPU time 2256.55 seconds
Started Jul 14 07:40:25 PM PDT 24
Finished Jul 14 08:18:02 PM PDT 24
Peak memory 575576 kb
Host smart-fbe63a6f-9634-48e0-a78d-5d2d73be54a3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254339998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_
device_slow_rsp.1254339998
Directory /workspace/72.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2108414114
Short name T59
Test name
Test status
Simulation time 5036248678 ps
CPU time 432.8 seconds
Started Jul 14 08:13:35 PM PDT 24
Finished Jul 14 08:20:48 PM PDT 24
Peak memory 623088 kb
Host smart-ae8b1bbf-5b59-4e24-a051-e967a9a7304e
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108414114 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.2108414114
Directory /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1679288799
Short name T1287
Test name
Test status
Simulation time 3492203200 ps
CPU time 387.81 seconds
Started Jul 14 07:54:54 PM PDT 24
Finished Jul 14 08:01:23 PM PDT 24
Peak memory 648256 kb
Host smart-b12c3403-7620-4dea-9f86-dacaf42cb04f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679288799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s
w_alert_handler_lpg_sleep_mode_alerts.1679288799
Directory /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/0.chip_sw_all_escalation_resets.3561393427
Short name T797
Test name
Test status
Simulation time 4555945300 ps
CPU time 756.52 seconds
Started Jul 14 07:53:11 PM PDT 24
Finished Jul 14 08:05:48 PM PDT 24
Peak memory 649556 kb
Host smart-872484cb-448a-446b-9f5a-f2aa82ecf835
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3561393427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.3561393427
Directory /workspace/0.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1977990067
Short name T798
Test name
Test status
Simulation time 3888143234 ps
CPU time 378.05 seconds
Started Jul 14 08:00:17 PM PDT 24
Finished Jul 14 08:06:36 PM PDT 24
Peak memory 648480 kb
Host smart-4378d2e1-d6c7-4033-8f44-704de1abe1a8
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977990067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s
w_alert_handler_lpg_sleep_mode_alerts.1977990067
Directory /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/1.chip_sw_all_escalation_resets.3691220369
Short name T725
Test name
Test status
Simulation time 5874393960 ps
CPU time 632.7 seconds
Started Jul 14 07:56:29 PM PDT 24
Finished Jul 14 08:07:02 PM PDT 24
Peak memory 649540 kb
Host smart-51a2b8be-041a-4c84-b446-b2230bc9f3db
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3691220369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.3691220369
Directory /workspace/1.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1367431718
Short name T729
Test name
Test status
Simulation time 3527202714 ps
CPU time 427.11 seconds
Started Jul 14 08:18:15 PM PDT 24
Finished Jul 14 08:25:23 PM PDT 24
Peak memory 648064 kb
Host smart-09f8397f-ad37-42e4-b0e6-efd3506edde5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367431718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1367431718
Directory /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/11.chip_sw_all_escalation_resets.4101121833
Short name T335
Test name
Test status
Simulation time 4412366400 ps
CPU time 598.3 seconds
Started Jul 14 08:18:27 PM PDT 24
Finished Jul 14 08:28:26 PM PDT 24
Peak memory 649268 kb
Host smart-b5d16613-4fcd-4d67-bba1-bfa27b642b7f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4101121833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.4101121833
Directory /workspace/11.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/12.chip_sw_all_escalation_resets.6780687
Short name T1268
Test name
Test status
Simulation time 6403162664 ps
CPU time 594.94 seconds
Started Jul 14 08:21:21 PM PDT 24
Finished Jul 14 08:31:17 PM PDT 24
Peak memory 649628 kb
Host smart-c3ceaf28-cbb7-435e-acb0-989531e028a0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
6780687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.6780687
Directory /workspace/12.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1915861019
Short name T767
Test name
Test status
Simulation time 3680261394 ps
CPU time 423.33 seconds
Started Jul 14 08:19:24 PM PDT 24
Finished Jul 14 08:26:28 PM PDT 24
Peak memory 647916 kb
Host smart-7ced7666-3aad-4c96-8116-74c11c97b94c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915861019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1915861019
Directory /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/13.chip_sw_all_escalation_resets.1835575585
Short name T270
Test name
Test status
Simulation time 4775922820 ps
CPU time 824.74 seconds
Started Jul 14 08:19:01 PM PDT 24
Finished Jul 14 08:32:47 PM PDT 24
Peak memory 649512 kb
Host smart-5a593809-ab63-422a-92ce-3aa194e8f02d
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1835575585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.1835575585
Directory /workspace/13.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2332258032
Short name T1021
Test name
Test status
Simulation time 4371254902 ps
CPU time 505.81 seconds
Started Jul 14 08:19:48 PM PDT 24
Finished Jul 14 08:28:15 PM PDT 24
Peak memory 648232 kb
Host smart-aa972040-f26a-40fd-8600-42c397cd52cd
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332258032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2332258032
Directory /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/14.chip_sw_all_escalation_resets.3349150957
Short name T1139
Test name
Test status
Simulation time 4734926866 ps
CPU time 654.02 seconds
Started Jul 14 08:18:40 PM PDT 24
Finished Jul 14 08:29:35 PM PDT 24
Peak memory 649392 kb
Host smart-3216f2ad-867a-49cd-b486-e481e1fae048
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3349150957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.3349150957
Directory /workspace/14.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/16.chip_sw_all_escalation_resets.1861483224
Short name T1113
Test name
Test status
Simulation time 5891048504 ps
CPU time 687.45 seconds
Started Jul 14 08:20:10 PM PDT 24
Finished Jul 14 08:31:38 PM PDT 24
Peak memory 649716 kb
Host smart-20d56ce4-a4fb-4697-a178-b5edf4ae0ef5
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1861483224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.1861483224
Directory /workspace/16.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3962513959
Short name T781
Test name
Test status
Simulation time 3876975552 ps
CPU time 476.76 seconds
Started Jul 14 08:19:24 PM PDT 24
Finished Jul 14 08:27:22 PM PDT 24
Peak memory 648444 kb
Host smart-16f9b45a-92b7-4f62-b6c6-876083939c46
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962513959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3962513959
Directory /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/18.chip_sw_all_escalation_resets.2862696519
Short name T363
Test name
Test status
Simulation time 5006398218 ps
CPU time 654.84 seconds
Started Jul 14 08:20:22 PM PDT 24
Finished Jul 14 08:31:18 PM PDT 24
Peak memory 649496 kb
Host smart-5eb04e7b-d951-40e1-bbcc-b75b67bde42a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2862696519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.2862696519
Directory /workspace/18.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2639288933
Short name T731
Test name
Test status
Simulation time 3296167350 ps
CPU time 426.71 seconds
Started Jul 14 08:18:49 PM PDT 24
Finished Jul 14 08:25:56 PM PDT 24
Peak memory 647924 kb
Host smart-44c06777-7522-43dc-b8ed-2dd927cd3b44
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639288933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2639288933
Directory /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/19.chip_sw_all_escalation_resets.3302614772
Short name T812
Test name
Test status
Simulation time 4909065596 ps
CPU time 641.19 seconds
Started Jul 14 08:20:11 PM PDT 24
Finished Jul 14 08:30:53 PM PDT 24
Peak memory 649632 kb
Host smart-f7d9f6bd-e8ae-42de-9616-bca4303ee886
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3302614772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.3302614772
Directory /workspace/19.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2099219055
Short name T770
Test name
Test status
Simulation time 3752351560 ps
CPU time 364.98 seconds
Started Jul 14 08:22:25 PM PDT 24
Finished Jul 14 08:28:31 PM PDT 24
Peak memory 648484 kb
Host smart-c3e0c544-74bd-43ac-b040-43adc1ef34ca
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099219055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2099219055
Directory /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/21.chip_sw_all_escalation_resets.2250452532
Short name T813
Test name
Test status
Simulation time 5946229844 ps
CPU time 598.96 seconds
Started Jul 14 08:19:33 PM PDT 24
Finished Jul 14 08:29:33 PM PDT 24
Peak memory 649500 kb
Host smart-453dddf0-a8e2-4bd4-9777-06c01db9af07
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2250452532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.2250452532
Directory /workspace/21.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.961860073
Short name T703
Test name
Test status
Simulation time 3349623310 ps
CPU time 470.19 seconds
Started Jul 14 08:19:36 PM PDT 24
Finished Jul 14 08:27:26 PM PDT 24
Peak memory 648196 kb
Host smart-9ef3e5b6-f938-4845-ae4b-a931bf70ebd8
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961860073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_s
w_alert_handler_lpg_sleep_mode_alerts.961860073
Directory /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1181392188
Short name T210
Test name
Test status
Simulation time 3353490420 ps
CPU time 407.91 seconds
Started Jul 14 08:22:24 PM PDT 24
Finished Jul 14 08:29:12 PM PDT 24
Peak memory 647944 kb
Host smart-b8099688-245e-4b57-9911-8a20c099e878
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181392188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1181392188
Directory /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/25.chip_sw_all_escalation_resets.2936495916
Short name T268
Test name
Test status
Simulation time 4840803768 ps
CPU time 689.9 seconds
Started Jul 14 08:20:10 PM PDT 24
Finished Jul 14 08:31:41 PM PDT 24
Peak memory 649488 kb
Host smart-da464973-f307-4878-9fc7-cd06c1af8ca9
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2936495916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.2936495916
Directory /workspace/25.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.87775977
Short name T745
Test name
Test status
Simulation time 3566478688 ps
CPU time 268.54 seconds
Started Jul 14 08:20:36 PM PDT 24
Finished Jul 14 08:25:05 PM PDT 24
Peak memory 648136 kb
Host smart-d891ea78-4326-4e42-aaf6-23624992dad5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87775977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_
escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw
_alert_handler_lpg_sleep_mode_alerts.87775977
Directory /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/26.chip_sw_all_escalation_resets.3436858439
Short name T358
Test name
Test status
Simulation time 5352926120 ps
CPU time 661.3 seconds
Started Jul 14 08:20:22 PM PDT 24
Finished Jul 14 08:31:24 PM PDT 24
Peak memory 649584 kb
Host smart-cdd54af6-d70a-4c4b-a207-6fb6f2eba611
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3436858439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.3436858439
Directory /workspace/26.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/27.chip_sw_all_escalation_resets.2791475433
Short name T772
Test name
Test status
Simulation time 4932080672 ps
CPU time 550.27 seconds
Started Jul 14 08:21:22 PM PDT 24
Finished Jul 14 08:30:33 PM PDT 24
Peak memory 649736 kb
Host smart-37a9534f-21bf-4b8b-907c-86fa0901bcbb
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2791475433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.2791475433
Directory /workspace/27.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.499426201
Short name T782
Test name
Test status
Simulation time 4555180064 ps
CPU time 361.46 seconds
Started Jul 14 08:23:25 PM PDT 24
Finished Jul 14 08:29:27 PM PDT 24
Peak memory 648764 kb
Host smart-6eb6068c-d73b-4f5e-a121-e6677a1ac376
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499426201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_s
w_alert_handler_lpg_sleep_mode_alerts.499426201
Directory /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/29.chip_sw_all_escalation_resets.777383361
Short name T793
Test name
Test status
Simulation time 5767273308 ps
CPU time 493.97 seconds
Started Jul 14 08:21:28 PM PDT 24
Finished Jul 14 08:29:42 PM PDT 24
Peak memory 649516 kb
Host smart-e9f318c1-5e8f-4f2e-ad16-f6bc9e21f1b0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
777383361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.777383361
Directory /workspace/29.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1070186742
Short name T726
Test name
Test status
Simulation time 3397629864 ps
CPU time 393.95 seconds
Started Jul 14 08:15:18 PM PDT 24
Finished Jul 14 08:21:53 PM PDT 24
Peak memory 648240 kb
Host smart-91196413-aa96-4aaf-9ea3-f421fa712f57
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070186742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s
w_alert_handler_lpg_sleep_mode_alerts.1070186742
Directory /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3152860876
Short name T307
Test name
Test status
Simulation time 3491907232 ps
CPU time 428.93 seconds
Started Jul 14 08:20:54 PM PDT 24
Finished Jul 14 08:28:05 PM PDT 24
Peak memory 648176 kb
Host smart-7ad99b18-3f47-468c-b476-db10c0eef299
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152860876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3152860876
Directory /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/30.chip_sw_all_escalation_resets.1490066588
Short name T765
Test name
Test status
Simulation time 5580764044 ps
CPU time 849.98 seconds
Started Jul 14 08:20:38 PM PDT 24
Finished Jul 14 08:34:49 PM PDT 24
Peak memory 649516 kb
Host smart-1a6dbeb1-ce7e-42d5-a5dc-3033aa59748b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1490066588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.1490066588
Directory /workspace/30.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2291557443
Short name T808
Test name
Test status
Simulation time 3930894594 ps
CPU time 329.27 seconds
Started Jul 14 08:22:27 PM PDT 24
Finished Jul 14 08:27:57 PM PDT 24
Peak memory 647936 kb
Host smart-3aa195c4-03dc-49f1-9a0f-697d5042fca5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291557443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2291557443
Directory /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/31.chip_sw_all_escalation_resets.737273455
Short name T777
Test name
Test status
Simulation time 4438947666 ps
CPU time 714.78 seconds
Started Jul 14 08:20:58 PM PDT 24
Finished Jul 14 08:32:53 PM PDT 24
Peak memory 649628 kb
Host smart-d1fca716-62fa-4dc2-b690-9e096391a2f7
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
737273455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.737273455
Directory /workspace/31.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/32.chip_sw_all_escalation_resets.2023674084
Short name T754
Test name
Test status
Simulation time 5330030224 ps
CPU time 539.44 seconds
Started Jul 14 08:21:14 PM PDT 24
Finished Jul 14 08:30:14 PM PDT 24
Peak memory 649648 kb
Host smart-fe3a40a0-0d06-4199-80cb-13457ec677aa
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2023674084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.2023674084
Directory /workspace/32.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3079171563
Short name T377
Test name
Test status
Simulation time 3925561796 ps
CPU time 419.19 seconds
Started Jul 14 08:21:22 PM PDT 24
Finished Jul 14 08:28:22 PM PDT 24
Peak memory 647964 kb
Host smart-2f9a5b9d-051b-4ce3-b381-5cc94d6faddd
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079171563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3079171563
Directory /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.264394180
Short name T386
Test name
Test status
Simulation time 3793857964 ps
CPU time 323.96 seconds
Started Jul 14 08:22:52 PM PDT 24
Finished Jul 14 08:28:17 PM PDT 24
Peak memory 648188 kb
Host smart-35d36612-f7b2-4ddc-af9f-3b1d29b0d688
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264394180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_s
w_alert_handler_lpg_sleep_mode_alerts.264394180
Directory /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/38.chip_sw_all_escalation_resets.3468143662
Short name T176
Test name
Test status
Simulation time 5420329952 ps
CPU time 559.96 seconds
Started Jul 14 08:21:16 PM PDT 24
Finished Jul 14 08:30:37 PM PDT 24
Peak memory 649608 kb
Host smart-61d7c1e6-f896-4212-8186-0d2275c4d4b1
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3468143662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.3468143662
Directory /workspace/38.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/40.chip_sw_all_escalation_resets.2320151016
Short name T773
Test name
Test status
Simulation time 4493580990 ps
CPU time 772.79 seconds
Started Jul 14 08:22:55 PM PDT 24
Finished Jul 14 08:35:49 PM PDT 24
Peak memory 649792 kb
Host smart-c1c655b5-db2c-49f3-8bd4-716701d3ba0f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2320151016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.2320151016
Directory /workspace/40.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/41.chip_sw_all_escalation_resets.3266704104
Short name T720
Test name
Test status
Simulation time 5491754632 ps
CPU time 724.61 seconds
Started Jul 14 08:22:00 PM PDT 24
Finished Jul 14 08:34:05 PM PDT 24
Peak memory 649628 kb
Host smart-c182eeb4-0fad-480a-8a03-3f9df124e1e3
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3266704104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.3266704104
Directory /workspace/41.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3566144721
Short name T467
Test name
Test status
Simulation time 3584512600 ps
CPU time 362.58 seconds
Started Jul 14 08:21:27 PM PDT 24
Finished Jul 14 08:27:30 PM PDT 24
Peak memory 648196 kb
Host smart-8d6f96a5-9947-410d-ad82-c879ae1d36c0
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566144721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3566144721
Directory /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/44.chip_sw_all_escalation_resets.2574849987
Short name T809
Test name
Test status
Simulation time 4931195952 ps
CPU time 633.76 seconds
Started Jul 14 08:22:25 PM PDT 24
Finished Jul 14 08:33:00 PM PDT 24
Peak memory 649632 kb
Host smart-440ae8ff-5838-49c4-ac0f-1847b17ef041
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2574849987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.2574849987
Directory /workspace/44.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2345836755
Short name T746
Test name
Test status
Simulation time 4066622774 ps
CPU time 578.29 seconds
Started Jul 14 08:23:11 PM PDT 24
Finished Jul 14 08:32:50 PM PDT 24
Peak memory 648164 kb
Host smart-a5ef8313-a98f-4b7c-a9c8-48f00769083f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345836755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2345836755
Directory /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/46.chip_sw_all_escalation_resets.2566244420
Short name T784
Test name
Test status
Simulation time 4505812240 ps
CPU time 670.79 seconds
Started Jul 14 08:23:18 PM PDT 24
Finished Jul 14 08:34:29 PM PDT 24
Peak memory 649676 kb
Host smart-05ca6e6b-46d8-4f38-8b47-0d886a299a9a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2566244420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.2566244420
Directory /workspace/46.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3945498949
Short name T815
Test name
Test status
Simulation time 4058310400 ps
CPU time 264.91 seconds
Started Jul 14 08:21:29 PM PDT 24
Finished Jul 14 08:25:55 PM PDT 24
Peak memory 647904 kb
Host smart-847af264-b906-461d-b775-39812d5d1672
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945498949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3945498949
Directory /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/48.chip_sw_all_escalation_resets.959233321
Short name T789
Test name
Test status
Simulation time 6426970912 ps
CPU time 603.97 seconds
Started Jul 14 08:22:32 PM PDT 24
Finished Jul 14 08:32:36 PM PDT 24
Peak memory 649540 kb
Host smart-dd2516d4-4a60-4576-b55a-e241239dab15
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
959233321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.959233321
Directory /workspace/48.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.166820510
Short name T759
Test name
Test status
Simulation time 3603267656 ps
CPU time 364.06 seconds
Started Jul 14 08:22:02 PM PDT 24
Finished Jul 14 08:28:06 PM PDT 24
Peak memory 648360 kb
Host smart-16af4fc7-5e56-4f21-8bf1-e5b88b3ef4c1
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166820510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_s
w_alert_handler_lpg_sleep_mode_alerts.166820510
Directory /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.622826126
Short name T388
Test name
Test status
Simulation time 4012129688 ps
CPU time 382 seconds
Started Jul 14 08:24:48 PM PDT 24
Finished Jul 14 08:31:11 PM PDT 24
Peak memory 648168 kb
Host smart-e98d0341-7b14-4a16-9596-47997736c493
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622826126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_s
w_alert_handler_lpg_sleep_mode_alerts.622826126
Directory /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3761154052
Short name T246
Test name
Test status
Simulation time 3644087260 ps
CPU time 617.17 seconds
Started Jul 14 08:22:41 PM PDT 24
Finished Jul 14 08:32:59 PM PDT 24
Peak memory 647964 kb
Host smart-ebd68e30-2118-4f2e-aa32-c017a5243e46
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761154052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3761154052
Directory /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3995418149
Short name T284
Test name
Test status
Simulation time 3595804772 ps
CPU time 405.49 seconds
Started Jul 14 08:22:43 PM PDT 24
Finished Jul 14 08:29:28 PM PDT 24
Peak memory 648248 kb
Host smart-6b7485e4-268f-4daf-bf30-575ec9d4ed88
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995418149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3995418149
Directory /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.682919807
Short name T724
Test name
Test status
Simulation time 3328822368 ps
CPU time 331.48 seconds
Started Jul 14 08:26:06 PM PDT 24
Finished Jul 14 08:31:38 PM PDT 24
Peak memory 648288 kb
Host smart-5ba0cb99-207e-4681-84d2-8227df671d3e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682919807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_s
w_alert_handler_lpg_sleep_mode_alerts.682919807
Directory /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3555959040
Short name T757
Test name
Test status
Simulation time 3508398792 ps
CPU time 384.51 seconds
Started Jul 14 08:24:51 PM PDT 24
Finished Jul 14 08:31:16 PM PDT 24
Peak memory 648252 kb
Host smart-b13923eb-0f27-4c5f-85a3-ac52ad59aac4
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555959040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3555959040
Directory /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2462726829
Short name T810
Test name
Test status
Simulation time 3855019144 ps
CPU time 377.73 seconds
Started Jul 14 08:25:04 PM PDT 24
Finished Jul 14 08:31:22 PM PDT 24
Peak memory 648036 kb
Host smart-b00d349e-bd99-4bc4-8821-7984d08e0709
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462726829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2462726829
Directory /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/59.chip_sw_all_escalation_resets.3907842193
Short name T788
Test name
Test status
Simulation time 4509512592 ps
CPU time 640.01 seconds
Started Jul 14 08:22:53 PM PDT 24
Finished Jul 14 08:33:34 PM PDT 24
Peak memory 649500 kb
Host smart-7e302846-deea-4d21-85c5-a0a803bbcc3c
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3907842193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.3907842193
Directory /workspace/59.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/6.chip_sw_all_escalation_resets.1088147187
Short name T241
Test name
Test status
Simulation time 6280327116 ps
CPU time 572.94 seconds
Started Jul 14 08:16:38 PM PDT 24
Finished Jul 14 08:26:12 PM PDT 24
Peak memory 649584 kb
Host smart-3775b4de-dba1-4380-96e0-fd0f88eb158f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1088147187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.1088147187
Directory /workspace/6.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/60.chip_sw_all_escalation_resets.702219370
Short name T721
Test name
Test status
Simulation time 4553871880 ps
CPU time 564.61 seconds
Started Jul 14 08:23:04 PM PDT 24
Finished Jul 14 08:32:29 PM PDT 24
Peak memory 649576 kb
Host smart-bc6b23bf-cd2a-4c84-b1be-8327e8e4492f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
702219370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.702219370
Directory /workspace/60.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/62.chip_sw_all_escalation_resets.1598553932
Short name T748
Test name
Test status
Simulation time 6162278100 ps
CPU time 692.55 seconds
Started Jul 14 08:23:52 PM PDT 24
Finished Jul 14 08:35:25 PM PDT 24
Peak memory 649496 kb
Host smart-72a705d6-1f54-4977-a680-4e0c520734e9
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1598553932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.1598553932
Directory /workspace/62.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.4092651519
Short name T219
Test name
Test status
Simulation time 3591939878 ps
CPU time 392.62 seconds
Started Jul 14 08:23:50 PM PDT 24
Finished Jul 14 08:30:23 PM PDT 24
Peak memory 647996 kb
Host smart-6f806025-d6cf-4f25-88ae-f0ee64c7a2e4
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092651519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4092651519
Directory /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.302541348
Short name T819
Test name
Test status
Simulation time 3487340128 ps
CPU time 486.51 seconds
Started Jul 14 08:27:27 PM PDT 24
Finished Jul 14 08:35:34 PM PDT 24
Peak memory 648264 kb
Host smart-a0cf4528-ae35-42b8-bd04-ffee7e8bc7f7
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302541348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_s
w_alert_handler_lpg_sleep_mode_alerts.302541348
Directory /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/68.chip_sw_all_escalation_resets.1286223790
Short name T242
Test name
Test status
Simulation time 6607218110 ps
CPU time 775.34 seconds
Started Jul 14 08:25:20 PM PDT 24
Finished Jul 14 08:38:15 PM PDT 24
Peak memory 649728 kb
Host smart-f96bba23-7072-45a9-8cbc-fa6acefc22e3
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1286223790 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.1286223790
Directory /workspace/68.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.192445749
Short name T755
Test name
Test status
Simulation time 3504295400 ps
CPU time 364.67 seconds
Started Jul 14 08:24:57 PM PDT 24
Finished Jul 14 08:31:02 PM PDT 24
Peak memory 648572 kb
Host smart-c1eee90c-dbbd-48fa-9b2b-8b7075c9d67d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192445749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_s
w_alert_handler_lpg_sleep_mode_alerts.192445749
Directory /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/75.chip_sw_all_escalation_resets.1798015387
Short name T744
Test name
Test status
Simulation time 5271948872 ps
CPU time 632.5 seconds
Started Jul 14 08:27:23 PM PDT 24
Finished Jul 14 08:37:56 PM PDT 24
Peak memory 649524 kb
Host smart-1bf52823-19f2-412d-9835-26a70c95a5bf
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1798015387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.1798015387
Directory /workspace/75.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/76.chip_sw_all_escalation_resets.251054169
Short name T364
Test name
Test status
Simulation time 4132552888 ps
CPU time 528.66 seconds
Started Jul 14 08:24:22 PM PDT 24
Finished Jul 14 08:33:11 PM PDT 24
Peak memory 649264 kb
Host smart-01890b76-2cfb-4a63-8920-a14a6df426d5
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
251054169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.251054169
Directory /workspace/76.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/77.chip_sw_all_escalation_resets.1484149302
Short name T732
Test name
Test status
Simulation time 5572966280 ps
CPU time 637.86 seconds
Started Jul 14 08:24:48 PM PDT 24
Finished Jul 14 08:35:27 PM PDT 24
Peak memory 649584 kb
Host smart-49395623-9a9c-4eef-bbb7-c196599e53bf
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1484149302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.1484149302
Directory /workspace/77.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2039635533
Short name T818
Test name
Test status
Simulation time 3257337494 ps
CPU time 372 seconds
Started Jul 14 08:26:35 PM PDT 24
Finished Jul 14 08:32:48 PM PDT 24
Peak memory 648104 kb
Host smart-4476524f-ad04-4ded-8626-baf53710649c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039635533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2039635533
Directory /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2514315172
Short name T806
Test name
Test status
Simulation time 3326304090 ps
CPU time 385.51 seconds
Started Jul 14 08:19:48 PM PDT 24
Finished Jul 14 08:26:14 PM PDT 24
Peak memory 647880 kb
Host smart-9614f1ec-00c5-4074-80f2-4ad206d44888
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514315172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s
w_alert_handler_lpg_sleep_mode_alerts.2514315172
Directory /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1776152449
Short name T790
Test name
Test status
Simulation time 3820974960 ps
CPU time 389.8 seconds
Started Jul 14 08:25:40 PM PDT 24
Finished Jul 14 08:32:11 PM PDT 24
Peak memory 648204 kb
Host smart-10937da2-9a67-453b-b102-bd217d979b66
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776152449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1776152449
Directory /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.964407970
Short name T751
Test name
Test status
Simulation time 3855900642 ps
CPU time 332.93 seconds
Started Jul 14 08:18:18 PM PDT 24
Finished Jul 14 08:23:52 PM PDT 24
Peak memory 648168 kb
Host smart-dac6a622-9093-4f8e-8b51-b9fcdabc9c99
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964407970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw
_alert_handler_lpg_sleep_mode_alerts.964407970
Directory /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/95.chip_sw_all_escalation_resets.1847823100
Short name T266
Test name
Test status
Simulation time 4874468800 ps
CPU time 510.97 seconds
Started Jul 14 08:27:51 PM PDT 24
Finished Jul 14 08:36:23 PM PDT 24
Peak memory 649764 kb
Host smart-feda227e-e461-450a-964a-4d23e604d7f0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1847823100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.1847823100
Directory /workspace/95.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/99.chip_sw_all_escalation_resets.3413103526
Short name T743
Test name
Test status
Simulation time 4453329904 ps
CPU time 522.75 seconds
Started Jul 14 08:25:36 PM PDT 24
Finished Jul 14 08:34:19 PM PDT 24
Peak memory 649536 kb
Host smart-27a153c3-ffea-42f1-a56e-9476fb12c4f8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3413103526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.3413103526
Directory /workspace/99.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1265734526
Short name T10
Test name
Test status
Simulation time 22695612892 ps
CPU time 1460.85 seconds
Started Jul 14 07:55:28 PM PDT 24
Finished Jul 14 08:19:50 PM PDT 24
Peak memory 609976 kb
Host smart-5319dff3-8888-44d6-82eb-67ac66f2ff03
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1265734526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1265734526
Directory /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2125690600
Short name T343
Test name
Test status
Simulation time 4191874712 ps
CPU time 391.04 seconds
Started Jul 14 07:55:02 PM PDT 24
Finished Jul 14 08:01:33 PM PDT 24
Peak memory 609112 kb
Host smart-c3596115-f8f1-42ee-95d6-130785824464
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125690600 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.2125690600
Directory /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2368781428
Short name T389
Test name
Test status
Simulation time 6136727288 ps
CPU time 357.71 seconds
Started Jul 14 07:53:16 PM PDT 24
Finished Jul 14 07:59:14 PM PDT 24
Peak memory 609928 kb
Host smart-2eeb4309-bf06-4972-bee3-0b1397b71b4b
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul
es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2368781428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s
leep_wake_up.2368781428
Directory /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1831003809
Short name T243
Test name
Test status
Simulation time 13189613300 ps
CPU time 1855.48 seconds
Started Jul 14 08:09:23 PM PDT 24
Finished Jul 14 08:40:20 PM PDT 24
Peak memory 610148 kb
Host smart-2945d71d-4f4d-44f4-ba64-5e0068eab076
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=1831003809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.1831003809
Directory /workspace/2.chip_sw_rstmgr_alert_info/latest

Test location /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.3486973803
Short name T406
Test name
Test status
Simulation time 30677103670 ps
CPU time 3860.95 seconds
Started Jul 14 07:27:12 PM PDT 24
Finished Jul 14 08:31:34 PM PDT 24
Peak memory 592988 kb
Host smart-e28279be-b35c-4e7f-b10c-068a85756a32
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486973803 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.3486973803
Directory /workspace/2.chip_same_csr_outstanding/latest

Test location /workspace/coverage/default/7.chip_sw_all_escalation_resets.3444119209
Short name T684
Test name
Test status
Simulation time 5057170952 ps
CPU time 582.09 seconds
Started Jul 14 08:17:35 PM PDT 24
Finished Jul 14 08:27:18 PM PDT 24
Peak memory 610172 kb
Host smart-7c85cfe8-a9b5-4b37-8ccb-1876e76f580b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3444119209 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.3444119209
Directory /workspace/7.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/0.chip_sw_plic_sw_irq.3517615456
Short name T251
Test name
Test status
Simulation time 2952872680 ps
CPU time 277.16 seconds
Started Jul 14 07:55:53 PM PDT 24
Finished Jul 14 08:00:31 PM PDT 24
Peak memory 609132 kb
Host smart-5f515017-ab07-472d-b7ac-4c6b6ca9109a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517615456 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.chip_sw_plic_sw_irq.3517615456
Directory /workspace/0.chip_sw_plic_sw_irq/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3796721529
Short name T139
Test name
Test status
Simulation time 8827821056 ps
CPU time 605.45 seconds
Started Jul 14 07:53:43 PM PDT 24
Finished Jul 14 08:03:50 PM PDT 24
Peak memory 609860 kb
Host smart-66b0e9b1-bc91-400c-95c1-0ac4e247c1a3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796721529 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.3796721529
Directory /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2286171808
Short name T161
Test name
Test status
Simulation time 3010914296 ps
CPU time 259.96 seconds
Started Jul 14 07:59:25 PM PDT 24
Finished Jul 14 08:03:45 PM PDT 24
Peak memory 620696 kb
Host smart-951a5b75-cf83-440d-8291-e2dab2e35659
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286171808 -assert nopost
proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.2286171808
Directory /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location /workspace/coverage/default/1.chip_tap_straps_dev.492934141
Short name T677
Test name
Test status
Simulation time 8387767407 ps
CPU time 849.45 seconds
Started Jul 14 08:02:48 PM PDT 24
Finished Jul 14 08:16:58 PM PDT 24
Peak memory 620340 kb
Host smart-943cce8f-5414-4c9e-9303-5b2b3d0317d0
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=492934141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.492934141
Directory /workspace/1.chip_tap_straps_dev/latest

Test location /workspace/coverage/cover_reg_top/13.chip_tl_errors.1108825137
Short name T636
Test name
Test status
Simulation time 3941908952 ps
CPU time 260.53 seconds
Started Jul 14 07:30:00 PM PDT 24
Finished Jul 14 07:34:21 PM PDT 24
Peak memory 598756 kb
Host smart-7697b3ae-c1a7-40d8-9f66-10e1dff67827
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108825137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.1108825137
Directory /workspace/13.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.2929289812
Short name T1605
Test name
Test status
Simulation time 80976324158 ps
CPU time 893.35 seconds
Started Jul 14 07:30:35 PM PDT 24
Finished Jul 14 07:45:28 PM PDT 24
Peak memory 575512 kb
Host smart-25e4ebfe-ea87-49ff-bcd6-f7f0eeadd57b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929289812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2929289812
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all.4227236759
Short name T530
Test name
Test status
Simulation time 5019648314 ps
CPU time 421.77 seconds
Started Jul 14 07:30:41 PM PDT 24
Finished Jul 14 07:37:44 PM PDT 24
Peak memory 575604 kb
Host smart-9cf92c0a-4685-42d7-926f-655f6f32b062
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227236759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.4227236759
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.2598844025
Short name T1454
Test name
Test status
Simulation time 730881613 ps
CPU time 30.57 seconds
Started Jul 14 07:31:40 PM PDT 24
Finished Jul 14 07:32:11 PM PDT 24
Peak memory 575320 kb
Host smart-41f727ef-0cd1-4614-9e18-50546d21995f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598844025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2598844025
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/default/0.chip_sw_gpio.976185597
Short name T38
Test name
Test status
Simulation time 3740161410 ps
CPU time 489.25 seconds
Started Jul 14 07:53:38 PM PDT 24
Finished Jul 14 08:01:48 PM PDT 24
Peak memory 609748 kb
Host smart-af4a389c-f4e3-4d6f-9886-673bff94440d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976185597 -assert nopostproc +UVM_TESTNAME=chip_base
_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.chip_sw_gpio.976185597
Directory /workspace/0.chip_sw_gpio/latest

Test location /workspace/coverage/default/1.chip_plic_all_irqs_10.1992474738
Short name T156
Test name
Test status
Simulation time 3507052342 ps
CPU time 478.74 seconds
Started Jul 14 08:01:13 PM PDT 24
Finished Jul 14 08:09:12 PM PDT 24
Peak memory 609208 kb
Host smart-748d1c55-e89d-4d96-b63c-8cd4d94dd0cb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992474738 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.chip_plic_all_irqs_10.1992474738
Directory /workspace/1.chip_plic_all_irqs_10/latest

Test location /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.6936985
Short name T367
Test name
Test status
Simulation time 18514510486 ps
CPU time 379.63 seconds
Started Jul 14 07:52:38 PM PDT 24
Finished Jul 14 07:58:58 PM PDT 24
Peak memory 618560 kb
Host smart-57042c89-acc9-45d1-8a7d-0b644105e485
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=6936985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.6936985
Directory /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.387755651
Short name T211
Test name
Test status
Simulation time 4561979964 ps
CPU time 905.4 seconds
Started Jul 14 07:52:01 PM PDT 24
Finished Jul 14 08:07:08 PM PDT 24
Peak memory 608796 kb
Host smart-ee1a7100-bc91-48f5-934b-1fa26490e776
User root
Command /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387755651 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.387755651
Directory /workspace/0.chip_sw_i2c_host_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3312573993
Short name T387
Test name
Test status
Simulation time 3953260520 ps
CPU time 691.48 seconds
Started Jul 14 07:52:56 PM PDT 24
Finished Jul 14 08:04:28 PM PDT 24
Peak memory 608764 kb
Host smart-b192c007-23eb-44e4-a9e7-770448ef2478
User root
Command /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312573993 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.3312573993
Directory /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.569340966
Short name T131
Test name
Test status
Simulation time 6281511455 ps
CPU time 340 seconds
Started Jul 14 07:27:08 PM PDT 24
Finished Jul 14 07:32:49 PM PDT 24
Peak memory 665184 kb
Host smart-73bd237b-72c9-4949-b549-d3a5b8eb3105
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569340966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_re
set.569340966
Directory /workspace/1.chip_csr_hw_reset/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1309294199
Short name T112
Test name
Test status
Simulation time 156005696188 ps
CPU time 22285.4 seconds
Started Jul 14 07:54:40 PM PDT 24
Finished Jul 15 02:06:09 AM PDT 24
Peak memory 610040 kb
Host smart-244f767c-2249-4021-9291-b8d3be0ab75d
User root
Command /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de
vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1309294199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.1309294199
Directory /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc.184906135
Short name T350
Test name
Test status
Simulation time 3258400718 ps
CPU time 315.88 seconds
Started Jul 14 07:53:05 PM PDT 24
Finished Jul 14 07:58:22 PM PDT 24
Peak memory 609124 kb
Host smart-b6c544f3-eb98-46e0-8d89-8d1103b91e22
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184906135 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_hmac_enc.184906135
Directory /workspace/0.chip_sw_hmac_enc/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.154747566
Short name T226
Test name
Test status
Simulation time 6240225700 ps
CPU time 1213.86 seconds
Started Jul 14 07:54:58 PM PDT 24
Finished Jul 14 08:15:12 PM PDT 24
Peak memory 610728 kb
Host smart-238201ab-5257-40b8-a219-90790298629a
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154747
566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.154747566
Directory /workspace/0.chip_sw_keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1131768489
Short name T168
Test name
Test status
Simulation time 4545268624 ps
CPU time 523.89 seconds
Started Jul 14 07:55:11 PM PDT 24
Finished Jul 14 08:03:55 PM PDT 24
Peak memory 610304 kb
Host smart-5b636907-e12d-4cd3-a74a-5d412ad7c3ed
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1131768489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.1131768489
Directory /workspace/0.chip_sw_lc_ctrl_program_error/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2017336895
Short name T1202
Test name
Test status
Simulation time 6117600820 ps
CPU time 513.19 seconds
Started Jul 14 07:53:05 PM PDT 24
Finished Jul 14 08:01:39 PM PDT 24
Peak memory 616504 kb
Host smart-79ee7fe8-ff41-4014-bcf8-f399ef557ba2
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2017336895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2017336895
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_error_random.555964214
Short name T621
Test name
Test status
Simulation time 494298665 ps
CPU time 39.38 seconds
Started Jul 14 07:29:38 PM PDT 24
Finished Jul 14 07:30:18 PM PDT 24
Peak memory 575280 kb
Host smart-e14171ac-3f54-4459-84fe-c69fae8d2d87
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555964214 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.555964214
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.2103197107
Short name T630
Test name
Test status
Simulation time 13915935571 ps
CPU time 490.22 seconds
Started Jul 14 07:33:20 PM PDT 24
Finished Jul 14 07:41:30 PM PDT 24
Peak memory 575564 kb
Host smart-f36fcd1d-80f5-48af-86f2-f06fe943ec74
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103197107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2103197107
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.2504809529
Short name T690
Test name
Test status
Simulation time 4343899182 ps
CPU time 226.36 seconds
Started Jul 14 07:34:24 PM PDT 24
Finished Jul 14 07:38:11 PM PDT 24
Peak memory 575592 kb
Host smart-d07863c5-3826-4891-b874-71d322f4c7df
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504809529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al
l_with_reset_error.2504809529
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.1493812962
Short name T686
Test name
Test status
Simulation time 3645044355 ps
CPU time 270.67 seconds
Started Jul 14 07:35:06 PM PDT 24
Finished Jul 14 07:39:37 PM PDT 24
Peak memory 575504 kb
Host smart-5ec4c44f-4d2a-4f04-9cd2-5b6809e39ed9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493812962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1493812962
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.606408943
Short name T628
Test name
Test status
Simulation time 3998303505 ps
CPU time 409.4 seconds
Started Jul 14 07:35:26 PM PDT 24
Finished Jul 14 07:42:16 PM PDT 24
Peak memory 575508 kb
Host smart-8e3c6956-de3b-43e6-9ff1-25ebd0f6c939
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606408943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all
_with_reset_error.606408943
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.2285057768
Short name T626
Test name
Test status
Simulation time 1737058894 ps
CPU time 131.06 seconds
Started Jul 14 07:36:45 PM PDT 24
Finished Jul 14 07:38:57 PM PDT 24
Peak memory 575496 kb
Host smart-51b44bec-b2b6-4362-83c5-20619373ac30
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285057768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2285057768
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.23862168
Short name T2517
Test name
Test status
Simulation time 12864309240 ps
CPU time 407.17 seconds
Started Jul 14 07:37:01 PM PDT 24
Finished Jul 14 07:43:49 PM PDT 24
Peak memory 575588 kb
Host smart-214db4ea-1129-40a7-8774-97215de00772
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23862168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.23862168
Directory /workspace/50.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.815382792
Short name T618
Test name
Test status
Simulation time 7938321815 ps
CPU time 326.23 seconds
Started Jul 14 07:43:45 PM PDT 24
Finished Jul 14 07:49:11 PM PDT 24
Peak memory 575600 kb
Host smart-60920327-f662-45ae-b2c5-27a9c0f7fe36
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815382792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all
_with_reset_error.815382792
Directory /workspace/94.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.993870906
Short name T371
Test name
Test status
Simulation time 4318367196 ps
CPU time 676.58 seconds
Started Jul 14 07:52:45 PM PDT 24
Finished Jul 14 08:04:02 PM PDT 24
Peak memory 608808 kb
Host smart-1684557e-4e6b-41bd-8ecc-23ae51a0cd3a
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993870906 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.993870906
Directory /workspace/0.chip_sw_flash_ctrl_ops/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1764133915
Short name T329
Test name
Test status
Simulation time 14104654476 ps
CPU time 1794.73 seconds
Started Jul 14 07:51:57 PM PDT 24
Finished Jul 14 08:21:53 PM PDT 24
Peak memory 610408 kb
Host smart-f0eacee4-a438-458e-999a-1d35b55d7871
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=1764133915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.1764133915
Directory /workspace/0.chip_sw_rstmgr_alert_info/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2272113910
Short name T255
Test name
Test status
Simulation time 5355129158 ps
CPU time 775.74 seconds
Started Jul 14 07:53:45 PM PDT 24
Finished Jul 14 08:06:41 PM PDT 24
Peak memory 608676 kb
Host smart-10b92888-1b2b-4708-9f7b-83110a167ca3
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22721
13910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.2272113910
Directory /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest

Test location /workspace/coverage/default/1.chip_sw_gpio.2752542309
Short name T37
Test name
Test status
Simulation time 3674575664 ps
CPU time 391.54 seconds
Started Jul 14 07:57:56 PM PDT 24
Finished Jul 14 08:04:28 PM PDT 24
Peak memory 609564 kb
Host smart-50de8542-69dd-4ddf-8441-ea3beb34b56c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752542309 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.chip_sw_gpio.2752542309
Directory /workspace/1.chip_sw_gpio/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1689621579
Short name T260
Test name
Test status
Simulation time 1962233976 ps
CPU time 162.52 seconds
Started Jul 14 07:53:42 PM PDT 24
Finished Jul 14 07:56:25 PM PDT 24
Peak memory 646144 kb
Host smart-0b807d99-7ecf-4040-a86b-39153eeb27ef
User root
Command /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689621579 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.1689621579
Directory /workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location /workspace/coverage/default/0.chip_sw_pattgen_ios.433867655
Short name T214
Test name
Test status
Simulation time 3271450878 ps
CPU time 267.21 seconds
Started Jul 14 07:51:48 PM PDT 24
Finished Jul 14 07:56:16 PM PDT 24
Peak memory 612592 kb
Host smart-8166f5c6-55a8-4032-979d-2096dc5d4f02
User root
Command /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433867655 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.433867655
Directory /workspace/0.chip_sw_pattgen_ios/latest

Test location /workspace/coverage/default/0.chip_sw_edn_boot_mode.3315002366
Short name T462
Test name
Test status
Simulation time 2866746194 ps
CPU time 615.81 seconds
Started Jul 14 07:54:04 PM PDT 24
Finished Jul 14 08:04:20 PM PDT 24
Peak memory 608820 kb
Host smart-8270c7e6-b28b-4f96-a185-cdad0c7d7e63
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc
elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315002366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_
boot_mode.3315002366
Directory /workspace/0.chip_sw_edn_boot_mode/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.4062080356
Short name T149
Test name
Test status
Simulation time 17338881792 ps
CPU time 3951.11 seconds
Started Jul 14 08:00:32 PM PDT 24
Finished Jul 14 09:06:24 PM PDT 24
Peak memory 609904 kb
Host smart-1424618d-50f5-4a50-aa5c-fb9395ba05e1
User root
Command /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_
rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4062080356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.4062080356
Directory /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2784584250
Short name T401
Test name
Test status
Simulation time 13039220996 ps
CPU time 1712.58 seconds
Started Jul 14 07:54:36 PM PDT 24
Finished Jul 14 08:23:10 PM PDT 24
Peak memory 610656 kb
Host smart-b2ae18d8-f1b3-4394-ad24-ab952eb9025f
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784
584250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.2784584250
Directory /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2183081999
Short name T1135
Test name
Test status
Simulation time 24454826600 ps
CPU time 5392.75 seconds
Started Jul 14 08:02:39 PM PDT 24
Finished Jul 14 09:32:33 PM PDT 24
Peak memory 608880 kb
Host smart-1a866299-854e-4ddd-893b-847c4bf79c80
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2183081999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2183081999
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3994078423
Short name T2081
Test name
Test status
Simulation time 28956545648 ps
CPU time 6264.93 seconds
Started Jul 14 07:26:45 PM PDT 24
Finished Jul 14 09:11:11 PM PDT 24
Peak memory 593852 kb
Host smart-fd570d08-a1aa-4d6a-935c-607be8000f27
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994078423 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.chip_csr_aliasing.3994078423
Directory /workspace/0.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2983734983
Short name T2006
Test name
Test status
Simulation time 10299028008 ps
CPU time 1425.95 seconds
Started Jul 14 07:26:42 PM PDT 24
Finished Jul 14 07:50:28 PM PDT 24
Peak memory 592896 kb
Host smart-30f48a7b-8edf-4bf2-b6f9-d0665ef40d23
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983734983 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.2983734983
Directory /workspace/0.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2364170180
Short name T138
Test name
Test status
Simulation time 7404150855 ps
CPU time 343.08 seconds
Started Jul 14 07:26:59 PM PDT 24
Finished Jul 14 07:32:42 PM PDT 24
Peak memory 661836 kb
Host smart-dfb6cc62-253f-42a0-9384-d365fbe32992
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364170180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r
eset.2364170180
Directory /workspace/0.chip_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_rw.1402139583
Short name T2729
Test name
Test status
Simulation time 4421046576 ps
CPU time 331.08 seconds
Started Jul 14 07:26:58 PM PDT 24
Finished Jul 14 07:32:29 PM PDT 24
Peak memory 598596 kb
Host smart-b762928b-f5f8-413d-850a-209185a455ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402139583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.1402139583
Directory /workspace/0.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.372887482
Short name T472
Test name
Test status
Simulation time 11503458612 ps
CPU time 462.56 seconds
Started Jul 14 07:26:48 PM PDT 24
Finished Jul 14 07:34:32 PM PDT 24
Peak memory 590608 kb
Host smart-7a29ca47-26f9-4cad-9b48-8b0d44b25f75
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372887482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.chip_prim_tl_access.372887482
Directory /workspace/0.chip_prim_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.579199308
Short name T1913
Test name
Test status
Simulation time 14490129242 ps
CPU time 533.68 seconds
Started Jul 14 07:26:49 PM PDT 24
Finished Jul 14 07:35:43 PM PDT 24
Peak memory 591476 kb
Host smart-54008e30-dfac-4f1c-9a05-7de62ac1834a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579199308 -assert nopostproc +UVM_TESTNAME=chip_base_te
st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.chip_rv_dm_lc_disabled.579199308
Directory /workspace/0.chip_rv_dm_lc_disabled/latest

Test location /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2783789906
Short name T398
Test name
Test status
Simulation time 16511364573 ps
CPU time 2245.04 seconds
Started Jul 14 07:26:44 PM PDT 24
Finished Jul 14 08:04:10 PM PDT 24
Peak memory 592960 kb
Host smart-f513c0b4-af4f-45cd-8216-306bf3900a51
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783789906 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.2783789906
Directory /workspace/0.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.chip_tl_errors.2666272476
Short name T698
Test name
Test status
Simulation time 3953934852 ps
CPU time 230.02 seconds
Started Jul 14 07:26:49 PM PDT 24
Finished Jul 14 07:30:39 PM PDT 24
Peak memory 603788 kb
Host smart-5596e5e7-01a5-47c4-9821-0c6ae5cd8d1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666272476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.2666272476
Directory /workspace/0.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_access_same_device.681305648
Short name T2645
Test name
Test status
Simulation time 1345057370 ps
CPU time 51.76 seconds
Started Jul 14 07:26:53 PM PDT 24
Finished Jul 14 07:27:45 PM PDT 24
Peak memory 575336 kb
Host smart-5e218546-ddec-4d5b-af61-a7f0027375d1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681305648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.681305648
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.4024269432
Short name T1461
Test name
Test status
Simulation time 88634043094 ps
CPU time 1576.92 seconds
Started Jul 14 07:26:56 PM PDT 24
Finished Jul 14 07:53:13 PM PDT 24
Peak memory 575524 kb
Host smart-5945370e-529d-4666-9234-5471c912076d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024269432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d
evice_slow_rsp.4024269432
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3373588376
Short name T1390
Test name
Test status
Simulation time 123163804 ps
CPU time 12.89 seconds
Started Jul 14 07:26:59 PM PDT 24
Finished Jul 14 07:27:12 PM PDT 24
Peak memory 575356 kb
Host smart-68ae962d-f3ac-491d-b848-f46ac1f81143
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373588376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr
.3373588376
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_error_random.2736808551
Short name T483
Test name
Test status
Simulation time 805661660 ps
CPU time 29.57 seconds
Started Jul 14 07:26:54 PM PDT 24
Finished Jul 14 07:27:24 PM PDT 24
Peak memory 575276 kb
Host smart-a36758cc-2f68-49fa-aea8-59bd70e2b131
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736808551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2736808551
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random.3502849917
Short name T1801
Test name
Test status
Simulation time 346953280 ps
CPU time 15.67 seconds
Started Jul 14 07:26:48 PM PDT 24
Finished Jul 14 07:27:05 PM PDT 24
Peak memory 575312 kb
Host smart-7bcfd6f7-f170-420c-8b9a-4ece63ca2a18
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502849917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.3502849917
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3847772128
Short name T2058
Test name
Test status
Simulation time 66453246599 ps
CPU time 694.93 seconds
Started Jul 14 07:26:59 PM PDT 24
Finished Jul 14 07:38:34 PM PDT 24
Peak memory 575532 kb
Host smart-7008b661-5484-4bc7-9cc2-d4b3ca58dc12
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847772128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3847772128
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1538792515
Short name T2114
Test name
Test status
Simulation time 54288065908 ps
CPU time 991.88 seconds
Started Jul 14 07:26:51 PM PDT 24
Finished Jul 14 07:43:24 PM PDT 24
Peak memory 575444 kb
Host smart-48b4aae5-a025-48ee-86c7-4477371b30ff
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538792515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1538792515
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.888671510
Short name T1357
Test name
Test status
Simulation time 226925853 ps
CPU time 23.6 seconds
Started Jul 14 07:26:49 PM PDT 24
Finished Jul 14 07:27:14 PM PDT 24
Peak memory 575348 kb
Host smart-864524d5-7bdc-43e4-be8e-d543b5c274d6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888671510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delay
s.888671510
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_same_source.1575696599
Short name T1689
Test name
Test status
Simulation time 2361067125 ps
CPU time 76.24 seconds
Started Jul 14 07:26:53 PM PDT 24
Finished Jul 14 07:28:09 PM PDT 24
Peak memory 575348 kb
Host smart-7d8ab5ca-50a5-4353-a21f-e68103c02506
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575696599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1575696599
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke.1269810881
Short name T1477
Test name
Test status
Simulation time 184776951 ps
CPU time 8.64 seconds
Started Jul 14 07:26:47 PM PDT 24
Finished Jul 14 07:26:57 PM PDT 24
Peak memory 573960 kb
Host smart-88d27842-2800-4edf-bd4b-0e9ce6a44526
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269810881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1269810881
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2729023214
Short name T1441
Test name
Test status
Simulation time 8862594260 ps
CPU time 95.68 seconds
Started Jul 14 07:26:47 PM PDT 24
Finished Jul 14 07:28:23 PM PDT 24
Peak memory 574136 kb
Host smart-bced1f62-4555-485e-9d73-091a8c3882f8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729023214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2729023214
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3200265909
Short name T1373
Test name
Test status
Simulation time 3042519218 ps
CPU time 56.82 seconds
Started Jul 14 07:26:49 PM PDT 24
Finished Jul 14 07:27:46 PM PDT 24
Peak memory 575380 kb
Host smart-c6433ea0-55fa-45f7-a661-1539b3de94fa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200265909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3200265909
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2836871058
Short name T2592
Test name
Test status
Simulation time 40644892 ps
CPU time 6.11 seconds
Started Jul 14 07:26:47 PM PDT 24
Finished Jul 14 07:26:54 PM PDT 24
Peak memory 574016 kb
Host smart-b7b64d61-c711-43fc-b1f1-ea77a261b8a6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836871058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays
.2836871058
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all.2487099199
Short name T2175
Test name
Test status
Simulation time 1144963636 ps
CPU time 99.43 seconds
Started Jul 14 07:26:54 PM PDT 24
Finished Jul 14 07:28:34 PM PDT 24
Peak memory 575496 kb
Host smart-d5c19b6e-b976-4898-ae3e-211dac6fe8d5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487099199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2487099199
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.988628033
Short name T841
Test name
Test status
Simulation time 1445208038 ps
CPU time 100.15 seconds
Started Jul 14 07:26:54 PM PDT 24
Finished Jul 14 07:28:35 PM PDT 24
Peak memory 575508 kb
Host smart-98165338-758d-4c9d-a71e-5a1eb367efaf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988628033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.988628033
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.914921320
Short name T2237
Test name
Test status
Simulation time 56048722 ps
CPU time 27.05 seconds
Started Jul 14 07:26:54 PM PDT 24
Finished Jul 14 07:27:22 PM PDT 24
Peak memory 575484 kb
Host smart-484eeb0c-9753-46e0-b27e-b33fe72b68cf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914921320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_w
ith_rand_reset.914921320
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2688875387
Short name T2734
Test name
Test status
Simulation time 9295733322 ps
CPU time 838.24 seconds
Started Jul 14 07:26:53 PM PDT 24
Finished Jul 14 07:40:52 PM PDT 24
Peak memory 582592 kb
Host smart-d77faa24-de65-4380-8edd-033fb9dbd98d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688875387 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all
_with_reset_error.2688875387
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1482382566
Short name T1712
Test name
Test status
Simulation time 40118114 ps
CPU time 7.91 seconds
Started Jul 14 07:26:55 PM PDT 24
Finished Jul 14 07:27:04 PM PDT 24
Peak memory 574148 kb
Host smart-646261e5-9561-4335-9b71-de72304e22df
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482382566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1482382566
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3262334143
Short name T475
Test name
Test status
Simulation time 8433801912 ps
CPU time 994.45 seconds
Started Jul 14 07:26:59 PM PDT 24
Finished Jul 14 07:43:34 PM PDT 24
Peak memory 592928 kb
Host smart-0dfac179-e9a6-4c41-b735-e5a55a29db31
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262334143 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.3262334143
Directory /workspace/1.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_rw.836834388
Short name T1621
Test name
Test status
Simulation time 5978893700 ps
CPU time 632.04 seconds
Started Jul 14 07:27:12 PM PDT 24
Finished Jul 14 07:37:45 PM PDT 24
Peak memory 599324 kb
Host smart-e4d3e952-ab78-40ba-8cba-e42b3facd5bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836834388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.836834388
Directory /workspace/1.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.4240801085
Short name T1764
Test name
Test status
Simulation time 4446470768 ps
CPU time 225.48 seconds
Started Jul 14 07:26:58 PM PDT 24
Finished Jul 14 07:30:44 PM PDT 24
Peak memory 589468 kb
Host smart-5971a0f5-e8fe-4d4e-b819-6cdb44d67839
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240801085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.chip_prim_tl_access.4240801085
Directory /workspace/1.chip_prim_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1207110774
Short name T2782
Test name
Test status
Simulation time 8862518404 ps
CPU time 356.25 seconds
Started Jul 14 07:27:01 PM PDT 24
Finished Jul 14 07:32:58 PM PDT 24
Peak memory 590380 kb
Host smart-1175a938-5599-412a-b7c1-8fa11baa617a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207110774 -assert nopostproc +UVM_TESTNAME=chip_base_t
est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.chip_rv_dm_lc_disabled.1207110774
Directory /workspace/1.chip_rv_dm_lc_disabled/latest

Test location /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.748124216
Short name T2262
Test name
Test status
Simulation time 15171425407 ps
CPU time 2042.29 seconds
Started Jul 14 07:26:58 PM PDT 24
Finished Jul 14 08:01:01 PM PDT 24
Peak memory 593048 kb
Host smart-13146a12-4242-4e2d-b2a8-178bf304473a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748124216 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.chip_same_csr_outstanding.748124216
Directory /workspace/1.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_access_same_device.462821958
Short name T2625
Test name
Test status
Simulation time 701641284 ps
CPU time 52.91 seconds
Started Jul 14 07:27:02 PM PDT 24
Finished Jul 14 07:27:56 PM PDT 24
Peak memory 575376 kb
Host smart-efdb2a69-b3fe-4322-bdf4-d679751284e3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462821958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.462821958
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.4129731083
Short name T2098
Test name
Test status
Simulation time 48571923104 ps
CPU time 833.39 seconds
Started Jul 14 07:27:06 PM PDT 24
Finished Jul 14 07:41:00 PM PDT 24
Peak memory 575544 kb
Host smart-e40fa006-0d81-49e0-ba7a-a562bbccc3e0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129731083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d
evice_slow_rsp.4129731083
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1349343963
Short name T2492
Test name
Test status
Simulation time 492095626 ps
CPU time 21.38 seconds
Started Jul 14 07:27:08 PM PDT 24
Finished Jul 14 07:27:30 PM PDT 24
Peak memory 575320 kb
Host smart-2dc4e20f-224a-4cc2-a2e3-b8e45eca8e89
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349343963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr
.1349343963
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_error_random.1645032706
Short name T1629
Test name
Test status
Simulation time 1266459750 ps
CPU time 44.32 seconds
Started Jul 14 07:27:16 PM PDT 24
Finished Jul 14 07:28:01 PM PDT 24
Peak memory 575268 kb
Host smart-e604c73d-cdb6-4779-b31a-64ee196355a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645032706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1645032706
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random.3735480390
Short name T2477
Test name
Test status
Simulation time 1821054061 ps
CPU time 72.19 seconds
Started Jul 14 07:27:05 PM PDT 24
Finished Jul 14 07:28:18 PM PDT 24
Peak memory 575340 kb
Host smart-5f429c19-cae9-46f4-955b-439d7d58621f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735480390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.3735480390
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3004115367
Short name T2151
Test name
Test status
Simulation time 79069436008 ps
CPU time 871.7 seconds
Started Jul 14 07:27:05 PM PDT 24
Finished Jul 14 07:41:37 PM PDT 24
Peak memory 575480 kb
Host smart-17a66f24-a31c-4d6e-9de0-2a74a21b0eb9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004115367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3004115367
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1074301375
Short name T2866
Test name
Test status
Simulation time 23409190735 ps
CPU time 407.39 seconds
Started Jul 14 07:27:03 PM PDT 24
Finished Jul 14 07:33:51 PM PDT 24
Peak memory 575420 kb
Host smart-def09bad-6d60-420e-a962-9d235591e41f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074301375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1074301375
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.80322553
Short name T571
Test name
Test status
Simulation time 598508542 ps
CPU time 55.83 seconds
Started Jul 14 07:27:03 PM PDT 24
Finished Jul 14 07:27:59 PM PDT 24
Peak memory 575328 kb
Host smart-8e45e399-fe21-4272-895d-29de6f630e4a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80322553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays
.80322553
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_same_source.2476852354
Short name T2013
Test name
Test status
Simulation time 2504568901 ps
CPU time 79.78 seconds
Started Jul 14 07:27:02 PM PDT 24
Finished Jul 14 07:28:23 PM PDT 24
Peak memory 575400 kb
Host smart-64883517-658c-4cbf-943c-a5e308e037d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476852354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2476852354
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke.2986862311
Short name T1649
Test name
Test status
Simulation time 179469049 ps
CPU time 8.15 seconds
Started Jul 14 07:27:05 PM PDT 24
Finished Jul 14 07:27:14 PM PDT 24
Peak memory 575156 kb
Host smart-3d11628c-388a-47ec-9d5b-563e3d206fa3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986862311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2986862311
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2641399746
Short name T2294
Test name
Test status
Simulation time 8696495589 ps
CPU time 103.32 seconds
Started Jul 14 07:27:02 PM PDT 24
Finished Jul 14 07:28:46 PM PDT 24
Peak memory 574200 kb
Host smart-771398f2-78d0-418b-9a56-10eba9cb626b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641399746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2641399746
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.892342087
Short name T1334
Test name
Test status
Simulation time 4669426627 ps
CPU time 82.18 seconds
Started Jul 14 07:27:03 PM PDT 24
Finished Jul 14 07:28:26 PM PDT 24
Peak memory 575392 kb
Host smart-3e82b052-bf36-4f63-9fc6-9b04d5d1229e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892342087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.892342087
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1358816033
Short name T1618
Test name
Test status
Simulation time 44022675 ps
CPU time 6.26 seconds
Started Jul 14 07:27:03 PM PDT 24
Finished Jul 14 07:27:09 PM PDT 24
Peak memory 574080 kb
Host smart-2a15e384-2a62-4a28-bb2a-6c3ce6c86f34
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358816033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays
.1358816033
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all.1401372326
Short name T2370
Test name
Test status
Simulation time 2321026427 ps
CPU time 197.84 seconds
Started Jul 14 07:27:08 PM PDT 24
Finished Jul 14 07:30:27 PM PDT 24
Peak memory 575560 kb
Host smart-4e606ec4-c11a-419a-986f-0363c0ca1c7c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401372326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1401372326
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.3703801978
Short name T2839
Test name
Test status
Simulation time 2189901086 ps
CPU time 75.5 seconds
Started Jul 14 07:27:16 PM PDT 24
Finished Jul 14 07:28:32 PM PDT 24
Peak memory 575312 kb
Host smart-a2fa37f6-8b61-4cf8-98e4-fc9fe50abf4c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703801978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.3703801978
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.951845896
Short name T1494
Test name
Test status
Simulation time 159767595 ps
CPU time 54.2 seconds
Started Jul 14 07:27:10 PM PDT 24
Finished Jul 14 07:28:04 PM PDT 24
Peak memory 575464 kb
Host smart-04a6d8ef-82e9-4519-a014-efaa05330ded
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951845896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_w
ith_rand_reset.951845896
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.961056042
Short name T1617
Test name
Test status
Simulation time 102829145 ps
CPU time 48.06 seconds
Started Jul 14 07:27:16 PM PDT 24
Finished Jul 14 07:28:05 PM PDT 24
Peak memory 575384 kb
Host smart-ab3fd242-2d85-45cc-9049-0ecdb277d33a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961056042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_
with_reset_error.961056042
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3617771202
Short name T2025
Test name
Test status
Simulation time 356686456 ps
CPU time 17.34 seconds
Started Jul 14 07:27:09 PM PDT 24
Finished Jul 14 07:27:27 PM PDT 24
Peak memory 575388 kb
Host smart-ca619b68-d4e2-4a62-93ed-88d29839942d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617771202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3617771202
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/10.chip_csr_rw.4148315137
Short name T2521
Test name
Test status
Simulation time 5983969140 ps
CPU time 606.86 seconds
Started Jul 14 07:29:34 PM PDT 24
Finished Jul 14 07:39:41 PM PDT 24
Peak memory 598784 kb
Host smart-27c9b413-a838-4847-bac6-0b3c8deb5ea4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148315137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.4148315137
Directory /workspace/10.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.656107724
Short name T474
Test name
Test status
Simulation time 14878275575 ps
CPU time 2079.94 seconds
Started Jul 14 07:29:19 PM PDT 24
Finished Jul 14 08:03:59 PM PDT 24
Peak memory 591820 kb
Host smart-1bf29f8f-f549-4565-b71f-bbfe368fbee3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656107724 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.chip_same_csr_outstanding.656107724
Directory /workspace/10.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.chip_tl_errors.3039043002
Short name T694
Test name
Test status
Simulation time 2960266638 ps
CPU time 168.14 seconds
Started Jul 14 07:29:22 PM PDT 24
Finished Jul 14 07:32:10 PM PDT 24
Peak memory 598732 kb
Host smart-99f4bffe-9fd5-4064-8f37-95a5a0cae4df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039043002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.3039043002
Directory /workspace/10.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_access_same_device.1229331387
Short name T2198
Test name
Test status
Simulation time 126503172 ps
CPU time 15.38 seconds
Started Jul 14 07:29:26 PM PDT 24
Finished Jul 14 07:29:42 PM PDT 24
Peak memory 575288 kb
Host smart-fc36eb28-d466-4fdd-b8bb-8e6ce1a8455e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229331387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device
.1229331387
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2248677728
Short name T1586
Test name
Test status
Simulation time 60182593442 ps
CPU time 1049.32 seconds
Started Jul 14 07:29:32 PM PDT 24
Finished Jul 14 07:47:02 PM PDT 24
Peak memory 575536 kb
Host smart-d43b05e4-445e-41eb-a9be-d74819d98321
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248677728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_
device_slow_rsp.2248677728
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1609089297
Short name T1756
Test name
Test status
Simulation time 66870942 ps
CPU time 9.42 seconds
Started Jul 14 07:29:30 PM PDT 24
Finished Jul 14 07:29:40 PM PDT 24
Peak memory 575348 kb
Host smart-9baee936-b759-41e5-ad36-584125acce6b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609089297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add
r.1609089297
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_error_random.373500698
Short name T1876
Test name
Test status
Simulation time 420902169 ps
CPU time 34.53 seconds
Started Jul 14 07:29:27 PM PDT 24
Finished Jul 14 07:30:02 PM PDT 24
Peak memory 575056 kb
Host smart-33d52801-fff5-4fa0-902d-9480b600482c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373500698 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.373500698
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random.3347401836
Short name T1718
Test name
Test status
Simulation time 199448025 ps
CPU time 17.32 seconds
Started Jul 14 07:29:26 PM PDT 24
Finished Jul 14 07:29:44 PM PDT 24
Peak memory 575324 kb
Host smart-14c38bc4-cab8-47f1-bd60-bf51534e668a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347401836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.3347401836
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3576595278
Short name T1674
Test name
Test status
Simulation time 77159480915 ps
CPU time 879.26 seconds
Started Jul 14 07:29:32 PM PDT 24
Finished Jul 14 07:44:12 PM PDT 24
Peak memory 575516 kb
Host smart-9d7d2291-5702-490a-9070-db0be1da0390
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576595278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3576595278
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3237936767
Short name T1998
Test name
Test status
Simulation time 6439601201 ps
CPU time 100.68 seconds
Started Jul 14 07:29:27 PM PDT 24
Finished Jul 14 07:31:08 PM PDT 24
Peak memory 575448 kb
Host smart-86526b92-4e97-4705-b6a9-46d478b1c289
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237936767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3237936767
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.2010143313
Short name T1705
Test name
Test status
Simulation time 578134643 ps
CPU time 45.62 seconds
Started Jul 14 07:29:26 PM PDT 24
Finished Jul 14 07:30:12 PM PDT 24
Peak memory 575372 kb
Host smart-56fe11b5-b864-4843-9a25-d92c7adb9dd0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010143313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_del
ays.2010143313
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_same_source.3313685578
Short name T2048
Test name
Test status
Simulation time 2219757868 ps
CPU time 58.12 seconds
Started Jul 14 07:29:26 PM PDT 24
Finished Jul 14 07:30:24 PM PDT 24
Peak memory 575448 kb
Host smart-420b42ef-9900-4fbf-9fee-32179285f464
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313685578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3313685578
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke.3454327361
Short name T2881
Test name
Test status
Simulation time 46791361 ps
CPU time 6.08 seconds
Started Jul 14 07:29:20 PM PDT 24
Finished Jul 14 07:29:27 PM PDT 24
Peak memory 575236 kb
Host smart-729c4c29-8552-482e-85d8-6ca6aa844fa9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454327361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3454327361
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1934311799
Short name T2889
Test name
Test status
Simulation time 10110353114 ps
CPU time 111.63 seconds
Started Jul 14 07:29:28 PM PDT 24
Finished Jul 14 07:31:20 PM PDT 24
Peak memory 575368 kb
Host smart-dc85e1e1-610d-44f7-8512-21551f4add33
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934311799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1934311799
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.664179904
Short name T1612
Test name
Test status
Simulation time 5042150365 ps
CPU time 97.17 seconds
Started Jul 14 07:29:26 PM PDT 24
Finished Jul 14 07:31:03 PM PDT 24
Peak memory 575428 kb
Host smart-ecb6551b-5eb5-4d8f-9c88-35d72f4852cb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664179904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.664179904
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2925022700
Short name T2385
Test name
Test status
Simulation time 47467976 ps
CPU time 6.44 seconds
Started Jul 14 07:29:26 PM PDT 24
Finished Jul 14 07:29:33 PM PDT 24
Peak memory 574028 kb
Host smart-d42f96a9-2bdb-4fb2-a3e8-fab8901692d8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925022700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay
s.2925022700
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all.2481661054
Short name T591
Test name
Test status
Simulation time 3296895553 ps
CPU time 127.32 seconds
Started Jul 14 07:29:30 PM PDT 24
Finished Jul 14 07:31:38 PM PDT 24
Peak memory 575556 kb
Host smart-e777a0b2-875a-424f-9053-fe3a60caa190
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481661054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2481661054
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.4002526216
Short name T2038
Test name
Test status
Simulation time 1492666682 ps
CPU time 117.78 seconds
Started Jul 14 07:29:32 PM PDT 24
Finished Jul 14 07:31:30 PM PDT 24
Peak memory 575452 kb
Host smart-0727a601-dc51-4396-82b9-2eaa6105048e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002526216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.4002526216
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2804414168
Short name T122
Test name
Test status
Simulation time 205119776 ps
CPU time 50.94 seconds
Started Jul 14 07:29:35 PM PDT 24
Finished Jul 14 07:30:26 PM PDT 24
Peak memory 575472 kb
Host smart-5773b6a7-c315-4628-9542-646e12020020
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804414168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all
_with_rand_reset.2804414168
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1382527390
Short name T1659
Test name
Test status
Simulation time 3692989160 ps
CPU time 412.25 seconds
Started Jul 14 07:29:31 PM PDT 24
Finished Jul 14 07:36:23 PM PDT 24
Peak memory 575524 kb
Host smart-46a2c053-d36a-411e-99da-6318eced2cd8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382527390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al
l_with_reset_error.1382527390
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.4045469998
Short name T1386
Test name
Test status
Simulation time 230092127 ps
CPU time 30.94 seconds
Started Jul 14 07:29:32 PM PDT 24
Finished Jul 14 07:30:03 PM PDT 24
Peak memory 575388 kb
Host smart-aaacdcff-de8c-45cd-a4ce-b4ebf628423c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045469998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.4045469998
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/11.chip_csr_rw.3619914364
Short name T415
Test name
Test status
Simulation time 4669773736 ps
CPU time 353.8 seconds
Started Jul 14 07:29:49 PM PDT 24
Finished Jul 14 07:35:44 PM PDT 24
Peak memory 598244 kb
Host smart-92358bab-ce49-4bfa-b9a2-a6a0d4f422f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619914364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.3619914364
Directory /workspace/11.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3708451946
Short name T405
Test name
Test status
Simulation time 29581955952 ps
CPU time 4752.36 seconds
Started Jul 14 07:29:35 PM PDT 24
Finished Jul 14 08:48:48 PM PDT 24
Peak memory 592960 kb
Host smart-98f67c7f-c36d-420c-87e4-1f7eca521a92
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708451946 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.3708451946
Directory /workspace/11.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.chip_tl_errors.4019537296
Short name T647
Test name
Test status
Simulation time 3410912770 ps
CPU time 136.72 seconds
Started Jul 14 07:29:30 PM PDT 24
Finished Jul 14 07:31:47 PM PDT 24
Peak memory 603912 kb
Host smart-172aba04-22f8-4aa6-a80a-dd579da84494
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019537296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.4019537296
Directory /workspace/11.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_access_same_device.642653722
Short name T2546
Test name
Test status
Simulation time 4029071060 ps
CPU time 166 seconds
Started Jul 14 07:29:39 PM PDT 24
Finished Jul 14 07:32:25 PM PDT 24
Peak memory 575432 kb
Host smart-82b33198-956b-4681-a4d8-984f69944123
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642653722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.
642653722
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1190853862
Short name T521
Test name
Test status
Simulation time 41377919134 ps
CPU time 726.09 seconds
Started Jul 14 07:29:37 PM PDT 24
Finished Jul 14 07:41:44 PM PDT 24
Peak memory 575468 kb
Host smart-4c30d9bc-a0e2-49e4-b1b0-8008df7ba829
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190853862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_
device_slow_rsp.1190853862
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.914330901
Short name T2628
Test name
Test status
Simulation time 24216272 ps
CPU time 5.68 seconds
Started Jul 14 07:29:39 PM PDT 24
Finished Jul 14 07:29:45 PM PDT 24
Peak memory 575256 kb
Host smart-31bf993c-055e-439d-8e00-c149dff63b18
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914330901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr
.914330901
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random.2150719856
Short name T2451
Test name
Test status
Simulation time 427980882 ps
CPU time 38.11 seconds
Started Jul 14 07:29:38 PM PDT 24
Finished Jul 14 07:30:17 PM PDT 24
Peak memory 575344 kb
Host smart-3ea56b3f-cdd2-4e91-a7a8-8b27db92947c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150719856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.2150719856
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3040444277
Short name T2419
Test name
Test status
Simulation time 49895196509 ps
CPU time 538.35 seconds
Started Jul 14 07:29:38 PM PDT 24
Finished Jul 14 07:38:37 PM PDT 24
Peak memory 575516 kb
Host smart-b8e2acad-50fa-4425-892e-065ccb3f58d2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040444277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3040444277
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3510393302
Short name T2803
Test name
Test status
Simulation time 19552839746 ps
CPU time 343.34 seconds
Started Jul 14 07:29:39 PM PDT 24
Finished Jul 14 07:35:23 PM PDT 24
Peak memory 575432 kb
Host smart-667ef65d-849c-458c-9d7e-06186f0fefab
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510393302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3510393302
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1592462411
Short name T1813
Test name
Test status
Simulation time 29919715 ps
CPU time 5.84 seconds
Started Jul 14 07:29:41 PM PDT 24
Finished Jul 14 07:29:47 PM PDT 24
Peak memory 575320 kb
Host smart-add1ea57-53ca-45e5-8a1f-107ad4d33fa6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592462411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del
ays.1592462411
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_same_source.925914277
Short name T1737
Test name
Test status
Simulation time 1934815361 ps
CPU time 59.46 seconds
Started Jul 14 07:29:39 PM PDT 24
Finished Jul 14 07:30:39 PM PDT 24
Peak memory 575336 kb
Host smart-845bdf48-d3af-4ffe-ae52-2982f6bb5bd2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925914277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.925914277
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke.232419529
Short name T1697
Test name
Test status
Simulation time 165436480 ps
CPU time 8.23 seconds
Started Jul 14 07:29:31 PM PDT 24
Finished Jul 14 07:29:40 PM PDT 24
Peak memory 575256 kb
Host smart-211a83d0-c2a2-4b32-97ac-261a970b4520
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232419529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.232419529
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.3806230252
Short name T1657
Test name
Test status
Simulation time 9492225361 ps
CPU time 106.21 seconds
Started Jul 14 07:29:38 PM PDT 24
Finished Jul 14 07:31:25 PM PDT 24
Peak memory 574180 kb
Host smart-847a9ea3-b9bf-4af8-bdc2-0778aac2461f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806230252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3806230252
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.399044321
Short name T2173
Test name
Test status
Simulation time 4756658068 ps
CPU time 86.7 seconds
Started Jul 14 07:29:38 PM PDT 24
Finished Jul 14 07:31:06 PM PDT 24
Peak memory 575416 kb
Host smart-97ab837a-14d9-44cf-9945-177383650c5e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399044321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.399044321
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.4213879244
Short name T89
Test name
Test status
Simulation time 48482293 ps
CPU time 6.43 seconds
Started Jul 14 07:29:31 PM PDT 24
Finished Jul 14 07:29:38 PM PDT 24
Peak memory 574040 kb
Host smart-da8dbd47-61ed-411b-8625-9cc3db002194
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213879244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay
s.4213879244
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all.248310187
Short name T2354
Test name
Test status
Simulation time 6972862018 ps
CPU time 287.79 seconds
Started Jul 14 07:29:40 PM PDT 24
Finished Jul 14 07:34:28 PM PDT 24
Peak memory 575620 kb
Host smart-dd1ce283-cd0e-4d61-8d17-2bfd7e2a5ba5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248310187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.248310187
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3287235498
Short name T2496
Test name
Test status
Simulation time 3620316334 ps
CPU time 154.9 seconds
Started Jul 14 07:29:42 PM PDT 24
Finished Jul 14 07:32:17 PM PDT 24
Peak memory 575520 kb
Host smart-18238dde-bf89-4eb0-8db4-4201d88ea5f1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287235498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3287235498
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2775453089
Short name T2251
Test name
Test status
Simulation time 323191655 ps
CPU time 166.2 seconds
Started Jul 14 07:29:39 PM PDT 24
Finished Jul 14 07:32:26 PM PDT 24
Peak memory 575476 kb
Host smart-5ddb3ae3-99c5-4ec7-a49b-315e4dfab760
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775453089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all
_with_rand_reset.2775453089
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.150205536
Short name T2446
Test name
Test status
Simulation time 3014973417 ps
CPU time 295.27 seconds
Started Jul 14 07:29:42 PM PDT 24
Finished Jul 14 07:34:38 PM PDT 24
Peak memory 575512 kb
Host smart-18105f21-9408-41b7-bc03-91a11753e041
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150205536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all
_with_reset_error.150205536
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.735939250
Short name T1381
Test name
Test status
Simulation time 126650260 ps
CPU time 17.49 seconds
Started Jul 14 07:29:43 PM PDT 24
Finished Jul 14 07:30:01 PM PDT 24
Peak memory 575584 kb
Host smart-b6da3cfc-8940-4265-91a3-68b99b3e8bc2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735939250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.735939250
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/12.chip_csr_rw.663120707
Short name T2424
Test name
Test status
Simulation time 6053105835 ps
CPU time 659.72 seconds
Started Jul 14 07:30:03 PM PDT 24
Finished Jul 14 07:41:03 PM PDT 24
Peak memory 599188 kb
Host smart-267bbc91-7072-4387-a4ae-6cb14fb5b7d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663120707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.663120707
Directory /workspace/12.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3627205115
Short name T143
Test name
Test status
Simulation time 15961237711 ps
CPU time 2037.4 seconds
Started Jul 14 07:29:50 PM PDT 24
Finished Jul 14 08:03:48 PM PDT 24
Peak memory 593352 kb
Host smart-83f12d6e-d859-4164-b01b-62d8a549db57
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627205115 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.3627205115
Directory /workspace/12.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.chip_tl_errors.1536867463
Short name T2503
Test name
Test status
Simulation time 5178227771 ps
CPU time 501.04 seconds
Started Jul 14 07:29:45 PM PDT 24
Finished Jul 14 07:38:06 PM PDT 24
Peak memory 603816 kb
Host smart-f8199495-5a29-481d-91ce-db5a1e879a2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536867463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.1536867463
Directory /workspace/12.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_access_same_device.16886559
Short name T1572
Test name
Test status
Simulation time 1740035322 ps
CPU time 79.93 seconds
Started Jul 14 07:29:47 PM PDT 24
Finished Jul 14 07:31:08 PM PDT 24
Peak memory 575296 kb
Host smart-951a4b4d-eac5-427c-a7de-2f91c390ad1f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16886559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.16886559
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.4072892548
Short name T827
Test name
Test status
Simulation time 146820146699 ps
CPU time 2943.06 seconds
Started Jul 14 07:29:47 PM PDT 24
Finished Jul 14 08:18:51 PM PDT 24
Peak memory 575540 kb
Host smart-681d4e89-1ed3-446a-853e-900fddee6c8d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072892548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_
device_slow_rsp.4072892548
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2003072242
Short name T1714
Test name
Test status
Simulation time 907717164 ps
CPU time 34.69 seconds
Started Jul 14 07:29:54 PM PDT 24
Finished Jul 14 07:30:29 PM PDT 24
Peak memory 575296 kb
Host smart-8c3ea29b-1e45-429d-ba1e-7e647ede5f60
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003072242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add
r.2003072242
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_error_random.3562345558
Short name T1792
Test name
Test status
Simulation time 512343425 ps
CPU time 18.8 seconds
Started Jul 14 07:29:52 PM PDT 24
Finished Jul 14 07:30:11 PM PDT 24
Peak memory 575284 kb
Host smart-35a86aca-1252-4921-871f-43f6be56d23c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562345558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.3562345558
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random.3798907927
Short name T594
Test name
Test status
Simulation time 358326970 ps
CPU time 31.54 seconds
Started Jul 14 07:29:48 PM PDT 24
Finished Jul 14 07:30:20 PM PDT 24
Peak memory 575336 kb
Host smart-8d296531-3c63-455c-9013-1fc028f5fd52
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798907927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.3798907927
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1096302661
Short name T1720
Test name
Test status
Simulation time 65615756229 ps
CPU time 728.3 seconds
Started Jul 14 07:29:47 PM PDT 24
Finished Jul 14 07:41:56 PM PDT 24
Peak memory 575460 kb
Host smart-9a58fea8-ff62-4eb6-99bf-e35d93fdd7d2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096302661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1096302661
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3654871569
Short name T1488
Test name
Test status
Simulation time 14427535283 ps
CPU time 257.52 seconds
Started Jul 14 07:29:47 PM PDT 24
Finished Jul 14 07:34:05 PM PDT 24
Peak memory 575468 kb
Host smart-58598466-f4a9-40b0-9dd0-f8ccb1a1dec1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654871569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3654871569
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2706874611
Short name T2766
Test name
Test status
Simulation time 295604259 ps
CPU time 28.59 seconds
Started Jul 14 07:29:49 PM PDT 24
Finished Jul 14 07:30:18 PM PDT 24
Peak memory 575272 kb
Host smart-011da953-256e-4457-b955-5923d02c1b9b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706874611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del
ays.2706874611
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_same_source.2351116525
Short name T1511
Test name
Test status
Simulation time 1862849799 ps
CPU time 59.74 seconds
Started Jul 14 07:29:53 PM PDT 24
Finished Jul 14 07:30:54 PM PDT 24
Peak memory 575312 kb
Host smart-b50e8823-9ce8-456d-a792-37eebb2ad1d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351116525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.2351116525
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke.428519913
Short name T2669
Test name
Test status
Simulation time 197377847 ps
CPU time 9.82 seconds
Started Jul 14 07:29:43 PM PDT 24
Finished Jul 14 07:29:53 PM PDT 24
Peak memory 573984 kb
Host smart-12538393-78e1-4f7f-b7cf-c3404bfbe7c4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428519913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.428519913
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.4038688149
Short name T2831
Test name
Test status
Simulation time 5661997535 ps
CPU time 66.97 seconds
Started Jul 14 07:29:45 PM PDT 24
Finished Jul 14 07:30:52 PM PDT 24
Peak memory 574392 kb
Host smart-171c53a3-5d24-442c-abcf-2efcebe260c2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038688149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.4038688149
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.965572239
Short name T2863
Test name
Test status
Simulation time 5434320637 ps
CPU time 101.73 seconds
Started Jul 14 07:29:42 PM PDT 24
Finished Jul 14 07:31:24 PM PDT 24
Peak memory 574248 kb
Host smart-ec8e3bc8-b107-4436-bf07-3a79b9be3531
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965572239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.965572239
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1313002276
Short name T1348
Test name
Test status
Simulation time 37982030 ps
CPU time 6.28 seconds
Started Jul 14 07:29:45 PM PDT 24
Finished Jul 14 07:29:52 PM PDT 24
Peak memory 574180 kb
Host smart-7ede4fb7-dfb5-46d0-b531-1fcb4d8364cc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313002276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay
s.1313002276
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all.2420347560
Short name T1870
Test name
Test status
Simulation time 3481582128 ps
CPU time 303.62 seconds
Started Jul 14 07:29:52 PM PDT 24
Finished Jul 14 07:34:56 PM PDT 24
Peak memory 575536 kb
Host smart-3229f7ec-f4a4-4775-b7bf-c565f94bf8a0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420347560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2420347560
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.913781550
Short name T2894
Test name
Test status
Simulation time 9400547717 ps
CPU time 322.88 seconds
Started Jul 14 07:29:55 PM PDT 24
Finished Jul 14 07:35:18 PM PDT 24
Peak memory 575600 kb
Host smart-6f935572-bb20-4b2c-8634-bbd204a298d7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913781550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.913781550
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2946761898
Short name T2298
Test name
Test status
Simulation time 4033213456 ps
CPU time 410.97 seconds
Started Jul 14 07:29:54 PM PDT 24
Finished Jul 14 07:36:45 PM PDT 24
Peak memory 575496 kb
Host smart-835db504-e694-4560-a45c-04856cb9f8f7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946761898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all
_with_rand_reset.2946761898
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.158025966
Short name T2356
Test name
Test status
Simulation time 1933752071 ps
CPU time 154.23 seconds
Started Jul 14 07:29:54 PM PDT 24
Finished Jul 14 07:32:28 PM PDT 24
Peak memory 575188 kb
Host smart-43236d7a-0c9e-4789-9e15-797dcb20d830
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158025966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all
_with_reset_error.158025966
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.123306860
Short name T2128
Test name
Test status
Simulation time 379825011 ps
CPU time 19.22 seconds
Started Jul 14 07:29:56 PM PDT 24
Finished Jul 14 07:30:15 PM PDT 24
Peak memory 575364 kb
Host smart-3a4561b4-e15f-4470-89f6-46152797da31
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123306860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.123306860
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1879869
Short name T2270
Test name
Test status
Simulation time 17074242182 ps
CPU time 2093.2 seconds
Started Jul 14 07:30:01 PM PDT 24
Finished Jul 14 08:04:55 PM PDT 24
Peak memory 593160 kb
Host smart-1882f917-d9f4-4c58-a54e-583d67382060
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879869 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.chip_same_csr_outstanding.1879869
Directory /workspace/13.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_access_same_device.1689712010
Short name T1368
Test name
Test status
Simulation time 878414107 ps
CPU time 41.23 seconds
Started Jul 14 07:30:00 PM PDT 24
Finished Jul 14 07:30:42 PM PDT 24
Peak memory 575332 kb
Host smart-f0c5fd02-5807-484b-9c8c-21a41e89610e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689712010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device
.1689712010
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1662265080
Short name T2396
Test name
Test status
Simulation time 78807673547 ps
CPU time 1464.95 seconds
Started Jul 14 07:30:05 PM PDT 24
Finished Jul 14 07:54:31 PM PDT 24
Peak memory 575520 kb
Host smart-c4dad8a5-9413-42e1-8fa9-8ec14143c812
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662265080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_
device_slow_rsp.1662265080
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.151513712
Short name T1534
Test name
Test status
Simulation time 1122863594 ps
CPU time 50.37 seconds
Started Jul 14 07:30:05 PM PDT 24
Finished Jul 14 07:30:56 PM PDT 24
Peak memory 575344 kb
Host smart-08c5e0cf-b38b-48d1-8949-d91afc555f4a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151513712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr
.151513712
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_error_random.1907920648
Short name T1688
Test name
Test status
Simulation time 275358961 ps
CPU time 24.23 seconds
Started Jul 14 07:30:04 PM PDT 24
Finished Jul 14 07:30:28 PM PDT 24
Peak memory 575276 kb
Host smart-62f633f0-88af-4b84-9f20-d01f174f9bc3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907920648 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1907920648
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random.3441737522
Short name T2004
Test name
Test status
Simulation time 105730331 ps
CPU time 11.38 seconds
Started Jul 14 07:30:03 PM PDT 24
Finished Jul 14 07:30:15 PM PDT 24
Peak memory 575352 kb
Host smart-e3929779-3c77-4292-a241-fe9e69707cc0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441737522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.3441737522
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2945782179
Short name T1408
Test name
Test status
Simulation time 49368998068 ps
CPU time 556.43 seconds
Started Jul 14 07:30:03 PM PDT 24
Finished Jul 14 07:39:20 PM PDT 24
Peak memory 575504 kb
Host smart-736c57f9-861b-44d2-afee-892db0f42999
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945782179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2945782179
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.4109632597
Short name T2533
Test name
Test status
Simulation time 52797596278 ps
CPU time 914.14 seconds
Started Jul 14 07:29:59 PM PDT 24
Finished Jul 14 07:45:15 PM PDT 24
Peak memory 575504 kb
Host smart-c7844730-7c80-4c4f-ab86-d2ce6d2ba2b7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109632597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.4109632597
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.2903601225
Short name T2149
Test name
Test status
Simulation time 24665623 ps
CPU time 5.81 seconds
Started Jul 14 07:29:58 PM PDT 24
Finished Jul 14 07:30:04 PM PDT 24
Peak memory 575328 kb
Host smart-a2a3e2fe-6a63-4bfc-b5bb-c85865874a6f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903601225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del
ays.2903601225
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_same_source.1582526555
Short name T2896
Test name
Test status
Simulation time 68811725 ps
CPU time 8.28 seconds
Started Jul 14 07:30:05 PM PDT 24
Finished Jul 14 07:30:14 PM PDT 24
Peak memory 575332 kb
Host smart-239f2c36-4395-4953-804a-28b48ca627ad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582526555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1582526555
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke.418331281
Short name T2747
Test name
Test status
Simulation time 215443965 ps
CPU time 10.01 seconds
Started Jul 14 07:29:58 PM PDT 24
Finished Jul 14 07:30:08 PM PDT 24
Peak memory 575332 kb
Host smart-8a0a3f5e-5041-4e2c-8949-0ee9e6465389
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418331281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.418331281
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.1489421280
Short name T2052
Test name
Test status
Simulation time 9735650780 ps
CPU time 106.67 seconds
Started Jul 14 07:30:00 PM PDT 24
Finished Jul 14 07:31:47 PM PDT 24
Peak memory 575424 kb
Host smart-d03c52af-b84d-4e07-b22a-b8c06b4595ae
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489421280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.1489421280
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.584534345
Short name T2608
Test name
Test status
Simulation time 6120642338 ps
CPU time 113.51 seconds
Started Jul 14 07:30:00 PM PDT 24
Finished Jul 14 07:31:54 PM PDT 24
Peak memory 575412 kb
Host smart-15658e13-50f4-469b-aa20-495d94ef9fd4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584534345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.584534345
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.625253794
Short name T1493
Test name
Test status
Simulation time 37448356 ps
CPU time 6.01 seconds
Started Jul 14 07:30:00 PM PDT 24
Finished Jul 14 07:30:07 PM PDT 24
Peak memory 573996 kb
Host smart-9e926a7f-729b-44ad-98cb-cd5ca14a36ed
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625253794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays
.625253794
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all.1124588120
Short name T620
Test name
Test status
Simulation time 6140611540 ps
CPU time 223.65 seconds
Started Jul 14 07:30:04 PM PDT 24
Finished Jul 14 07:33:49 PM PDT 24
Peak memory 575620 kb
Host smart-a9951701-0b00-4044-8fbb-1d3a74ff92d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124588120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1124588120
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.4131705350
Short name T1685
Test name
Test status
Simulation time 9806868378 ps
CPU time 365.15 seconds
Started Jul 14 07:30:05 PM PDT 24
Finished Jul 14 07:36:10 PM PDT 24
Peak memory 575572 kb
Host smart-cc7738a8-c773-4896-aa73-962aa3d95e9f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131705350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.4131705350
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3574360175
Short name T868
Test name
Test status
Simulation time 315202633 ps
CPU time 130.98 seconds
Started Jul 14 07:30:05 PM PDT 24
Finished Jul 14 07:32:17 PM PDT 24
Peak memory 575484 kb
Host smart-829ca4e9-5769-4d4f-b741-82e943d5a750
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574360175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all
_with_rand_reset.3574360175
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3100276255
Short name T2890
Test name
Test status
Simulation time 23399049 ps
CPU time 22.53 seconds
Started Jul 14 07:30:15 PM PDT 24
Finished Jul 14 07:30:38 PM PDT 24
Peak memory 575476 kb
Host smart-3788cb2b-ee26-4b4b-a0ea-aa690150d665
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100276255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al
l_with_reset_error.3100276255
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.556438077
Short name T2861
Test name
Test status
Simulation time 68730159 ps
CPU time 6.67 seconds
Started Jul 14 07:30:19 PM PDT 24
Finished Jul 14 07:30:26 PM PDT 24
Peak memory 575344 kb
Host smart-7fc59028-00ca-4d61-b6e0-daff01b9de70
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556438077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.556438077
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/14.chip_csr_rw.2960683450
Short name T476
Test name
Test status
Simulation time 3854381368 ps
CPU time 291.23 seconds
Started Jul 14 07:30:15 PM PDT 24
Finished Jul 14 07:35:06 PM PDT 24
Peak memory 597292 kb
Host smart-56d19847-dab9-41f7-a0dc-8f506ba9bb00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960683450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.2960683450
Directory /workspace/14.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3628906833
Short name T2272
Test name
Test status
Simulation time 28658297719 ps
CPU time 4239.27 seconds
Started Jul 14 07:30:04 PM PDT 24
Finished Jul 14 08:40:45 PM PDT 24
Peak memory 593548 kb
Host smart-22c8da1b-8938-4531-9df6-423bd79d3439
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628906833 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.3628906833
Directory /workspace/14.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_access_same_device.1873986103
Short name T2696
Test name
Test status
Simulation time 128338349 ps
CPU time 14.21 seconds
Started Jul 14 07:30:15 PM PDT 24
Finished Jul 14 07:30:30 PM PDT 24
Peak memory 575340 kb
Host smart-17dce8b9-3fbc-4a91-9f6b-8b439e7fda77
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873986103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device
.1873986103
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3653867409
Short name T2239
Test name
Test status
Simulation time 34078882382 ps
CPU time 596.19 seconds
Started Jul 14 07:30:11 PM PDT 24
Finished Jul 14 07:40:08 PM PDT 24
Peak memory 575528 kb
Host smart-7cc1e477-5b84-4af4-81aa-62c44a1d1537
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653867409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_
device_slow_rsp.3653867409
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3157781949
Short name T2416
Test name
Test status
Simulation time 1238681975 ps
CPU time 44.91 seconds
Started Jul 14 07:30:15 PM PDT 24
Finished Jul 14 07:31:00 PM PDT 24
Peak memory 575304 kb
Host smart-75c794a8-37ad-48e6-a9ca-dc6df9f7e99d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157781949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add
r.3157781949
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_error_random.1913227372
Short name T2600
Test name
Test status
Simulation time 725172890 ps
CPU time 27.73 seconds
Started Jul 14 07:30:15 PM PDT 24
Finished Jul 14 07:30:44 PM PDT 24
Peak memory 575304 kb
Host smart-12031ac6-ddd5-47c4-ab90-56a5d89e4aaa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913227372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1913227372
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random.2215470032
Short name T649
Test name
Test status
Simulation time 1489361652 ps
CPU time 60.77 seconds
Started Jul 14 07:30:10 PM PDT 24
Finished Jul 14 07:31:11 PM PDT 24
Peak memory 575380 kb
Host smart-898ff73e-b814-4f2a-a118-68bee7c669e3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215470032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.2215470032
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.120163245
Short name T651
Test name
Test status
Simulation time 21375153630 ps
CPU time 232.01 seconds
Started Jul 14 07:30:13 PM PDT 24
Finished Jul 14 07:34:05 PM PDT 24
Peak memory 575524 kb
Host smart-d5b3d800-bcb2-4e41-bd21-53f74a02389f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120163245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.120163245
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.336366244
Short name T2310
Test name
Test status
Simulation time 8651056336 ps
CPU time 150.09 seconds
Started Jul 14 07:30:10 PM PDT 24
Finished Jul 14 07:32:40 PM PDT 24
Peak memory 575448 kb
Host smart-f2a1fe2e-fded-4b6f-a5fc-0995e7b20e5c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336366244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.336366244
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.1353990123
Short name T1502
Test name
Test status
Simulation time 286069628 ps
CPU time 27.04 seconds
Started Jul 14 07:30:14 PM PDT 24
Finished Jul 14 07:30:42 PM PDT 24
Peak memory 575304 kb
Host smart-7801b44c-957a-4617-9395-dea53d71842e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353990123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del
ays.1353990123
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_same_source.3317246806
Short name T2133
Test name
Test status
Simulation time 1430926627 ps
CPU time 44.41 seconds
Started Jul 14 07:30:15 PM PDT 24
Finished Jul 14 07:31:00 PM PDT 24
Peak memory 575332 kb
Host smart-0873d225-d295-4522-8d1f-0b65ba2bced7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317246806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3317246806
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke.1156332485
Short name T2085
Test name
Test status
Simulation time 54088824 ps
CPU time 6.73 seconds
Started Jul 14 07:30:11 PM PDT 24
Finished Jul 14 07:30:18 PM PDT 24
Peak memory 575268 kb
Host smart-fbd92df3-d196-4ab0-be71-279e3b80c312
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156332485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1156332485
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.1837976402
Short name T1646
Test name
Test status
Simulation time 8984374968 ps
CPU time 97.87 seconds
Started Jul 14 07:30:09 PM PDT 24
Finished Jul 14 07:31:47 PM PDT 24
Peak memory 574236 kb
Host smart-48370555-12a3-4220-b440-172451d1bf05
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837976402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1837976402
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1807478510
Short name T2240
Test name
Test status
Simulation time 4106212205 ps
CPU time 74.39 seconds
Started Jul 14 07:30:18 PM PDT 24
Finished Jul 14 07:31:33 PM PDT 24
Peak memory 575336 kb
Host smart-1d0208e9-602f-4836-8d67-efc130f0b963
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807478510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1807478510
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3585197487
Short name T705
Test name
Test status
Simulation time 37740776 ps
CPU time 5.59 seconds
Started Jul 14 07:30:13 PM PDT 24
Finished Jul 14 07:30:18 PM PDT 24
Peak memory 575260 kb
Host smart-7fa1742c-e976-43d6-8282-5b43b827d737
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585197487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay
s.3585197487
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all.2490415153
Short name T489
Test name
Test status
Simulation time 2264899353 ps
CPU time 184.98 seconds
Started Jul 14 07:30:15 PM PDT 24
Finished Jul 14 07:33:21 PM PDT 24
Peak memory 575424 kb
Host smart-b7a28eaf-ce0e-47ac-8ee2-41cb4b08dc12
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490415153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2490415153
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.3328770067
Short name T1389
Test name
Test status
Simulation time 8642080546 ps
CPU time 337.79 seconds
Started Jul 14 07:30:21 PM PDT 24
Finished Jul 14 07:35:59 PM PDT 24
Peak memory 575620 kb
Host smart-8c35f727-cdea-443a-8a25-fe34792ad830
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328770067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3328770067
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.1484504996
Short name T1782
Test name
Test status
Simulation time 3779804806 ps
CPU time 305.41 seconds
Started Jul 14 07:30:15 PM PDT 24
Finished Jul 14 07:35:21 PM PDT 24
Peak memory 575460 kb
Host smart-9c72b9ba-cd5a-4030-9d5d-deb369f7b693
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484504996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all
_with_rand_reset.1484504996
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1030994116
Short name T2819
Test name
Test status
Simulation time 9369330840 ps
CPU time 821.43 seconds
Started Jul 14 07:30:18 PM PDT 24
Finished Jul 14 07:44:00 PM PDT 24
Peak memory 578432 kb
Host smart-ca35df45-afaf-4454-8fe0-19a31b4a8d2c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030994116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al
l_with_reset_error.1030994116
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.374998768
Short name T2598
Test name
Test status
Simulation time 1330813731 ps
CPU time 57.74 seconds
Started Jul 14 07:30:16 PM PDT 24
Finished Jul 14 07:31:14 PM PDT 24
Peak memory 575428 kb
Host smart-6242b6c4-ca7e-484d-a238-b128bc976890
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374998768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.374998768
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/15.chip_csr_rw.3050434528
Short name T1794
Test name
Test status
Simulation time 5765827941 ps
CPU time 633.82 seconds
Started Jul 14 07:30:26 PM PDT 24
Finished Jul 14 07:41:01 PM PDT 24
Peak memory 598616 kb
Host smart-1fca690e-f37a-437a-944a-563f44dab9e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050434528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.3050434528
Directory /workspace/15.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.2473056868
Short name T2361
Test name
Test status
Simulation time 15483824372 ps
CPU time 1782.97 seconds
Started Jul 14 07:30:16 PM PDT 24
Finished Jul 14 08:00:00 PM PDT 24
Peak memory 593128 kb
Host smart-cbf3f5fc-1728-4181-880f-507db2352490
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473056868 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.2473056868
Directory /workspace/15.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_access_same_device.3136158784
Short name T1585
Test name
Test status
Simulation time 103991138 ps
CPU time 11.76 seconds
Started Jul 14 07:30:23 PM PDT 24
Finished Jul 14 07:30:35 PM PDT 24
Peak memory 575348 kb
Host smart-a8bb5910-156f-4cd4-b130-11da69d1c6d3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136158784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device
.3136158784
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.1594062469
Short name T1887
Test name
Test status
Simulation time 148724322499 ps
CPU time 2884.39 seconds
Started Jul 14 07:30:24 PM PDT 24
Finished Jul 14 08:18:30 PM PDT 24
Peak memory 575620 kb
Host smart-186cde2b-2200-424f-b564-5a530d71b177
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594062469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_
device_slow_rsp.1594062469
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.466854760
Short name T1839
Test name
Test status
Simulation time 125346354 ps
CPU time 14.58 seconds
Started Jul 14 07:30:26 PM PDT 24
Finished Jul 14 07:30:42 PM PDT 24
Peak memory 575340 kb
Host smart-c3a4672e-e3b8-41f2-8e50-b63fea6bb5d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466854760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr
.466854760
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_error_random.1165701180
Short name T2677
Test name
Test status
Simulation time 284524251 ps
CPU time 12.43 seconds
Started Jul 14 07:30:27 PM PDT 24
Finished Jul 14 07:30:40 PM PDT 24
Peak memory 575260 kb
Host smart-e43fd1f0-1d32-42db-a9d7-97c5d4bb23c3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165701180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1165701180
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random.212368789
Short name T2470
Test name
Test status
Simulation time 392892907 ps
CPU time 34.01 seconds
Started Jul 14 07:30:20 PM PDT 24
Finished Jul 14 07:30:55 PM PDT 24
Peak memory 575356 kb
Host smart-55bcda87-d831-4339-a099-7c54eb9fdb88
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212368789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.212368789
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.1146406051
Short name T2771
Test name
Test status
Simulation time 43255496525 ps
CPU time 468.61 seconds
Started Jul 14 07:30:21 PM PDT 24
Finished Jul 14 07:38:10 PM PDT 24
Peak memory 575468 kb
Host smart-299685a2-4796-487a-ac42-ecf2e3033653
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146406051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1146406051
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.3956528682
Short name T1837
Test name
Test status
Simulation time 12065481371 ps
CPU time 222.6 seconds
Started Jul 14 07:30:20 PM PDT 24
Finished Jul 14 07:34:03 PM PDT 24
Peak memory 575476 kb
Host smart-7873ff46-fc19-4050-9345-35e7914ed644
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956528682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3956528682
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.2341168563
Short name T2693
Test name
Test status
Simulation time 396697568 ps
CPU time 35.69 seconds
Started Jul 14 07:30:20 PM PDT 24
Finished Jul 14 07:30:56 PM PDT 24
Peak memory 575312 kb
Host smart-03157dff-aabf-49d3-89b6-72f7bf156e4e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341168563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del
ays.2341168563
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_same_source.1720694957
Short name T2238
Test name
Test status
Simulation time 1351106737 ps
CPU time 44.46 seconds
Started Jul 14 07:30:25 PM PDT 24
Finished Jul 14 07:31:09 PM PDT 24
Peak memory 575336 kb
Host smart-a1bd127f-b1d2-4413-9458-4f151d772f21
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720694957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1720694957
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke.1845225664
Short name T2157
Test name
Test status
Simulation time 175655620 ps
CPU time 8.68 seconds
Started Jul 14 07:30:24 PM PDT 24
Finished Jul 14 07:30:33 PM PDT 24
Peak memory 574032 kb
Host smart-debfea60-0d32-4d1b-8b50-186580e70e74
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845225664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1845225664
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.4111970129
Short name T2150
Test name
Test status
Simulation time 7791227962 ps
CPU time 87.53 seconds
Started Jul 14 07:30:19 PM PDT 24
Finished Jul 14 07:31:47 PM PDT 24
Peak memory 574180 kb
Host smart-3769de86-46fa-4829-b197-f88c7e039092
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111970129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.4111970129
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.4059164251
Short name T2031
Test name
Test status
Simulation time 5828785838 ps
CPU time 103.1 seconds
Started Jul 14 07:30:20 PM PDT 24
Finished Jul 14 07:32:04 PM PDT 24
Peak memory 575404 kb
Host smart-48d694c0-cc2d-4014-bcef-3a8540673ff3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059164251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.4059164251
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.323464363
Short name T2315
Test name
Test status
Simulation time 40508910 ps
CPU time 6.02 seconds
Started Jul 14 07:30:26 PM PDT 24
Finished Jul 14 07:30:33 PM PDT 24
Peak memory 575268 kb
Host smart-81bd1da5-8e90-4c00-a013-539dd86aaab2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323464363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays
.323464363
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all.310370356
Short name T1651
Test name
Test status
Simulation time 2074011658 ps
CPU time 70.27 seconds
Started Jul 14 07:30:28 PM PDT 24
Finished Jul 14 07:31:39 PM PDT 24
Peak memory 575508 kb
Host smart-5e99a9da-3255-4a43-bbd9-42696af09c19
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310370356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.310370356
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.595532448
Short name T1763
Test name
Test status
Simulation time 2173636089 ps
CPU time 176.28 seconds
Started Jul 14 07:30:25 PM PDT 24
Finished Jul 14 07:33:22 PM PDT 24
Peak memory 575552 kb
Host smart-c7903355-a3ea-43aa-88a1-631957389982
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595532448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.595532448
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.4058124036
Short name T2829
Test name
Test status
Simulation time 17488287801 ps
CPU time 810.03 seconds
Started Jul 14 07:30:24 PM PDT 24
Finished Jul 14 07:43:55 PM PDT 24
Peak memory 575612 kb
Host smart-8a86110f-368b-49dd-b9bd-9d58115fa474
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058124036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all
_with_rand_reset.4058124036
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.4076803205
Short name T2325
Test name
Test status
Simulation time 6232265431 ps
CPU time 299.18 seconds
Started Jul 14 07:30:28 PM PDT 24
Finished Jul 14 07:35:28 PM PDT 24
Peak memory 575636 kb
Host smart-3db73efb-5ba2-45d5-8a86-c04cb81dad64
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076803205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al
l_with_reset_error.4076803205
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.3321367961
Short name T613
Test name
Test status
Simulation time 225148762 ps
CPU time 28.95 seconds
Started Jul 14 07:30:27 PM PDT 24
Finished Jul 14 07:30:57 PM PDT 24
Peak memory 575316 kb
Host smart-770a784c-501e-416a-98d4-dd3c260b427f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321367961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3321367961
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/16.chip_csr_rw.147388112
Short name T2711
Test name
Test status
Simulation time 4051171060 ps
CPU time 242.24 seconds
Started Jul 14 07:30:44 PM PDT 24
Finished Jul 14 07:34:47 PM PDT 24
Peak memory 598888 kb
Host smart-5db13d68-c6ce-4f8f-a175-f092b8ceee28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147388112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.147388112
Directory /workspace/16.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.1470251175
Short name T2907
Test name
Test status
Simulation time 15210619317 ps
CPU time 2328.6 seconds
Started Jul 14 07:30:34 PM PDT 24
Finished Jul 14 08:09:24 PM PDT 24
Peak memory 593228 kb
Host smart-ae181fb1-8de9-4097-a95c-70556f0bccd5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470251175 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.1470251175
Directory /workspace/16.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.chip_tl_errors.2353753657
Short name T558
Test name
Test status
Simulation time 4520189175 ps
CPU time 339.27 seconds
Started Jul 14 07:30:33 PM PDT 24
Finished Jul 14 07:36:13 PM PDT 24
Peak memory 603852 kb
Host smart-3f41755a-69ec-4acc-83d5-2c69511bd50a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353753657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.2353753657
Directory /workspace/16.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_access_same_device.3941694969
Short name T1819
Test name
Test status
Simulation time 435020486 ps
CPU time 21.31 seconds
Started Jul 14 07:30:37 PM PDT 24
Finished Jul 14 07:30:58 PM PDT 24
Peak memory 575352 kb
Host smart-e9c35dd9-2830-46fc-a096-9260412a8848
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941694969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device
.3941694969
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.3234471415
Short name T1832
Test name
Test status
Simulation time 130590094115 ps
CPU time 2550.63 seconds
Started Jul 14 07:30:36 PM PDT 24
Finished Jul 14 08:13:07 PM PDT 24
Peak memory 575476 kb
Host smart-7167c4fe-b9af-4855-962f-cf7e4ab2df7a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234471415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_
device_slow_rsp.3234471415
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.3718096110
Short name T2088
Test name
Test status
Simulation time 104272954 ps
CPU time 11.7 seconds
Started Jul 14 07:30:46 PM PDT 24
Finished Jul 14 07:30:58 PM PDT 24
Peak memory 575292 kb
Host smart-c8bd4006-d0ac-4a7c-94f0-db40a770be4d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718096110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add
r.3718096110
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_error_random.450604106
Short name T1365
Test name
Test status
Simulation time 419877870 ps
CPU time 33.38 seconds
Started Jul 14 07:30:39 PM PDT 24
Finished Jul 14 07:31:13 PM PDT 24
Peak memory 575296 kb
Host smart-7b4579ec-87e8-485e-81e4-a4377041491c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450604106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.450604106
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random.755135615
Short name T2534
Test name
Test status
Simulation time 232702483 ps
CPU time 11.78 seconds
Started Jul 14 07:30:32 PM PDT 24
Finished Jul 14 07:30:44 PM PDT 24
Peak memory 575344 kb
Host smart-e45b9792-6d4e-4beb-a572-f39c3b3f4d93
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755135615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.755135615
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.2477483736
Short name T2071
Test name
Test status
Simulation time 62939365997 ps
CPU time 1131.75 seconds
Started Jul 14 07:30:37 PM PDT 24
Finished Jul 14 07:49:29 PM PDT 24
Peak memory 575704 kb
Host smart-ee902fe5-8e76-49b4-b656-5718c7456722
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477483736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2477483736
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.82633658
Short name T1419
Test name
Test status
Simulation time 662815327 ps
CPU time 51.15 seconds
Started Jul 14 07:30:39 PM PDT 24
Finished Jul 14 07:31:31 PM PDT 24
Peak memory 575288 kb
Host smart-97c4bbdd-d42e-452f-a749-71003607b794
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82633658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delay
s.82633658
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_same_source.4052222754
Short name T1994
Test name
Test status
Simulation time 2436004982 ps
CPU time 68.62 seconds
Started Jul 14 07:30:38 PM PDT 24
Finished Jul 14 07:31:47 PM PDT 24
Peak memory 575360 kb
Host smart-ce9ae127-d6cc-468d-8d46-7028760e4304
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052222754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.4052222754
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke.2103533310
Short name T2755
Test name
Test status
Simulation time 159915728 ps
CPU time 8.46 seconds
Started Jul 14 07:30:31 PM PDT 24
Finished Jul 14 07:30:40 PM PDT 24
Peak memory 573984 kb
Host smart-69b6e279-e407-46d8-ad80-cc449a304482
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103533310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2103533310
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.1420910529
Short name T1655
Test name
Test status
Simulation time 7899691200 ps
CPU time 93.8 seconds
Started Jul 14 07:30:33 PM PDT 24
Finished Jul 14 07:32:07 PM PDT 24
Peak memory 574172 kb
Host smart-de0765d5-ffe1-40c8-bbe9-dbc4807c2f45
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420910529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1420910529
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1049700351
Short name T1809
Test name
Test status
Simulation time 3792775539 ps
CPU time 66.08 seconds
Started Jul 14 07:30:31 PM PDT 24
Finished Jul 14 07:31:37 PM PDT 24
Peak memory 574076 kb
Host smart-32432277-e7a7-4095-b099-68e3749b2105
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049700351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1049700351
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.964660574
Short name T2435
Test name
Test status
Simulation time 34580736 ps
CPU time 5.99 seconds
Started Jul 14 07:30:32 PM PDT 24
Finished Jul 14 07:30:38 PM PDT 24
Peak memory 574052 kb
Host smart-376229ed-ba13-443f-a6cf-c132d63f2115
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964660574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays
.964660574
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.4013404125
Short name T1729
Test name
Test status
Simulation time 1896440773 ps
CPU time 57.92 seconds
Started Jul 14 07:30:43 PM PDT 24
Finished Jul 14 07:31:41 PM PDT 24
Peak memory 575300 kb
Host smart-6600ae61-d93e-478e-adf1-1fa5ed090137
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013404125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.4013404125
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.2553897642
Short name T874
Test name
Test status
Simulation time 30329523 ps
CPU time 7.25 seconds
Started Jul 14 07:30:46 PM PDT 24
Finished Jul 14 07:30:53 PM PDT 24
Peak memory 574204 kb
Host smart-70f54ed4-494e-4b36-ad32-a149ff036987
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553897642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all
_with_rand_reset.2553897642
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.418224654
Short name T1504
Test name
Test status
Simulation time 2507693426 ps
CPU time 305.84 seconds
Started Jul 14 07:30:45 PM PDT 24
Finished Jul 14 07:35:51 PM PDT 24
Peak memory 575536 kb
Host smart-481f73e7-d9a3-48df-9614-22a5b8bdf5e9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418224654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all
_with_reset_error.418224654
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.3752809927
Short name T2404
Test name
Test status
Simulation time 1219286314 ps
CPU time 49.32 seconds
Started Jul 14 07:30:39 PM PDT 24
Finished Jul 14 07:31:29 PM PDT 24
Peak memory 575468 kb
Host smart-0ca672a9-2645-4a1e-8c4f-c28c7a805f73
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752809927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3752809927
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/17.chip_csr_rw.3809297704
Short name T2871
Test name
Test status
Simulation time 6416698600 ps
CPU time 542.68 seconds
Started Jul 14 07:30:57 PM PDT 24
Finished Jul 14 07:40:01 PM PDT 24
Peak memory 598972 kb
Host smart-58ce9608-4062-4404-b955-0556eb05d01b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809297704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.3809297704
Directory /workspace/17.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.3234924635
Short name T2794
Test name
Test status
Simulation time 14809445415 ps
CPU time 2177.98 seconds
Started Jul 14 07:30:43 PM PDT 24
Finished Jul 14 08:07:02 PM PDT 24
Peak memory 591956 kb
Host smart-250f6422-0aeb-4cb3-99ae-d553f89f7150
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234924635 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.3234924635
Directory /workspace/17.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.chip_tl_errors.2217539748
Short name T697
Test name
Test status
Simulation time 4981983304 ps
CPU time 466.03 seconds
Started Jul 14 07:30:42 PM PDT 24
Finished Jul 14 07:38:29 PM PDT 24
Peak memory 603952 kb
Host smart-82e3ae72-1ad6-49e6-9dfb-335b67476ce9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217539748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.2217539748
Directory /workspace/17.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_access_same_device.3281046518
Short name T2867
Test name
Test status
Simulation time 668042960 ps
CPU time 53.09 seconds
Started Jul 14 07:30:53 PM PDT 24
Finished Jul 14 07:31:46 PM PDT 24
Peak memory 575360 kb
Host smart-b3db66f9-a31a-4e95-81ba-0670be889f1a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281046518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device
.3281046518
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2943739177
Short name T1911
Test name
Test status
Simulation time 216039199 ps
CPU time 23.64 seconds
Started Jul 14 07:31:00 PM PDT 24
Finished Jul 14 07:31:24 PM PDT 24
Peak memory 575504 kb
Host smart-ed627f94-71e5-4f22-a831-52bbd3353580
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943739177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add
r.2943739177
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_error_random.1213838976
Short name T2607
Test name
Test status
Simulation time 1323453634 ps
CPU time 46.72 seconds
Started Jul 14 07:30:52 PM PDT 24
Finished Jul 14 07:31:39 PM PDT 24
Peak memory 575308 kb
Host smart-55a97358-546d-40d0-8d4c-d7b67180377f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213838976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1213838976
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random.2783557019
Short name T589
Test name
Test status
Simulation time 70342912 ps
CPU time 8.67 seconds
Started Jul 14 07:30:50 PM PDT 24
Finished Jul 14 07:30:59 PM PDT 24
Peak memory 575344 kb
Host smart-22302ff4-893b-4f41-bcb0-2d84cd97380d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783557019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.2783557019
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.2410855305
Short name T2448
Test name
Test status
Simulation time 96271181536 ps
CPU time 1068.29 seconds
Started Jul 14 07:30:51 PM PDT 24
Finished Jul 14 07:48:40 PM PDT 24
Peak memory 575500 kb
Host smart-6c974e33-a6f1-4fb6-9374-74f6f9d238f1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410855305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2410855305
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.1450667257
Short name T2401
Test name
Test status
Simulation time 43827219752 ps
CPU time 805.86 seconds
Started Jul 14 07:30:51 PM PDT 24
Finished Jul 14 07:44:17 PM PDT 24
Peak memory 575436 kb
Host smart-0c5ea2cb-6176-42a3-816c-db62670f5c0a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450667257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.1450667257
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.2286634918
Short name T1475
Test name
Test status
Simulation time 590858445 ps
CPU time 53.25 seconds
Started Jul 14 07:30:50 PM PDT 24
Finished Jul 14 07:31:44 PM PDT 24
Peak memory 575288 kb
Host smart-e5834a62-8b0e-4b09-9437-1ae63f472559
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286634918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del
ays.2286634918
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_same_source.2328564957
Short name T598
Test name
Test status
Simulation time 355700337 ps
CPU time 28.73 seconds
Started Jul 14 07:30:51 PM PDT 24
Finished Jul 14 07:31:20 PM PDT 24
Peak memory 575372 kb
Host smart-aa04d573-aead-48a0-98d7-6868667e02dd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328564957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2328564957
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke.3970370062
Short name T2453
Test name
Test status
Simulation time 168008341 ps
CPU time 7.67 seconds
Started Jul 14 07:30:46 PM PDT 24
Finished Jul 14 07:30:54 PM PDT 24
Peak memory 575224 kb
Host smart-62294170-b356-48a9-86b6-b44c305dc2f2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970370062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3970370062
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.1958088095
Short name T2321
Test name
Test status
Simulation time 8344692141 ps
CPU time 98.79 seconds
Started Jul 14 07:30:45 PM PDT 24
Finished Jul 14 07:32:24 PM PDT 24
Peak memory 575416 kb
Host smart-011e01f4-ce30-43b8-a2bd-55632ac2f938
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958088095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1958088095
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.4221581379
Short name T1400
Test name
Test status
Simulation time 4218610786 ps
CPU time 77.5 seconds
Started Jul 14 07:30:51 PM PDT 24
Finished Jul 14 07:32:09 PM PDT 24
Peak memory 574080 kb
Host smart-126c1ab5-4e9c-497f-897b-2a72961d7096
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221581379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.4221581379
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.121269313
Short name T2291
Test name
Test status
Simulation time 41468642 ps
CPU time 5.82 seconds
Started Jul 14 07:30:42 PM PDT 24
Finished Jul 14 07:30:48 PM PDT 24
Peak memory 574008 kb
Host smart-31c2be13-a3f0-4b41-89e1-b97b40bbc94f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121269313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays
.121269313
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all.1948589695
Short name T2706
Test name
Test status
Simulation time 11601060751 ps
CPU time 435.81 seconds
Started Jul 14 07:30:58 PM PDT 24
Finished Jul 14 07:38:15 PM PDT 24
Peak memory 575600 kb
Host smart-2f012d7d-f435-4dee-9767-89e6ab521743
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948589695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1948589695
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.2567520232
Short name T1977
Test name
Test status
Simulation time 1180136434 ps
CPU time 93.48 seconds
Started Jul 14 07:30:58 PM PDT 24
Finished Jul 14 07:32:32 PM PDT 24
Peak memory 575460 kb
Host smart-f9e7aa81-baa1-49fc-882d-70b82faf9d81
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567520232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2567520232
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.1888589519
Short name T583
Test name
Test status
Simulation time 1369959124 ps
CPU time 137.54 seconds
Started Jul 14 07:30:59 PM PDT 24
Finished Jul 14 07:33:17 PM PDT 24
Peak memory 575500 kb
Host smart-251803bb-311f-4622-bd08-4b858a60083d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888589519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all
_with_rand_reset.1888589519
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.106084513
Short name T2884
Test name
Test status
Simulation time 77720553 ps
CPU time 22.2 seconds
Started Jul 14 07:31:00 PM PDT 24
Finished Jul 14 07:31:23 PM PDT 24
Peak memory 575412 kb
Host smart-5296c6e5-88f0-472c-bcda-caa57ec84bcb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106084513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all
_with_reset_error.106084513
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.1662702139
Short name T1591
Test name
Test status
Simulation time 878278195 ps
CPU time 39.3 seconds
Started Jul 14 07:30:52 PM PDT 24
Finished Jul 14 07:31:32 PM PDT 24
Peak memory 575424 kb
Host smart-2b290833-f0a0-463a-a9a1-24ebd9334577
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662702139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1662702139
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/18.chip_csr_rw.3017734289
Short name T384
Test name
Test status
Simulation time 4833318626 ps
CPU time 410.29 seconds
Started Jul 14 07:31:03 PM PDT 24
Finished Jul 14 07:37:54 PM PDT 24
Peak memory 598080 kb
Host smart-ad951d2f-d370-45f6-83e0-2b72b4c00554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017734289 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.3017734289
Directory /workspace/18.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_access_same_device.214208637
Short name T550
Test name
Test status
Simulation time 889414668 ps
CPU time 84.72 seconds
Started Jul 14 07:30:56 PM PDT 24
Finished Jul 14 07:32:22 PM PDT 24
Peak memory 575392 kb
Host smart-8a8ed9b9-5fc3-4bd0-809c-9c0386fdf0d1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214208637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.
214208637
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3816780375
Short name T2075
Test name
Test status
Simulation time 29078819633 ps
CPU time 546.95 seconds
Started Jul 14 07:31:01 PM PDT 24
Finished Jul 14 07:40:08 PM PDT 24
Peak memory 575596 kb
Host smart-67bb33b1-81e9-44e0-b641-9387a2beb710
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816780375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_
device_slow_rsp.3816780375
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.1341881955
Short name T1892
Test name
Test status
Simulation time 932315249 ps
CPU time 41.6 seconds
Started Jul 14 07:31:03 PM PDT 24
Finished Jul 14 07:31:46 PM PDT 24
Peak memory 575328 kb
Host smart-58bd8b96-083c-474d-8a87-f897a092c893
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341881955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add
r.1341881955
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_error_random.2996262555
Short name T2514
Test name
Test status
Simulation time 238952376 ps
CPU time 22.65 seconds
Started Jul 14 07:31:03 PM PDT 24
Finished Jul 14 07:31:26 PM PDT 24
Peak memory 575280 kb
Host smart-99cc7262-a0e9-4b0b-8048-d5d976f9a40b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996262555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2996262555
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random.457136379
Short name T2562
Test name
Test status
Simulation time 1829700452 ps
CPU time 64.39 seconds
Started Jul 14 07:31:01 PM PDT 24
Finished Jul 14 07:32:06 PM PDT 24
Peak memory 575308 kb
Host smart-9071eebd-69d5-4eb0-850f-546e6eeed837
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457136379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.457136379
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.139552606
Short name T2767
Test name
Test status
Simulation time 21848807802 ps
CPU time 248.18 seconds
Started Jul 14 07:30:58 PM PDT 24
Finished Jul 14 07:35:06 PM PDT 24
Peak memory 575420 kb
Host smart-b78be274-d870-4c33-89ee-ffda81272516
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139552606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.139552606
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.2066740916
Short name T2556
Test name
Test status
Simulation time 44490694396 ps
CPU time 800.91 seconds
Started Jul 14 07:30:57 PM PDT 24
Finished Jul 14 07:44:19 PM PDT 24
Peak memory 575504 kb
Host smart-a1d544a3-11ab-4c1a-9f43-8d52fbef73ac
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066740916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2066740916
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.2674561233
Short name T1539
Test name
Test status
Simulation time 218833032 ps
CPU time 18.74 seconds
Started Jul 14 07:31:00 PM PDT 24
Finished Jul 14 07:31:20 PM PDT 24
Peak memory 575352 kb
Host smart-14ede2da-9d98-4d8d-8efb-895ba028024f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674561233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del
ays.2674561233
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_same_source.2033148380
Short name T514
Test name
Test status
Simulation time 2585783760 ps
CPU time 85.63 seconds
Started Jul 14 07:31:06 PM PDT 24
Finished Jul 14 07:32:32 PM PDT 24
Peak memory 575336 kb
Host smart-4266e7a2-b2e6-455e-82cc-e7b58b225287
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033148380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2033148380
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke.468438309
Short name T1363
Test name
Test status
Simulation time 241214494 ps
CPU time 9.28 seconds
Started Jul 14 07:30:57 PM PDT 24
Finished Jul 14 07:31:07 PM PDT 24
Peak memory 574012 kb
Host smart-30106cb1-4f3d-4875-8306-67d782536ec2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468438309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.468438309
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.1821448553
Short name T638
Test name
Test status
Simulation time 8184193189 ps
CPU time 95.8 seconds
Started Jul 14 07:30:57 PM PDT 24
Finished Jul 14 07:32:33 PM PDT 24
Peak memory 575440 kb
Host smart-695091ad-6bca-4012-8b28-a8e3c423e3a3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821448553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1821448553
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3035089154
Short name T2820
Test name
Test status
Simulation time 5330279442 ps
CPU time 94.42 seconds
Started Jul 14 07:30:58 PM PDT 24
Finished Jul 14 07:32:33 PM PDT 24
Peak memory 574204 kb
Host smart-bb6b15ce-8b01-4ee5-a127-221fbe4f37a9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035089154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3035089154
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.2466140641
Short name T2899
Test name
Test status
Simulation time 37929135 ps
CPU time 6.14 seconds
Started Jul 14 07:31:00 PM PDT 24
Finished Jul 14 07:31:06 PM PDT 24
Peak memory 574036 kb
Host smart-1c989c15-54c6-449d-b9a3-5c9e15905bd2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466140641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay
s.2466140641
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all.4230404981
Short name T2877
Test name
Test status
Simulation time 17677128226 ps
CPU time 711.96 seconds
Started Jul 14 07:31:05 PM PDT 24
Finished Jul 14 07:42:57 PM PDT 24
Peak memory 575636 kb
Host smart-f27f825e-cb46-4b40-a451-caed6f805535
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230404981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.4230404981
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.4043783906
Short name T1787
Test name
Test status
Simulation time 15968615762 ps
CPU time 620.17 seconds
Started Jul 14 07:31:05 PM PDT 24
Finished Jul 14 07:41:25 PM PDT 24
Peak memory 575540 kb
Host smart-736fc76d-5178-4378-bfeb-a3da4e934404
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043783906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.4043783906
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.3849888635
Short name T1950
Test name
Test status
Simulation time 17172559864 ps
CPU time 815.9 seconds
Started Jul 14 07:31:06 PM PDT 24
Finished Jul 14 07:44:43 PM PDT 24
Peak memory 575792 kb
Host smart-d399e8fa-70f1-4c19-83bd-d3c6b30f85b5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849888635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all
_with_rand_reset.3849888635
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.3058512879
Short name T2108
Test name
Test status
Simulation time 13994248514 ps
CPU time 1183.96 seconds
Started Jul 14 07:31:01 PM PDT 24
Finished Jul 14 07:50:45 PM PDT 24
Peak memory 584032 kb
Host smart-504aaa5a-cef3-4e79-8369-1c41bb92a94e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058512879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al
l_with_reset_error.3058512879
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.1041748331
Short name T1910
Test name
Test status
Simulation time 210998447 ps
CPU time 27.35 seconds
Started Jul 14 07:31:04 PM PDT 24
Finished Jul 14 07:31:32 PM PDT 24
Peak memory 575456 kb
Host smart-7e660123-6a55-439d-9936-7c6a5448163c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041748331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1041748331
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/19.chip_csr_rw.1276022717
Short name T543
Test name
Test status
Simulation time 5929703719 ps
CPU time 609.3 seconds
Started Jul 14 07:31:23 PM PDT 24
Finished Jul 14 07:41:33 PM PDT 24
Peak memory 598492 kb
Host smart-b8088300-05c7-4baa-9d1f-ad85974518b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276022717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.1276022717
Directory /workspace/19.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.15640494
Short name T2140
Test name
Test status
Simulation time 14658693520 ps
CPU time 2046.43 seconds
Started Jul 14 07:31:07 PM PDT 24
Finished Jul 14 08:05:14 PM PDT 24
Peak memory 593224 kb
Host smart-9ab15d1a-a59b-4ae3-9e45-35fadeb7e7d2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15640494 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.chip_same_csr_outstanding.15640494
Directory /workspace/19.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.chip_tl_errors.1344156773
Short name T2505
Test name
Test status
Simulation time 2906757236 ps
CPU time 182.36 seconds
Started Jul 14 07:31:04 PM PDT 24
Finished Jul 14 07:34:07 PM PDT 24
Peak memory 598784 kb
Host smart-19c4f86b-ef4b-4f21-9b16-b9b4ecf749f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344156773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.1344156773
Directory /workspace/19.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_access_same_device.2261192115
Short name T2231
Test name
Test status
Simulation time 1527512539 ps
CPU time 52.61 seconds
Started Jul 14 07:31:11 PM PDT 24
Finished Jul 14 07:32:05 PM PDT 24
Peak memory 575412 kb
Host smart-a398cb7d-c089-496d-a347-0ea64d5b1541
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261192115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device
.2261192115
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2704868923
Short name T2730
Test name
Test status
Simulation time 116188180648 ps
CPU time 2378.96 seconds
Started Jul 14 07:31:14 PM PDT 24
Finished Jul 14 08:10:54 PM PDT 24
Peak memory 575592 kb
Host smart-babdfc71-1d11-452c-b183-768c6f3fefaf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704868923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_
device_slow_rsp.2704868923
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.570489250
Short name T1634
Test name
Test status
Simulation time 51528401 ps
CPU time 8.31 seconds
Started Jul 14 07:31:17 PM PDT 24
Finished Jul 14 07:31:26 PM PDT 24
Peak memory 575320 kb
Host smart-8349b72f-5fc3-4e6d-99e2-d80b38c09a83
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570489250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr
.570489250
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_error_random.1147245977
Short name T1544
Test name
Test status
Simulation time 293679954 ps
CPU time 13.01 seconds
Started Jul 14 07:31:17 PM PDT 24
Finished Jul 14 07:31:30 PM PDT 24
Peak memory 575332 kb
Host smart-6df7e802-3f6f-4e82-a47d-220dcd560c39
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147245977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1147245977
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random.2150261003
Short name T1675
Test name
Test status
Simulation time 321627821 ps
CPU time 29.17 seconds
Started Jul 14 07:31:09 PM PDT 24
Finished Jul 14 07:31:38 PM PDT 24
Peak memory 575384 kb
Host smart-d3b74856-5675-4377-92dc-67396bae5a80
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150261003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.2150261003
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.3828668173
Short name T2749
Test name
Test status
Simulation time 17067197342 ps
CPU time 198.94 seconds
Started Jul 14 07:31:09 PM PDT 24
Finished Jul 14 07:34:29 PM PDT 24
Peak memory 575676 kb
Host smart-b5f7d2a9-1f04-4b34-b0b6-8dce064b5725
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828668173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3828668173
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.924841794
Short name T2165
Test name
Test status
Simulation time 3607769757 ps
CPU time 69.33 seconds
Started Jul 14 07:31:08 PM PDT 24
Finished Jul 14 07:32:18 PM PDT 24
Peak memory 574092 kb
Host smart-6d643cd3-8ec2-4255-8e83-4b351e932563
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924841794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.924841794
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.2234288367
Short name T1519
Test name
Test status
Simulation time 52085237 ps
CPU time 7.98 seconds
Started Jul 14 07:31:09 PM PDT 24
Finished Jul 14 07:31:17 PM PDT 24
Peak memory 574092 kb
Host smart-98624e7f-8d5f-43b0-8a02-0629f010ee3f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234288367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del
ays.2234288367
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_same_source.2830137536
Short name T2616
Test name
Test status
Simulation time 141664080 ps
CPU time 7.4 seconds
Started Jul 14 07:31:15 PM PDT 24
Finished Jul 14 07:31:23 PM PDT 24
Peak memory 573996 kb
Host smart-8af555ca-df9e-4975-9681-272b9f13c4b5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830137536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2830137536
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke.3102446983
Short name T2576
Test name
Test status
Simulation time 50825265 ps
CPU time 6.88 seconds
Started Jul 14 07:31:10 PM PDT 24
Finished Jul 14 07:31:18 PM PDT 24
Peak memory 574036 kb
Host smart-d5388ee7-7037-4e56-9193-5d220353b2cf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102446983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3102446983
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.386116994
Short name T1378
Test name
Test status
Simulation time 5863382755 ps
CPU time 61.87 seconds
Started Jul 14 07:31:09 PM PDT 24
Finished Jul 14 07:32:11 PM PDT 24
Peak memory 574136 kb
Host smart-e8907905-5cbc-44cb-b43d-f63579b9eccd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386116994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.386116994
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.3002582498
Short name T1939
Test name
Test status
Simulation time 6057391285 ps
CPU time 106.77 seconds
Started Jul 14 07:31:08 PM PDT 24
Finished Jul 14 07:32:56 PM PDT 24
Peak memory 574152 kb
Host smart-e7786d5e-58bc-4270-bead-d17e0e326c55
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002582498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3002582498
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.3705586399
Short name T2277
Test name
Test status
Simulation time 52358137 ps
CPU time 7.11 seconds
Started Jul 14 07:31:11 PM PDT 24
Finished Jul 14 07:31:19 PM PDT 24
Peak memory 574032 kb
Host smart-21b0fc1c-0cbc-4818-ad3e-d67063258d29
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705586399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay
s.3705586399
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all.3073816121
Short name T2769
Test name
Test status
Simulation time 12914714311 ps
CPU time 502.81 seconds
Started Jul 14 07:31:16 PM PDT 24
Finished Jul 14 07:39:39 PM PDT 24
Peak memory 575624 kb
Host smart-76a4d7da-4d06-4d1e-b378-bfd2be0b16c4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073816121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3073816121
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.3307101883
Short name T2159
Test name
Test status
Simulation time 3591096342 ps
CPU time 119.82 seconds
Started Jul 14 07:31:15 PM PDT 24
Finished Jul 14 07:33:15 PM PDT 24
Peak memory 575464 kb
Host smart-d85678fa-6423-46e7-803c-c2b4b9d96603
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307101883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3307101883
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.3264033603
Short name T2850
Test name
Test status
Simulation time 22329653 ps
CPU time 21.82 seconds
Started Jul 14 07:31:17 PM PDT 24
Finished Jul 14 07:31:39 PM PDT 24
Peak memory 575500 kb
Host smart-58c97c3c-6286-48bc-932d-c8a3211baaae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264033603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all
_with_rand_reset.3264033603
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.2927747209
Short name T1984
Test name
Test status
Simulation time 271723072 ps
CPU time 96.78 seconds
Started Jul 14 07:31:17 PM PDT 24
Finished Jul 14 07:32:54 PM PDT 24
Peak memory 575172 kb
Host smart-a4cfee1a-6c36-4f17-9125-43fa25ec6e06
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927747209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al
l_with_reset_error.2927747209
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.3950754021
Short name T1517
Test name
Test status
Simulation time 110326942 ps
CPU time 15.28 seconds
Started Jul 14 07:31:14 PM PDT 24
Finished Jul 14 07:31:29 PM PDT 24
Peak memory 575384 kb
Host smart-2b94512d-40b5-4a55-9268-91c4d968c18f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950754021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3950754021
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.2470331236
Short name T417
Test name
Test status
Simulation time 54773939755 ps
CPU time 10225 seconds
Started Jul 14 07:27:14 PM PDT 24
Finished Jul 14 10:17:40 PM PDT 24
Peak memory 640848 kb
Host smart-5d1af129-b755-478d-b0e4-1544850440ee
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470331236 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.chip_csr_aliasing.2470331236
Directory /workspace/2.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.3272880773
Short name T2430
Test name
Test status
Simulation time 6002335700 ps
CPU time 594.08 seconds
Started Jul 14 07:27:14 PM PDT 24
Finished Jul 14 07:37:09 PM PDT 24
Peak memory 592500 kb
Host smart-2f6cb059-4a63-4717-a6d0-90124201a5da
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272880773 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.3272880773
Directory /workspace/2.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3959545443
Short name T477
Test name
Test status
Simulation time 4154983444 ps
CPU time 253.24 seconds
Started Jul 14 07:27:24 PM PDT 24
Finished Jul 14 07:31:38 PM PDT 24
Peak memory 662136 kb
Host smart-bf192fc9-999a-4138-81bc-d347f528d361
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959545443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r
eset.3959545443
Directory /workspace/2.chip_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_rw.2691800541
Short name T2885
Test name
Test status
Simulation time 5630752759 ps
CPU time 537.39 seconds
Started Jul 14 07:27:26 PM PDT 24
Finished Jul 14 07:36:23 PM PDT 24
Peak memory 599156 kb
Host smart-b7b22fdc-b1d4-4a6e-8f51-6d163312e361
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691800541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.2691800541
Directory /workspace/2.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.3712847817
Short name T1450
Test name
Test status
Simulation time 6262277770 ps
CPU time 171.64 seconds
Started Jul 14 07:27:16 PM PDT 24
Finished Jul 14 07:30:08 PM PDT 24
Peak memory 590164 kb
Host smart-165701cc-a1c1-4cde-bcb8-ce5f269e22f5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712847817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.chip_prim_tl_access.3712847817
Directory /workspace/2.chip_prim_tl_access/latest

Test location /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.2381195930
Short name T1663
Test name
Test status
Simulation time 18433571091 ps
CPU time 520.37 seconds
Started Jul 14 07:27:14 PM PDT 24
Finished Jul 14 07:35:55 PM PDT 24
Peak memory 591424 kb
Host smart-5565e11c-6fa7-475d-b51e-68a3fe515a41
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381195930 -assert nopostproc +UVM_TESTNAME=chip_base_t
est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.chip_rv_dm_lc_disabled.2381195930
Directory /workspace/2.chip_rv_dm_lc_disabled/latest

Test location /workspace/coverage/cover_reg_top/2.chip_tl_errors.3085378199
Short name T699
Test name
Test status
Simulation time 5051734920 ps
CPU time 500.97 seconds
Started Jul 14 07:27:16 PM PDT 24
Finished Jul 14 07:35:37 PM PDT 24
Peak memory 599040 kb
Host smart-f5366d7a-ad8c-453e-abb4-8e3ce3ba5e93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085378199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.3085378199
Directory /workspace/2.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_access_same_device.2603097015
Short name T1879
Test name
Test status
Simulation time 1888047637 ps
CPU time 68.45 seconds
Started Jul 14 07:27:24 PM PDT 24
Finished Jul 14 07:28:33 PM PDT 24
Peak memory 575460 kb
Host smart-f8295fe4-aeb5-490b-9eda-0b2b380a7f72
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603097015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.
2603097015
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2804678824
Short name T1593
Test name
Test status
Simulation time 76879801831 ps
CPU time 1348.85 seconds
Started Jul 14 07:27:25 PM PDT 24
Finished Jul 14 07:49:54 PM PDT 24
Peak memory 575584 kb
Host smart-f662cfd2-527e-4517-9618-49bbda5349b1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804678824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d
evice_slow_rsp.2804678824
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.3141453731
Short name T2804
Test name
Test status
Simulation time 1311366263 ps
CPU time 51.56 seconds
Started Jul 14 07:27:17 PM PDT 24
Finished Jul 14 07:28:09 PM PDT 24
Peak memory 575296 kb
Host smart-7145f2ec-746a-45d5-97a2-8631f7609e57
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141453731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr
.3141453731
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_error_random.1117682835
Short name T2179
Test name
Test status
Simulation time 2777279056 ps
CPU time 85.62 seconds
Started Jul 14 07:27:24 PM PDT 24
Finished Jul 14 07:28:51 PM PDT 24
Peak memory 575392 kb
Host smart-06a33af1-a38e-4c5c-9722-37103461a956
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117682835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1117682835
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random.3559685956
Short name T450
Test name
Test status
Simulation time 2019713526 ps
CPU time 72.16 seconds
Started Jul 14 07:27:15 PM PDT 24
Finished Jul 14 07:28:28 PM PDT 24
Peak memory 575304 kb
Host smart-193389a6-43c7-466c-980b-b05c19deb6e5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559685956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.3559685956
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.1967977154
Short name T2781
Test name
Test status
Simulation time 83200260165 ps
CPU time 928.88 seconds
Started Jul 14 07:27:20 PM PDT 24
Finished Jul 14 07:42:49 PM PDT 24
Peak memory 575504 kb
Host smart-f31f6878-e30d-4b2b-966d-fb4c230d625d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967977154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1967977154
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.3008707249
Short name T1455
Test name
Test status
Simulation time 16171340636 ps
CPU time 299.38 seconds
Started Jul 14 07:27:19 PM PDT 24
Finished Jul 14 07:32:18 PM PDT 24
Peak memory 575492 kb
Host smart-9d2ce4f1-69c6-47af-864c-b031f43196b8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008707249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3008707249
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.3706306825
Short name T2772
Test name
Test status
Simulation time 215886704 ps
CPU time 19.97 seconds
Started Jul 14 07:27:13 PM PDT 24
Finished Jul 14 07:27:34 PM PDT 24
Peak memory 575312 kb
Host smart-2105fe30-3a25-47dc-baa5-3f80110f582f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706306825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela
ys.3706306825
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_same_source.2902181323
Short name T2186
Test name
Test status
Simulation time 2510323995 ps
CPU time 73.87 seconds
Started Jul 14 07:27:19 PM PDT 24
Finished Jul 14 07:28:33 PM PDT 24
Peak memory 575556 kb
Host smart-d5dd0b24-ccf7-44a3-b77b-51ad9cf33746
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902181323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2902181323
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke.2797113473
Short name T1352
Test name
Test status
Simulation time 50885543 ps
CPU time 6.02 seconds
Started Jul 14 07:27:14 PM PDT 24
Finished Jul 14 07:27:20 PM PDT 24
Peak memory 574020 kb
Host smart-b5133963-505d-4c43-92c2-27e4b7c6eddf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797113473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2797113473
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.1678122426
Short name T1411
Test name
Test status
Simulation time 7738476592 ps
CPU time 88.83 seconds
Started Jul 14 07:27:12 PM PDT 24
Finished Jul 14 07:28:41 PM PDT 24
Peak memory 574112 kb
Host smart-5cc49fac-0463-4287-8ed8-91364e9a7a47
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678122426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1678122426
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.4070444038
Short name T655
Test name
Test status
Simulation time 5887249268 ps
CPU time 104.6 seconds
Started Jul 14 07:27:14 PM PDT 24
Finished Jul 14 07:28:59 PM PDT 24
Peak memory 574156 kb
Host smart-ab3ccfca-9795-46ed-85cc-a8b02eb83b8f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070444038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.4070444038
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.2480361969
Short name T2378
Test name
Test status
Simulation time 40280608 ps
CPU time 6.29 seconds
Started Jul 14 07:27:13 PM PDT 24
Finished Jul 14 07:27:20 PM PDT 24
Peak memory 574028 kb
Host smart-10db0731-ad79-4b90-88c0-393383bca1c2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480361969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays
.2480361969
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all.1038576937
Short name T2421
Test name
Test status
Simulation time 6155271066 ps
CPU time 271.07 seconds
Started Jul 14 07:27:21 PM PDT 24
Finished Jul 14 07:31:52 PM PDT 24
Peak memory 575584 kb
Host smart-c3d2b82e-8153-4524-b65e-7765a5879771
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038576937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.1038576937
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.4033514824
Short name T1535
Test name
Test status
Simulation time 15479651298 ps
CPU time 571.03 seconds
Started Jul 14 07:27:18 PM PDT 24
Finished Jul 14 07:36:49 PM PDT 24
Peak memory 575608 kb
Host smart-f82bc489-5138-4c14-a352-c00ca46ad07a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033514824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.4033514824
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.2298738335
Short name T1574
Test name
Test status
Simulation time 281350387 ps
CPU time 96.22 seconds
Started Jul 14 07:27:18 PM PDT 24
Finished Jul 14 07:28:55 PM PDT 24
Peak memory 575484 kb
Host smart-ff3cac9c-c532-4407-9151-1203e968efa6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298738335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_
with_rand_reset.2298738335
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.1178454903
Short name T2739
Test name
Test status
Simulation time 9703282998 ps
CPU time 845.87 seconds
Started Jul 14 07:27:22 PM PDT 24
Finished Jul 14 07:41:29 PM PDT 24
Peak memory 598712 kb
Host smart-b51e8db6-0a47-40a6-8cd3-5061a7490020
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178454903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all
_with_reset_error.1178454903
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.2000881354
Short name T2548
Test name
Test status
Simulation time 115763304 ps
CPU time 13.93 seconds
Started Jul 14 07:27:25 PM PDT 24
Finished Jul 14 07:27:40 PM PDT 24
Peak memory 575468 kb
Host smart-0142eb94-5e4f-467b-b09c-a623fc94592e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000881354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2000881354
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/20.chip_tl_errors.3423024938
Short name T2285
Test name
Test status
Simulation time 3943666128 ps
CPU time 281.88 seconds
Started Jul 14 07:31:21 PM PDT 24
Finished Jul 14 07:36:03 PM PDT 24
Peak memory 603816 kb
Host smart-a24c0d0d-9d2b-4f8e-bdd2-98b38da79623
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423024938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.3423024938
Directory /workspace/20.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_access_same_device.197576511
Short name T1967
Test name
Test status
Simulation time 3326278295 ps
CPU time 143.12 seconds
Started Jul 14 07:31:29 PM PDT 24
Finished Jul 14 07:33:53 PM PDT 24
Peak memory 575516 kb
Host smart-f3da26b9-fc39-49d2-bfc9-929e160c8c91
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197576511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.
197576511
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.3827259772
Short name T1527
Test name
Test status
Simulation time 45101308814 ps
CPU time 747.68 seconds
Started Jul 14 07:31:28 PM PDT 24
Finished Jul 14 07:43:56 PM PDT 24
Peak memory 575576 kb
Host smart-7e342c1e-a758-4c5b-a6f8-da50c3929c80
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827259772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_
device_slow_rsp.3827259772
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.3385747671
Short name T2304
Test name
Test status
Simulation time 272641897 ps
CPU time 30.08 seconds
Started Jul 14 07:31:35 PM PDT 24
Finished Jul 14 07:32:06 PM PDT 24
Peak memory 575324 kb
Host smart-ffb40df8-bce8-404c-afa6-6c55b8aa094e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385747671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add
r.3385747671
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_error_random.1238302178
Short name T1628
Test name
Test status
Simulation time 707447637 ps
CPU time 23.66 seconds
Started Jul 14 07:31:28 PM PDT 24
Finished Jul 14 07:31:53 PM PDT 24
Peak memory 575324 kb
Host smart-3154b1d3-8be2-4ec9-96de-c93172ab3af3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238302178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.1238302178
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random.94250791
Short name T1670
Test name
Test status
Simulation time 529731530 ps
CPU time 47.58 seconds
Started Jul 14 07:31:21 PM PDT 24
Finished Jul 14 07:32:09 PM PDT 24
Peak memory 575384 kb
Host smart-2425bc1e-4edd-4b7b-b16a-a0f375abb0b2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94250791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.94250791
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.2589030504
Short name T2793
Test name
Test status
Simulation time 49808794270 ps
CPU time 557.65 seconds
Started Jul 14 07:31:21 PM PDT 24
Finished Jul 14 07:40:39 PM PDT 24
Peak memory 575484 kb
Host smart-b7266991-9acd-407a-b36e-c88b56bfa411
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589030504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2589030504
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.3704584081
Short name T2259
Test name
Test status
Simulation time 18521747387 ps
CPU time 322.47 seconds
Started Jul 14 07:31:28 PM PDT 24
Finished Jul 14 07:36:51 PM PDT 24
Peak memory 575468 kb
Host smart-b79e2aa5-0519-4644-9613-484bc673b6f2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704584081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3704584081
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.4396342
Short name T449
Test name
Test status
Simulation time 485971078 ps
CPU time 41.01 seconds
Started Jul 14 07:31:22 PM PDT 24
Finished Jul 14 07:32:04 PM PDT 24
Peak memory 575348 kb
Host smart-5a9b0d6e-b2a3-4a14-9f93-be02d62efaa6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4396342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.4396342
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_same_source.529830457
Short name T576
Test name
Test status
Simulation time 1062300264 ps
CPU time 33.93 seconds
Started Jul 14 07:31:28 PM PDT 24
Finished Jul 14 07:32:02 PM PDT 24
Peak memory 575316 kb
Host smart-d155d8c0-6531-454a-91d0-b892aad829ab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529830457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.529830457
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke.3602257367
Short name T2171
Test name
Test status
Simulation time 144493791 ps
CPU time 7.5 seconds
Started Jul 14 07:31:24 PM PDT 24
Finished Jul 14 07:31:32 PM PDT 24
Peak memory 575284 kb
Host smart-c041fc5d-3d7d-45d2-9f8b-bcc7797a6744
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602257367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.3602257367
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.3670679226
Short name T1925
Test name
Test status
Simulation time 7548418397 ps
CPU time 88.95 seconds
Started Jul 14 07:31:22 PM PDT 24
Finished Jul 14 07:32:51 PM PDT 24
Peak memory 575416 kb
Host smart-d4583afd-601d-47ab-89b5-5b845e0494d9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670679226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3670679226
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2754238922
Short name T1747
Test name
Test status
Simulation time 5756992320 ps
CPU time 105.87 seconds
Started Jul 14 07:31:19 PM PDT 24
Finished Jul 14 07:33:05 PM PDT 24
Peak memory 575444 kb
Host smart-94072187-4d6d-4a18-a006-3127bc7037b9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754238922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2754238922
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.602727682
Short name T2525
Test name
Test status
Simulation time 52374969 ps
CPU time 6.46 seconds
Started Jul 14 07:31:24 PM PDT 24
Finished Jul 14 07:31:31 PM PDT 24
Peak memory 574004 kb
Host smart-83f5fef4-5d63-4734-99e1-03609dfaea7b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602727682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays
.602727682
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all.212530719
Short name T603
Test name
Test status
Simulation time 4696308546 ps
CPU time 175.42 seconds
Started Jul 14 07:31:36 PM PDT 24
Finished Jul 14 07:34:32 PM PDT 24
Peak memory 575616 kb
Host smart-93d8d3c1-3fe1-4b5d-bb2c-8a9c63ac2bfe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212530719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.212530719
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.2960276136
Short name T2101
Test name
Test status
Simulation time 13574049203 ps
CPU time 509.43 seconds
Started Jul 14 07:31:34 PM PDT 24
Finished Jul 14 07:40:04 PM PDT 24
Peak memory 575568 kb
Host smart-741dd998-e76f-48a6-b360-59547314bf0b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960276136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2960276136
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.1017198065
Short name T2274
Test name
Test status
Simulation time 143763341 ps
CPU time 39.93 seconds
Started Jul 14 07:31:34 PM PDT 24
Finished Jul 14 07:32:15 PM PDT 24
Peak memory 575452 kb
Host smart-9fa4f7af-2479-437d-a008-b8d446bc350f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017198065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all
_with_rand_reset.1017198065
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.3852616644
Short name T2014
Test name
Test status
Simulation time 315486253 ps
CPU time 74.96 seconds
Started Jul 14 07:31:34 PM PDT 24
Finished Jul 14 07:32:49 PM PDT 24
Peak memory 575428 kb
Host smart-4fc4e13c-518a-404c-ae88-25709dd113a7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852616644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al
l_with_reset_error.3852616644
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.357142878
Short name T2652
Test name
Test status
Simulation time 265076257 ps
CPU time 30.72 seconds
Started Jul 14 07:31:29 PM PDT 24
Finished Jul 14 07:32:00 PM PDT 24
Peak memory 575380 kb
Host smart-d8b5ca17-babc-4840-88e1-2d62ee910f55
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357142878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.357142878
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_access_same_device.1076999366
Short name T2494
Test name
Test status
Simulation time 1112716543 ps
CPU time 41.9 seconds
Started Jul 14 07:31:34 PM PDT 24
Finished Jul 14 07:32:17 PM PDT 24
Peak memory 575344 kb
Host smart-679d44bd-a135-44f7-9059-a3aab99dc00c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076999366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device
.1076999366
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.1911429140
Short name T821
Test name
Test status
Simulation time 55066206280 ps
CPU time 946.68 seconds
Started Jul 14 07:31:39 PM PDT 24
Finished Jul 14 07:47:26 PM PDT 24
Peak memory 575504 kb
Host smart-19159d64-cd3a-4a81-ac13-48420011ccfa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911429140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_
device_slow_rsp.1911429140
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.1672178876
Short name T2489
Test name
Test status
Simulation time 77086615 ps
CPU time 11.12 seconds
Started Jul 14 07:31:40 PM PDT 24
Finished Jul 14 07:31:52 PM PDT 24
Peak memory 575344 kb
Host smart-82123c05-627a-43c1-8bcf-012a133d8874
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672178876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add
r.1672178876
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_error_random.3187244128
Short name T1626
Test name
Test status
Simulation time 495098463 ps
CPU time 35.49 seconds
Started Jul 14 07:31:40 PM PDT 24
Finished Jul 14 07:32:16 PM PDT 24
Peak memory 575272 kb
Host smart-23bc7e3a-9a5c-4ec7-abeb-73eae5b4da47
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187244128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3187244128
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random.8392431
Short name T595
Test name
Test status
Simulation time 1834651176 ps
CPU time 69.84 seconds
Started Jul 14 07:31:35 PM PDT 24
Finished Jul 14 07:32:45 PM PDT 24
Peak memory 575360 kb
Host smart-8510f825-4d25-458a-856d-2fd6bb6d3cdc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8392431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.8392431
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.2247546993
Short name T499
Test name
Test status
Simulation time 63181037636 ps
CPU time 762.15 seconds
Started Jul 14 07:31:35 PM PDT 24
Finished Jul 14 07:44:18 PM PDT 24
Peak memory 575560 kb
Host smart-dd99643b-a042-42fd-8499-19ff7f19df38
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247546993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2247546993
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.3199749024
Short name T2649
Test name
Test status
Simulation time 55377405992 ps
CPU time 941.99 seconds
Started Jul 14 07:31:34 PM PDT 24
Finished Jul 14 07:47:18 PM PDT 24
Peak memory 575564 kb
Host smart-6f2a9c5f-a35e-437e-a03b-d898ee16f4db
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199749024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3199749024
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.73657611
Short name T2340
Test name
Test status
Simulation time 328788164 ps
CPU time 28.77 seconds
Started Jul 14 07:31:35 PM PDT 24
Finished Jul 14 07:32:05 PM PDT 24
Peak memory 575312 kb
Host smart-f00f91b0-27cb-4b51-ab7e-b4f350203c7a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73657611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delay
s.73657611
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_same_source.1307812205
Short name T1761
Test name
Test status
Simulation time 205833502 ps
CPU time 16.47 seconds
Started Jul 14 07:31:41 PM PDT 24
Finished Jul 14 07:31:58 PM PDT 24
Peak memory 575316 kb
Host smart-8a670c72-46f6-407d-83d1-158cc7433435
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307812205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1307812205
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke.2095250278
Short name T2161
Test name
Test status
Simulation time 42284808 ps
CPU time 6.05 seconds
Started Jul 14 07:31:35 PM PDT 24
Finished Jul 14 07:31:42 PM PDT 24
Peak memory 573984 kb
Host smart-fd30e9f5-98d5-411e-8257-7d2aa0d259e8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095250278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2095250278
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.2603246629
Short name T1624
Test name
Test status
Simulation time 9174151975 ps
CPU time 100.38 seconds
Started Jul 14 07:31:36 PM PDT 24
Finished Jul 14 07:33:17 PM PDT 24
Peak memory 575424 kb
Host smart-13a43e7d-6dfd-4bf8-b11b-340fa2ab9175
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603246629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2603246629
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.3023235532
Short name T1922
Test name
Test status
Simulation time 3341520904 ps
CPU time 59.57 seconds
Started Jul 14 07:31:33 PM PDT 24
Finished Jul 14 07:32:33 PM PDT 24
Peak memory 575328 kb
Host smart-1c002636-7427-49f3-b1cc-be3b82549f9a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023235532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3023235532
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.1129687435
Short name T2833
Test name
Test status
Simulation time 51462422 ps
CPU time 6.27 seconds
Started Jul 14 07:31:34 PM PDT 24
Finished Jul 14 07:31:41 PM PDT 24
Peak memory 574052 kb
Host smart-b9eb3807-845a-4c86-8382-a9e7485c13ff
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129687435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay
s.1129687435
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all.1485665638
Short name T2679
Test name
Test status
Simulation time 2582988304 ps
CPU time 94.41 seconds
Started Jul 14 07:31:41 PM PDT 24
Finished Jul 14 07:33:16 PM PDT 24
Peak memory 575508 kb
Host smart-72121800-62ec-4e3b-9aed-4200f6123fd7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485665638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1485665638
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.3848160902
Short name T1771
Test name
Test status
Simulation time 12069118597 ps
CPU time 456.67 seconds
Started Jul 14 07:31:41 PM PDT 24
Finished Jul 14 07:39:18 PM PDT 24
Peak memory 575612 kb
Host smart-08b88fca-7749-4385-9f17-254609d4dd6b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848160902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3848160902
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.2541291081
Short name T2194
Test name
Test status
Simulation time 1509505694 ps
CPU time 139.55 seconds
Started Jul 14 07:31:39 PM PDT 24
Finished Jul 14 07:33:59 PM PDT 24
Peak memory 575476 kb
Host smart-196c8e92-5353-40ea-86d0-51c4601f5b50
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541291081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all
_with_rand_reset.2541291081
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.2785276496
Short name T2635
Test name
Test status
Simulation time 80766939 ps
CPU time 34.58 seconds
Started Jul 14 07:31:46 PM PDT 24
Finished Jul 14 07:32:21 PM PDT 24
Peak memory 575456 kb
Host smart-e3fc1dee-317e-45db-904d-3980d318d60e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785276496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al
l_with_reset_error.2785276496
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/22.chip_tl_errors.2240843971
Short name T2412
Test name
Test status
Simulation time 4054039845 ps
CPU time 256.71 seconds
Started Jul 14 07:31:49 PM PDT 24
Finished Jul 14 07:36:06 PM PDT 24
Peak memory 598692 kb
Host smart-140c27b3-eabf-4246-9f02-1c5886262109
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240843971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.2240843971
Directory /workspace/22.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_access_same_device.1672019826
Short name T1453
Test name
Test status
Simulation time 208456794 ps
CPU time 19.91 seconds
Started Jul 14 07:31:48 PM PDT 24
Finished Jul 14 07:32:08 PM PDT 24
Peak memory 575340 kb
Host smart-46c0449f-f4f4-4e12-804a-a101be36bd28
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672019826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device
.1672019826
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.3936339406
Short name T2671
Test name
Test status
Simulation time 145451317583 ps
CPU time 2759.03 seconds
Started Jul 14 07:31:47 PM PDT 24
Finished Jul 14 08:17:47 PM PDT 24
Peak memory 575596 kb
Host smart-33bf3204-b0d2-4a88-9004-3214c3b98234
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936339406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_
device_slow_rsp.3936339406
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.2676862444
Short name T1868
Test name
Test status
Simulation time 123267399 ps
CPU time 15.85 seconds
Started Jul 14 07:31:48 PM PDT 24
Finished Jul 14 07:32:04 PM PDT 24
Peak memory 575300 kb
Host smart-187c63ac-b4c7-4c5b-aac1-8b32ca22ec29
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676862444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add
r.2676862444
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_error_random.2379919818
Short name T2506
Test name
Test status
Simulation time 578026836 ps
CPU time 45.55 seconds
Started Jul 14 07:31:50 PM PDT 24
Finished Jul 14 07:32:36 PM PDT 24
Peak memory 575260 kb
Host smart-d531d0a7-2d2e-4508-8678-70621177408c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379919818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2379919818
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random.1185273764
Short name T2147
Test name
Test status
Simulation time 62399491 ps
CPU time 8.08 seconds
Started Jul 14 07:31:51 PM PDT 24
Finished Jul 14 07:32:00 PM PDT 24
Peak memory 575352 kb
Host smart-8ca3684b-6354-4d43-8d68-169fa6e05518
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185273764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.1185273764
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.3186086091
Short name T1884
Test name
Test status
Simulation time 91507030875 ps
CPU time 982.56 seconds
Started Jul 14 07:31:48 PM PDT 24
Finished Jul 14 07:48:12 PM PDT 24
Peak memory 575556 kb
Host smart-177a6583-0320-4b6f-834a-b1661e3b6128
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186086091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3186086091
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.1737818778
Short name T2750
Test name
Test status
Simulation time 18800485817 ps
CPU time 343.65 seconds
Started Jul 14 07:31:46 PM PDT 24
Finished Jul 14 07:37:30 PM PDT 24
Peak memory 575464 kb
Host smart-05d0323d-17db-418d-97cf-91a3602024c4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737818778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1737818778
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.3669905561
Short name T1885
Test name
Test status
Simulation time 66505811 ps
CPU time 8.34 seconds
Started Jul 14 07:31:50 PM PDT 24
Finished Jul 14 07:31:59 PM PDT 24
Peak memory 575256 kb
Host smart-dd9427d1-ffbc-4107-a208-36d27d37504a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669905561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del
ays.3669905561
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_same_source.825491419
Short name T1568
Test name
Test status
Simulation time 2028140045 ps
CPU time 58.21 seconds
Started Jul 14 07:31:49 PM PDT 24
Finished Jul 14 07:32:48 PM PDT 24
Peak memory 575352 kb
Host smart-77242764-79d8-482f-ab4f-e8f0c1c1abdc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825491419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.825491419
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke.2516016483
Short name T2152
Test name
Test status
Simulation time 189449562 ps
CPU time 7.87 seconds
Started Jul 14 07:31:51 PM PDT 24
Finished Jul 14 07:31:59 PM PDT 24
Peak memory 575276 kb
Host smart-0492a51f-ec19-4d53-9e26-4c7b3016a806
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516016483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2516016483
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.3006827211
Short name T2093
Test name
Test status
Simulation time 6414134082 ps
CPU time 69.18 seconds
Started Jul 14 07:31:47 PM PDT 24
Finished Jul 14 07:32:57 PM PDT 24
Peak memory 575488 kb
Host smart-adb2483c-5bcc-41fa-b745-d2f325f3148a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006827211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.3006827211
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.4101168345
Short name T2538
Test name
Test status
Simulation time 4121236801 ps
CPU time 81.66 seconds
Started Jul 14 07:31:46 PM PDT 24
Finished Jul 14 07:33:08 PM PDT 24
Peak memory 574068 kb
Host smart-a79e111d-dc2a-4632-8430-c346f53301dd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101168345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.4101168345
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.4248521689
Short name T1619
Test name
Test status
Simulation time 46906952 ps
CPU time 6.1 seconds
Started Jul 14 07:31:47 PM PDT 24
Finished Jul 14 07:31:54 PM PDT 24
Peak memory 574000 kb
Host smart-a2371bcb-5e56-43b1-9a54-c68a75a07a4f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248521689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay
s.4248521689
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all.303929948
Short name T2542
Test name
Test status
Simulation time 2072875283 ps
CPU time 179.2 seconds
Started Jul 14 07:31:55 PM PDT 24
Finished Jul 14 07:34:55 PM PDT 24
Peak memory 575476 kb
Host smart-ed2f7322-8941-46ef-9366-21c21e92ca9a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303929948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.303929948
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.2606907209
Short name T1759
Test name
Test status
Simulation time 3163592322 ps
CPU time 256.42 seconds
Started Jul 14 07:31:56 PM PDT 24
Finished Jul 14 07:36:13 PM PDT 24
Peak memory 575532 kb
Host smart-ff198e89-b07a-4d22-be70-2e6bfbdba347
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606907209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2606907209
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.1379505715
Short name T2540
Test name
Test status
Simulation time 11646614296 ps
CPU time 571.64 seconds
Started Jul 14 07:31:55 PM PDT 24
Finished Jul 14 07:41:27 PM PDT 24
Peak memory 575632 kb
Host smart-78599815-1c99-450b-b859-973ccd7276a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379505715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all
_with_rand_reset.1379505715
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.2074308018
Short name T1773
Test name
Test status
Simulation time 3429525625 ps
CPU time 430.03 seconds
Started Jul 14 07:31:57 PM PDT 24
Finished Jul 14 07:39:08 PM PDT 24
Peak memory 575516 kb
Host smart-29118232-822d-4e72-9174-adda92eb0b1d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074308018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al
l_with_reset_error.2074308018
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.3095215312
Short name T2012
Test name
Test status
Simulation time 1152427798 ps
CPU time 52.01 seconds
Started Jul 14 07:31:48 PM PDT 24
Finished Jul 14 07:32:40 PM PDT 24
Peak memory 575376 kb
Host smart-3645aeb2-98ef-40db-9f98-6272ba568239
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095215312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3095215312
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_access_same_device.2778843828
Short name T842
Test name
Test status
Simulation time 2018519511 ps
CPU time 94.2 seconds
Started Jul 14 07:31:58 PM PDT 24
Finished Jul 14 07:33:33 PM PDT 24
Peak memory 575472 kb
Host smart-8156d16a-ceae-499a-a41e-6eaf3a2175f4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778843828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device
.2778843828
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2389182183
Short name T542
Test name
Test status
Simulation time 115023643877 ps
CPU time 2114.24 seconds
Started Jul 14 07:31:57 PM PDT 24
Finished Jul 14 08:07:12 PM PDT 24
Peak memory 575588 kb
Host smart-f3cebbb5-f6de-4ec6-9de7-8684eea2f9f7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389182183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_
device_slow_rsp.2389182183
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.2559732990
Short name T1645
Test name
Test status
Simulation time 754675203 ps
CPU time 31.95 seconds
Started Jul 14 07:31:57 PM PDT 24
Finished Jul 14 07:32:30 PM PDT 24
Peak memory 575236 kb
Host smart-02e26c60-c208-4f48-80a5-a8f198b9bce4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559732990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add
r.2559732990
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_error_random.4078914578
Short name T2490
Test name
Test status
Simulation time 1256110912 ps
CPU time 41.79 seconds
Started Jul 14 07:31:58 PM PDT 24
Finished Jul 14 07:32:41 PM PDT 24
Peak memory 575248 kb
Host smart-46416a75-f6a8-4abf-be4d-a8cf0b81565d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078914578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.4078914578
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random.2248641893
Short name T2807
Test name
Test status
Simulation time 213838063 ps
CPU time 21.84 seconds
Started Jul 14 07:31:56 PM PDT 24
Finished Jul 14 07:32:18 PM PDT 24
Peak memory 575352 kb
Host smart-4b6200cd-de7b-427e-945e-2a015a3d56f2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248641893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.2248641893
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.2277411494
Short name T2582
Test name
Test status
Simulation time 18035922132 ps
CPU time 212.04 seconds
Started Jul 14 07:31:55 PM PDT 24
Finished Jul 14 07:35:28 PM PDT 24
Peak memory 575504 kb
Host smart-62eabc19-0704-4696-9491-d449b1b66b9b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277411494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2277411494
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.2408648664
Short name T1850
Test name
Test status
Simulation time 67808190875 ps
CPU time 1109.54 seconds
Started Jul 14 07:31:59 PM PDT 24
Finished Jul 14 07:50:29 PM PDT 24
Peak memory 575484 kb
Host smart-e86da44a-5f9b-4d2f-8536-83fc7b33219f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408648664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2408648664
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.2335397900
Short name T2268
Test name
Test status
Simulation time 421079877 ps
CPU time 38.77 seconds
Started Jul 14 07:31:58 PM PDT 24
Finished Jul 14 07:32:37 PM PDT 24
Peak memory 575296 kb
Host smart-204362cb-4142-4ec0-9a02-c7c7fc448972
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335397900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del
ays.2335397900
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_same_source.4042389716
Short name T1676
Test name
Test status
Simulation time 357193755 ps
CPU time 14.35 seconds
Started Jul 14 07:31:59 PM PDT 24
Finished Jul 14 07:32:14 PM PDT 24
Peak memory 575300 kb
Host smart-bdfaf489-87ed-43dc-9ffe-812726028cbe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042389716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.4042389716
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke.1365160623
Short name T2376
Test name
Test status
Simulation time 244666721 ps
CPU time 9.66 seconds
Started Jul 14 07:31:56 PM PDT 24
Finished Jul 14 07:32:06 PM PDT 24
Peak memory 574052 kb
Host smart-c363f90e-dd5b-48c5-9608-4a3ae424c12d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365160623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1365160623
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.2149208337
Short name T2853
Test name
Test status
Simulation time 6634720772 ps
CPU time 72.47 seconds
Started Jul 14 07:31:57 PM PDT 24
Finished Jul 14 07:33:10 PM PDT 24
Peak memory 574156 kb
Host smart-563ed87e-bee7-4a60-842e-005802ac73a5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149208337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2149208337
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.1501241001
Short name T2413
Test name
Test status
Simulation time 3838873680 ps
CPU time 69.63 seconds
Started Jul 14 07:31:55 PM PDT 24
Finished Jul 14 07:33:05 PM PDT 24
Peak memory 574072 kb
Host smart-a829b53a-9fc3-492c-8d76-58c7ca8fc6eb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501241001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1501241001
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.1129181866
Short name T2119
Test name
Test status
Simulation time 49670720 ps
CPU time 5.81 seconds
Started Jul 14 07:31:56 PM PDT 24
Finished Jul 14 07:32:03 PM PDT 24
Peak memory 575272 kb
Host smart-47b5ee7b-4766-4aca-872e-cb7856b1122e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129181866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay
s.1129181866
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all.753546370
Short name T510
Test name
Test status
Simulation time 6882224840 ps
CPU time 243.06 seconds
Started Jul 14 07:31:59 PM PDT 24
Finished Jul 14 07:36:03 PM PDT 24
Peak memory 575584 kb
Host smart-9512b1aa-d276-4a88-9ad8-74c70759bd48
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753546370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.753546370
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.2805422747
Short name T2535
Test name
Test status
Simulation time 7339007139 ps
CPU time 267.65 seconds
Started Jul 14 07:32:00 PM PDT 24
Finished Jul 14 07:36:28 PM PDT 24
Peak memory 575516 kb
Host smart-a2b5e528-65ad-4c4b-bb89-e3124e8b0e44
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805422747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2805422747
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.2586807181
Short name T2647
Test name
Test status
Simulation time 97496880 ps
CPU time 17.44 seconds
Started Jul 14 07:31:58 PM PDT 24
Finished Jul 14 07:32:16 PM PDT 24
Peak memory 574180 kb
Host smart-9727baba-75a1-4ada-93ab-acbf9d7a3fbc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586807181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al
l_with_reset_error.2586807181
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.450456281
Short name T1350
Test name
Test status
Simulation time 91101726 ps
CPU time 12.41 seconds
Started Jul 14 07:31:58 PM PDT 24
Finished Jul 14 07:32:11 PM PDT 24
Peak memory 575376 kb
Host smart-a053dbe4-6296-4996-ad2e-9afdabc80789
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450456281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.450456281
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/24.chip_tl_errors.219148169
Short name T553
Test name
Test status
Simulation time 3656411244 ps
CPU time 236.2 seconds
Started Jul 14 07:31:58 PM PDT 24
Finished Jul 14 07:35:55 PM PDT 24
Peak memory 603956 kb
Host smart-401d8012-2c69-4779-8f86-9f5fed5cb8a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219148169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.219148169
Directory /workspace/24.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.4187457380
Short name T837
Test name
Test status
Simulation time 165269910865 ps
CPU time 3145.64 seconds
Started Jul 14 07:32:09 PM PDT 24
Finished Jul 14 08:24:35 PM PDT 24
Peak memory 575648 kb
Host smart-e1d7f550-684f-43ca-8f9f-6e5d74848769
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187457380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_
device_slow_rsp.4187457380
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.4226494066
Short name T1974
Test name
Test status
Simulation time 592932020 ps
CPU time 22.78 seconds
Started Jul 14 07:32:10 PM PDT 24
Finished Jul 14 07:32:33 PM PDT 24
Peak memory 575324 kb
Host smart-eabded29-ef35-4b5b-a972-ac418b498b77
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226494066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add
r.4226494066
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_error_random.456146615
Short name T2437
Test name
Test status
Simulation time 1929694682 ps
CPU time 64.06 seconds
Started Jul 14 07:32:05 PM PDT 24
Finished Jul 14 07:33:10 PM PDT 24
Peak memory 575260 kb
Host smart-b15ef73e-c906-4525-bf49-00f5b3b550a0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456146615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.456146615
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random.665086216
Short name T643
Test name
Test status
Simulation time 2498282274 ps
CPU time 96.11 seconds
Started Jul 14 07:32:06 PM PDT 24
Finished Jul 14 07:33:42 PM PDT 24
Peak memory 575452 kb
Host smart-ef612d1f-657c-4f9b-a9ed-36c7dffdabdf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665086216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.665086216
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.2741790321
Short name T2722
Test name
Test status
Simulation time 61481605511 ps
CPU time 730 seconds
Started Jul 14 07:32:06 PM PDT 24
Finished Jul 14 07:44:16 PM PDT 24
Peak memory 575564 kb
Host smart-6fed1844-9a61-4f9c-81f2-c2677d1447ad
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741790321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2741790321
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.1452164228
Short name T1904
Test name
Test status
Simulation time 58496778756 ps
CPU time 1072.53 seconds
Started Jul 14 07:32:05 PM PDT 24
Finished Jul 14 07:49:58 PM PDT 24
Peak memory 575500 kb
Host smart-c9f6ec61-e919-48b0-9800-48aa55055d4c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452164228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1452164228
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.2708524378
Short name T2247
Test name
Test status
Simulation time 504382435 ps
CPU time 43.34 seconds
Started Jul 14 07:32:07 PM PDT 24
Finished Jul 14 07:32:51 PM PDT 24
Peak memory 575292 kb
Host smart-da63f433-3d42-404c-a827-ae79069d6488
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708524378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del
ays.2708524378
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_same_source.1018981416
Short name T2215
Test name
Test status
Simulation time 198600251 ps
CPU time 16.27 seconds
Started Jul 14 07:32:04 PM PDT 24
Finished Jul 14 07:32:20 PM PDT 24
Peak memory 575312 kb
Host smart-05589c94-550c-4d75-88a0-d030b7afef20
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018981416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1018981416
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke.2584305381
Short name T2472
Test name
Test status
Simulation time 235784421 ps
CPU time 10.51 seconds
Started Jul 14 07:32:03 PM PDT 24
Finished Jul 14 07:32:14 PM PDT 24
Peak memory 575252 kb
Host smart-249c4732-2524-4e76-8331-1092d96756b6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584305381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2584305381
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.1155082257
Short name T1594
Test name
Test status
Simulation time 8391452629 ps
CPU time 96.06 seconds
Started Jul 14 07:32:05 PM PDT 24
Finished Jul 14 07:33:41 PM PDT 24
Peak memory 574132 kb
Host smart-55e8a73e-665b-4809-b96a-2dce109e3b6a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155082257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1155082257
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.1873117767
Short name T1877
Test name
Test status
Simulation time 4642454381 ps
CPU time 91.1 seconds
Started Jul 14 07:32:06 PM PDT 24
Finished Jul 14 07:33:38 PM PDT 24
Peak memory 575384 kb
Host smart-87381c59-6da7-4e96-bcd3-86c5b61e9309
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873117767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1873117767
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.1640363767
Short name T2659
Test name
Test status
Simulation time 47544049 ps
CPU time 6.42 seconds
Started Jul 14 07:32:08 PM PDT 24
Finished Jul 14 07:32:15 PM PDT 24
Peak memory 575300 kb
Host smart-81f06a8d-9710-4fd7-a34c-76a5b2a6a8c4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640363767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delay
s.1640363767
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all.3917700517
Short name T1844
Test name
Test status
Simulation time 6112741776 ps
CPU time 218.78 seconds
Started Jul 14 07:32:10 PM PDT 24
Finished Jul 14 07:35:50 PM PDT 24
Peak memory 575544 kb
Host smart-0339b3d7-008c-4883-89ff-95be0165f281
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917700517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3917700517
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.4083249084
Short name T2864
Test name
Test status
Simulation time 2435655301 ps
CPU time 71.87 seconds
Started Jul 14 07:32:12 PM PDT 24
Finished Jul 14 07:33:24 PM PDT 24
Peak memory 575308 kb
Host smart-39c86950-8e6e-48b5-94fe-a24317da746c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083249084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.4083249084
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.2273758990
Short name T2554
Test name
Test status
Simulation time 1830820269 ps
CPU time 329.66 seconds
Started Jul 14 07:32:16 PM PDT 24
Finished Jul 14 07:37:46 PM PDT 24
Peak memory 575480 kb
Host smart-73da37cd-11c6-4701-b2d8-fe073cf2481a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273758990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all
_with_rand_reset.2273758990
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.1149015777
Short name T2791
Test name
Test status
Simulation time 455925078 ps
CPU time 94.32 seconds
Started Jul 14 07:32:12 PM PDT 24
Finished Jul 14 07:33:47 PM PDT 24
Peak memory 575404 kb
Host smart-aac657c2-f7c9-45e1-ae4f-966c477129ca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149015777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al
l_with_reset_error.1149015777
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.3878872682
Short name T657
Test name
Test status
Simulation time 953143768 ps
CPU time 40.67 seconds
Started Jul 14 07:32:10 PM PDT 24
Finished Jul 14 07:32:51 PM PDT 24
Peak memory 575340 kb
Host smart-777208df-4abf-4740-9d23-e28bd4489b85
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878872682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3878872682
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_access_same_device.594637942
Short name T1360
Test name
Test status
Simulation time 1193902327 ps
CPU time 47.54 seconds
Started Jul 14 07:32:26 PM PDT 24
Finished Jul 14 07:33:14 PM PDT 24
Peak memory 575292 kb
Host smart-c6e87c27-17b1-46a5-a91e-d3b4f96e299d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594637942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.
594637942
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.36389284
Short name T2799
Test name
Test status
Simulation time 20066260737 ps
CPU time 332.03 seconds
Started Jul 14 07:32:21 PM PDT 24
Finished Jul 14 07:37:53 PM PDT 24
Peak memory 575448 kb
Host smart-8c88edff-bd73-422c-8151-d4d57c929ac7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36389284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_de
vice_slow_rsp.36389284
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.3110106982
Short name T2438
Test name
Test status
Simulation time 162114890 ps
CPU time 20.19 seconds
Started Jul 14 07:32:27 PM PDT 24
Finished Jul 14 07:32:48 PM PDT 24
Peak memory 575340 kb
Host smart-4fc299d8-1b78-47b7-873e-a25470b38352
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110106982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add
r.3110106982
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_error_random.554510563
Short name T2741
Test name
Test status
Simulation time 349427627 ps
CPU time 33.8 seconds
Started Jul 14 07:32:21 PM PDT 24
Finished Jul 14 07:32:55 PM PDT 24
Peak memory 575304 kb
Host smart-7edab539-d296-439f-adef-ce0bf0be7f9c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554510563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.554510563
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random.3325073765
Short name T2059
Test name
Test status
Simulation time 149546913 ps
CPU time 18.19 seconds
Started Jul 14 07:32:14 PM PDT 24
Finished Jul 14 07:32:33 PM PDT 24
Peak memory 575340 kb
Host smart-5b80e7c9-776a-478f-bc6b-41df8b44ea2a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325073765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.3325073765
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.3018899056
Short name T2076
Test name
Test status
Simulation time 51048654760 ps
CPU time 563.99 seconds
Started Jul 14 07:32:15 PM PDT 24
Finished Jul 14 07:41:40 PM PDT 24
Peak memory 575512 kb
Host smart-6ece65d7-ce6a-4522-803e-5e323a295a66
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018899056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3018899056
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.4279236599
Short name T619
Test name
Test status
Simulation time 54165197250 ps
CPU time 967.63 seconds
Started Jul 14 07:32:15 PM PDT 24
Finished Jul 14 07:48:23 PM PDT 24
Peak memory 575436 kb
Host smart-8cf83695-c789-4149-be36-0dabbedbfc4f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279236599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.4279236599
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.780538811
Short name T2627
Test name
Test status
Simulation time 324070454 ps
CPU time 31.54 seconds
Started Jul 14 07:32:14 PM PDT 24
Finished Jul 14 07:32:46 PM PDT 24
Peak memory 575316 kb
Host smart-3c3ce38f-4fb9-492e-bd98-a397c6ca5235
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780538811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_dela
ys.780538811
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_same_source.3031594419
Short name T1878
Test name
Test status
Simulation time 1376905551 ps
CPU time 38.67 seconds
Started Jul 14 07:32:20 PM PDT 24
Finished Jul 14 07:32:59 PM PDT 24
Peak memory 575312 kb
Host smart-79b78002-ceb6-4efb-98ca-74e79977a501
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031594419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3031594419
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke.3697963528
Short name T2543
Test name
Test status
Simulation time 227102235 ps
CPU time 9.41 seconds
Started Jul 14 07:32:10 PM PDT 24
Finished Jul 14 07:32:20 PM PDT 24
Peak memory 575260 kb
Host smart-69b1bcab-a365-4188-b52b-2632fffe3e5a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697963528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.3697963528
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.3670443888
Short name T653
Test name
Test status
Simulation time 6164287332 ps
CPU time 70.2 seconds
Started Jul 14 07:32:15 PM PDT 24
Finished Jul 14 07:33:25 PM PDT 24
Peak memory 574212 kb
Host smart-63403850-5aff-4f25-81b4-1c5c9d82d0f3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670443888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3670443888
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.4104598162
Short name T1846
Test name
Test status
Simulation time 6360201717 ps
CPU time 107.88 seconds
Started Jul 14 07:32:18 PM PDT 24
Finished Jul 14 07:34:07 PM PDT 24
Peak memory 574160 kb
Host smart-5230d742-98ef-41b1-b6f3-f6e93ec7dcd5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104598162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.4104598162
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.585839794
Short name T2026
Test name
Test status
Simulation time 55997119 ps
CPU time 6.52 seconds
Started Jul 14 07:32:10 PM PDT 24
Finished Jul 14 07:32:18 PM PDT 24
Peak memory 573988 kb
Host smart-79cee7ca-cb17-4be9-bd43-3a3d890f8882
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585839794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays
.585839794
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all.1115250399
Short name T2474
Test name
Test status
Simulation time 5593092281 ps
CPU time 189.54 seconds
Started Jul 14 07:32:33 PM PDT 24
Finished Jul 14 07:35:43 PM PDT 24
Peak memory 575560 kb
Host smart-249e57b4-ee38-4865-a933-2586d9edac62
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115250399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1115250399
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.1680617965
Short name T1536
Test name
Test status
Simulation time 19702923581 ps
CPU time 697.4 seconds
Started Jul 14 07:32:29 PM PDT 24
Finished Jul 14 07:44:07 PM PDT 24
Peak memory 575580 kb
Host smart-2a3dcd7d-52b1-44a0-b145-b85ece6ed0f5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680617965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1680617965
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.3774235691
Short name T523
Test name
Test status
Simulation time 2602332887 ps
CPU time 411.9 seconds
Started Jul 14 07:32:32 PM PDT 24
Finished Jul 14 07:39:25 PM PDT 24
Peak memory 575536 kb
Host smart-e6e5a058-1a9f-46dc-a31e-d7409e4c9eec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774235691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all
_with_rand_reset.3774235691
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.3082338481
Short name T2573
Test name
Test status
Simulation time 4389418903 ps
CPU time 327.89 seconds
Started Jul 14 07:32:29 PM PDT 24
Finished Jul 14 07:37:58 PM PDT 24
Peak memory 575784 kb
Host smart-81126d2e-1ae1-4073-bb1a-05a123b7b35f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082338481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al
l_with_reset_error.3082338481
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.1266188402
Short name T1970
Test name
Test status
Simulation time 226323821 ps
CPU time 13.47 seconds
Started Jul 14 07:32:26 PM PDT 24
Finished Jul 14 07:32:39 PM PDT 24
Peak memory 575412 kb
Host smart-f923ca28-6913-4113-8aca-f74b65f5300e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266188402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.1266188402
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/26.chip_tl_errors.3459354545
Short name T2333
Test name
Test status
Simulation time 4092115296 ps
CPU time 320.56 seconds
Started Jul 14 07:32:32 PM PDT 24
Finished Jul 14 07:37:53 PM PDT 24
Peak memory 603864 kb
Host smart-9e281101-65a0-4863-af20-a63e4c5fda96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459354545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.3459354545
Directory /workspace/26.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_access_same_device.3078957395
Short name T828
Test name
Test status
Simulation time 1430661438 ps
CPU time 59.69 seconds
Started Jul 14 07:32:35 PM PDT 24
Finished Jul 14 07:33:35 PM PDT 24
Peak memory 575380 kb
Host smart-2a705848-c1e2-4bad-a017-48526c6e17fc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078957395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device
.3078957395
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.3335788494
Short name T1703
Test name
Test status
Simulation time 53356505193 ps
CPU time 887.14 seconds
Started Jul 14 07:32:34 PM PDT 24
Finished Jul 14 07:47:22 PM PDT 24
Peak memory 575544 kb
Host smart-0bc846e2-f527-40b8-b6f7-4d3d10ae8b13
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335788494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_
device_slow_rsp.3335788494
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.3934318464
Short name T2513
Test name
Test status
Simulation time 21660798 ps
CPU time 5.49 seconds
Started Jul 14 07:32:35 PM PDT 24
Finished Jul 14 07:32:41 PM PDT 24
Peak memory 573956 kb
Host smart-4778325c-ce11-4d8e-be2c-ba40af79c99f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934318464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add
r.3934318464
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_error_random.454769269
Short name T2415
Test name
Test status
Simulation time 489806411 ps
CPU time 36.14 seconds
Started Jul 14 07:32:33 PM PDT 24
Finished Jul 14 07:33:10 PM PDT 24
Peak memory 575340 kb
Host smart-d55b109b-966e-4f15-9fba-f77335b94edb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454769269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.454769269
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random.2441045924
Short name T2469
Test name
Test status
Simulation time 516829367 ps
CPU time 21.95 seconds
Started Jul 14 07:32:28 PM PDT 24
Finished Jul 14 07:32:51 PM PDT 24
Peak memory 575280 kb
Host smart-be737217-11df-4d25-8dbc-55126c7f0135
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441045924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.2441045924
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.4140792131
Short name T1722
Test name
Test status
Simulation time 22060725243 ps
CPU time 239.55 seconds
Started Jul 14 07:32:34 PM PDT 24
Finished Jul 14 07:36:34 PM PDT 24
Peak memory 575520 kb
Host smart-afbc342a-b120-4d6e-9f6d-c00b0736940c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140792131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.4140792131
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.1649167151
Short name T2757
Test name
Test status
Simulation time 68263075354 ps
CPU time 1270.79 seconds
Started Jul 14 07:32:34 PM PDT 24
Finished Jul 14 07:53:46 PM PDT 24
Peak memory 575524 kb
Host smart-23243174-cb16-479a-90b3-2f321447113a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649167151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1649167151
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.3982948507
Short name T2666
Test name
Test status
Simulation time 36873525 ps
CPU time 6.2 seconds
Started Jul 14 07:32:35 PM PDT 24
Finished Jul 14 07:32:42 PM PDT 24
Peak memory 575324 kb
Host smart-256807b5-04bd-4419-9ebf-ce69447db5fe
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982948507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del
ays.3982948507
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_same_source.3160765441
Short name T1521
Test name
Test status
Simulation time 260204587 ps
CPU time 20.27 seconds
Started Jul 14 07:32:38 PM PDT 24
Finished Jul 14 07:32:59 PM PDT 24
Peak memory 575336 kb
Host smart-a4536200-f692-46dc-83e2-d0f0735017b6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160765441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3160765441
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke.1228190097
Short name T2005
Test name
Test status
Simulation time 120141182 ps
CPU time 6.91 seconds
Started Jul 14 07:32:28 PM PDT 24
Finished Jul 14 07:32:36 PM PDT 24
Peak memory 575284 kb
Host smart-81f958d5-1a26-46ce-b29a-449dfc6dd2cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228190097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1228190097
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.3746669773
Short name T1666
Test name
Test status
Simulation time 7907983401 ps
CPU time 89.41 seconds
Started Jul 14 07:32:31 PM PDT 24
Finished Jul 14 07:34:01 PM PDT 24
Peak memory 574184 kb
Host smart-44046ef6-74d0-4fb9-bc68-2183b279ea36
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746669773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3746669773
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.1073709422
Short name T1779
Test name
Test status
Simulation time 3567600991 ps
CPU time 61.46 seconds
Started Jul 14 07:32:30 PM PDT 24
Finished Jul 14 07:33:32 PM PDT 24
Peak memory 575356 kb
Host smart-6f360a72-9e61-4e0e-8dd8-eb52da0d70d5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073709422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1073709422
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.4275130573
Short name T2841
Test name
Test status
Simulation time 35656439 ps
CPU time 5.86 seconds
Started Jul 14 07:32:27 PM PDT 24
Finished Jul 14 07:32:34 PM PDT 24
Peak memory 574028 kb
Host smart-57f25d60-f83c-4b3f-b640-4e0eecae0096
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275130573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay
s.4275130573
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all.1250089879
Short name T2526
Test name
Test status
Simulation time 2294940320 ps
CPU time 183.35 seconds
Started Jul 14 07:32:35 PM PDT 24
Finished Jul 14 07:35:39 PM PDT 24
Peak memory 575544 kb
Host smart-cfc33c69-2baa-4ce7-9737-6a7fa30f5083
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250089879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1250089879
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.2330338895
Short name T2783
Test name
Test status
Simulation time 3577421422 ps
CPU time 329.43 seconds
Started Jul 14 07:32:43 PM PDT 24
Finished Jul 14 07:38:13 PM PDT 24
Peak memory 575544 kb
Host smart-4644ed35-d3e2-4995-b84f-cfc3a0986868
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330338895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2330338895
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.212913499
Short name T2351
Test name
Test status
Simulation time 2178109662 ps
CPU time 241.03 seconds
Started Jul 14 07:32:34 PM PDT 24
Finished Jul 14 07:36:35 PM PDT 24
Peak memory 575524 kb
Host smart-057005cd-44ab-49b4-b152-b752e5045151
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212913499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_
with_rand_reset.212913499
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3757770716
Short name T2688
Test name
Test status
Simulation time 273587364 ps
CPU time 144.85 seconds
Started Jul 14 07:32:42 PM PDT 24
Finished Jul 14 07:35:07 PM PDT 24
Peak memory 575660 kb
Host smart-435358be-3e5f-4d1e-a7b7-59a3a959dd8a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757770716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al
l_with_reset_error.3757770716
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.2128975024
Short name T2009
Test name
Test status
Simulation time 1119767009 ps
CPU time 48.82 seconds
Started Jul 14 07:33:21 PM PDT 24
Finished Jul 14 07:34:11 PM PDT 24
Peak memory 575436 kb
Host smart-2af16525-886f-4b10-bc7e-00b389fbd8c0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128975024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2128975024
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/27.chip_tl_errors.1335225259
Short name T2683
Test name
Test status
Simulation time 3158006422 ps
CPU time 190.13 seconds
Started Jul 14 07:32:42 PM PDT 24
Finished Jul 14 07:35:53 PM PDT 24
Peak memory 598784 kb
Host smart-e5bc8bd1-3e93-4f14-9c25-c1084c3f0eb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335225259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.1335225259
Directory /workspace/27.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_access_same_device.2989960692
Short name T2581
Test name
Test status
Simulation time 1438408302 ps
CPU time 61.72 seconds
Started Jul 14 07:32:48 PM PDT 24
Finished Jul 14 07:33:50 PM PDT 24
Peak memory 575384 kb
Host smart-240e09a7-72fc-480a-8f13-1e4c9b98e723
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989960692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device
.2989960692
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.4154251091
Short name T2493
Test name
Test status
Simulation time 86386299115 ps
CPU time 1500.47 seconds
Started Jul 14 07:32:55 PM PDT 24
Finished Jul 14 07:57:57 PM PDT 24
Peak memory 575584 kb
Host smart-39ec825d-1d11-4f38-9fe8-225b8dbc582c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154251091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_
device_slow_rsp.4154251091
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.2168469082
Short name T1355
Test name
Test status
Simulation time 126415170 ps
CPU time 14.63 seconds
Started Jul 14 07:32:55 PM PDT 24
Finished Jul 14 07:33:11 PM PDT 24
Peak memory 575328 kb
Host smart-183144c1-4540-41e8-b86d-62da43d3fdfd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168469082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add
r.2168469082
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_error_random.3011313474
Short name T2844
Test name
Test status
Simulation time 1783161541 ps
CPU time 62.06 seconds
Started Jul 14 07:32:51 PM PDT 24
Finished Jul 14 07:33:53 PM PDT 24
Peak memory 575276 kb
Host smart-df3268e6-77d6-4edd-9e78-1c00e5399681
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011313474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3011313474
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random.696916
Short name T1859
Test name
Test status
Simulation time 1811259062 ps
CPU time 66.87 seconds
Started Jul 14 07:32:55 PM PDT 24
Finished Jul 14 07:34:02 PM PDT 24
Peak memory 575372 kb
Host smart-786afe91-26f3-4237-8fa4-f9e7c641ed8d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.696916
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.3698486678
Short name T2849
Test name
Test status
Simulation time 59108389475 ps
CPU time 677.92 seconds
Started Jul 14 07:32:46 PM PDT 24
Finished Jul 14 07:44:05 PM PDT 24
Peak memory 575452 kb
Host smart-4a0f47b7-e954-408d-8c15-b681b931d187
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698486678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3698486678
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.1477186247
Short name T2842
Test name
Test status
Simulation time 45256043832 ps
CPU time 789.2 seconds
Started Jul 14 07:32:48 PM PDT 24
Finished Jul 14 07:45:58 PM PDT 24
Peak memory 575468 kb
Host smart-ac3b31c1-3d19-4973-b27a-098d7a26fa6b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477186247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1477186247
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.1240572873
Short name T577
Test name
Test status
Simulation time 548326866 ps
CPU time 47.69 seconds
Started Jul 14 07:32:46 PM PDT 24
Finished Jul 14 07:33:34 PM PDT 24
Peak memory 575272 kb
Host smart-4b3722b3-1631-4357-8e20-0dae6bb82148
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240572873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del
ays.1240572873
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_same_source.3845553662
Short name T661
Test name
Test status
Simulation time 513139584 ps
CPU time 17.56 seconds
Started Jul 14 07:32:49 PM PDT 24
Finished Jul 14 07:33:07 PM PDT 24
Peak memory 575304 kb
Host smart-25d24ca9-70ac-49ba-a9af-b7898df4a960
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845553662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3845553662
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke.2425742364
Short name T1731
Test name
Test status
Simulation time 48809569 ps
CPU time 6.9 seconds
Started Jul 14 07:32:41 PM PDT 24
Finished Jul 14 07:32:48 PM PDT 24
Peak memory 575268 kb
Host smart-94f32757-259f-4546-9b82-13041107848a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425742364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2425742364
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.1534602787
Short name T2307
Test name
Test status
Simulation time 8325508720 ps
CPU time 92.79 seconds
Started Jul 14 07:32:43 PM PDT 24
Finished Jul 14 07:34:17 PM PDT 24
Peak memory 574160 kb
Host smart-c335f241-bf89-4094-8009-e1a35e3339cc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534602787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1534602787
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.4024110804
Short name T2551
Test name
Test status
Simulation time 5367867885 ps
CPU time 91.43 seconds
Started Jul 14 07:32:46 PM PDT 24
Finished Jul 14 07:34:18 PM PDT 24
Peak memory 574188 kb
Host smart-77a2e35d-aa5e-400e-a419-253a9c871d69
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024110804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.4024110804
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.2615280695
Short name T1726
Test name
Test status
Simulation time 46689395 ps
CPU time 5.85 seconds
Started Jul 14 07:32:44 PM PDT 24
Finished Jul 14 07:32:50 PM PDT 24
Peak memory 575284 kb
Host smart-d23c82fc-ab12-41b6-8258-f9bb3f9a4f78
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615280695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay
s.2615280695
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all.2992098140
Short name T2539
Test name
Test status
Simulation time 1771450086 ps
CPU time 148.47 seconds
Started Jul 14 07:32:51 PM PDT 24
Finished Jul 14 07:35:19 PM PDT 24
Peak memory 575476 kb
Host smart-59b98c18-e348-4053-974b-649896430fa5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992098140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2992098140
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.3868913521
Short name T1893
Test name
Test status
Simulation time 4351073768 ps
CPU time 173.65 seconds
Started Jul 14 07:32:48 PM PDT 24
Finished Jul 14 07:35:43 PM PDT 24
Peak memory 575616 kb
Host smart-15102d70-2b5d-49b0-8af3-aac5fed1dc97
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868913521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3868913521
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.2088034942
Short name T572
Test name
Test status
Simulation time 1560342751 ps
CPU time 270.65 seconds
Started Jul 14 07:32:50 PM PDT 24
Finished Jul 14 07:37:21 PM PDT 24
Peak memory 575512 kb
Host smart-4afa4831-130f-4d4e-8039-db04ee508858
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088034942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all
_with_rand_reset.2088034942
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.1835736927
Short name T860
Test name
Test status
Simulation time 1058153567 ps
CPU time 234.44 seconds
Started Jul 14 07:32:48 PM PDT 24
Finished Jul 14 07:36:43 PM PDT 24
Peak memory 575480 kb
Host smart-f0007ea3-0bfb-487f-b5f2-34ec5befada1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835736927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al
l_with_reset_error.1835736927
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.1447286914
Short name T2350
Test name
Test status
Simulation time 643441804 ps
CPU time 28.49 seconds
Started Jul 14 07:32:47 PM PDT 24
Finished Jul 14 07:33:16 PM PDT 24
Peak memory 575400 kb
Host smart-8b19ae7f-3374-40c2-9f5d-e94679a0e06a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447286914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1447286914
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/28.chip_tl_errors.4063662852
Short name T2284
Test name
Test status
Simulation time 3774853304 ps
CPU time 186.36 seconds
Started Jul 14 07:32:58 PM PDT 24
Finished Jul 14 07:36:04 PM PDT 24
Peak memory 598948 kb
Host smart-cb340c0d-c87b-4d27-b32c-7d47359c5bf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063662852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.4063662852
Directory /workspace/28.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_access_same_device.2836392657
Short name T1696
Test name
Test status
Simulation time 1731110259 ps
CPU time 69.75 seconds
Started Jul 14 07:33:02 PM PDT 24
Finished Jul 14 07:34:12 PM PDT 24
Peak memory 575316 kb
Host smart-d6f2693a-238d-4e85-ab50-defca38cc9e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836392657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device
.2836392657
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.3737497742
Short name T840
Test name
Test status
Simulation time 45632541582 ps
CPU time 816.07 seconds
Started Jul 14 07:32:56 PM PDT 24
Finished Jul 14 07:46:32 PM PDT 24
Peak memory 575532 kb
Host smart-690ad6ea-8c6e-49b8-9363-42a98131cd61
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737497742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_
device_slow_rsp.3737497742
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.1040685136
Short name T1900
Test name
Test status
Simulation time 140312149 ps
CPU time 8.81 seconds
Started Jul 14 07:33:07 PM PDT 24
Finished Jul 14 07:33:17 PM PDT 24
Peak memory 574036 kb
Host smart-ecb1b57c-9873-4b33-91e9-5ac43af4bd5e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040685136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add
r.1040685136
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_error_random.957034799
Short name T2467
Test name
Test status
Simulation time 120534849 ps
CPU time 11.95 seconds
Started Jul 14 07:33:05 PM PDT 24
Finished Jul 14 07:33:18 PM PDT 24
Peak memory 575284 kb
Host smart-6c9005b3-41c6-4108-aaf0-a20696e5099e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957034799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.957034799
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random.2006677077
Short name T2630
Test name
Test status
Simulation time 407941579 ps
CPU time 34.87 seconds
Started Jul 14 07:33:00 PM PDT 24
Finished Jul 14 07:33:35 PM PDT 24
Peak memory 575304 kb
Host smart-0adae24b-d95d-4591-9d0f-9e7d46c12b0b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006677077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.2006677077
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.3937799321
Short name T658
Test name
Test status
Simulation time 59409198117 ps
CPU time 660.46 seconds
Started Jul 14 07:32:56 PM PDT 24
Finished Jul 14 07:43:57 PM PDT 24
Peak memory 575460 kb
Host smart-b7a361ee-22c3-45fe-bc81-f8949ba7282d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937799321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3937799321
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.408039031
Short name T2481
Test name
Test status
Simulation time 6102791734 ps
CPU time 114.01 seconds
Started Jul 14 07:33:01 PM PDT 24
Finished Jul 14 07:34:56 PM PDT 24
Peak memory 575480 kb
Host smart-0870697b-bd08-42f6-964f-bb160b4ae935
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408039031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.408039031
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.4161910076
Short name T1976
Test name
Test status
Simulation time 285619279 ps
CPU time 28.41 seconds
Started Jul 14 07:32:56 PM PDT 24
Finished Jul 14 07:33:25 PM PDT 24
Peak memory 575340 kb
Host smart-d030b0d8-afe2-4e14-a421-b6ec2410223c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161910076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del
ays.4161910076
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_same_source.2026897548
Short name T2888
Test name
Test status
Simulation time 239725878 ps
CPU time 18.38 seconds
Started Jul 14 07:32:58 PM PDT 24
Finished Jul 14 07:33:17 PM PDT 24
Peak memory 575332 kb
Host smart-37021239-a982-4197-8c03-d78ef889bf7d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026897548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2026897548
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke.1291701227
Short name T1888
Test name
Test status
Simulation time 190945425 ps
CPU time 8.87 seconds
Started Jul 14 07:32:56 PM PDT 24
Finished Jul 14 07:33:06 PM PDT 24
Peak memory 575300 kb
Host smart-b90296c9-1ba5-4776-9547-86ab1d91db63
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291701227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1291701227
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.955291648
Short name T1418
Test name
Test status
Simulation time 7654571081 ps
CPU time 83.79 seconds
Started Jul 14 07:32:56 PM PDT 24
Finished Jul 14 07:34:21 PM PDT 24
Peak memory 575416 kb
Host smart-0c0fd505-e9cf-41a2-9fd9-edc635d09c53
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955291648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.955291648
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.1964274773
Short name T2662
Test name
Test status
Simulation time 5435470773 ps
CPU time 90.92 seconds
Started Jul 14 07:33:01 PM PDT 24
Finished Jul 14 07:34:32 PM PDT 24
Peak memory 574128 kb
Host smart-54053d2f-f7b8-42b4-b2a6-de3abb90c4fb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964274773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1964274773
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1148764972
Short name T2433
Test name
Test status
Simulation time 46179707 ps
CPU time 6.01 seconds
Started Jul 14 07:32:56 PM PDT 24
Finished Jul 14 07:33:03 PM PDT 24
Peak memory 575296 kb
Host smart-d82aaa17-43a1-4b95-b3a7-cbd77f1059c3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148764972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay
s.1148764972
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all.2960100847
Short name T2018
Test name
Test status
Simulation time 3168831256 ps
CPU time 247.08 seconds
Started Jul 14 07:33:02 PM PDT 24
Finished Jul 14 07:37:09 PM PDT 24
Peak memory 575476 kb
Host smart-28e4565d-04fc-48ea-9292-f8962dcf7cd5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960100847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2960100847
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.3654665066
Short name T715
Test name
Test status
Simulation time 7749575746 ps
CPU time 262.31 seconds
Started Jul 14 07:33:08 PM PDT 24
Finished Jul 14 07:37:31 PM PDT 24
Peak memory 575528 kb
Host smart-9d34d323-c9fd-46c7-b0df-ee711ac05029
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654665066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3654665066
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.3600098805
Short name T2612
Test name
Test status
Simulation time 99738832 ps
CPU time 10.61 seconds
Started Jul 14 07:33:01 PM PDT 24
Finished Jul 14 07:33:13 PM PDT 24
Peak memory 574208 kb
Host smart-5b437bf2-0903-4a03-b8e2-38833aace9d5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600098805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all
_with_rand_reset.3600098805
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.1358413095
Short name T1843
Test name
Test status
Simulation time 5876662619 ps
CPU time 212.51 seconds
Started Jul 14 07:33:00 PM PDT 24
Finished Jul 14 07:36:33 PM PDT 24
Peak memory 575604 kb
Host smart-07639eef-e896-4b49-a6fc-86f186f7d96f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358413095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al
l_with_reset_error.1358413095
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.548880578
Short name T1384
Test name
Test status
Simulation time 134426287 ps
CPU time 16.14 seconds
Started Jul 14 07:33:08 PM PDT 24
Finished Jul 14 07:33:25 PM PDT 24
Peak memory 575412 kb
Host smart-250db8f1-7905-4edd-98ef-b1c925c738ac
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548880578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.548880578
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/29.chip_tl_errors.1153414148
Short name T2408
Test name
Test status
Simulation time 4250838104 ps
CPU time 288.41 seconds
Started Jul 14 07:33:02 PM PDT 24
Finished Jul 14 07:37:51 PM PDT 24
Peak memory 603912 kb
Host smart-ab6433ac-1f9e-49d0-811f-76e03f4bac40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153414148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.1153414148
Directory /workspace/29.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_access_same_device.1668217768
Short name T1652
Test name
Test status
Simulation time 871205405 ps
CPU time 69.73 seconds
Started Jul 14 07:33:11 PM PDT 24
Finished Jul 14 07:34:21 PM PDT 24
Peak memory 575364 kb
Host smart-ff13844e-1547-4d01-8a95-2401b60df8dd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668217768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device
.1668217768
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.1218444259
Short name T2132
Test name
Test status
Simulation time 30096612555 ps
CPU time 563.92 seconds
Started Jul 14 07:33:06 PM PDT 24
Finished Jul 14 07:42:30 PM PDT 24
Peak memory 575548 kb
Host smart-30cbb754-ae2f-4d70-955b-1a63ed580ffb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218444259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_
device_slow_rsp.1218444259
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.4105882292
Short name T2832
Test name
Test status
Simulation time 355471111 ps
CPU time 15.87 seconds
Started Jul 14 07:33:06 PM PDT 24
Finished Jul 14 07:33:23 PM PDT 24
Peak memory 575312 kb
Host smart-b89b69d5-c8b2-439c-b3b3-f1712caaeb9a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105882292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add
r.4105882292
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_error_random.3460149675
Short name T1738
Test name
Test status
Simulation time 365891043 ps
CPU time 14.07 seconds
Started Jul 14 07:33:21 PM PDT 24
Finished Jul 14 07:33:36 PM PDT 24
Peak memory 575324 kb
Host smart-e8040b92-a516-4edf-9d89-64eac74941bf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460149675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3460149675
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random.2341381672
Short name T2566
Test name
Test status
Simulation time 2533430335 ps
CPU time 102.56 seconds
Started Jul 14 07:33:08 PM PDT 24
Finished Jul 14 07:34:51 PM PDT 24
Peak memory 575432 kb
Host smart-bfcd402f-f63f-48ca-8b38-4a11105f71b9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341381672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.2341381672
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.1097246435
Short name T605
Test name
Test status
Simulation time 82156541154 ps
CPU time 921.58 seconds
Started Jul 14 07:33:20 PM PDT 24
Finished Jul 14 07:48:42 PM PDT 24
Peak memory 575468 kb
Host smart-90a791c3-1116-4a4e-836c-861d4fd389df
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097246435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1097246435
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.3366718147
Short name T2345
Test name
Test status
Simulation time 62735140693 ps
CPU time 1197.3 seconds
Started Jul 14 07:33:07 PM PDT 24
Finished Jul 14 07:53:05 PM PDT 24
Peak memory 575512 kb
Host smart-67b63243-2234-4359-a0c6-70e31a888cc1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366718147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3366718147
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.427875273
Short name T1472
Test name
Test status
Simulation time 336766371 ps
CPU time 25.99 seconds
Started Jul 14 07:33:21 PM PDT 24
Finished Jul 14 07:33:47 PM PDT 24
Peak memory 575344 kb
Host smart-4198ed38-f6c3-4e37-a275-626b687c4c46
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427875273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_dela
ys.427875273
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_same_source.3094513473
Short name T617
Test name
Test status
Simulation time 1560672906 ps
CPU time 46.41 seconds
Started Jul 14 07:33:10 PM PDT 24
Finished Jul 14 07:33:57 PM PDT 24
Peak memory 575332 kb
Host smart-bacbf05d-8aa8-4146-8374-95efac11dca4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094513473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3094513473
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke.4121873444
Short name T1711
Test name
Test status
Simulation time 234115397 ps
CPU time 9.63 seconds
Started Jul 14 07:33:01 PM PDT 24
Finished Jul 14 07:33:12 PM PDT 24
Peak memory 574044 kb
Host smart-8d19e60a-4d46-49fa-be59-f39ddd9a531d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121873444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.4121873444
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.1733394252
Short name T2808
Test name
Test status
Simulation time 9651129621 ps
CPU time 105.77 seconds
Started Jul 14 07:33:09 PM PDT 24
Finished Jul 14 07:34:55 PM PDT 24
Peak memory 574216 kb
Host smart-f7124d31-aeaf-47f4-81c5-c3b0897a4554
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733394252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1733394252
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.162903811
Short name T548
Test name
Test status
Simulation time 4634242089 ps
CPU time 81.87 seconds
Started Jul 14 07:33:07 PM PDT 24
Finished Jul 14 07:34:29 PM PDT 24
Peak memory 574160 kb
Host smart-39a6a666-9948-46bf-b467-ea7b5a5e5502
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162903811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.162903811
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.568987053
Short name T1687
Test name
Test status
Simulation time 48712633 ps
CPU time 6.39 seconds
Started Jul 14 07:33:11 PM PDT 24
Finished Jul 14 07:33:17 PM PDT 24
Peak memory 574056 kb
Host smart-0495d419-6498-4a94-b027-8956c1c49ef3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568987053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays
.568987053
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all.556809221
Short name T1983
Test name
Test status
Simulation time 845372456 ps
CPU time 65.1 seconds
Started Jul 14 07:33:06 PM PDT 24
Finished Jul 14 07:34:12 PM PDT 24
Peak memory 575472 kb
Host smart-1727c2a3-3eb8-45d1-8458-2e792a46707c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556809221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.556809221
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.1133126849
Short name T1827
Test name
Test status
Simulation time 2804828855 ps
CPU time 230.33 seconds
Started Jul 14 07:33:13 PM PDT 24
Finished Jul 14 07:37:04 PM PDT 24
Peak memory 575584 kb
Host smart-09e5ef44-2afd-474e-b1e6-9ba01c7892d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133126849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1133126849
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.2003783140
Short name T625
Test name
Test status
Simulation time 4982930906 ps
CPU time 205.05 seconds
Started Jul 14 07:33:27 PM PDT 24
Finished Jul 14 07:36:53 PM PDT 24
Peak memory 575576 kb
Host smart-fb10e667-c42a-4a17-82cf-2d9b4aff3479
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003783140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all
_with_rand_reset.2003783140
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.4199457104
Short name T2596
Test name
Test status
Simulation time 1636212661 ps
CPU time 216.2 seconds
Started Jul 14 07:33:12 PM PDT 24
Finished Jul 14 07:36:49 PM PDT 24
Peak memory 575496 kb
Host smart-017205e4-ef4a-488f-bada-b36fa66d9771
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199457104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al
l_with_reset_error.4199457104
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.937789395
Short name T1996
Test name
Test status
Simulation time 426653115 ps
CPU time 20.33 seconds
Started Jul 14 07:33:06 PM PDT 24
Finished Jul 14 07:33:26 PM PDT 24
Peak memory 575304 kb
Host smart-82c35626-1d8a-431d-aadc-45bc0add776a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937789395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.937789395
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.3104047775
Short name T2327
Test name
Test status
Simulation time 64184390770 ps
CPU time 10266.7 seconds
Started Jul 14 07:27:24 PM PDT 24
Finished Jul 14 10:18:33 PM PDT 24
Peak memory 641324 kb
Host smart-8fc8b8ae-b47f-469f-a62b-a413765a870d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104047775 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.chip_csr_aliasing.3104047775
Directory /workspace/3.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.1511243826
Short name T2109
Test name
Test status
Simulation time 11430159318 ps
CPU time 1114.92 seconds
Started Jul 14 07:27:27 PM PDT 24
Finished Jul 14 07:46:03 PM PDT 24
Peak memory 593292 kb
Host smart-0f38081e-4325-4653-8516-ec7c361835ee
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511243826 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.1511243826
Directory /workspace/3.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_rw.2300274144
Short name T407
Test name
Test status
Simulation time 5192453670 ps
CPU time 616.06 seconds
Started Jul 14 07:27:37 PM PDT 24
Finished Jul 14 07:37:54 PM PDT 24
Peak memory 598328 kb
Host smart-6ff9d77a-c1a2-4661-8c92-03e3dbb36919
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300274144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.2300274144
Directory /workspace/3.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.2360370680
Short name T2590
Test name
Test status
Simulation time 17445524516 ps
CPU time 2141.65 seconds
Started Jul 14 07:27:27 PM PDT 24
Finished Jul 14 08:03:10 PM PDT 24
Peak memory 593172 kb
Host smart-ad10a31b-737c-4005-899a-1369c5d979c7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360370680 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.2360370680
Directory /workspace/3.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.chip_tl_errors.3441922723
Short name T2552
Test name
Test status
Simulation time 3681500672 ps
CPU time 237.4 seconds
Started Jul 14 07:27:23 PM PDT 24
Finished Jul 14 07:31:22 PM PDT 24
Peak memory 598856 kb
Host smart-6b325d1a-5e82-49bf-bacb-24a292f32de1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441922723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.3441922723
Directory /workspace/3.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_access_same_device.1839280338
Short name T1395
Test name
Test status
Simulation time 2416750040 ps
CPU time 124.1 seconds
Started Jul 14 07:27:29 PM PDT 24
Finished Jul 14 07:29:34 PM PDT 24
Peak memory 575444 kb
Host smart-4cee052f-ca12-40aa-a8a8-33deac354d4d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839280338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.
1839280338
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3506250896
Short name T2205
Test name
Test status
Simulation time 130713074345 ps
CPU time 2484.53 seconds
Started Jul 14 07:27:30 PM PDT 24
Finished Jul 14 08:08:56 PM PDT 24
Peak memory 575616 kb
Host smart-b37d7bbb-a76c-49cd-afd9-1f67a1166607
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506250896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d
evice_slow_rsp.3506250896
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.9593296
Short name T2155
Test name
Test status
Simulation time 119895485 ps
CPU time 14.42 seconds
Started Jul 14 07:27:31 PM PDT 24
Finished Jul 14 07:27:46 PM PDT 24
Peak memory 575272 kb
Host smart-e7facf71-db94-4343-83df-6a662d4d763e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9593296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.9593296
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_error_random.154457407
Short name T2409
Test name
Test status
Simulation time 1756820378 ps
CPU time 59.96 seconds
Started Jul 14 07:27:28 PM PDT 24
Finished Jul 14 07:28:29 PM PDT 24
Peak memory 575268 kb
Host smart-09d38625-1abb-4548-9e17-0929d911d870
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154457407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.154457407
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random.1340364905
Short name T2384
Test name
Test status
Simulation time 294996669 ps
CPU time 26.84 seconds
Started Jul 14 07:27:24 PM PDT 24
Finished Jul 14 07:27:52 PM PDT 24
Peak memory 575408 kb
Host smart-4e78be51-a252-4fe8-81c4-91ea9ce77f39
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340364905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.1340364905
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.2418213089
Short name T2880
Test name
Test status
Simulation time 91713923738 ps
CPU time 1053.04 seconds
Started Jul 14 07:27:31 PM PDT 24
Finished Jul 14 07:45:05 PM PDT 24
Peak memory 575484 kb
Host smart-4c0e0682-c34b-4741-9711-6a0519354626
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418213089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2418213089
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.2673875770
Short name T1686
Test name
Test status
Simulation time 50725557476 ps
CPU time 942.29 seconds
Started Jul 14 07:27:30 PM PDT 24
Finished Jul 14 07:43:13 PM PDT 24
Peak memory 575524 kb
Host smart-931ead99-2018-4cfb-b7d3-253a120e8a37
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673875770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.2673875770
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.888838529
Short name T2434
Test name
Test status
Simulation time 182617550 ps
CPU time 17.14 seconds
Started Jul 14 07:27:25 PM PDT 24
Finished Jul 14 07:27:43 PM PDT 24
Peak memory 575308 kb
Host smart-2e4dcd6b-46b3-451c-b908-d2d1a62e4762
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888838529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delay
s.888838529
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_same_source.3702987504
Short name T1915
Test name
Test status
Simulation time 310694131 ps
CPU time 22.35 seconds
Started Jul 14 07:27:28 PM PDT 24
Finished Jul 14 07:27:51 PM PDT 24
Peak memory 575380 kb
Host smart-68c9d0a1-1398-4337-a216-215b76414adc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702987504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3702987504
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke.439381786
Short name T2843
Test name
Test status
Simulation time 224130274 ps
CPU time 10.43 seconds
Started Jul 14 07:27:27 PM PDT 24
Finished Jul 14 07:27:38 PM PDT 24
Peak memory 575304 kb
Host smart-a501a2c3-3d13-4de3-966e-5bf6edf10b35
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439381786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.439381786
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.3728366659
Short name T1438
Test name
Test status
Simulation time 9138866067 ps
CPU time 100.52 seconds
Started Jul 14 07:27:25 PM PDT 24
Finished Jul 14 07:29:06 PM PDT 24
Peak memory 574172 kb
Host smart-85b4b54e-4c32-44e9-a9fd-501d8791e904
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728366659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3728366659
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2876773668
Short name T1641
Test name
Test status
Simulation time 5398612065 ps
CPU time 102.72 seconds
Started Jul 14 07:27:24 PM PDT 24
Finished Jul 14 07:29:07 PM PDT 24
Peak memory 575444 kb
Host smart-7f5aa5c0-8e6a-464a-9904-c5efcd270d7d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876773668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2876773668
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.2310590100
Short name T2188
Test name
Test status
Simulation time 45407175 ps
CPU time 6.01 seconds
Started Jul 14 07:27:23 PM PDT 24
Finished Jul 14 07:27:30 PM PDT 24
Peak memory 574044 kb
Host smart-9b909d91-b7fb-4507-b819-2d2b3a6a41f6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310590100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays
.2310590100
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all.243684798
Short name T1944
Test name
Test status
Simulation time 5198508407 ps
CPU time 444.63 seconds
Started Jul 14 07:27:34 PM PDT 24
Finished Jul 14 07:34:59 PM PDT 24
Peak memory 575600 kb
Host smart-cda95e8e-fa67-4258-a737-ef91fbd92d23
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243684798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.243684798
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.4157127927
Short name T1599
Test name
Test status
Simulation time 1697252143 ps
CPU time 131.15 seconds
Started Jul 14 07:27:35 PM PDT 24
Finished Jul 14 07:29:47 PM PDT 24
Peak memory 575416 kb
Host smart-31901c40-fed4-4ac5-bf5f-19e0315ec018
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157127927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.4157127927
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.4171485615
Short name T866
Test name
Test status
Simulation time 10418567137 ps
CPU time 658.73 seconds
Started Jul 14 07:27:34 PM PDT 24
Finished Jul 14 07:38:34 PM PDT 24
Peak memory 575608 kb
Host smart-86e89a8c-3801-4882-9688-22638d359f8f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171485615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_
with_rand_reset.4171485615
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.2699632099
Short name T862
Test name
Test status
Simulation time 4923535473 ps
CPU time 199.49 seconds
Started Jul 14 07:27:35 PM PDT 24
Finished Jul 14 07:30:55 PM PDT 24
Peak memory 575616 kb
Host smart-30419b58-b8a4-4a8c-bd4e-02c4c177d29a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699632099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all
_with_reset_error.2699632099
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.1447412293
Short name T1465
Test name
Test status
Simulation time 169272227 ps
CPU time 21.22 seconds
Started Jul 14 07:27:29 PM PDT 24
Finished Jul 14 07:27:50 PM PDT 24
Peak memory 575428 kb
Host smart-e1ce08d3-dec7-4040-9553-eec7273cfff3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447412293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1447412293
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_access_same_device.2451138869
Short name T2166
Test name
Test status
Simulation time 495372674 ps
CPU time 19.27 seconds
Started Jul 14 07:33:11 PM PDT 24
Finished Jul 14 07:33:31 PM PDT 24
Peak memory 575276 kb
Host smart-6c75cc92-a903-4105-b42f-4c3f089b3be7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451138869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device
.2451138869
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2331376727
Short name T2267
Test name
Test status
Simulation time 128264028320 ps
CPU time 2259.06 seconds
Started Jul 14 07:33:12 PM PDT 24
Finished Jul 14 08:10:52 PM PDT 24
Peak memory 575524 kb
Host smart-394a00f3-9d82-4efb-a45b-8592d783f93b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331376727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_
device_slow_rsp.2331376727
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.2088332972
Short name T2051
Test name
Test status
Simulation time 60530630 ps
CPU time 9.51 seconds
Started Jul 14 07:33:21 PM PDT 24
Finished Jul 14 07:33:31 PM PDT 24
Peak memory 575288 kb
Host smart-6474de8d-bbd0-467e-90e0-62ea7c4876fa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088332972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add
r.2088332972
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_error_random.4138535289
Short name T1952
Test name
Test status
Simulation time 1267083855 ps
CPU time 41.75 seconds
Started Jul 14 07:33:28 PM PDT 24
Finished Jul 14 07:34:10 PM PDT 24
Peak memory 575280 kb
Host smart-65b17c0d-091c-41a7-a89c-046aa8e5f562
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138535289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.4138535289
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random.3136907724
Short name T607
Test name
Test status
Simulation time 2203883342 ps
CPU time 89.52 seconds
Started Jul 14 07:33:13 PM PDT 24
Finished Jul 14 07:34:43 PM PDT 24
Peak memory 575388 kb
Host smart-1b558a0a-25fb-4f86-84f7-76fa3011da10
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136907724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.3136907724
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.1073658695
Short name T1774
Test name
Test status
Simulation time 72082397962 ps
CPU time 750.99 seconds
Started Jul 14 07:33:28 PM PDT 24
Finished Jul 14 07:45:59 PM PDT 24
Peak memory 575492 kb
Host smart-802f7631-287c-4e69-b45d-3727ce73c409
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073658695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1073658695
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.2154494773
Short name T2429
Test name
Test status
Simulation time 3455067441 ps
CPU time 62.29 seconds
Started Jul 14 07:33:12 PM PDT 24
Finished Jul 14 07:34:14 PM PDT 24
Peak memory 575312 kb
Host smart-c63bfcf4-52c0-450f-97c2-83607c6093c3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154494773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.2154494773
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.3668005184
Short name T2395
Test name
Test status
Simulation time 299077290 ps
CPU time 25.46 seconds
Started Jul 14 07:33:23 PM PDT 24
Finished Jul 14 07:33:49 PM PDT 24
Peak memory 575368 kb
Host smart-02f52bf7-1844-45ad-872d-20df92a0ea5f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668005184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del
ays.3668005184
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_same_source.1181054990
Short name T2789
Test name
Test status
Simulation time 2548451008 ps
CPU time 85.5 seconds
Started Jul 14 07:33:13 PM PDT 24
Finished Jul 14 07:34:38 PM PDT 24
Peak memory 575400 kb
Host smart-10601b71-58a0-436e-abe3-12859a40674b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181054990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1181054990
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke.1245098653
Short name T2124
Test name
Test status
Simulation time 227631346 ps
CPU time 9.15 seconds
Started Jul 14 07:33:27 PM PDT 24
Finished Jul 14 07:33:37 PM PDT 24
Peak memory 575316 kb
Host smart-32af468a-da9b-4988-94a7-ba9d139b705b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245098653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1245098653
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.3797684793
Short name T2721
Test name
Test status
Simulation time 9808480351 ps
CPU time 105.5 seconds
Started Jul 14 07:33:14 PM PDT 24
Finished Jul 14 07:35:00 PM PDT 24
Peak memory 575384 kb
Host smart-5905d881-0759-4dcc-9320-872953e2cbe0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797684793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3797684793
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.2313370014
Short name T2455
Test name
Test status
Simulation time 5512474924 ps
CPU time 89.18 seconds
Started Jul 14 07:33:23 PM PDT 24
Finished Jul 14 07:34:52 PM PDT 24
Peak memory 575428 kb
Host smart-3d891d9c-887f-4cf8-a5e1-cbc65acc4dd1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313370014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2313370014
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2940509377
Short name T2860
Test name
Test status
Simulation time 51693052 ps
CPU time 6.73 seconds
Started Jul 14 07:33:21 PM PDT 24
Finished Jul 14 07:33:28 PM PDT 24
Peak memory 574028 kb
Host smart-12c4b4b7-f287-4d5f-b8d1-71e637b48518
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940509377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay
s.2940509377
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all.3656056259
Short name T1677
Test name
Test status
Simulation time 7325503813 ps
CPU time 297.99 seconds
Started Jul 14 07:33:20 PM PDT 24
Finished Jul 14 07:38:18 PM PDT 24
Peak memory 575580 kb
Host smart-c9e3e11b-83ac-4643-aef7-cb61e778658e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656056259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3656056259
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.2405722259
Short name T1964
Test name
Test status
Simulation time 638952381 ps
CPU time 57.4 seconds
Started Jul 14 07:33:33 PM PDT 24
Finished Jul 14 07:34:31 PM PDT 24
Peak memory 575496 kb
Host smart-43f450cd-c267-474f-a760-5cfd3396809e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405722259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all
_with_rand_reset.2405722259
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.4101529349
Short name T2210
Test name
Test status
Simulation time 63198948 ps
CPU time 10.17 seconds
Started Jul 14 07:33:21 PM PDT 24
Finished Jul 14 07:33:32 PM PDT 24
Peak memory 575432 kb
Host smart-9eb8eb4c-da23-422c-bf1a-73b363d1ff74
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101529349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al
l_with_reset_error.4101529349
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.4144236163
Short name T2265
Test name
Test status
Simulation time 59233797 ps
CPU time 9.03 seconds
Started Jul 14 07:33:31 PM PDT 24
Finished Jul 14 07:33:41 PM PDT 24
Peak memory 575432 kb
Host smart-71a42001-4509-47ab-be3c-64dd13cae62a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144236163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.4144236163
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_access_same_device.1200048299
Short name T2708
Test name
Test status
Simulation time 1205453742 ps
CPU time 48.41 seconds
Started Jul 14 07:33:22 PM PDT 24
Finished Jul 14 07:34:11 PM PDT 24
Peak memory 575332 kb
Host smart-eb58a881-d552-4222-b908-fff8bddd2b9d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200048299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device
.1200048299
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.2920835590
Short name T1648
Test name
Test status
Simulation time 14251089699 ps
CPU time 241.49 seconds
Started Jul 14 07:33:22 PM PDT 24
Finished Jul 14 07:37:24 PM PDT 24
Peak memory 575500 kb
Host smart-1fcaadfb-9eea-426e-9ace-9b77df84a314
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920835590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_
device_slow_rsp.2920835590
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.2703073332
Short name T1766
Test name
Test status
Simulation time 147100608 ps
CPU time 19.8 seconds
Started Jul 14 07:33:25 PM PDT 24
Finished Jul 14 07:33:46 PM PDT 24
Peak memory 575328 kb
Host smart-ba0bf738-d433-4a9d-99e5-80cb69dc84f7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703073332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add
r.2703073332
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_error_random.4107984189
Short name T1341
Test name
Test status
Simulation time 369255392 ps
CPU time 15.89 seconds
Started Jul 14 07:33:27 PM PDT 24
Finished Jul 14 07:33:44 PM PDT 24
Peak memory 575312 kb
Host smart-1e5d4abf-8a5a-4ab5-9445-a8acdc65f61d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107984189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.4107984189
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random.4113404080
Short name T1897
Test name
Test status
Simulation time 1171626230 ps
CPU time 42.57 seconds
Started Jul 14 07:33:20 PM PDT 24
Finished Jul 14 07:34:03 PM PDT 24
Peak memory 575384 kb
Host smart-641b2158-7168-451f-899b-cf05902d3579
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113404080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.4113404080
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.505034439
Short name T540
Test name
Test status
Simulation time 32407427761 ps
CPU time 360.37 seconds
Started Jul 14 07:33:21 PM PDT 24
Finished Jul 14 07:39:22 PM PDT 24
Peak memory 575492 kb
Host smart-bd27d7b4-49cb-4149-9cc9-c327afb2a701
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505034439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.505034439
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.1671319111
Short name T629
Test name
Test status
Simulation time 3663064376 ps
CPU time 62.13 seconds
Started Jul 14 07:33:22 PM PDT 24
Finished Jul 14 07:34:25 PM PDT 24
Peak memory 574148 kb
Host smart-c6846ef2-cf1c-416a-bff5-b59b6bab7746
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671319111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1671319111
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.2187110128
Short name T2190
Test name
Test status
Simulation time 142320331 ps
CPU time 14.72 seconds
Started Jul 14 07:33:21 PM PDT 24
Finished Jul 14 07:33:37 PM PDT 24
Peak memory 575296 kb
Host smart-66a392b2-dacd-4c5f-b92e-ea481506b8ca
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187110128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del
ays.2187110128
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_same_source.3358428383
Short name T575
Test name
Test status
Simulation time 343850460 ps
CPU time 27.3 seconds
Started Jul 14 07:33:21 PM PDT 24
Finished Jul 14 07:33:49 PM PDT 24
Peak memory 575328 kb
Host smart-e3a6d07b-a019-4490-bf98-01f943809abd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358428383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3358428383
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke.200556655
Short name T2115
Test name
Test status
Simulation time 214577471 ps
CPU time 9.31 seconds
Started Jul 14 07:33:20 PM PDT 24
Finished Jul 14 07:33:30 PM PDT 24
Peak memory 574004 kb
Host smart-f00a6687-99d8-4e2f-94b5-7e3bc425b34a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200556655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.200556655
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.167573265
Short name T1337
Test name
Test status
Simulation time 7323387065 ps
CPU time 77.83 seconds
Started Jul 14 07:33:20 PM PDT 24
Finished Jul 14 07:34:39 PM PDT 24
Peak memory 574172 kb
Host smart-5d78b5d2-fcd1-4406-8a9f-b3ecd998c82d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167573265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.167573265
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.1747773508
Short name T1376
Test name
Test status
Simulation time 5172420089 ps
CPU time 91.23 seconds
Started Jul 14 07:33:20 PM PDT 24
Finished Jul 14 07:34:51 PM PDT 24
Peak memory 575460 kb
Host smart-acd1a142-dca8-4dbb-a56f-cbc74eb99fa9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747773508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1747773508
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.2246543983
Short name T1330
Test name
Test status
Simulation time 54293298 ps
CPU time 6.48 seconds
Started Jul 14 07:33:32 PM PDT 24
Finished Jul 14 07:33:39 PM PDT 24
Peak memory 574048 kb
Host smart-ba90e07e-de53-4a06-bf94-5d86499dd0af
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246543983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay
s.2246543983
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all.294805329
Short name T2632
Test name
Test status
Simulation time 1330089102 ps
CPU time 109.86 seconds
Started Jul 14 07:33:25 PM PDT 24
Finished Jul 14 07:35:16 PM PDT 24
Peak memory 575388 kb
Host smart-712f82d3-c7bd-4a42-b092-c0acbf466cc1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294805329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.294805329
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.781839730
Short name T2371
Test name
Test status
Simulation time 4224783174 ps
CPU time 299.02 seconds
Started Jul 14 07:33:27 PM PDT 24
Finished Jul 14 07:38:27 PM PDT 24
Peak memory 575536 kb
Host smart-2e1717fd-73e2-4f38-8ede-940ffdcbe3e0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781839730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.781839730
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1286156361
Short name T1485
Test name
Test status
Simulation time 37567126 ps
CPU time 48.85 seconds
Started Jul 14 07:33:27 PM PDT 24
Finished Jul 14 07:34:16 PM PDT 24
Peak memory 574204 kb
Host smart-4e55afc3-265d-4959-ba5b-0981300697c1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286156361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all
_with_rand_reset.1286156361
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.1014336450
Short name T2073
Test name
Test status
Simulation time 436483624 ps
CPU time 21.47 seconds
Started Jul 14 07:33:28 PM PDT 24
Finished Jul 14 07:33:50 PM PDT 24
Peak memory 575404 kb
Host smart-65ada0a9-091a-4382-918e-943e0b40490b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014336450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1014336450
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_access_same_device.2750615031
Short name T2811
Test name
Test status
Simulation time 1636110945 ps
CPU time 57.24 seconds
Started Jul 14 07:33:33 PM PDT 24
Finished Jul 14 07:34:31 PM PDT 24
Peak memory 575352 kb
Host smart-92349277-3912-4e1a-a131-b6ac5b0ff4b4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750615031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device
.2750615031
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.3433779373
Short name T2411
Test name
Test status
Simulation time 58531955119 ps
CPU time 1045.29 seconds
Started Jul 14 07:33:37 PM PDT 24
Finished Jul 14 07:51:03 PM PDT 24
Peak memory 575480 kb
Host smart-1a47919e-384c-49e6-aa8e-c3038b186316
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433779373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_
device_slow_rsp.3433779373
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.597155181
Short name T1546
Test name
Test status
Simulation time 64790464 ps
CPU time 10.38 seconds
Started Jul 14 07:33:32 PM PDT 24
Finished Jul 14 07:33:43 PM PDT 24
Peak memory 575324 kb
Host smart-dee652ed-a0b1-4a49-abcf-248e9c6dc422
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597155181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr
.597155181
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_error_random.1387869041
Short name T1667
Test name
Test status
Simulation time 688027062 ps
CPU time 24.94 seconds
Started Jul 14 07:33:37 PM PDT 24
Finished Jul 14 07:34:02 PM PDT 24
Peak memory 575272 kb
Host smart-ebcaba03-4304-4299-9744-a4661d633f7b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387869041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1387869041
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random.1083754126
Short name T2246
Test name
Test status
Simulation time 101045069 ps
CPU time 11.9 seconds
Started Jul 14 07:33:27 PM PDT 24
Finished Jul 14 07:33:39 PM PDT 24
Peak memory 575376 kb
Host smart-584b383c-e38b-44a7-b0a4-98489dadfa3b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083754126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.1083754126
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.1608085014
Short name T1814
Test name
Test status
Simulation time 71425858904 ps
CPU time 812.08 seconds
Started Jul 14 07:33:33 PM PDT 24
Finished Jul 14 07:47:06 PM PDT 24
Peak memory 575524 kb
Host smart-c1549582-afe1-489e-a757-1d6212dbca0c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608085014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1608085014
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.1114826054
Short name T1823
Test name
Test status
Simulation time 47091642118 ps
CPU time 845.57 seconds
Started Jul 14 07:33:33 PM PDT 24
Finished Jul 14 07:47:39 PM PDT 24
Peak memory 575532 kb
Host smart-4576d1bf-f374-4f1d-bad8-49415378fe20
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114826054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1114826054
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.919593029
Short name T2795
Test name
Test status
Simulation time 373478148 ps
CPU time 33.69 seconds
Started Jul 14 07:33:34 PM PDT 24
Finished Jul 14 07:34:08 PM PDT 24
Peak memory 575344 kb
Host smart-2cc559c5-b3fa-433a-b4d1-8845dbddf9a7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919593029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_dela
ys.919593029
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_same_source.2379615488
Short name T1658
Test name
Test status
Simulation time 1019566882 ps
CPU time 32.84 seconds
Started Jul 14 07:33:33 PM PDT 24
Finished Jul 14 07:34:06 PM PDT 24
Peak memory 575340 kb
Host smart-702242e1-65e4-4cb0-9cbb-d25629a49ad1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379615488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2379615488
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke.1806003745
Short name T1326
Test name
Test status
Simulation time 213498972 ps
CPU time 9.29 seconds
Started Jul 14 07:33:27 PM PDT 24
Finished Jul 14 07:33:37 PM PDT 24
Peak memory 574000 kb
Host smart-fc0baaf0-d451-4fad-9dba-3baade675d1a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806003745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1806003745
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.2134796949
Short name T2100
Test name
Test status
Simulation time 8310036720 ps
CPU time 93.47 seconds
Started Jul 14 07:33:33 PM PDT 24
Finished Jul 14 07:35:07 PM PDT 24
Peak memory 575472 kb
Host smart-9657d2fb-0e4a-411d-a735-a09b269b9912
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134796949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2134796949
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.4273410549
Short name T2697
Test name
Test status
Simulation time 4851691192 ps
CPU time 85.86 seconds
Started Jul 14 07:33:28 PM PDT 24
Finished Jul 14 07:34:55 PM PDT 24
Peak memory 574152 kb
Host smart-0a573b35-5dbf-4df1-bfb0-adf788076f2e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273410549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.4273410549
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.127858629
Short name T1716
Test name
Test status
Simulation time 39779745 ps
CPU time 6.11 seconds
Started Jul 14 07:33:26 PM PDT 24
Finished Jul 14 07:33:33 PM PDT 24
Peak memory 573996 kb
Host smart-b95cf448-e620-4962-bc5e-e2099c1f423e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127858629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays
.127858629
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all.2209120120
Short name T2440
Test name
Test status
Simulation time 1074326454 ps
CPU time 84.93 seconds
Started Jul 14 07:33:40 PM PDT 24
Finished Jul 14 07:35:06 PM PDT 24
Peak memory 575488 kb
Host smart-f42ba68b-fdeb-4411-901c-6a0c179aa8ed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209120120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2209120120
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.4063214695
Short name T1470
Test name
Test status
Simulation time 7486015374 ps
CPU time 259.16 seconds
Started Jul 14 07:33:41 PM PDT 24
Finished Jul 14 07:38:01 PM PDT 24
Peak memory 575580 kb
Host smart-36cea37b-aa3d-4190-8717-73447537c542
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063214695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.4063214695
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.114288058
Short name T1772
Test name
Test status
Simulation time 507122190 ps
CPU time 203.46 seconds
Started Jul 14 07:33:40 PM PDT 24
Finished Jul 14 07:37:04 PM PDT 24
Peak memory 575488 kb
Host smart-76cdf890-377d-41c0-a0ee-84b7724828f5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114288058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_
with_rand_reset.114288058
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.781472277
Short name T1622
Test name
Test status
Simulation time 59044782 ps
CPU time 38.45 seconds
Started Jul 14 07:33:41 PM PDT 24
Finished Jul 14 07:34:20 PM PDT 24
Peak memory 575488 kb
Host smart-5aff43ad-1f38-4442-93cc-c13f526f1d0d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781472277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all
_with_reset_error.781472277
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.2504770454
Short name T1526
Test name
Test status
Simulation time 341947096 ps
CPU time 16.89 seconds
Started Jul 14 07:33:33 PM PDT 24
Finished Jul 14 07:33:50 PM PDT 24
Peak memory 575396 kb
Host smart-dc73f3db-9789-42a4-ad92-aa07fc2329bb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504770454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2504770454
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_access_same_device.4251027871
Short name T2834
Test name
Test status
Simulation time 2567433741 ps
CPU time 96.76 seconds
Started Jul 14 07:33:45 PM PDT 24
Finished Jul 14 07:35:22 PM PDT 24
Peak memory 575388 kb
Host smart-e3b286cb-165c-4689-8ad0-dc9e01fb1dc7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251027871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device
.4251027871
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1621813067
Short name T2758
Test name
Test status
Simulation time 52141418072 ps
CPU time 1042.6 seconds
Started Jul 14 07:33:44 PM PDT 24
Finished Jul 14 07:51:07 PM PDT 24
Peak memory 575744 kb
Host smart-de7540d6-ab73-4448-8236-937d702d5948
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621813067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_
device_slow_rsp.1621813067
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.3046909403
Short name T1415
Test name
Test status
Simulation time 396437913 ps
CPU time 16.96 seconds
Started Jul 14 07:33:47 PM PDT 24
Finished Jul 14 07:34:05 PM PDT 24
Peak memory 575332 kb
Host smart-971d1cb2-09bc-43c3-ac7d-88dfe29be54d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046909403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add
r.3046909403
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_error_random.177323877
Short name T674
Test name
Test status
Simulation time 523383714 ps
CPU time 48.18 seconds
Started Jul 14 07:33:46 PM PDT 24
Finished Jul 14 07:34:35 PM PDT 24
Peak memory 575344 kb
Host smart-994ea691-6688-4168-b42e-abe9db2081a0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177323877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.177323877
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random.2911435635
Short name T2577
Test name
Test status
Simulation time 2231531837 ps
CPU time 81.41 seconds
Started Jul 14 07:33:42 PM PDT 24
Finished Jul 14 07:35:03 PM PDT 24
Peak memory 575404 kb
Host smart-86590d74-243e-45b5-aea7-106e85735024
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911435635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.2911435635
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.3951758778
Short name T1683
Test name
Test status
Simulation time 70345257299 ps
CPU time 813.06 seconds
Started Jul 14 07:33:40 PM PDT 24
Finished Jul 14 07:47:13 PM PDT 24
Peak memory 575448 kb
Host smart-1ff05fba-3337-4ce6-a806-1a72fb410092
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951758778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3951758778
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.1189040331
Short name T2816
Test name
Test status
Simulation time 31537326454 ps
CPU time 530.77 seconds
Started Jul 14 07:33:46 PM PDT 24
Finished Jul 14 07:42:37 PM PDT 24
Peak memory 575536 kb
Host smart-0c98957f-45dc-4dbc-a4d8-e48790498b7f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189040331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.1189040331
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.1754557569
Short name T1862
Test name
Test status
Simulation time 90911826 ps
CPU time 11.91 seconds
Started Jul 14 07:33:39 PM PDT 24
Finished Jul 14 07:33:51 PM PDT 24
Peak memory 575308 kb
Host smart-6fe31c19-0ccd-4c78-9ec5-231025344c63
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754557569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del
ays.1754557569
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_same_source.596906459
Short name T2289
Test name
Test status
Simulation time 472530748 ps
CPU time 33.82 seconds
Started Jul 14 07:33:45 PM PDT 24
Finished Jul 14 07:34:20 PM PDT 24
Peak memory 575240 kb
Host smart-df8509c5-1c8c-4361-9d83-e729f77eaa6c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596906459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.596906459
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke.1438343939
Short name T1432
Test name
Test status
Simulation time 38959875 ps
CPU time 5.74 seconds
Started Jul 14 07:33:41 PM PDT 24
Finished Jul 14 07:33:47 PM PDT 24
Peak memory 574044 kb
Host smart-9a0a51a6-7c54-4fc1-ba8d-c416d8cd1667
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438343939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1438343939
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.3592447471
Short name T2185
Test name
Test status
Simulation time 6136609278 ps
CPU time 72.32 seconds
Started Jul 14 07:33:43 PM PDT 24
Finished Jul 14 07:34:56 PM PDT 24
Peak memory 575444 kb
Host smart-6072c1e5-ab79-4508-8eef-536c8105f7d2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592447471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3592447471
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.3791098648
Short name T2610
Test name
Test status
Simulation time 4888843676 ps
CPU time 87.26 seconds
Started Jul 14 07:33:41 PM PDT 24
Finished Jul 14 07:35:08 PM PDT 24
Peak memory 575408 kb
Host smart-3d2d49cb-a6a9-47f9-86f6-3ec8ab65bf36
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791098648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3791098648
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.1334725230
Short name T2288
Test name
Test status
Simulation time 41877699 ps
CPU time 6.49 seconds
Started Jul 14 07:33:41 PM PDT 24
Finished Jul 14 07:33:48 PM PDT 24
Peak memory 575232 kb
Host smart-7e9c1e19-ac6c-4c8b-916d-4d5cc271ee15
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334725230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay
s.1334725230
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all.671826049
Short name T2255
Test name
Test status
Simulation time 5167939655 ps
CPU time 193.35 seconds
Started Jul 14 07:33:53 PM PDT 24
Finished Jul 14 07:37:06 PM PDT 24
Peak memory 575536 kb
Host smart-e78c6b8d-3759-41b0-87e8-2e78f68709a4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671826049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.671826049
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.2564166303
Short name T2536
Test name
Test status
Simulation time 4629738253 ps
CPU time 158.22 seconds
Started Jul 14 07:33:54 PM PDT 24
Finished Jul 14 07:36:32 PM PDT 24
Peak memory 575612 kb
Host smart-28bf2b33-ae4c-4c0f-a01b-c5664040bc5f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564166303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2564166303
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.1267473292
Short name T1973
Test name
Test status
Simulation time 344627023 ps
CPU time 149.27 seconds
Started Jul 14 07:33:46 PM PDT 24
Finished Jul 14 07:36:16 PM PDT 24
Peak memory 575452 kb
Host smart-f12f2fb7-9229-4dcf-ae5a-9c223c8f038f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267473292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all
_with_rand_reset.1267473292
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.260709875
Short name T861
Test name
Test status
Simulation time 4605690231 ps
CPU time 301.14 seconds
Started Jul 14 07:33:47 PM PDT 24
Finished Jul 14 07:38:49 PM PDT 24
Peak memory 575576 kb
Host smart-3b6b3573-7187-44c2-9030-92f73cbedb50
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260709875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all
_with_reset_error.260709875
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.2007607479
Short name T2547
Test name
Test status
Simulation time 56291503 ps
CPU time 8.64 seconds
Started Jul 14 07:33:46 PM PDT 24
Finished Jul 14 07:33:55 PM PDT 24
Peak memory 575400 kb
Host smart-161b251a-153c-447b-8d52-58b7153934f1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007607479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2007607479
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_access_same_device.1188667140
Short name T838
Test name
Test status
Simulation time 961033481 ps
CPU time 68.86 seconds
Started Jul 14 07:33:53 PM PDT 24
Finished Jul 14 07:35:03 PM PDT 24
Peak memory 575416 kb
Host smart-fa81fbb4-a920-40ff-a8ad-5e2db8832b6d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188667140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device
.1188667140
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.2078281051
Short name T1505
Test name
Test status
Simulation time 68747480202 ps
CPU time 1360.54 seconds
Started Jul 14 07:34:01 PM PDT 24
Finished Jul 14 07:56:42 PM PDT 24
Peak memory 575528 kb
Host smart-4ff07b72-9e4e-40bd-92e8-dfcbfd4a0fb0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078281051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_
device_slow_rsp.2078281051
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.3320920791
Short name T2673
Test name
Test status
Simulation time 195804251 ps
CPU time 22.13 seconds
Started Jul 14 07:34:02 PM PDT 24
Finished Jul 14 07:34:24 PM PDT 24
Peak memory 575060 kb
Host smart-14c427bd-20aa-4332-9415-adb7ddc4f354
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320920791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add
r.3320920791
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_error_random.1971208724
Short name T2283
Test name
Test status
Simulation time 1822545664 ps
CPU time 69.78 seconds
Started Jul 14 07:34:02 PM PDT 24
Finished Jul 14 07:35:12 PM PDT 24
Peak memory 575260 kb
Host smart-cefb7324-d78d-4de5-b53d-b792e1bbb72f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971208724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1971208724
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random.2902452013
Short name T1364
Test name
Test status
Simulation time 1351946510 ps
CPU time 44.95 seconds
Started Jul 14 07:33:55 PM PDT 24
Finished Jul 14 07:34:40 PM PDT 24
Peak memory 575360 kb
Host smart-6862d06e-7c54-4cf1-a2b2-18b06897af17
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902452013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.2902452013
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.2279755926
Short name T1396
Test name
Test status
Simulation time 73613237241 ps
CPU time 909.48 seconds
Started Jul 14 07:33:52 PM PDT 24
Finished Jul 14 07:49:03 PM PDT 24
Peak memory 575456 kb
Host smart-301af7d9-1cb8-4286-9b1c-e2dd601236e4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279755926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2279755926
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.2522309527
Short name T2520
Test name
Test status
Simulation time 44761446100 ps
CPU time 851.75 seconds
Started Jul 14 07:33:52 PM PDT 24
Finished Jul 14 07:48:05 PM PDT 24
Peak memory 575440 kb
Host smart-27f90a54-c34c-40dd-8118-9341592bafc1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522309527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2522309527
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.2647189128
Short name T2788
Test name
Test status
Simulation time 96912153 ps
CPU time 11.54 seconds
Started Jul 14 07:33:53 PM PDT 24
Finished Jul 14 07:34:05 PM PDT 24
Peak memory 575288 kb
Host smart-dcbb729b-36fb-451c-9b68-b9590f0112ce
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647189128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del
ays.2647189128
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_same_source.2867941721
Short name T2139
Test name
Test status
Simulation time 446114355 ps
CPU time 14.55 seconds
Started Jul 14 07:34:06 PM PDT 24
Finished Jul 14 07:34:21 PM PDT 24
Peak memory 575296 kb
Host smart-ceed5e6c-177d-4c2e-a8f7-13f6de27e195
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867941721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2867941721
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke.2369963373
Short name T1446
Test name
Test status
Simulation time 43355364 ps
CPU time 6.73 seconds
Started Jul 14 07:33:54 PM PDT 24
Finished Jul 14 07:34:01 PM PDT 24
Peak memory 575244 kb
Host smart-efd190ee-ffc7-473c-ab68-09773f6db645
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369963373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2369963373
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.2677444012
Short name T1433
Test name
Test status
Simulation time 7740465061 ps
CPU time 87.14 seconds
Started Jul 14 07:33:51 PM PDT 24
Finished Jul 14 07:35:19 PM PDT 24
Peak memory 574220 kb
Host smart-737e80ec-41c4-4a70-ad6c-d5a8847edc31
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677444012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2677444012
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.2925136364
Short name T2893
Test name
Test status
Simulation time 4073624957 ps
CPU time 72.5 seconds
Started Jul 14 07:33:53 PM PDT 24
Finished Jul 14 07:35:06 PM PDT 24
Peak memory 575392 kb
Host smart-d3b22b2a-48ba-4965-966d-2f504dec509a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925136364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2925136364
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.3964253832
Short name T2131
Test name
Test status
Simulation time 49040375 ps
CPU time 6.26 seconds
Started Jul 14 07:33:53 PM PDT 24
Finished Jul 14 07:33:59 PM PDT 24
Peak memory 575276 kb
Host smart-8fe8744f-2c8e-495c-a088-33c15f641c32
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964253832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay
s.3964253832
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all.1982875738
Short name T1908
Test name
Test status
Simulation time 764129579 ps
CPU time 58.22 seconds
Started Jul 14 07:34:00 PM PDT 24
Finished Jul 14 07:34:59 PM PDT 24
Peak memory 575392 kb
Host smart-78f36abb-7e65-4aa7-b8cf-e9afc515d68a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982875738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1982875738
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.184152826
Short name T1614
Test name
Test status
Simulation time 6078359901 ps
CPU time 184.34 seconds
Started Jul 14 07:34:03 PM PDT 24
Finished Jul 14 07:37:08 PM PDT 24
Peak memory 575560 kb
Host smart-fb8b753f-d7a9-4034-b949-bfb6b88ac5b9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184152826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.184152826
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.2068133334
Short name T2717
Test name
Test status
Simulation time 43238713 ps
CPU time 41.13 seconds
Started Jul 14 07:34:01 PM PDT 24
Finished Jul 14 07:34:42 PM PDT 24
Peak memory 575480 kb
Host smart-8d734948-b15e-476c-b3c2-c6475ae6732c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068133334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all
_with_rand_reset.2068133334
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.602148856
Short name T1654
Test name
Test status
Simulation time 80484905 ps
CPU time 24.88 seconds
Started Jul 14 07:34:03 PM PDT 24
Finished Jul 14 07:34:29 PM PDT 24
Peak memory 575480 kb
Host smart-ffc6416c-8325-4e54-833f-2ebbfc742c06
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602148856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all
_with_reset_error.602148856
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.879014308
Short name T2814
Test name
Test status
Simulation time 630810418 ps
CPU time 27.56 seconds
Started Jul 14 07:34:01 PM PDT 24
Finished Jul 14 07:34:29 PM PDT 24
Peak memory 575360 kb
Host smart-edbd77aa-b2ba-4406-83e1-33fe8f771076
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879014308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.879014308
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_access_same_device.552691661
Short name T2738
Test name
Test status
Simulation time 303974005 ps
CPU time 16.92 seconds
Started Jul 14 07:34:10 PM PDT 24
Finished Jul 14 07:34:27 PM PDT 24
Peak memory 575328 kb
Host smart-32e68340-0f0d-4a87-bc73-87ba108f2ad9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552691661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.
552691661
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.3701704720
Short name T1917
Test name
Test status
Simulation time 48066697327 ps
CPU time 786.2 seconds
Started Jul 14 07:34:10 PM PDT 24
Finished Jul 14 07:47:16 PM PDT 24
Peak memory 575500 kb
Host smart-a2ff1a36-3ff6-4dd8-8a4f-a023f002c980
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701704720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_
device_slow_rsp.3701704720
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.242727983
Short name T1745
Test name
Test status
Simulation time 113010414 ps
CPU time 13.26 seconds
Started Jul 14 07:34:11 PM PDT 24
Finished Jul 14 07:34:24 PM PDT 24
Peak memory 575316 kb
Host smart-8cba6078-25de-4856-8053-ebf50bc15727
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242727983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr
.242727983
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_error_random.890188564
Short name T1940
Test name
Test status
Simulation time 1810036030 ps
CPU time 60.42 seconds
Started Jul 14 07:34:10 PM PDT 24
Finished Jul 14 07:35:10 PM PDT 24
Peak memory 575312 kb
Host smart-08759a3f-cf6a-40f5-b5a1-4687184dbd06
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890188564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.890188564
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random.1505126599
Short name T2568
Test name
Test status
Simulation time 1776855184 ps
CPU time 67.31 seconds
Started Jul 14 07:34:09 PM PDT 24
Finished Jul 14 07:35:16 PM PDT 24
Peak memory 575356 kb
Host smart-b67371a3-0cb3-44b4-88da-79a29d6ef925
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505126599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.1505126599
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.3351516839
Short name T1700
Test name
Test status
Simulation time 103121949803 ps
CPU time 1079.7 seconds
Started Jul 14 07:34:11 PM PDT 24
Finished Jul 14 07:52:11 PM PDT 24
Peak memory 575476 kb
Host smart-0a5ffaf9-f850-4495-991a-419ce122fbbb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351516839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3351516839
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.3251684655
Short name T2218
Test name
Test status
Simulation time 34167634138 ps
CPU time 617.98 seconds
Started Jul 14 07:34:09 PM PDT 24
Finished Jul 14 07:44:27 PM PDT 24
Peak memory 575536 kb
Host smart-3c45ef10-07f3-40ca-93c5-231e440d2e2d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251684655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3251684655
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.3146907055
Short name T2381
Test name
Test status
Simulation time 269710897 ps
CPU time 25.91 seconds
Started Jul 14 07:34:09 PM PDT 24
Finished Jul 14 07:34:35 PM PDT 24
Peak memory 575284 kb
Host smart-04da8035-e1f9-4d8d-b2d0-31452711a4b4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146907055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_del
ays.3146907055
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_same_source.826058054
Short name T2045
Test name
Test status
Simulation time 2559249935 ps
CPU time 77.46 seconds
Started Jul 14 07:34:11 PM PDT 24
Finished Jul 14 07:35:29 PM PDT 24
Peak memory 575424 kb
Host smart-c4bf0142-c504-4403-83cf-7253a297a3ee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826058054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.826058054
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke.54991841
Short name T1457
Test name
Test status
Simulation time 44730151 ps
CPU time 5.88 seconds
Started Jul 14 07:34:01 PM PDT 24
Finished Jul 14 07:34:07 PM PDT 24
Peak memory 574020 kb
Host smart-08a7dfd0-7b9a-455d-95be-d0adbf344617
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54991841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.54991841
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.3652218152
Short name T1551
Test name
Test status
Simulation time 8308325067 ps
CPU time 89.9 seconds
Started Jul 14 07:34:00 PM PDT 24
Finished Jul 14 07:35:30 PM PDT 24
Peak memory 574140 kb
Host smart-959ff28c-7e11-4e76-886d-db90dd08edda
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652218152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3652218152
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.1648512458
Short name T1329
Test name
Test status
Simulation time 5390061654 ps
CPU time 90.44 seconds
Started Jul 14 07:34:01 PM PDT 24
Finished Jul 14 07:35:32 PM PDT 24
Peak memory 575452 kb
Host smart-1cc015df-17d1-415e-9bb7-bf1057d8ff93
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648512458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1648512458
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.3275676820
Short name T1359
Test name
Test status
Simulation time 53282321 ps
CPU time 6.85 seconds
Started Jul 14 07:34:01 PM PDT 24
Finished Jul 14 07:34:08 PM PDT 24
Peak memory 574080 kb
Host smart-76945edb-61a7-4ac2-b4c7-d144ac442a91
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275676820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay
s.3275676820
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all.1262154544
Short name T2099
Test name
Test status
Simulation time 745495163 ps
CPU time 75.24 seconds
Started Jul 14 07:34:11 PM PDT 24
Finished Jul 14 07:35:26 PM PDT 24
Peak memory 575484 kb
Host smart-85ec522a-6bef-45af-b192-e3e0cdf804ae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262154544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1262154544
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.3841490883
Short name T2225
Test name
Test status
Simulation time 5687448 ps
CPU time 3.82 seconds
Started Jul 14 07:34:16 PM PDT 24
Finished Jul 14 07:34:20 PM PDT 24
Peak memory 565688 kb
Host smart-9bfc0c44-bb0c-4880-9ad1-26aabf4ca4ef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841490883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3841490883
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.916474025
Short name T2523
Test name
Test status
Simulation time 12045046451 ps
CPU time 650.24 seconds
Started Jul 14 07:34:18 PM PDT 24
Finished Jul 14 07:45:08 PM PDT 24
Peak memory 575552 kb
Host smart-c2f082f6-123a-45bd-9192-88dce7f75de2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916474025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_
with_rand_reset.916474025
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.623633951
Short name T2587
Test name
Test status
Simulation time 940550383 ps
CPU time 38.51 seconds
Started Jul 14 07:34:12 PM PDT 24
Finished Jul 14 07:34:50 PM PDT 24
Peak memory 575408 kb
Host smart-97def668-90f9-4d6b-a53a-487cf49ed9d2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623633951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.623633951
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_access_same_device.1181621363
Short name T1707
Test name
Test status
Simulation time 2722076503 ps
CPU time 115.84 seconds
Started Jul 14 07:34:16 PM PDT 24
Finished Jul 14 07:36:12 PM PDT 24
Peak memory 575380 kb
Host smart-bb3040bc-c0ff-4d07-a1ea-1ab516fa928d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181621363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device
.1181621363
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.4020805088
Short name T2541
Test name
Test status
Simulation time 68489222227 ps
CPU time 1250.17 seconds
Started Jul 14 07:34:17 PM PDT 24
Finished Jul 14 07:55:08 PM PDT 24
Peak memory 575524 kb
Host smart-c72a187b-4eed-47ce-a811-5b3a6968115e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020805088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_
device_slow_rsp.4020805088
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3998576021
Short name T716
Test name
Test status
Simulation time 603659821 ps
CPU time 27.19 seconds
Started Jul 14 07:34:22 PM PDT 24
Finished Jul 14 07:34:49 PM PDT 24
Peak memory 575328 kb
Host smart-5b20f9a3-d6d1-40fe-933a-88cb64434e71
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998576021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add
r.3998576021
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random.1640326290
Short name T2123
Test name
Test status
Simulation time 1454465067 ps
CPU time 50.96 seconds
Started Jul 14 07:34:15 PM PDT 24
Finished Jul 14 07:35:06 PM PDT 24
Peak memory 575336 kb
Host smart-0d77db37-2cca-483d-9022-272739f74e2b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640326290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.1640326290
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.1875716854
Short name T2530
Test name
Test status
Simulation time 64297010944 ps
CPU time 766.52 seconds
Started Jul 14 07:34:16 PM PDT 24
Finished Jul 14 07:47:03 PM PDT 24
Peak memory 575460 kb
Host smart-d499ed80-7e36-4302-8ee4-2923228c8f83
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875716854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1875716854
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.3122131197
Short name T2263
Test name
Test status
Simulation time 30844699146 ps
CPU time 521.69 seconds
Started Jul 14 07:34:15 PM PDT 24
Finished Jul 14 07:42:57 PM PDT 24
Peak memory 575448 kb
Host smart-7a3d649b-0d53-47fe-b05e-fcca37013af1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122131197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3122131197
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.1906092050
Short name T532
Test name
Test status
Simulation time 445150875 ps
CPU time 33.43 seconds
Started Jul 14 07:34:23 PM PDT 24
Finished Jul 14 07:34:57 PM PDT 24
Peak memory 575260 kb
Host smart-25e2bf0a-99cb-4819-b4fd-eb54f64cd2e0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906092050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del
ays.1906092050
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_same_source.2617963823
Short name T2056
Test name
Test status
Simulation time 1700500320 ps
CPU time 48.54 seconds
Started Jul 14 07:34:22 PM PDT 24
Finished Jul 14 07:35:11 PM PDT 24
Peak memory 575268 kb
Host smart-407cf271-8d7a-4184-ba61-736eac33dbc6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617963823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2617963823
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke.1905763212
Short name T2873
Test name
Test status
Simulation time 171195438 ps
CPU time 8.08 seconds
Started Jul 14 07:34:23 PM PDT 24
Finished Jul 14 07:34:32 PM PDT 24
Peak memory 573972 kb
Host smart-fac69722-eb71-405e-a36d-5f55ea189d2a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905763212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1905763212
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.3963636941
Short name T2785
Test name
Test status
Simulation time 8455035282 ps
CPU time 90.97 seconds
Started Jul 14 07:34:22 PM PDT 24
Finished Jul 14 07:35:54 PM PDT 24
Peak memory 575376 kb
Host smart-c2a03f51-2483-466b-9bea-4a5cdc9cf81d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963636941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3963636941
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.783861927
Short name T1743
Test name
Test status
Simulation time 5028479062 ps
CPU time 88.43 seconds
Started Jul 14 07:34:17 PM PDT 24
Finished Jul 14 07:35:46 PM PDT 24
Peak memory 574180 kb
Host smart-d0d4f803-8b04-4161-8f76-f4c2b0c8d13d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783861927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.783861927
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.575188643
Short name T2502
Test name
Test status
Simulation time 45413408 ps
CPU time 6.16 seconds
Started Jul 14 07:34:18 PM PDT 24
Finished Jul 14 07:34:24 PM PDT 24
Peak memory 574004 kb
Host smart-ea30cea0-d579-4ada-82ee-73b1852d4ca2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575188643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays
.575188643
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all.529554406
Short name T1942
Test name
Test status
Simulation time 3291285943 ps
CPU time 252.43 seconds
Started Jul 14 07:34:25 PM PDT 24
Finished Jul 14 07:38:38 PM PDT 24
Peak memory 575532 kb
Host smart-5293a719-dce0-459f-b974-0482e86b80d4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529554406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.529554406
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.2470090032
Short name T2278
Test name
Test status
Simulation time 6512645122 ps
CPU time 227.03 seconds
Started Jul 14 07:34:22 PM PDT 24
Finished Jul 14 07:38:10 PM PDT 24
Peak memory 575532 kb
Host smart-75466e10-e2c2-49f9-ae0f-65396368f84f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470090032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2470090032
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.3654808178
Short name T2141
Test name
Test status
Simulation time 11123895 ps
CPU time 19.3 seconds
Started Jul 14 07:34:24 PM PDT 24
Finished Jul 14 07:34:44 PM PDT 24
Peak memory 574120 kb
Host smart-274ba177-03b6-4e9a-9625-f4bc0ebef516
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654808178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all
_with_rand_reset.3654808178
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.4116033757
Short name T2250
Test name
Test status
Simulation time 235952908 ps
CPU time 29.86 seconds
Started Jul 14 07:34:24 PM PDT 24
Finished Jul 14 07:34:55 PM PDT 24
Peak memory 575452 kb
Host smart-90dfd52d-c9a6-4bd7-a38d-7889d6fa55f7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116033757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.4116033757
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_access_same_device.3788535464
Short name T1392
Test name
Test status
Simulation time 46756656 ps
CPU time 13.26 seconds
Started Jul 14 07:34:30 PM PDT 24
Finished Jul 14 07:34:44 PM PDT 24
Peak memory 575252 kb
Host smart-d50d17da-a2b8-451d-8c9a-ba333f67d921
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788535464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device
.3788535464
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.2198810150
Short name T2712
Test name
Test status
Simulation time 72119932405 ps
CPU time 1319.71 seconds
Started Jul 14 07:34:30 PM PDT 24
Finished Jul 14 07:56:31 PM PDT 24
Peak memory 575556 kb
Host smart-6938c4bc-5a70-4b21-ba14-ca59f1fe0fd9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198810150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_
device_slow_rsp.2198810150
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.30689288
Short name T1579
Test name
Test status
Simulation time 263637642 ps
CPU time 27.78 seconds
Started Jul 14 07:34:31 PM PDT 24
Finished Jul 14 07:34:59 PM PDT 24
Peak memory 575224 kb
Host smart-c6099767-430f-46ae-81fa-57e13856dfce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30689288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.30689288
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_error_random.3919374448
Short name T1387
Test name
Test status
Simulation time 599707418 ps
CPU time 46.12 seconds
Started Jul 14 07:34:30 PM PDT 24
Finished Jul 14 07:35:17 PM PDT 24
Peak memory 575348 kb
Host smart-52ff8cb5-e0c2-453b-8fa3-38f464fe0474
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919374448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3919374448
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random.1189201904
Short name T1570
Test name
Test status
Simulation time 218746954 ps
CPU time 20.13 seconds
Started Jul 14 07:34:22 PM PDT 24
Finished Jul 14 07:34:43 PM PDT 24
Peak memory 575368 kb
Host smart-5ce2ed33-acc4-4d7c-b563-2579d8bfa534
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189201904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.1189201904
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.3790220118
Short name T485
Test name
Test status
Simulation time 37228229803 ps
CPU time 405.44 seconds
Started Jul 14 07:34:29 PM PDT 24
Finished Jul 14 07:41:14 PM PDT 24
Peak memory 575508 kb
Host smart-68b413e0-f226-423e-ab96-670629ee8f38
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790220118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3790220118
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.1959796944
Short name T1532
Test name
Test status
Simulation time 23938148646 ps
CPU time 412.89 seconds
Started Jul 14 07:34:33 PM PDT 24
Finished Jul 14 07:41:26 PM PDT 24
Peak memory 575528 kb
Host smart-f1b511ab-ef12-4aee-876b-b8707916b4d9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959796944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1959796944
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.3581705356
Short name T1573
Test name
Test status
Simulation time 531855341 ps
CPU time 46.13 seconds
Started Jul 14 07:34:24 PM PDT 24
Finished Jul 14 07:35:11 PM PDT 24
Peak memory 575264 kb
Host smart-44566af7-4c7d-4154-bcbb-d1c6733dbf4f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581705356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del
ays.3581705356
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_same_source.2458202979
Short name T2390
Test name
Test status
Simulation time 248327549 ps
CPU time 10.76 seconds
Started Jul 14 07:34:32 PM PDT 24
Finished Jul 14 07:34:43 PM PDT 24
Peak memory 574048 kb
Host smart-f5878c8b-d6bd-4d4f-9e31-4a48a115a1f0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458202979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2458202979
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke.4001565059
Short name T2303
Test name
Test status
Simulation time 218712300 ps
CPU time 9.88 seconds
Started Jul 14 07:34:23 PM PDT 24
Finished Jul 14 07:34:33 PM PDT 24
Peak memory 573988 kb
Host smart-fe6ba16e-42f0-4059-bfcb-a889b0ce136d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001565059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.4001565059
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.622030240
Short name T2509
Test name
Test status
Simulation time 8980517517 ps
CPU time 96.87 seconds
Started Jul 14 07:34:23 PM PDT 24
Finished Jul 14 07:36:01 PM PDT 24
Peak memory 575456 kb
Host smart-9f218719-0a5b-4551-b77f-f4434b4f4ec1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622030240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.622030240
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.1495196615
Short name T2654
Test name
Test status
Simulation time 3320316895 ps
CPU time 60.55 seconds
Started Jul 14 07:34:24 PM PDT 24
Finished Jul 14 07:35:25 PM PDT 24
Peak memory 574148 kb
Host smart-b5dbb45a-3fd1-4fdc-bbbe-e6b717e234c0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495196615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1495196615
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.695814908
Short name T1962
Test name
Test status
Simulation time 40459341 ps
CPU time 6.05 seconds
Started Jul 14 07:34:23 PM PDT 24
Finished Jul 14 07:34:29 PM PDT 24
Peak memory 573996 kb
Host smart-4a72f9d5-cef4-4fac-b221-39222d83a729
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695814908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays
.695814908
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all.3144291225
Short name T426
Test name
Test status
Simulation time 7159609615 ps
CPU time 287.3 seconds
Started Jul 14 07:34:33 PM PDT 24
Finished Jul 14 07:39:21 PM PDT 24
Peak memory 575588 kb
Host smart-d86728c5-1389-4c64-aa8e-f667ddbc87e7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144291225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3144291225
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.1547127823
Short name T1914
Test name
Test status
Simulation time 1702595734 ps
CPU time 127.32 seconds
Started Jul 14 07:34:33 PM PDT 24
Finished Jul 14 07:36:41 PM PDT 24
Peak memory 575484 kb
Host smart-d5d85866-824a-455b-a5c4-67bca040ab7e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547127823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1547127823
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.2003466205
Short name T2227
Test name
Test status
Simulation time 1553209385 ps
CPU time 136.29 seconds
Started Jul 14 07:34:30 PM PDT 24
Finished Jul 14 07:36:47 PM PDT 24
Peak memory 575484 kb
Host smart-068c8b61-fcca-44df-ae64-6936aef4592e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003466205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all
_with_rand_reset.2003466205
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.999279322
Short name T2393
Test name
Test status
Simulation time 89905201 ps
CPU time 7.27 seconds
Started Jul 14 07:34:30 PM PDT 24
Finished Jul 14 07:34:38 PM PDT 24
Peak memory 574048 kb
Host smart-c15630f9-4e75-4a2b-b2ce-12b7030e6cdf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999279322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.999279322
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_access_same_device.2495483181
Short name T1982
Test name
Test status
Simulation time 1088895103 ps
CPU time 79.88 seconds
Started Jul 14 07:34:37 PM PDT 24
Finished Jul 14 07:35:57 PM PDT 24
Peak memory 575372 kb
Host smart-6f10ae7c-f32f-496b-83d0-ae3fdc72a995
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495483181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device
.2495483181
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.3918842963
Short name T2511
Test name
Test status
Simulation time 121473840224 ps
CPU time 2512.06 seconds
Started Jul 14 07:34:35 PM PDT 24
Finished Jul 14 08:16:27 PM PDT 24
Peak memory 575548 kb
Host smart-8a4ecce2-1819-4714-8b9f-b06bb96612e3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918842963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_
device_slow_rsp.3918842963
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.1231025037
Short name T1437
Test name
Test status
Simulation time 1183004712 ps
CPU time 44.39 seconds
Started Jul 14 07:34:46 PM PDT 24
Finished Jul 14 07:35:31 PM PDT 24
Peak memory 575360 kb
Host smart-d2346a7f-9d8f-41ff-890a-1247b4f8cc2d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231025037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add
r.1231025037
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_error_random.2142936867
Short name T1338
Test name
Test status
Simulation time 316252991 ps
CPU time 28.02 seconds
Started Jul 14 07:34:43 PM PDT 24
Finished Jul 14 07:35:12 PM PDT 24
Peak memory 575272 kb
Host smart-3036d94d-5fa8-4739-a18a-9a9b7560a6be
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142936867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2142936867
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random.2701074782
Short name T2431
Test name
Test status
Simulation time 321241155 ps
CPU time 28.03 seconds
Started Jul 14 07:34:39 PM PDT 24
Finished Jul 14 07:35:08 PM PDT 24
Peak memory 575372 kb
Host smart-08052470-1c3b-486f-8294-29e97667aa3a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701074782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.2701074782
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.4164246474
Short name T2337
Test name
Test status
Simulation time 68377699566 ps
CPU time 737.58 seconds
Started Jul 14 07:34:36 PM PDT 24
Finished Jul 14 07:46:54 PM PDT 24
Peak memory 575516 kb
Host smart-7b5c1f26-5282-45a5-a06e-0da420f594ea
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164246474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.4164246474
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.3861599409
Short name T2104
Test name
Test status
Simulation time 3163457575 ps
CPU time 56.41 seconds
Started Jul 14 07:34:38 PM PDT 24
Finished Jul 14 07:35:35 PM PDT 24
Peak memory 574100 kb
Host smart-15aa2392-69a0-441e-b996-6874e4082a23
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861599409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3861599409
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.2417738033
Short name T1480
Test name
Test status
Simulation time 231061920 ps
CPU time 21.74 seconds
Started Jul 14 07:34:36 PM PDT 24
Finished Jul 14 07:34:58 PM PDT 24
Peak memory 575312 kb
Host smart-c012bd0a-7a2c-4ca6-81ed-6e06c4bdc0e7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417738033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del
ays.2417738033
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_same_source.90387694
Short name T587
Test name
Test status
Simulation time 293042864 ps
CPU time 21.4 seconds
Started Jul 14 07:34:39 PM PDT 24
Finished Jul 14 07:35:01 PM PDT 24
Peak memory 575360 kb
Host smart-8fc38e32-0080-4f75-b84c-332be9fbfeac
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90387694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.90387694
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke.3728637893
Short name T1861
Test name
Test status
Simulation time 42175092 ps
CPU time 6.21 seconds
Started Jul 14 07:34:37 PM PDT 24
Finished Jul 14 07:34:44 PM PDT 24
Peak memory 575260 kb
Host smart-f62becff-e510-4c84-8c3b-655bed9c8ed8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728637893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3728637893
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.2551677548
Short name T2064
Test name
Test status
Simulation time 8569836345 ps
CPU time 95.63 seconds
Started Jul 14 07:34:37 PM PDT 24
Finished Jul 14 07:36:13 PM PDT 24
Peak memory 574172 kb
Host smart-78fd5f76-17cd-4c89-b003-e98c29a7bd2d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551677548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2551677548
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.3364762216
Short name T2153
Test name
Test status
Simulation time 5739746878 ps
CPU time 101.6 seconds
Started Jul 14 07:34:36 PM PDT 24
Finished Jul 14 07:36:18 PM PDT 24
Peak memory 574224 kb
Host smart-d8657d12-a49e-4bea-8f5f-c18d0a642fc7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364762216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3364762216
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.403703338
Short name T1328
Test name
Test status
Simulation time 42834905 ps
CPU time 5.65 seconds
Started Jul 14 07:34:36 PM PDT 24
Finished Jul 14 07:34:42 PM PDT 24
Peak memory 575260 kb
Host smart-945054d5-3abc-4613-b880-e1817063d9ba
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403703338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays
.403703338
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all.135780090
Short name T1937
Test name
Test status
Simulation time 11599013084 ps
CPU time 495.87 seconds
Started Jul 14 07:34:45 PM PDT 24
Finished Jul 14 07:43:01 PM PDT 24
Peak memory 575620 kb
Host smart-f87a7aba-e5b9-4d5e-b8e8-25fcd114fd66
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135780090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.135780090
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.3882128114
Short name T1542
Test name
Test status
Simulation time 12715657532 ps
CPU time 459.19 seconds
Started Jul 14 07:34:42 PM PDT 24
Finished Jul 14 07:42:22 PM PDT 24
Peak memory 575604 kb
Host smart-8c399d25-da0a-4d30-a968-efe07641c50f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882128114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3882128114
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2845096396
Short name T2172
Test name
Test status
Simulation time 6840493145 ps
CPU time 398.44 seconds
Started Jul 14 07:34:42 PM PDT 24
Finished Jul 14 07:41:21 PM PDT 24
Peak memory 575584 kb
Host smart-17a6bd17-c53e-418e-9020-2a9a2b6e5854
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845096396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al
l_with_reset_error.2845096396
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.1712045040
Short name T2516
Test name
Test status
Simulation time 52202507 ps
CPU time 8.3 seconds
Started Jul 14 07:34:43 PM PDT 24
Finished Jul 14 07:34:52 PM PDT 24
Peak memory 575388 kb
Host smart-f7d5ba5f-30e8-4afe-8f1e-917aa7d0131a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712045040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1712045040
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_access_same_device.2858984830
Short name T2845
Test name
Test status
Simulation time 2668903017 ps
CPU time 114.95 seconds
Started Jul 14 07:34:50 PM PDT 24
Finished Jul 14 07:36:45 PM PDT 24
Peak memory 575376 kb
Host smart-a03f2cc4-685e-48c1-a7bb-a6f07c5ca78e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858984830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device
.2858984830
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.2429325567
Short name T1995
Test name
Test status
Simulation time 44179627637 ps
CPU time 799.83 seconds
Started Jul 14 07:34:49 PM PDT 24
Finished Jul 14 07:48:09 PM PDT 24
Peak memory 575536 kb
Host smart-9c4f4226-ea93-48e6-9fd5-cc70df9042aa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429325567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_
device_slow_rsp.2429325567
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.2346013172
Short name T1550
Test name
Test status
Simulation time 788432865 ps
CPU time 33.61 seconds
Started Jul 14 07:34:54 PM PDT 24
Finished Jul 14 07:35:29 PM PDT 24
Peak memory 575324 kb
Host smart-fefaf8e0-b8f8-496b-bda7-85fa487511b6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346013172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add
r.2346013172
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_error_random.1947290684
Short name T718
Test name
Test status
Simulation time 621622054 ps
CPU time 49.11 seconds
Started Jul 14 07:34:52 PM PDT 24
Finished Jul 14 07:35:42 PM PDT 24
Peak memory 575296 kb
Host smart-8fb62348-d3b4-41b9-a596-cfa64c3eb9c6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947290684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1947290684
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random.1622159818
Short name T2037
Test name
Test status
Simulation time 994992850 ps
CPU time 36.14 seconds
Started Jul 14 07:34:49 PM PDT 24
Finished Jul 14 07:35:26 PM PDT 24
Peak memory 575336 kb
Host smart-f7726eb5-8d85-495b-9180-a2c83af9db79
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622159818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.1622159818
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.2439362388
Short name T1451
Test name
Test status
Simulation time 55203767818 ps
CPU time 972.87 seconds
Started Jul 14 07:34:53 PM PDT 24
Finished Jul 14 07:51:07 PM PDT 24
Peak memory 575508 kb
Host smart-5f7d7e83-95c5-450d-be15-f4e9c679e725
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439362388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2439362388
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.1588765860
Short name T1353
Test name
Test status
Simulation time 42942596 ps
CPU time 6.79 seconds
Started Jul 14 07:34:51 PM PDT 24
Finished Jul 14 07:34:58 PM PDT 24
Peak memory 574040 kb
Host smart-7fc4cd75-3e32-47bf-9c99-3ce4904059d4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588765860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_del
ays.1588765860
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_same_source.4150020917
Short name T1507
Test name
Test status
Simulation time 1924409879 ps
CPU time 64.04 seconds
Started Jul 14 07:34:50 PM PDT 24
Finished Jul 14 07:35:55 PM PDT 24
Peak memory 575424 kb
Host smart-355c4edb-892a-480f-931e-0055d182b075
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150020917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.4150020917
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke.534596141
Short name T1742
Test name
Test status
Simulation time 253386021 ps
CPU time 10.44 seconds
Started Jul 14 07:34:45 PM PDT 24
Finished Jul 14 07:34:56 PM PDT 24
Peak memory 575508 kb
Host smart-d79827e9-7804-4713-ae37-6da9398f800c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534596141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.534596141
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.900364034
Short name T508
Test name
Test status
Simulation time 5311553796 ps
CPU time 56.04 seconds
Started Jul 14 07:34:45 PM PDT 24
Finished Jul 14 07:35:41 PM PDT 24
Peak memory 574148 kb
Host smart-0e2facaf-f44d-4d6d-a137-f212e44e9072
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900364034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.900364034
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.2609703619
Short name T1555
Test name
Test status
Simulation time 5107324873 ps
CPU time 91.84 seconds
Started Jul 14 07:34:43 PM PDT 24
Finished Jul 14 07:36:16 PM PDT 24
Peak memory 575380 kb
Host smart-eac3c2ca-efdf-4531-a083-8f928f30997e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609703619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2609703619
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.3517422585
Short name T2091
Test name
Test status
Simulation time 43415392 ps
CPU time 6.29 seconds
Started Jul 14 07:34:46 PM PDT 24
Finished Jul 14 07:34:53 PM PDT 24
Peak memory 574008 kb
Host smart-6a15f250-2774-41e9-8ab3-1e6f3cac02c7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517422585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay
s.3517422585
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all.2629506545
Short name T427
Test name
Test status
Simulation time 6269688107 ps
CPU time 195.82 seconds
Started Jul 14 07:34:57 PM PDT 24
Finished Jul 14 07:38:14 PM PDT 24
Peak memory 575592 kb
Host smart-7e59e43a-b5a7-4631-8e54-b9feec88e2e5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629506545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.2629506545
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.3284051458
Short name T2367
Test name
Test status
Simulation time 3253238703 ps
CPU time 133.43 seconds
Started Jul 14 07:34:57 PM PDT 24
Finished Jul 14 07:37:11 PM PDT 24
Peak memory 575416 kb
Host smart-a47b44af-94b2-46e7-a23a-aa190f08cd71
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284051458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3284051458
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.3214136003
Short name T2719
Test name
Test status
Simulation time 82924070 ps
CPU time 9.76 seconds
Started Jul 14 07:34:59 PM PDT 24
Finished Jul 14 07:35:09 PM PDT 24
Peak memory 574136 kb
Host smart-1be2130f-3d3e-4524-a85a-be1ed8c850b5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214136003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al
l_with_reset_error.3214136003
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.1567516654
Short name T2107
Test name
Test status
Simulation time 1334144105 ps
CPU time 51.88 seconds
Started Jul 14 07:34:52 PM PDT 24
Finished Jul 14 07:35:44 PM PDT 24
Peak memory 575340 kb
Host smart-d51bfc3b-a5b6-4133-916a-f6941659fe84
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567516654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1567516654
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.110058692
Short name T2436
Test name
Test status
Simulation time 39269022905 ps
CPU time 6711.91 seconds
Started Jul 14 07:27:34 PM PDT 24
Finished Jul 14 09:19:27 PM PDT 24
Peak memory 593864 kb
Host smart-c9ea0d61-523b-4f05-b946-0cd367c880f6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110058692 -assert nopostproc +UVM_TESTNAME=chip_b
ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.chip_csr_aliasing.110058692
Directory /workspace/4.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.1284980238
Short name T2260
Test name
Test status
Simulation time 5952153456 ps
CPU time 577.14 seconds
Started Jul 14 07:27:34 PM PDT 24
Finished Jul 14 07:37:12 PM PDT 24
Peak memory 590624 kb
Host smart-cd310e3c-3bbf-47b9-bb45-eb070b7cac4f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284980238 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.1284980238
Directory /workspace/4.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_rw.3780399757
Short name T2134
Test name
Test status
Simulation time 6181698601 ps
CPU time 563.54 seconds
Started Jul 14 07:27:52 PM PDT 24
Finished Jul 14 07:37:16 PM PDT 24
Peak memory 599344 kb
Host smart-3a54e939-141e-443c-86a6-39c1c98a7184
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780399757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.3780399757
Directory /workspace/4.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.2148305435
Short name T2716
Test name
Test status
Simulation time 15355284150 ps
CPU time 2154.42 seconds
Started Jul 14 07:27:35 PM PDT 24
Finished Jul 14 08:03:30 PM PDT 24
Peak memory 592888 kb
Host smart-d7b11b35-3a2e-48f6-83fb-a527ccec2093
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148305435 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.2148305435
Directory /workspace/4.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.chip_tl_errors.3318952148
Short name T2687
Test name
Test status
Simulation time 4273117100 ps
CPU time 325.14 seconds
Started Jul 14 07:27:36 PM PDT 24
Finished Jul 14 07:33:02 PM PDT 24
Peak memory 599724 kb
Host smart-62de9b5e-6b6a-4dc8-9fde-89daff4ca8eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318952148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.3318952148
Directory /workspace/4.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_access_same_device.3770461207
Short name T2224
Test name
Test status
Simulation time 2281010096 ps
CPU time 95.96 seconds
Started Jul 14 07:27:40 PM PDT 24
Finished Jul 14 07:29:17 PM PDT 24
Peak memory 575408 kb
Host smart-db2862bb-4f53-4c22-9871-6c85ef57e8b1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770461207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.
3770461207
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.1536492808
Short name T1495
Test name
Test status
Simulation time 148967270003 ps
CPU time 2993.21 seconds
Started Jul 14 07:27:45 PM PDT 24
Finished Jul 14 08:17:40 PM PDT 24
Peak memory 575472 kb
Host smart-93fd16c8-b84c-4a85-a3c0-8374e4cf9aa7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536492808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d
evice_slow_rsp.1536492808
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.3135679490
Short name T672
Test name
Test status
Simulation time 1435340701 ps
CPU time 55.84 seconds
Started Jul 14 07:27:46 PM PDT 24
Finished Jul 14 07:28:43 PM PDT 24
Peak memory 575316 kb
Host smart-cf517921-e5a8-486a-909a-7b9a25cdd712
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135679490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr
.3135679490
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_error_random.4015930331
Short name T1347
Test name
Test status
Simulation time 446823942 ps
CPU time 39.93 seconds
Started Jul 14 07:27:46 PM PDT 24
Finished Jul 14 07:28:27 PM PDT 24
Peak memory 575324 kb
Host smart-5cd40163-6515-414b-91cf-47ec84ffb6e2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015930331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.4015930331
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random.301322107
Short name T2252
Test name
Test status
Simulation time 1614229370 ps
CPU time 63.39 seconds
Started Jul 14 07:27:41 PM PDT 24
Finished Jul 14 07:28:45 PM PDT 24
Peak memory 575332 kb
Host smart-99bc16db-e835-4a3d-af55-4bd6b850a499
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301322107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.301322107
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.4116873345
Short name T1927
Test name
Test status
Simulation time 23904134925 ps
CPU time 268.02 seconds
Started Jul 14 07:27:40 PM PDT 24
Finished Jul 14 07:32:09 PM PDT 24
Peak memory 575440 kb
Host smart-834cca4f-50d4-44af-9d36-d65a0a84166e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116873345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.4116873345
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.3092872360
Short name T2117
Test name
Test status
Simulation time 10755928632 ps
CPU time 186.87 seconds
Started Jul 14 07:27:41 PM PDT 24
Finished Jul 14 07:30:49 PM PDT 24
Peak memory 575484 kb
Host smart-69208324-ddd3-4d55-8a26-ece17e8b31a4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092872360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3092872360
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.3328618724
Short name T2637
Test name
Test status
Simulation time 159620909 ps
CPU time 15.03 seconds
Started Jul 14 07:27:40 PM PDT 24
Finished Jul 14 07:27:56 PM PDT 24
Peak memory 575288 kb
Host smart-d10e2b36-bdc5-4537-90f2-d5eb6d8ba731
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328618724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela
ys.3328618724
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_same_source.1571414667
Short name T1627
Test name
Test status
Simulation time 559438329 ps
CPU time 39.66 seconds
Started Jul 14 07:27:46 PM PDT 24
Finished Jul 14 07:28:27 PM PDT 24
Peak memory 575284 kb
Host smart-1d76cbed-c781-43e5-afda-3b52b6758621
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571414667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1571414667
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke.3269006850
Short name T2202
Test name
Test status
Simulation time 201509082 ps
CPU time 8.91 seconds
Started Jul 14 07:27:38 PM PDT 24
Finished Jul 14 07:27:48 PM PDT 24
Peak memory 575248 kb
Host smart-1d9c2169-b1f4-4b63-a163-e389c7d3ca09
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269006850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3269006850
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.2847256561
Short name T2736
Test name
Test status
Simulation time 6850398602 ps
CPU time 74.71 seconds
Started Jul 14 07:27:40 PM PDT 24
Finished Jul 14 07:28:55 PM PDT 24
Peak memory 574096 kb
Host smart-43a0b448-cec4-4c1c-94ed-fcc52442e417
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847256561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2847256561
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.2471890757
Short name T1959
Test name
Test status
Simulation time 3417142422 ps
CPU time 59.51 seconds
Started Jul 14 07:27:40 PM PDT 24
Finished Jul 14 07:28:40 PM PDT 24
Peak memory 574032 kb
Host smart-6390562d-636d-4109-b6ed-d239237ee7fd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471890757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2471890757
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.1416628880
Short name T1596
Test name
Test status
Simulation time 55032776 ps
CPU time 6.69 seconds
Started Jul 14 07:27:42 PM PDT 24
Finished Jul 14 07:27:49 PM PDT 24
Peak memory 573948 kb
Host smart-6be437d5-a407-4d98-b023-b5fab27814e4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416628880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays
.1416628880
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all.441112501
Short name T470
Test name
Test status
Simulation time 2791255594 ps
CPU time 100.17 seconds
Started Jul 14 07:27:51 PM PDT 24
Finished Jul 14 07:29:31 PM PDT 24
Peak memory 575508 kb
Host smart-18335024-ccd1-41e8-a1ce-b28f22ea3a2c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441112501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.441112501
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.1236707224
Short name T2447
Test name
Test status
Simulation time 7301190577 ps
CPU time 283.67 seconds
Started Jul 14 07:27:52 PM PDT 24
Finished Jul 14 07:32:36 PM PDT 24
Peak memory 575560 kb
Host smart-02588831-6c7f-4a63-92ce-b2c5cdb0261b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236707224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1236707224
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2403966006
Short name T2426
Test name
Test status
Simulation time 160371636 ps
CPU time 43.7 seconds
Started Jul 14 07:27:50 PM PDT 24
Finished Jul 14 07:28:34 PM PDT 24
Peak memory 575604 kb
Host smart-552c37a0-5051-41be-8072-e237b9080df6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403966006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_
with_rand_reset.2403966006
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.4002765118
Short name T869
Test name
Test status
Simulation time 1124391124 ps
CPU time 154.33 seconds
Started Jul 14 07:27:51 PM PDT 24
Finished Jul 14 07:30:26 PM PDT 24
Peak memory 575476 kb
Host smart-cd1276fc-d2a3-4815-af1f-0c2e10334a6c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002765118 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all
_with_reset_error.4002765118
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.1261597825
Short name T1777
Test name
Test status
Simulation time 685625287 ps
CPU time 34.28 seconds
Started Jul 14 07:27:46 PM PDT 24
Finished Jul 14 07:28:21 PM PDT 24
Peak memory 575392 kb
Host smart-2946fcd8-0861-47ad-825f-7ac6c8101e3c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261597825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1261597825
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_access_same_device.3951042702
Short name T1424
Test name
Test status
Simulation time 2988436453 ps
CPU time 128.67 seconds
Started Jul 14 07:34:57 PM PDT 24
Finished Jul 14 07:37:06 PM PDT 24
Peak memory 575428 kb
Host smart-98720fa8-7c68-46dd-a9e4-5abf76b3feb4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951042702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device
.3951042702
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.693622593
Short name T2041
Test name
Test status
Simulation time 20128260429 ps
CPU time 348.27 seconds
Started Jul 14 07:35:04 PM PDT 24
Finished Jul 14 07:40:53 PM PDT 24
Peak memory 575468 kb
Host smart-1a1deaa9-7952-4f37-82df-b6ad2e4d797a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693622593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_d
evice_slow_rsp.693622593
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.3523884102
Short name T2144
Test name
Test status
Simulation time 119320314 ps
CPU time 15.04 seconds
Started Jul 14 07:35:04 PM PDT 24
Finished Jul 14 07:35:20 PM PDT 24
Peak memory 575252 kb
Host smart-1a2730df-0676-40ce-92fc-8e0111fba5bf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523884102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add
r.3523884102
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_error_random.3699912528
Short name T2223
Test name
Test status
Simulation time 248662020 ps
CPU time 20.51 seconds
Started Jul 14 07:35:04 PM PDT 24
Finished Jul 14 07:35:25 PM PDT 24
Peak memory 575260 kb
Host smart-8b1b5659-1d6e-4a3d-8d12-d7584cb304f9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699912528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3699912528
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random.2644347121
Short name T2836
Test name
Test status
Simulation time 194607186 ps
CPU time 11.3 seconds
Started Jul 14 07:34:59 PM PDT 24
Finished Jul 14 07:35:11 PM PDT 24
Peak memory 575308 kb
Host smart-10b11342-5eed-4826-bbfb-3ba4be6e0b4c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644347121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.2644347121
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.3899600676
Short name T1871
Test name
Test status
Simulation time 60279067406 ps
CPU time 641.88 seconds
Started Jul 14 07:35:01 PM PDT 24
Finished Jul 14 07:45:43 PM PDT 24
Peak memory 575440 kb
Host smart-0b42cbb7-a10c-4814-9d4e-9826d7c9345b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899600676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3899600676
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.1248696443
Short name T1644
Test name
Test status
Simulation time 55078840393 ps
CPU time 1014.98 seconds
Started Jul 14 07:34:56 PM PDT 24
Finished Jul 14 07:51:52 PM PDT 24
Peak memory 575444 kb
Host smart-5964047b-f135-493f-9889-c45f51530134
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248696443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1248696443
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.2108763022
Short name T1587
Test name
Test status
Simulation time 449149817 ps
CPU time 37.66 seconds
Started Jul 14 07:34:56 PM PDT 24
Finished Jul 14 07:35:34 PM PDT 24
Peak memory 575248 kb
Host smart-baef97ac-b26f-4edf-a431-1400b17a91cc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108763022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del
ays.2108763022
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_same_source.3656696055
Short name T2079
Test name
Test status
Simulation time 1811216054 ps
CPU time 53.88 seconds
Started Jul 14 07:35:05 PM PDT 24
Finished Jul 14 07:35:59 PM PDT 24
Peak memory 575296 kb
Host smart-83da3c0f-a2ab-4ce5-b4ff-bb8c8a8fb3f8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656696055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3656696055
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke.3745685623
Short name T1895
Test name
Test status
Simulation time 160641491 ps
CPU time 8.15 seconds
Started Jul 14 07:34:56 PM PDT 24
Finished Jul 14 07:35:05 PM PDT 24
Peak memory 575292 kb
Host smart-4a35f580-c9eb-4a6e-ba8b-b3163a0b788e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745685623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3745685623
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.3681973235
Short name T640
Test name
Test status
Simulation time 7406905937 ps
CPU time 85.01 seconds
Started Jul 14 07:34:57 PM PDT 24
Finished Jul 14 07:36:23 PM PDT 24
Peak memory 574136 kb
Host smart-e11a680a-e870-49ef-b173-805dbf5ceef3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681973235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.3681973235
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.50276329
Short name T1625
Test name
Test status
Simulation time 5178029671 ps
CPU time 91.01 seconds
Started Jul 14 07:34:59 PM PDT 24
Finished Jul 14 07:36:30 PM PDT 24
Peak memory 575392 kb
Host smart-29e64775-a018-4c4b-b5ff-d727a12e4535
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50276329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.50276329
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.2122141091
Short name T1484
Test name
Test status
Simulation time 40912716 ps
CPU time 6.35 seconds
Started Jul 14 07:34:56 PM PDT 24
Finished Jul 14 07:35:03 PM PDT 24
Peak memory 575172 kb
Host smart-104da7bd-18b3-4c02-a75c-128725b9c192
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122141091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay
s.2122141091
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all.3729579552
Short name T2211
Test name
Test status
Simulation time 4350419834 ps
CPU time 352.51 seconds
Started Jul 14 07:35:06 PM PDT 24
Finished Jul 14 07:40:59 PM PDT 24
Peak memory 575600 kb
Host smart-ff46e2f7-a41c-4a4d-bbb5-d0abedeb35e7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729579552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3729579552
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.3045170687
Short name T579
Test name
Test status
Simulation time 9756580767 ps
CPU time 454.62 seconds
Started Jul 14 07:35:04 PM PDT 24
Finished Jul 14 07:42:39 PM PDT 24
Peak memory 575568 kb
Host smart-28d1069e-37ac-45cb-9db2-30777250df11
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045170687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all
_with_rand_reset.3045170687
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3068888822
Short name T1765
Test name
Test status
Simulation time 7316886192 ps
CPU time 292.56 seconds
Started Jul 14 07:35:05 PM PDT 24
Finished Jul 14 07:39:58 PM PDT 24
Peak memory 575608 kb
Host smart-1a4de2bf-27cb-4236-a703-b89cf82c316a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068888822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al
l_with_reset_error.3068888822
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.3727818479
Short name T2191
Test name
Test status
Simulation time 1200931625 ps
CPU time 49.16 seconds
Started Jul 14 07:35:07 PM PDT 24
Finished Jul 14 07:35:57 PM PDT 24
Peak memory 575436 kb
Host smart-f3f45b7a-a8ab-469f-b443-dee6e737dce9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727818479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3727818479
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_access_same_device.3382967520
Short name T2102
Test name
Test status
Simulation time 1790872663 ps
CPU time 80.32 seconds
Started Jul 14 07:35:16 PM PDT 24
Finished Jul 14 07:36:37 PM PDT 24
Peak memory 575388 kb
Host smart-fd3fc8a2-4883-4b13-8854-c6469dda9595
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382967520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device
.3382967520
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.894955686
Short name T1972
Test name
Test status
Simulation time 137772145261 ps
CPU time 2642.48 seconds
Started Jul 14 07:35:16 PM PDT 24
Finished Jul 14 08:19:19 PM PDT 24
Peak memory 575532 kb
Host smart-885fcfd9-faad-4102-a233-2f48aa63766b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894955686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_d
evice_slow_rsp.894955686
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.992473083
Short name T2478
Test name
Test status
Simulation time 332236902 ps
CPU time 33.17 seconds
Started Jul 14 07:35:20 PM PDT 24
Finished Jul 14 07:35:54 PM PDT 24
Peak memory 575076 kb
Host smart-f896506f-727d-4dd7-8645-132b36fd1883
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992473083 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr
.992473083
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_error_random.3408680539
Short name T2840
Test name
Test status
Simulation time 2162743338 ps
CPU time 74.19 seconds
Started Jul 14 07:35:20 PM PDT 24
Finished Jul 14 07:36:34 PM PDT 24
Peak memory 575380 kb
Host smart-28b25f4d-7680-49ae-8e86-099b7189fdbc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408680539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3408680539
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random.3386771858
Short name T573
Test name
Test status
Simulation time 454029174 ps
CPU time 40.16 seconds
Started Jul 14 07:35:17 PM PDT 24
Finished Jul 14 07:35:58 PM PDT 24
Peak memory 575360 kb
Host smart-b3be3449-acab-477f-bfce-ec3f960c4bfd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386771858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.3386771858
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.2008689166
Short name T2136
Test name
Test status
Simulation time 44089498731 ps
CPU time 466.83 seconds
Started Jul 14 07:35:20 PM PDT 24
Finished Jul 14 07:43:08 PM PDT 24
Peak memory 575492 kb
Host smart-26166686-9217-4a45-8668-12750fa5c628
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008689166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2008689166
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.1248829356
Short name T1966
Test name
Test status
Simulation time 42007977910 ps
CPU time 786.82 seconds
Started Jul 14 07:35:18 PM PDT 24
Finished Jul 14 07:48:26 PM PDT 24
Peak memory 575472 kb
Host smart-a19205b6-fb0a-4cc3-853c-2e4e2f8eacfb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248829356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1248829356
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.2126105001
Short name T1783
Test name
Test status
Simulation time 534325556 ps
CPU time 49.79 seconds
Started Jul 14 07:35:17 PM PDT 24
Finished Jul 14 07:36:07 PM PDT 24
Peak memory 575364 kb
Host smart-efb12ebe-c184-4280-a484-67f67b3df38b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126105001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del
ays.2126105001
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_same_source.3888055414
Short name T1571
Test name
Test status
Simulation time 2449112006 ps
CPU time 67.6 seconds
Started Jul 14 07:35:20 PM PDT 24
Finished Jul 14 07:36:28 PM PDT 24
Peak memory 575340 kb
Host smart-26d92ac3-7cf2-45fe-b5e6-ce452a6d3e54
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888055414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3888055414
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke.2889476261
Short name T1752
Test name
Test status
Simulation time 254931223 ps
CPU time 9.51 seconds
Started Jul 14 07:35:16 PM PDT 24
Finished Jul 14 07:35:26 PM PDT 24
Peak memory 574076 kb
Host smart-246095da-b952-4243-b72a-ce654de64caa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889476261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2889476261
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.2949327982
Short name T2021
Test name
Test status
Simulation time 8699710746 ps
CPU time 101.6 seconds
Started Jul 14 07:35:18 PM PDT 24
Finished Jul 14 07:36:59 PM PDT 24
Peak memory 575452 kb
Host smart-2d643e91-154a-4ac8-bd36-ece14354a132
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949327982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2949327982
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.345549797
Short name T2168
Test name
Test status
Simulation time 5577032126 ps
CPU time 104.82 seconds
Started Jul 14 07:35:17 PM PDT 24
Finished Jul 14 07:37:03 PM PDT 24
Peak memory 574160 kb
Host smart-6f774d68-3060-41a9-aaf4-d35d13f3e43c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345549797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.345549797
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.3363920892
Short name T2705
Test name
Test status
Simulation time 50529507 ps
CPU time 6.45 seconds
Started Jul 14 07:35:17 PM PDT 24
Finished Jul 14 07:35:24 PM PDT 24
Peak memory 574008 kb
Host smart-0b4fc242-ae31-4b7c-b85b-fc72eb0c9cff
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363920892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay
s.3363920892
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all.3940429240
Short name T495
Test name
Test status
Simulation time 5859877294 ps
CPU time 248.46 seconds
Started Jul 14 07:35:16 PM PDT 24
Finished Jul 14 07:39:25 PM PDT 24
Peak memory 575568 kb
Host smart-bf76c725-6b25-41ef-93f6-af9b9fe4d38d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940429240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3940429240
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.1017099852
Short name T2296
Test name
Test status
Simulation time 9183667233 ps
CPU time 304.18 seconds
Started Jul 14 07:35:17 PM PDT 24
Finished Jul 14 07:40:21 PM PDT 24
Peak memory 575604 kb
Host smart-fc56332c-5751-47ed-a89b-375d512cda4a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017099852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1017099852
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.4067255095
Short name T2792
Test name
Test status
Simulation time 427243608 ps
CPU time 177.02 seconds
Started Jul 14 07:35:20 PM PDT 24
Finished Jul 14 07:38:18 PM PDT 24
Peak memory 575464 kb
Host smart-f56c38c1-5405-4c5b-8d42-efdf9d2d52c0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067255095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all
_with_rand_reset.4067255095
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.850693765
Short name T857
Test name
Test status
Simulation time 5335155675 ps
CPU time 595.79 seconds
Started Jul 14 07:35:19 PM PDT 24
Finished Jul 14 07:45:16 PM PDT 24
Peak memory 578300 kb
Host smart-7aab95e8-9434-4837-ace8-e8894d590fe8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850693765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all
_with_reset_error.850693765
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.2453260406
Short name T2588
Test name
Test status
Simulation time 101835855 ps
CPU time 13.88 seconds
Started Jul 14 07:35:20 PM PDT 24
Finished Jul 14 07:35:34 PM PDT 24
Peak memory 575408 kb
Host smart-6147f877-aa9a-4519-83bf-2886771a2cd0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453260406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2453260406
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_access_same_device.4181901376
Short name T2169
Test name
Test status
Simulation time 1668521662 ps
CPU time 65.66 seconds
Started Jul 14 07:35:24 PM PDT 24
Finished Jul 14 07:36:30 PM PDT 24
Peak memory 575348 kb
Host smart-2ef1bba8-b25e-422c-8f6d-2c98c8120d17
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181901376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device
.4181901376
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.1004715759
Short name T1404
Test name
Test status
Simulation time 14059183226 ps
CPU time 251.17 seconds
Started Jul 14 07:35:18 PM PDT 24
Finished Jul 14 07:39:30 PM PDT 24
Peak memory 575456 kb
Host smart-15fce06e-e9bd-4f5f-a823-fc60e677926a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004715759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_
device_slow_rsp.1004715759
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.2589342930
Short name T1382
Test name
Test status
Simulation time 1266669459 ps
CPU time 46.48 seconds
Started Jul 14 07:35:26 PM PDT 24
Finished Jul 14 07:36:14 PM PDT 24
Peak memory 575360 kb
Host smart-d6087568-e6f2-46e8-aa77-4db2c1749f3b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589342930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add
r.2589342930
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_error_random.89790836
Short name T1366
Test name
Test status
Simulation time 623664596 ps
CPU time 24.72 seconds
Started Jul 14 07:35:30 PM PDT 24
Finished Jul 14 07:35:55 PM PDT 24
Peak memory 575044 kb
Host smart-00d06de6-5be3-4244-84aa-134e6c3a300f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89790836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.89790836
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random.1278782986
Short name T2403
Test name
Test status
Simulation time 479931579 ps
CPU time 44.02 seconds
Started Jul 14 07:35:22 PM PDT 24
Finished Jul 14 07:36:07 PM PDT 24
Peak memory 575408 kb
Host smart-cc84f599-c395-468b-9910-937025749392
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278782986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.1278782986
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.3426036705
Short name T2053
Test name
Test status
Simulation time 61592661145 ps
CPU time 656.09 seconds
Started Jul 14 07:35:22 PM PDT 24
Finished Jul 14 07:46:19 PM PDT 24
Peak memory 575468 kb
Host smart-501a50be-3093-451c-bbbe-8031e404f861
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426036705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3426036705
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.1097101391
Short name T1452
Test name
Test status
Simulation time 38219175247 ps
CPU time 693.38 seconds
Started Jul 14 07:35:24 PM PDT 24
Finished Jul 14 07:46:58 PM PDT 24
Peak memory 575504 kb
Host smart-a235f50b-e41f-4be8-8f17-fb56ba03c0a5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097101391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1097101391
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.2617861523
Short name T606
Test name
Test status
Simulation time 472743671 ps
CPU time 40.3 seconds
Started Jul 14 07:35:20 PM PDT 24
Finished Jul 14 07:36:01 PM PDT 24
Peak memory 575328 kb
Host smart-0b85bc94-c660-46bc-80e5-0e52dc1e41c3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617861523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del
ays.2617861523
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_same_source.1795516258
Short name T2389
Test name
Test status
Simulation time 433268257 ps
CPU time 33.6 seconds
Started Jul 14 07:35:25 PM PDT 24
Finished Jul 14 07:35:59 PM PDT 24
Peak memory 575328 kb
Host smart-ec9e1623-ae05-46c0-a51e-162964b385b2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795516258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1795516258
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke.1487472303
Short name T2626
Test name
Test status
Simulation time 44580515 ps
CPU time 5.7 seconds
Started Jul 14 07:35:18 PM PDT 24
Finished Jul 14 07:35:24 PM PDT 24
Peak memory 575296 kb
Host smart-a4cd2d78-2acc-45c6-bd14-803c34009747
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487472303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1487472303
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.2358818038
Short name T1537
Test name
Test status
Simulation time 10144613562 ps
CPU time 112.17 seconds
Started Jul 14 07:35:19 PM PDT 24
Finished Jul 14 07:37:12 PM PDT 24
Peak memory 574184 kb
Host smart-d476fa65-14e4-4fd7-8b35-72a77164d250
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358818038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2358818038
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.2823829591
Short name T1826
Test name
Test status
Simulation time 6035302540 ps
CPU time 104.45 seconds
Started Jul 14 07:35:21 PM PDT 24
Finished Jul 14 07:37:06 PM PDT 24
Peak memory 574204 kb
Host smart-70b010bd-8e51-427b-a75b-3242262e3f49
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823829591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.2823829591
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.3950929209
Short name T2618
Test name
Test status
Simulation time 44461266 ps
CPU time 6.02 seconds
Started Jul 14 07:35:20 PM PDT 24
Finished Jul 14 07:35:26 PM PDT 24
Peak memory 574020 kb
Host smart-1765ae33-64b2-481a-af9d-fa2aa1548dbc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950929209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay
s.3950929209
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all.2242673051
Short name T1604
Test name
Test status
Simulation time 10029340295 ps
CPU time 412.12 seconds
Started Jul 14 07:35:25 PM PDT 24
Finished Jul 14 07:42:18 PM PDT 24
Peak memory 575548 kb
Host smart-c4b56fcd-ce18-4128-9271-1342032e076d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242673051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2242673051
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.2608527211
Short name T2580
Test name
Test status
Simulation time 553748934 ps
CPU time 46.98 seconds
Started Jul 14 07:35:26 PM PDT 24
Finished Jul 14 07:36:14 PM PDT 24
Peak memory 575348 kb
Host smart-e0774207-f39a-4700-9383-1acc5ffd0949
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608527211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2608527211
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.350882967
Short name T1615
Test name
Test status
Simulation time 2531515327 ps
CPU time 344.1 seconds
Started Jul 14 07:35:24 PM PDT 24
Finished Jul 14 07:41:08 PM PDT 24
Peak memory 575540 kb
Host smart-95014b4f-e200-4d05-80b3-8c21fd2a43f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350882967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_
with_rand_reset.350882967
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.1451163554
Short name T2145
Test name
Test status
Simulation time 636908073 ps
CPU time 29.28 seconds
Started Jul 14 07:35:26 PM PDT 24
Finished Jul 14 07:35:56 PM PDT 24
Peak memory 575448 kb
Host smart-1eadb283-f9f0-4dbb-953e-4869e93593a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451163554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.1451163554
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_access_same_device.1582917598
Short name T1963
Test name
Test status
Simulation time 211132154 ps
CPU time 20.27 seconds
Started Jul 14 07:35:34 PM PDT 24
Finished Jul 14 07:35:54 PM PDT 24
Peak memory 575360 kb
Host smart-0f7a9287-75c8-45e2-be17-c5767d863e38
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582917598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device
.1582917598
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.674842724
Short name T1487
Test name
Test status
Simulation time 229874035 ps
CPU time 24.41 seconds
Started Jul 14 07:35:33 PM PDT 24
Finished Jul 14 07:35:58 PM PDT 24
Peak memory 575336 kb
Host smart-7c18f4ac-c1cd-4e52-a9d6-21716f559650
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674842724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr
.674842724
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_error_random.1434150973
Short name T1442
Test name
Test status
Simulation time 153629924 ps
CPU time 7.86 seconds
Started Jul 14 07:35:36 PM PDT 24
Finished Jul 14 07:35:44 PM PDT 24
Peak memory 574036 kb
Host smart-a4f8717e-7a89-47cf-a3a4-038d28ec7e66
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434150973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1434150973
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random.272320811
Short name T2070
Test name
Test status
Simulation time 227352105 ps
CPU time 24.7 seconds
Started Jul 14 07:35:36 PM PDT 24
Finished Jul 14 07:36:01 PM PDT 24
Peak memory 575400 kb
Host smart-7df136e5-6902-4c13-b860-30a04353db42
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272320811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.272320811
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.2681991478
Short name T2212
Test name
Test status
Simulation time 40321313002 ps
CPU time 451.28 seconds
Started Jul 14 07:35:32 PM PDT 24
Finished Jul 14 07:43:03 PM PDT 24
Peak memory 575404 kb
Host smart-0de6b215-44cf-483b-92a0-08e6658b7f97
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681991478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2681991478
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.55891860
Short name T2193
Test name
Test status
Simulation time 27387494600 ps
CPU time 492.61 seconds
Started Jul 14 07:35:35 PM PDT 24
Finished Jul 14 07:43:48 PM PDT 24
Peak memory 575508 kb
Host smart-28f28bed-75a3-425d-bf91-49b1736f5210
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55891860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.55891860
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.1427771970
Short name T2653
Test name
Test status
Simulation time 108709100 ps
CPU time 12.62 seconds
Started Jul 14 07:35:34 PM PDT 24
Finished Jul 14 07:35:47 PM PDT 24
Peak memory 575312 kb
Host smart-afbc0bb7-a6b9-4b18-837a-53e11aaabd60
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427771970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del
ays.1427771970
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_same_source.3719130482
Short name T2174
Test name
Test status
Simulation time 1580431987 ps
CPU time 46.95 seconds
Started Jul 14 07:35:32 PM PDT 24
Finished Jul 14 07:36:19 PM PDT 24
Peak memory 575336 kb
Host smart-4008e499-3656-4f20-9c33-daeadd1ac1b5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719130482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3719130482
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke.184187502
Short name T2835
Test name
Test status
Simulation time 173770156 ps
CPU time 8.04 seconds
Started Jul 14 07:35:26 PM PDT 24
Finished Jul 14 07:35:35 PM PDT 24
Peak memory 573996 kb
Host smart-adcd256d-e5d6-4913-b027-f7d13255b5a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184187502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.184187502
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.2500335913
Short name T2142
Test name
Test status
Simulation time 8231190722 ps
CPU time 86.53 seconds
Started Jul 14 07:35:31 PM PDT 24
Finished Jul 14 07:36:57 PM PDT 24
Peak memory 574156 kb
Host smart-18bc37d8-2704-4004-b509-96575767e103
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500335913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2500335913
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.1349612662
Short name T2827
Test name
Test status
Simulation time 6164419573 ps
CPU time 116.7 seconds
Started Jul 14 07:35:34 PM PDT 24
Finished Jul 14 07:37:31 PM PDT 24
Peak memory 574336 kb
Host smart-b9fa171e-39b8-4913-a386-b10caf1998bd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349612662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1349612662
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.1561764883
Short name T1778
Test name
Test status
Simulation time 58675884 ps
CPU time 7.05 seconds
Started Jul 14 07:35:26 PM PDT 24
Finished Jul 14 07:35:34 PM PDT 24
Peak memory 575232 kb
Host smart-2c7a9b0c-6a33-48b9-b774-44789aee400f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561764883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay
s.1561764883
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all.3865027309
Short name T2475
Test name
Test status
Simulation time 7025058283 ps
CPU time 277.92 seconds
Started Jul 14 07:35:33 PM PDT 24
Finished Jul 14 07:40:12 PM PDT 24
Peak memory 575580 kb
Host smart-f47de8b4-ad16-4d74-b48f-d16507b521a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865027309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3865027309
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.521366576
Short name T2000
Test name
Test status
Simulation time 16604051476 ps
CPU time 583.72 seconds
Started Jul 14 07:35:43 PM PDT 24
Finished Jul 14 07:45:27 PM PDT 24
Peak memory 575580 kb
Host smart-b503e4bf-bac2-4b5d-9337-dcf43b94c5ad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521366576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.521366576
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.1286074990
Short name T2399
Test name
Test status
Simulation time 11524708082 ps
CPU time 688.36 seconds
Started Jul 14 07:35:33 PM PDT 24
Finished Jul 14 07:47:01 PM PDT 24
Peak memory 575560 kb
Host smart-c6af781f-da01-4421-a19f-a05bca451db5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286074990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all
_with_rand_reset.1286074990
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.1075348242
Short name T1429
Test name
Test status
Simulation time 13546582 ps
CPU time 13.63 seconds
Started Jul 14 07:35:40 PM PDT 24
Finished Jul 14 07:35:54 PM PDT 24
Peak memory 574224 kb
Host smart-94d6f564-120e-4166-9564-f44ff8c69fdc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075348242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al
l_with_reset_error.1075348242
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.4095211969
Short name T1549
Test name
Test status
Simulation time 233451072 ps
CPU time 11.84 seconds
Started Jul 14 07:35:33 PM PDT 24
Finished Jul 14 07:35:46 PM PDT 24
Peak memory 575352 kb
Host smart-7f0bebe9-bae1-4d1a-b6b1-ab04f794dbf9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095211969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.4095211969
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_access_same_device.3010453213
Short name T2482
Test name
Test status
Simulation time 2886041443 ps
CPU time 118.43 seconds
Started Jul 14 07:35:42 PM PDT 24
Finished Jul 14 07:37:41 PM PDT 24
Peak memory 575412 kb
Host smart-b47d99ba-8321-4a81-a936-73b867b682af
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010453213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device
.3010453213
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.188468550
Short name T2468
Test name
Test status
Simulation time 30491895762 ps
CPU time 541.89 seconds
Started Jul 14 07:35:50 PM PDT 24
Finished Jul 14 07:44:52 PM PDT 24
Peak memory 575576 kb
Host smart-3af5bb3f-38b9-4547-aaaa-5e67e4fbc84d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188468550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_d
evice_slow_rsp.188468550
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.3957453015
Short name T1449
Test name
Test status
Simulation time 76281004 ps
CPU time 6.12 seconds
Started Jul 14 07:35:50 PM PDT 24
Finished Jul 14 07:35:57 PM PDT 24
Peak memory 573960 kb
Host smart-7d15707d-722a-4c9a-9e45-28149adffbd4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957453015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add
r.3957453015
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_error_random.2950938145
Short name T2078
Test name
Test status
Simulation time 1367933223 ps
CPU time 47.34 seconds
Started Jul 14 07:35:48 PM PDT 24
Finished Jul 14 07:36:36 PM PDT 24
Peak memory 575328 kb
Host smart-911e204d-8f16-4c14-af00-3d489e234afd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950938145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2950938145
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random.4018174468
Short name T599
Test name
Test status
Simulation time 531682145 ps
CPU time 47.24 seconds
Started Jul 14 07:35:41 PM PDT 24
Finished Jul 14 07:36:28 PM PDT 24
Peak memory 575336 kb
Host smart-6c56376a-f454-4f1d-97d9-452052594ff7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018174468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.4018174468
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.2471222752
Short name T1342
Test name
Test status
Simulation time 27387575896 ps
CPU time 331.3 seconds
Started Jul 14 07:35:41 PM PDT 24
Finished Jul 14 07:41:13 PM PDT 24
Peak memory 575476 kb
Host smart-c2585d9e-1d13-48d3-808f-0171cabdfbd7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471222752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2471222752
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.1548378950
Short name T2725
Test name
Test status
Simulation time 54416381637 ps
CPU time 964.27 seconds
Started Jul 14 07:35:42 PM PDT 24
Finished Jul 14 07:51:47 PM PDT 24
Peak memory 575460 kb
Host smart-31d43359-0095-4deb-ade3-d769a2794a30
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548378950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1548378950
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.3726278957
Short name T1636
Test name
Test status
Simulation time 229726396 ps
CPU time 21.3 seconds
Started Jul 14 07:35:40 PM PDT 24
Finished Jul 14 07:36:02 PM PDT 24
Peak memory 575344 kb
Host smart-7a8320e6-2095-4fa4-9f17-6ab589458708
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726278957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del
ays.3726278957
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_same_source.2996733796
Short name T2895
Test name
Test status
Simulation time 444740720 ps
CPU time 34.91 seconds
Started Jul 14 07:35:47 PM PDT 24
Finished Jul 14 07:36:23 PM PDT 24
Peak memory 575352 kb
Host smart-44853549-8a92-4961-9ccc-6ae76da5844b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996733796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2996733796
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke.2256174780
Short name T1375
Test name
Test status
Simulation time 230018862 ps
CPU time 9.45 seconds
Started Jul 14 07:35:40 PM PDT 24
Finished Jul 14 07:35:50 PM PDT 24
Peak memory 574016 kb
Host smart-7f928f65-4505-4c62-acba-df18a9b08ff1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256174780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2256174780
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.3096687504
Short name T2439
Test name
Test status
Simulation time 6392112449 ps
CPU time 69.05 seconds
Started Jul 14 07:35:40 PM PDT 24
Finished Jul 14 07:36:50 PM PDT 24
Peak memory 574220 kb
Host smart-037ddf50-8fa2-4699-9f1c-cf2970199b37
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096687504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3096687504
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.4064997073
Short name T2830
Test name
Test status
Simulation time 6109910667 ps
CPU time 104.95 seconds
Started Jul 14 07:35:42 PM PDT 24
Finished Jul 14 07:37:28 PM PDT 24
Peak memory 575404 kb
Host smart-8e3de6dc-c311-4396-ad38-a5cd6bf23496
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064997073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.4064997073
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.909757597
Short name T2473
Test name
Test status
Simulation time 52078919 ps
CPU time 6.78 seconds
Started Jul 14 07:35:43 PM PDT 24
Finished Jul 14 07:35:50 PM PDT 24
Peak memory 575228 kb
Host smart-42f0f320-f630-47bb-9120-6a505539e64a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909757597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays
.909757597
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all.1986892119
Short name T525
Test name
Test status
Simulation time 818037951 ps
CPU time 69.54 seconds
Started Jul 14 07:35:50 PM PDT 24
Finished Jul 14 07:37:00 PM PDT 24
Peak memory 575460 kb
Host smart-e436c8c6-a438-4b8c-b5af-9f7293a2d4d9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986892119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1986892119
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.2303822225
Short name T1410
Test name
Test status
Simulation time 4545139816 ps
CPU time 162.33 seconds
Started Jul 14 07:35:50 PM PDT 24
Finished Jul 14 07:38:33 PM PDT 24
Peak memory 575632 kb
Host smart-3ff5f705-67ac-4896-93a5-3438a2262a88
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303822225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2303822225
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.140769421
Short name T515
Test name
Test status
Simulation time 3109688101 ps
CPU time 232.45 seconds
Started Jul 14 07:35:47 PM PDT 24
Finished Jul 14 07:39:40 PM PDT 24
Peak memory 575476 kb
Host smart-e51ea881-9435-48d1-8e02-c86f4cbfb049
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140769421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_
with_rand_reset.140769421
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.3463178349
Short name T2328
Test name
Test status
Simulation time 781469613 ps
CPU time 276.87 seconds
Started Jul 14 07:35:47 PM PDT 24
Finished Jul 14 07:40:25 PM PDT 24
Peak memory 575504 kb
Host smart-e524a65b-b194-4df2-9808-030c653122ec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463178349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al
l_with_reset_error.3463178349
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.1174481666
Short name T650
Test name
Test status
Simulation time 312069722 ps
CPU time 32.1 seconds
Started Jul 14 07:35:49 PM PDT 24
Finished Jul 14 07:36:21 PM PDT 24
Peak memory 575432 kb
Host smart-53406d6a-f681-402c-bf7b-db0fa686db6a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174481666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1174481666
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_access_same_device.2486176643
Short name T820
Test name
Test status
Simulation time 925923101 ps
CPU time 37.6 seconds
Started Jul 14 07:36:02 PM PDT 24
Finished Jul 14 07:36:40 PM PDT 24
Peak memory 575396 kb
Host smart-e1dea5b4-b234-4013-a339-9b84b7ad4ff9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486176643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device
.2486176643
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.3412606837
Short name T1691
Test name
Test status
Simulation time 162833039097 ps
CPU time 3065.67 seconds
Started Jul 14 07:36:01 PM PDT 24
Finished Jul 14 08:27:08 PM PDT 24
Peak memory 575528 kb
Host smart-1bb53854-ddeb-4451-9d37-c74c0aa9afd8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412606837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_
device_slow_rsp.3412606837
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.2718073337
Short name T2904
Test name
Test status
Simulation time 301135624 ps
CPU time 30.11 seconds
Started Jul 14 07:36:00 PM PDT 24
Finished Jul 14 07:36:31 PM PDT 24
Peak memory 575336 kb
Host smart-28e2889e-8053-489d-95b0-6d262b427d70
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718073337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add
r.2718073337
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_error_random.75903258
Short name T1469
Test name
Test status
Simulation time 269913044 ps
CPU time 26.87 seconds
Started Jul 14 07:36:00 PM PDT 24
Finished Jul 14 07:36:27 PM PDT 24
Peak memory 575304 kb
Host smart-ec6baacf-89ac-4b0a-baca-fd04b1f53e97
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75903258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.75903258
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random.2278717325
Short name T2374
Test name
Test status
Simulation time 441492059 ps
CPU time 39.95 seconds
Started Jul 14 07:35:53 PM PDT 24
Finished Jul 14 07:36:34 PM PDT 24
Peak memory 575388 kb
Host smart-c1293b5f-c57b-4d11-81e5-d5f14957013a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278717325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.2278717325
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.805161244
Short name T2213
Test name
Test status
Simulation time 70835960866 ps
CPU time 800.92 seconds
Started Jul 14 07:35:54 PM PDT 24
Finished Jul 14 07:49:16 PM PDT 24
Peak memory 575528 kb
Host smart-be909cce-0a90-4179-8966-43e9bb2c08bc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805161244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.805161244
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.1121693428
Short name T611
Test name
Test status
Simulation time 28792322871 ps
CPU time 529.3 seconds
Started Jul 14 07:35:54 PM PDT 24
Finished Jul 14 07:44:44 PM PDT 24
Peak memory 575488 kb
Host smart-f4b9edaf-c146-4b51-a133-25895a6a84ed
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121693428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1121693428
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.458855407
Short name T568
Test name
Test status
Simulation time 334752208 ps
CPU time 33.53 seconds
Started Jul 14 07:35:54 PM PDT 24
Finished Jul 14 07:36:28 PM PDT 24
Peak memory 575396 kb
Host smart-59c1c21c-ffba-4767-ac78-1cec8112a35f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458855407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_dela
ys.458855407
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_same_source.963980976
Short name T2111
Test name
Test status
Simulation time 426995971 ps
CPU time 31.06 seconds
Started Jul 14 07:36:02 PM PDT 24
Finished Jul 14 07:36:33 PM PDT 24
Peak memory 575280 kb
Host smart-ebcddb53-1722-4e30-94b6-841e65e6c137
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963980976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.963980976
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke.1888904327
Short name T1331
Test name
Test status
Simulation time 227220107 ps
CPU time 9.27 seconds
Started Jul 14 07:35:49 PM PDT 24
Finished Jul 14 07:35:58 PM PDT 24
Peak memory 575276 kb
Host smart-112fc2d5-7835-4b63-aecb-bf036697c0a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888904327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1888904327
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.202449563
Short name T1869
Test name
Test status
Simulation time 5863065522 ps
CPU time 65.64 seconds
Started Jul 14 07:35:48 PM PDT 24
Finished Jul 14 07:36:54 PM PDT 24
Peak memory 574160 kb
Host smart-2c4416d6-06b9-4689-9063-f89eabe50e49
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202449563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.202449563
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.1523849945
Short name T1482
Test name
Test status
Simulation time 5062505847 ps
CPU time 96.84 seconds
Started Jul 14 07:35:46 PM PDT 24
Finished Jul 14 07:37:23 PM PDT 24
Peak memory 575380 kb
Host smart-0830789e-7545-4bb9-a7ef-832cdafe20a1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523849945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1523849945
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.4080793000
Short name T1354
Test name
Test status
Simulation time 50417802 ps
CPU time 6.77 seconds
Started Jul 14 07:35:48 PM PDT 24
Finished Jul 14 07:35:55 PM PDT 24
Peak memory 575296 kb
Host smart-cc18ecfe-2a14-4ae4-b905-458613db1866
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080793000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay
s.4080793000
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all.1015422269
Short name T2887
Test name
Test status
Simulation time 544963403 ps
CPU time 43.32 seconds
Started Jul 14 07:36:02 PM PDT 24
Finished Jul 14 07:36:46 PM PDT 24
Peak memory 575468 kb
Host smart-3e6d85a8-2734-4225-9137-e2a782a4f220
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015422269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1015422269
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.4048480267
Short name T1458
Test name
Test status
Simulation time 4229300479 ps
CPU time 343.88 seconds
Started Jul 14 07:36:04 PM PDT 24
Finished Jul 14 07:41:48 PM PDT 24
Peak memory 575516 kb
Host smart-84e2b8d2-795b-49e4-8acb-d5763bb419d2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048480267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.4048480267
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3065101168
Short name T847
Test name
Test status
Simulation time 297957397 ps
CPU time 173.71 seconds
Started Jul 14 07:36:01 PM PDT 24
Finished Jul 14 07:38:55 PM PDT 24
Peak memory 575484 kb
Host smart-3b0b775c-3d79-4574-848e-a433618251d3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065101168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all
_with_rand_reset.3065101168
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.2788377682
Short name T2341
Test name
Test status
Simulation time 926136609 ps
CPU time 231.17 seconds
Started Jul 14 07:36:01 PM PDT 24
Finished Jul 14 07:39:52 PM PDT 24
Peak memory 575416 kb
Host smart-c5f62449-e4ef-4363-86a4-e64bf6d921dd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788377682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al
l_with_reset_error.2788377682
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.257935534
Short name T2405
Test name
Test status
Simulation time 284004367 ps
CPU time 33.43 seconds
Started Jul 14 07:36:02 PM PDT 24
Finished Jul 14 07:36:36 PM PDT 24
Peak memory 575376 kb
Host smart-8c61de79-1947-4c4b-a6f1-5b01ac2f2909
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257935534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.257935534
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_access_same_device.2429913805
Short name T2465
Test name
Test status
Simulation time 273550023 ps
CPU time 15.55 seconds
Started Jul 14 07:36:09 PM PDT 24
Finished Jul 14 07:36:25 PM PDT 24
Peak memory 575320 kb
Host smart-b4ed7ae1-9440-4f32-9439-884b78931320
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429913805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device
.2429913805
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.4021746326
Short name T494
Test name
Test status
Simulation time 191956396234 ps
CPU time 3465.21 seconds
Started Jul 14 07:36:09 PM PDT 24
Finished Jul 14 08:33:55 PM PDT 24
Peak memory 575592 kb
Host smart-dc009320-c770-4c21-aa66-2597cc6fcf20
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021746326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_
device_slow_rsp.4021746326
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.4067557551
Short name T2774
Test name
Test status
Simulation time 517106129 ps
CPU time 22.36 seconds
Started Jul 14 07:36:11 PM PDT 24
Finished Jul 14 07:36:33 PM PDT 24
Peak memory 575324 kb
Host smart-ad84d31f-a734-4960-b811-9bd806ba5355
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067557551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add
r.4067557551
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_error_random.3962056196
Short name T2639
Test name
Test status
Simulation time 407247667 ps
CPU time 15.66 seconds
Started Jul 14 07:36:10 PM PDT 24
Finished Jul 14 07:36:26 PM PDT 24
Peak memory 575320 kb
Host smart-09944a80-3e67-4c62-94e4-6d046349df58
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962056196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.3962056196
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random.1229858652
Short name T490
Test name
Test status
Simulation time 504519234 ps
CPU time 48.17 seconds
Started Jul 14 07:36:00 PM PDT 24
Finished Jul 14 07:36:49 PM PDT 24
Peak memory 575320 kb
Host smart-9aaa4693-9896-49dd-8d9e-4bb7ae2d7209
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229858652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.1229858652
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.2870388442
Short name T2230
Test name
Test status
Simulation time 61530917457 ps
CPU time 675.56 seconds
Started Jul 14 07:36:02 PM PDT 24
Finished Jul 14 07:47:18 PM PDT 24
Peak memory 575452 kb
Host smart-2b0c80bf-c2d2-4703-82d7-32ed9b826884
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870388442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2870388442
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.2754808353
Short name T1562
Test name
Test status
Simulation time 26323948957 ps
CPU time 444.61 seconds
Started Jul 14 07:36:09 PM PDT 24
Finished Jul 14 07:43:34 PM PDT 24
Peak memory 575504 kb
Host smart-d2203954-6f02-416e-81b4-be5a0e0e19dc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754808353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2754808353
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.2580921105
Short name T2510
Test name
Test status
Simulation time 53525814 ps
CPU time 7.87 seconds
Started Jul 14 07:36:01 PM PDT 24
Finished Jul 14 07:36:09 PM PDT 24
Peak memory 574072 kb
Host smart-3615a490-315f-414b-875a-1c6dbfb04c54
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580921105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del
ays.2580921105
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_same_source.1076001816
Short name T612
Test name
Test status
Simulation time 343230050 ps
CPU time 23.98 seconds
Started Jul 14 07:36:12 PM PDT 24
Finished Jul 14 07:36:36 PM PDT 24
Peak memory 575348 kb
Host smart-b77f859f-c996-4fb4-a1b6-537bf319d745
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076001816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1076001816
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke.2325266691
Short name T1560
Test name
Test status
Simulation time 39367960 ps
CPU time 5.99 seconds
Started Jul 14 07:36:00 PM PDT 24
Finished Jul 14 07:36:06 PM PDT 24
Peak memory 575280 kb
Host smart-b4d0ddeb-63e7-4efd-b612-c10589e25f3a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325266691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2325266691
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.2711259949
Short name T1380
Test name
Test status
Simulation time 8929122196 ps
CPU time 97.95 seconds
Started Jul 14 07:36:00 PM PDT 24
Finished Jul 14 07:37:38 PM PDT 24
Peak memory 575412 kb
Host smart-ef17bb21-741f-4399-a9eb-bc8ac4759991
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711259949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2711259949
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.977755294
Short name T2330
Test name
Test status
Simulation time 4210703880 ps
CPU time 76.96 seconds
Started Jul 14 07:36:03 PM PDT 24
Finished Jul 14 07:37:21 PM PDT 24
Peak memory 575336 kb
Host smart-50ff6d16-11c6-42ea-89d2-6cfac56fd27d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977755294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.977755294
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.226374395
Short name T1425
Test name
Test status
Simulation time 42765724 ps
CPU time 5.79 seconds
Started Jul 14 07:36:02 PM PDT 24
Finished Jul 14 07:36:09 PM PDT 24
Peak memory 575236 kb
Host smart-3c67d5cc-d566-4edd-a655-87a983cb493c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226374395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays
.226374395
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all.2919588568
Short name T2763
Test name
Test status
Simulation time 5697456129 ps
CPU time 200.91 seconds
Started Jul 14 07:36:10 PM PDT 24
Finished Jul 14 07:39:32 PM PDT 24
Peak memory 575524 kb
Host smart-b4693387-2c2a-45b3-af6b-1e3217e55856
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919588568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2919588568
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.2703273751
Short name T2379
Test name
Test status
Simulation time 2991266652 ps
CPU time 242.18 seconds
Started Jul 14 07:36:08 PM PDT 24
Finished Jul 14 07:40:11 PM PDT 24
Peak memory 575520 kb
Host smart-f4734f2c-e470-40a7-b57c-4680cd13864c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703273751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2703273751
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.1568359709
Short name T2432
Test name
Test status
Simulation time 5686717 ps
CPU time 3.85 seconds
Started Jul 14 07:36:11 PM PDT 24
Finished Jul 14 07:36:15 PM PDT 24
Peak memory 565664 kb
Host smart-44910121-6437-421a-a916-cca0e97a7d52
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568359709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all
_with_rand_reset.1568359709
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.1160198128
Short name T1920
Test name
Test status
Simulation time 2022775388 ps
CPU time 269.27 seconds
Started Jul 14 07:36:07 PM PDT 24
Finished Jul 14 07:40:36 PM PDT 24
Peak memory 575224 kb
Host smart-40342db4-8aca-4a9b-b08d-de27434764ac
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160198128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al
l_with_reset_error.1160198128
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.3490183601
Short name T1776
Test name
Test status
Simulation time 115278312 ps
CPU time 15.27 seconds
Started Jul 14 07:36:08 PM PDT 24
Finished Jul 14 07:36:24 PM PDT 24
Peak memory 575352 kb
Host smart-ac31a429-cbca-4b1a-bc09-1fa61dc4467f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490183601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.3490183601
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_access_same_device.1870865035
Short name T1598
Test name
Test status
Simulation time 2077605859 ps
CPU time 88.18 seconds
Started Jul 14 07:36:18 PM PDT 24
Finished Jul 14 07:37:47 PM PDT 24
Peak memory 575356 kb
Host smart-f8c4146c-f855-4f63-bba5-18a867a30c19
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870865035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device
.1870865035
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.1970928555
Short name T2062
Test name
Test status
Simulation time 158276146705 ps
CPU time 3072.45 seconds
Started Jul 14 07:36:17 PM PDT 24
Finished Jul 14 08:27:30 PM PDT 24
Peak memory 575560 kb
Host smart-d8c7b5ae-6c6e-4a89-9856-6c8e72b7a1b3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970928555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_
device_slow_rsp.1970928555
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.360153628
Short name T2039
Test name
Test status
Simulation time 207076530 ps
CPU time 22.47 seconds
Started Jul 14 07:36:16 PM PDT 24
Finished Jul 14 07:36:39 PM PDT 24
Peak memory 575360 kb
Host smart-9921cd3c-44f1-4da9-ac74-df814ba41b9d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360153628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr
.360153628
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_error_random.163450883
Short name T2244
Test name
Test status
Simulation time 1557174266 ps
CPU time 54.17 seconds
Started Jul 14 07:36:18 PM PDT 24
Finished Jul 14 07:37:12 PM PDT 24
Peak memory 575296 kb
Host smart-d5d087ac-a102-4d0f-bed0-f7c3404ceae9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163450883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.163450883
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random.961847627
Short name T1990
Test name
Test status
Simulation time 458839893 ps
CPU time 18.81 seconds
Started Jul 14 07:36:17 PM PDT 24
Finished Jul 14 07:36:37 PM PDT 24
Peak memory 575348 kb
Host smart-751320cd-cdea-4feb-9c56-011c75973281
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961847627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.961847627
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.3317639638
Short name T1602
Test name
Test status
Simulation time 118405053159 ps
CPU time 1454.34 seconds
Started Jul 14 07:36:19 PM PDT 24
Finished Jul 14 08:00:34 PM PDT 24
Peak memory 575504 kb
Host smart-68fd0f87-4c5a-4553-a655-2e4ef560200b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317639638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3317639638
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.1052534496
Short name T2585
Test name
Test status
Simulation time 55132677370 ps
CPU time 1073.08 seconds
Started Jul 14 07:36:21 PM PDT 24
Finished Jul 14 07:54:15 PM PDT 24
Peak memory 575656 kb
Host smart-d94983f0-1a4b-4597-a91b-05c2ac6aa092
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052534496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1052534496
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.832941744
Short name T2329
Test name
Test status
Simulation time 263260073 ps
CPU time 26.73 seconds
Started Jul 14 07:36:17 PM PDT 24
Finished Jul 14 07:36:45 PM PDT 24
Peak memory 575312 kb
Host smart-fbca88ab-0ee1-41af-8feb-7402855c8edb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832941744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_dela
ys.832941744
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_same_source.1848350278
Short name T1588
Test name
Test status
Simulation time 659488435 ps
CPU time 21.84 seconds
Started Jul 14 07:36:18 PM PDT 24
Finished Jul 14 07:36:41 PM PDT 24
Peak memory 575316 kb
Host smart-f0d88f6d-1463-44a7-a8f6-c4f5472f9a45
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848350278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1848350278
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke.677344435
Short name T2515
Test name
Test status
Simulation time 187210578 ps
CPU time 9.76 seconds
Started Jul 14 07:36:09 PM PDT 24
Finished Jul 14 07:36:19 PM PDT 24
Peak memory 574244 kb
Host smart-5fec5d94-92eb-435a-9160-361d7b59d4cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677344435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.677344435
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.2415212028
Short name T2082
Test name
Test status
Simulation time 9534984334 ps
CPU time 110.69 seconds
Started Jul 14 07:36:19 PM PDT 24
Finished Jul 14 07:38:10 PM PDT 24
Peak memory 575428 kb
Host smart-f62b5db0-a7db-42c0-9f49-1659dfe5c22a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415212028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2415212028
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.3400387660
Short name T1426
Test name
Test status
Simulation time 4537440662 ps
CPU time 77.79 seconds
Started Jul 14 07:36:16 PM PDT 24
Finished Jul 14 07:37:34 PM PDT 24
Peak memory 575428 kb
Host smart-3176bced-93b7-41cd-b6e7-4009f35a6988
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400387660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3400387660
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.2381217832
Short name T2369
Test name
Test status
Simulation time 48530252 ps
CPU time 5.94 seconds
Started Jul 14 07:36:09 PM PDT 24
Finished Jul 14 07:36:15 PM PDT 24
Peak memory 573988 kb
Host smart-b3769ff2-aeb9-4bbd-a9d4-4dc82b41cc7a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381217832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay
s.2381217832
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all.1367079189
Short name T2365
Test name
Test status
Simulation time 4792668013 ps
CPU time 364.81 seconds
Started Jul 14 07:36:17 PM PDT 24
Finished Jul 14 07:42:22 PM PDT 24
Peak memory 575624 kb
Host smart-089efdea-7dc1-4c0e-ab8f-7d126f1516a9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367079189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1367079189
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.272028340
Short name T1533
Test name
Test status
Simulation time 2146968324 ps
CPU time 146.36 seconds
Started Jul 14 07:36:17 PM PDT 24
Finished Jul 14 07:38:44 PM PDT 24
Peak memory 575476 kb
Host smart-8400af8b-e1a7-4d6f-acd1-81d4e2f7e8ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272028340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.272028340
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.3538133812
Short name T428
Test name
Test status
Simulation time 2890141543 ps
CPU time 428.83 seconds
Started Jul 14 07:36:17 PM PDT 24
Finished Jul 14 07:43:27 PM PDT 24
Peak memory 575520 kb
Host smart-4d801ceb-97ef-4fff-974a-6c53138d61fe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538133812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all
_with_rand_reset.3538133812
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.1264873856
Short name T1991
Test name
Test status
Simulation time 101429194 ps
CPU time 26.79 seconds
Started Jul 14 07:36:36 PM PDT 24
Finished Jul 14 07:37:03 PM PDT 24
Peak memory 574168 kb
Host smart-cf396cee-d129-4e29-b664-de84fe040037
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264873856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al
l_with_reset_error.1264873856
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.3516439157
Short name T2702
Test name
Test status
Simulation time 73604377 ps
CPU time 11.37 seconds
Started Jul 14 07:36:21 PM PDT 24
Finished Jul 14 07:36:33 PM PDT 24
Peak memory 575392 kb
Host smart-2c7095f3-b7c0-4381-9041-1772abceadc3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516439157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3516439157
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_access_same_device.4023541000
Short name T528
Test name
Test status
Simulation time 1168632278 ps
CPU time 85.28 seconds
Started Jul 14 07:36:23 PM PDT 24
Finished Jul 14 07:37:49 PM PDT 24
Peak memory 575344 kb
Host smart-1bbbe5e2-c9c2-48a2-bd18-2a0ee247d640
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023541000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device
.4023541000
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.3956677453
Short name T2674
Test name
Test status
Simulation time 24643133780 ps
CPU time 419.11 seconds
Started Jul 14 07:36:21 PM PDT 24
Finished Jul 14 07:43:21 PM PDT 24
Peak memory 575488 kb
Host smart-bf10641b-46f2-4b84-9219-5dc6f30f648b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956677453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_
device_slow_rsp.3956677453
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.1564474781
Short name T2828
Test name
Test status
Simulation time 895467361 ps
CPU time 38.14 seconds
Started Jul 14 07:36:31 PM PDT 24
Finished Jul 14 07:37:09 PM PDT 24
Peak memory 575284 kb
Host smart-7517938d-11b8-4f5d-8789-6753f4b05043
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564474781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add
r.1564474781
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_error_random.2360195047
Short name T2464
Test name
Test status
Simulation time 285746473 ps
CPU time 25.01 seconds
Started Jul 14 07:36:30 PM PDT 24
Finished Jul 14 07:36:55 PM PDT 24
Peak memory 575264 kb
Host smart-bff939ba-f5e0-4c51-8886-0af75565f677
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360195047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2360195047
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random.2020938030
Short name T1516
Test name
Test status
Simulation time 401213539 ps
CPU time 16.18 seconds
Started Jul 14 07:36:37 PM PDT 24
Finished Jul 14 07:36:55 PM PDT 24
Peak memory 575340 kb
Host smart-3f76f716-e053-428a-91b8-efc8c5e3328e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020938030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.2020938030
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.430656870
Short name T556
Test name
Test status
Simulation time 84871727642 ps
CPU time 1096.54 seconds
Started Jul 14 07:36:22 PM PDT 24
Finished Jul 14 07:54:39 PM PDT 24
Peak memory 575468 kb
Host smart-a8730962-d17b-41eb-9997-1f5d5d4bdc6e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430656870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.430656870
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.3532816808
Short name T529
Test name
Test status
Simulation time 10736473849 ps
CPU time 188.9 seconds
Started Jul 14 07:36:37 PM PDT 24
Finished Jul 14 07:39:47 PM PDT 24
Peak memory 575508 kb
Host smart-51fe1cf0-7dd4-4dd2-905f-65f4c858df8d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532816808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3532816808
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.2582667025
Short name T1762
Test name
Test status
Simulation time 277982457 ps
CPU time 23.98 seconds
Started Jul 14 07:36:22 PM PDT 24
Finished Jul 14 07:36:46 PM PDT 24
Peak memory 575264 kb
Host smart-201f3719-0ba4-43d0-bceb-6423d6824438
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582667025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del
ays.2582667025
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_same_source.3732605690
Short name T1498
Test name
Test status
Simulation time 383234114 ps
CPU time 29.02 seconds
Started Jul 14 07:36:30 PM PDT 24
Finished Jul 14 07:36:59 PM PDT 24
Peak memory 575344 kb
Host smart-602eee04-37f5-4fbd-bff0-d91be94a64ef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732605690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3732605690
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke.2789726217
Short name T539
Test name
Test status
Simulation time 42690322 ps
CPU time 5.8 seconds
Started Jul 14 07:36:36 PM PDT 24
Finished Jul 14 07:36:43 PM PDT 24
Peak memory 574060 kb
Host smart-5c31f5e3-274b-449c-882b-31a6e744ea4f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789726217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2789726217
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.271759103
Short name T2728
Test name
Test status
Simulation time 7011590573 ps
CPU time 80.2 seconds
Started Jul 14 07:36:37 PM PDT 24
Finished Jul 14 07:37:58 PM PDT 24
Peak memory 574156 kb
Host smart-b2b2f65e-dba3-438d-acba-a6245982e88c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271759103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.271759103
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.832396770
Short name T2449
Test name
Test status
Simulation time 4436670235 ps
CPU time 78.1 seconds
Started Jul 14 07:36:21 PM PDT 24
Finished Jul 14 07:37:40 PM PDT 24
Peak memory 574120 kb
Host smart-6ac26b98-21b0-43ec-a57e-e44aa9b4b4c0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832396770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.832396770
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.2484588689
Short name T1932
Test name
Test status
Simulation time 41133057 ps
CPU time 5.87 seconds
Started Jul 14 07:36:37 PM PDT 24
Finished Jul 14 07:36:44 PM PDT 24
Peak memory 575260 kb
Host smart-4c2a7348-9b31-428a-9fb3-3215f5506384
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484588689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delay
s.2484588689
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all.2194355792
Short name T496
Test name
Test status
Simulation time 8876143886 ps
CPU time 287.31 seconds
Started Jul 14 07:36:32 PM PDT 24
Finished Jul 14 07:41:20 PM PDT 24
Peak memory 575588 kb
Host smart-3945fba6-bbc4-4c97-81c7-852ac0ff524b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194355792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2194355792
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.375164979
Short name T1702
Test name
Test status
Simulation time 424892920 ps
CPU time 32.87 seconds
Started Jul 14 07:36:37 PM PDT 24
Finished Jul 14 07:37:10 PM PDT 24
Peak memory 575316 kb
Host smart-b5c48230-558d-47cc-904a-571dd60d50e5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375164979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.375164979
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.3250048219
Short name T876
Test name
Test status
Simulation time 299589956 ps
CPU time 185.36 seconds
Started Jul 14 07:36:36 PM PDT 24
Finished Jul 14 07:39:42 PM PDT 24
Peak memory 575428 kb
Host smart-5a44e78b-8518-4ce1-89a9-8642bd48c63b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250048219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all
_with_rand_reset.3250048219
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.3681866235
Short name T2236
Test name
Test status
Simulation time 2277461396 ps
CPU time 305.95 seconds
Started Jul 14 07:36:31 PM PDT 24
Finished Jul 14 07:41:37 PM PDT 24
Peak memory 575492 kb
Host smart-d90fe5cd-8126-4f6b-8e5c-31882fc03e2c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681866235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al
l_with_reset_error.3681866235
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.33866408
Short name T2686
Test name
Test status
Simulation time 277234351 ps
CPU time 12.58 seconds
Started Jul 14 07:36:32 PM PDT 24
Finished Jul 14 07:36:45 PM PDT 24
Peak memory 575372 kb
Host smart-f39ae56a-cf75-4854-9db7-df194abeb639
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33866408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.33866408
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_access_same_device.4005319407
Short name T1459
Test name
Test status
Simulation time 791618998 ps
CPU time 60.03 seconds
Started Jul 14 07:36:39 PM PDT 24
Finished Jul 14 07:37:40 PM PDT 24
Peak memory 575332 kb
Host smart-c4d3a62b-272f-4d09-8c9a-9f5a1923d958
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005319407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device
.4005319407
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.3411043342
Short name T2256
Test name
Test status
Simulation time 62937812857 ps
CPU time 1179.86 seconds
Started Jul 14 07:36:38 PM PDT 24
Finished Jul 14 07:56:19 PM PDT 24
Peak memory 575588 kb
Host smart-6e03adce-2aa5-4efa-bcca-c3e8e5315ef6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411043342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_
device_slow_rsp.3411043342
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.1452823529
Short name T1393
Test name
Test status
Simulation time 216529489 ps
CPU time 25.29 seconds
Started Jul 14 07:36:38 PM PDT 24
Finished Jul 14 07:37:04 PM PDT 24
Peak memory 575324 kb
Host smart-aa1136f0-95ab-41e0-a5f3-846c62a346a6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452823529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add
r.1452823529
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_error_random.2389241433
Short name T1421
Test name
Test status
Simulation time 301694026 ps
CPU time 13.78 seconds
Started Jul 14 07:36:37 PM PDT 24
Finished Jul 14 07:36:51 PM PDT 24
Peak memory 575292 kb
Host smart-431ae84e-ef0f-4020-914d-9561e6a46d7b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389241433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2389241433
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random.610636787
Short name T2029
Test name
Test status
Simulation time 1818072192 ps
CPU time 58.25 seconds
Started Jul 14 07:36:39 PM PDT 24
Finished Jul 14 07:37:38 PM PDT 24
Peak memory 575368 kb
Host smart-65693ab0-792c-4957-8a3c-11db5a54931c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610636787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.610636787
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.2083363640
Short name T2800
Test name
Test status
Simulation time 61163523600 ps
CPU time 607.58 seconds
Started Jul 14 07:36:40 PM PDT 24
Finished Jul 14 07:46:48 PM PDT 24
Peak memory 575472 kb
Host smart-115e4c0c-6574-463e-96b0-d08da8deca11
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083363640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2083363640
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.1239775128
Short name T518
Test name
Test status
Simulation time 43074858516 ps
CPU time 820.82 seconds
Started Jul 14 07:36:37 PM PDT 24
Finished Jul 14 07:50:19 PM PDT 24
Peak memory 575440 kb
Host smart-bf7b8f47-7050-4164-ad80-7c48d1d9c428
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239775128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1239775128
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.2970351509
Short name T447
Test name
Test status
Simulation time 582917462 ps
CPU time 51.91 seconds
Started Jul 14 07:36:39 PM PDT 24
Finished Jul 14 07:37:32 PM PDT 24
Peak memory 575340 kb
Host smart-b834f39a-6bd7-42c4-9be2-de33462a3596
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970351509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del
ays.2970351509
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_same_source.3592958574
Short name T1500
Test name
Test status
Simulation time 102389384 ps
CPU time 9.23 seconds
Started Jul 14 07:36:40 PM PDT 24
Finished Jul 14 07:36:49 PM PDT 24
Peak memory 575312 kb
Host smart-e8abe104-7030-4e7c-ad52-3799029780bf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592958574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3592958574
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke.514130764
Short name T1997
Test name
Test status
Simulation time 251501748 ps
CPU time 9.52 seconds
Started Jul 14 07:36:29 PM PDT 24
Finished Jul 14 07:36:39 PM PDT 24
Peak memory 575268 kb
Host smart-ab339025-0a3a-4c33-b291-3ec8894e568d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514130764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.514130764
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.189167235
Short name T2611
Test name
Test status
Simulation time 6484229469 ps
CPU time 69.8 seconds
Started Jul 14 07:36:28 PM PDT 24
Finished Jul 14 07:37:38 PM PDT 24
Peak memory 574076 kb
Host smart-2bae0c0b-fc63-4a6e-a154-77607fb3d2b8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189167235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.189167235
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.1219966390
Short name T2601
Test name
Test status
Simulation time 4868115324 ps
CPU time 91.15 seconds
Started Jul 14 07:36:39 PM PDT 24
Finished Jul 14 07:38:10 PM PDT 24
Peak memory 574148 kb
Host smart-ff7f586b-e7e6-47f9-adc5-9f2957732791
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219966390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1219966390
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3649119412
Short name T1889
Test name
Test status
Simulation time 45785908 ps
CPU time 6.09 seconds
Started Jul 14 07:36:31 PM PDT 24
Finished Jul 14 07:36:38 PM PDT 24
Peak memory 574060 kb
Host smart-ec107c37-2fe8-44a7-8be3-49f1875b2a81
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649119412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay
s.3649119412
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all.747245452
Short name T2681
Test name
Test status
Simulation time 3773189324 ps
CPU time 160.32 seconds
Started Jul 14 07:36:39 PM PDT 24
Finished Jul 14 07:39:20 PM PDT 24
Peak memory 575576 kb
Host smart-efff6c6d-9fae-4bd7-aac3-6ff17c719e84
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747245452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.747245452
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.223897001
Short name T2784
Test name
Test status
Simulation time 62852358 ps
CPU time 34.25 seconds
Started Jul 14 07:36:46 PM PDT 24
Finished Jul 14 07:37:20 PM PDT 24
Peak memory 575480 kb
Host smart-a989da10-c7c8-4f6d-8780-2ea2f8839fe3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223897001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_
with_rand_reset.223897001
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.111981628
Short name T2206
Test name
Test status
Simulation time 154861224 ps
CPU time 42.74 seconds
Started Jul 14 07:36:53 PM PDT 24
Finished Jul 14 07:37:36 PM PDT 24
Peak memory 575460 kb
Host smart-2038155d-1813-4214-aedd-da6b8714b0f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111981628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all
_with_reset_error.111981628
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.581252117
Short name T2589
Test name
Test status
Simulation time 579764140 ps
CPU time 26.11 seconds
Started Jul 14 07:36:39 PM PDT 24
Finished Jul 14 07:37:05 PM PDT 24
Peak memory 575392 kb
Host smart-42ba8de1-f80a-4751-921a-3fd785e8cbbd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581252117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.581252117
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/5.chip_csr_rw.3495218092
Short name T2276
Test name
Test status
Simulation time 5064643616 ps
CPU time 342.31 seconds
Started Jul 14 07:28:12 PM PDT 24
Finished Jul 14 07:33:55 PM PDT 24
Peak memory 598432 kb
Host smart-18125c89-d2fd-48ff-b9be-1b1bfc23665e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495218092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.3495218092
Directory /workspace/5.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.1926099986
Short name T2352
Test name
Test status
Simulation time 17181624561 ps
CPU time 1812.59 seconds
Started Jul 14 07:27:55 PM PDT 24
Finished Jul 14 07:58:08 PM PDT 24
Peak memory 593376 kb
Host smart-d6cd2887-01a8-4b8b-a6a5-85aadd68e6c7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926099986 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.1926099986
Directory /workspace/5.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.chip_tl_errors.3887913173
Short name T2643
Test name
Test status
Simulation time 4476791992 ps
CPU time 345.45 seconds
Started Jul 14 07:27:59 PM PDT 24
Finished Jul 14 07:33:45 PM PDT 24
Peak memory 598728 kb
Host smart-24aa5ed0-1d4b-451b-ab50-dfd8fcac1984
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887913173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.3887913173
Directory /workspace/5.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_access_same_device.900897935
Short name T685
Test name
Test status
Simulation time 228952578 ps
CPU time 22.4 seconds
Started Jul 14 07:28:08 PM PDT 24
Finished Jul 14 07:28:31 PM PDT 24
Peak memory 575348 kb
Host smart-61ce0470-d282-4298-baa6-97af30bceb15
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900897935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.900897935
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.739423519
Short name T1673
Test name
Test status
Simulation time 52304073858 ps
CPU time 937.75 seconds
Started Jul 14 07:28:15 PM PDT 24
Finished Jul 14 07:43:53 PM PDT 24
Peak memory 575516 kb
Host smart-74bb12c8-aed6-47d5-b09d-e4ca64de5e13
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739423519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_de
vice_slow_rsp.739423519
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.2429345999
Short name T2787
Test name
Test status
Simulation time 36638906 ps
CPU time 6.91 seconds
Started Jul 14 07:28:10 PM PDT 24
Finished Jul 14 07:28:18 PM PDT 24
Peak memory 575280 kb
Host smart-aa8e4d55-1917-4024-aa9b-c48bc3fa5e4a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429345999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr
.2429345999
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_error_random.341506169
Short name T1845
Test name
Test status
Simulation time 442857476 ps
CPU time 37.01 seconds
Started Jul 14 07:28:07 PM PDT 24
Finished Jul 14 07:28:44 PM PDT 24
Peak memory 575280 kb
Host smart-ddfe5402-6496-4bd6-8859-04544ca846de
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341506169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.341506169
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random.411110752
Short name T549
Test name
Test status
Simulation time 740032521 ps
CPU time 30.17 seconds
Started Jul 14 07:28:00 PM PDT 24
Finished Jul 14 07:28:31 PM PDT 24
Peak memory 575376 kb
Host smart-91f8cba5-005c-44de-908a-97537f58142c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411110752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.411110752
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.1626130861
Short name T2512
Test name
Test status
Simulation time 28616489034 ps
CPU time 299.26 seconds
Started Jul 14 07:28:03 PM PDT 24
Finished Jul 14 07:33:03 PM PDT 24
Peak memory 575496 kb
Host smart-8f6e8e62-a860-4d49-bd7a-ba5476fd5c1a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626130861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1626130861
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.2447295337
Short name T1715
Test name
Test status
Simulation time 9633560400 ps
CPU time 173.59 seconds
Started Jul 14 07:28:15 PM PDT 24
Finished Jul 14 07:31:09 PM PDT 24
Peak memory 575492 kb
Host smart-f64b3d63-0e6b-438f-add1-3115a1eee52f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447295337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2447295337
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.859601501
Short name T2870
Test name
Test status
Simulation time 569131979 ps
CPU time 48.52 seconds
Started Jul 14 07:28:01 PM PDT 24
Finished Jul 14 07:28:50 PM PDT 24
Peak memory 575308 kb
Host smart-2c4e0d18-9d86-4b0f-9475-ecf4aa36cdef
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859601501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delay
s.859601501
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_same_source.3206952667
Short name T1422
Test name
Test status
Simulation time 1981531362 ps
CPU time 58.99 seconds
Started Jul 14 07:28:11 PM PDT 24
Finished Jul 14 07:29:11 PM PDT 24
Peak memory 575244 kb
Host smart-ad8369f5-f294-4482-8e38-c98c07d50322
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206952667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3206952667
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke.3743614746
Short name T1728
Test name
Test status
Simulation time 41049042 ps
CPU time 6.49 seconds
Started Jul 14 07:27:56 PM PDT 24
Finished Jul 14 07:28:03 PM PDT 24
Peak memory 574044 kb
Host smart-92887a69-20d7-4acc-a798-2a6753ad3d33
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743614746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3743614746
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.1288686382
Short name T2043
Test name
Test status
Simulation time 6320430536 ps
CPU time 72.26 seconds
Started Jul 14 07:28:02 PM PDT 24
Finished Jul 14 07:29:15 PM PDT 24
Peak memory 574228 kb
Host smart-710db5d3-b3f7-42f3-b94a-a00110a36fa7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288686382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.1288686382
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.2555282671
Short name T1327
Test name
Test status
Simulation time 5788182587 ps
CPU time 97.37 seconds
Started Jul 14 07:28:02 PM PDT 24
Finished Jul 14 07:29:40 PM PDT 24
Peak memory 575428 kb
Host smart-e65cec35-c778-4d5c-b086-f6f0dc0c2726
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555282671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2555282671
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.263870095
Short name T1361
Test name
Test status
Simulation time 48244990 ps
CPU time 6.12 seconds
Started Jul 14 07:27:57 PM PDT 24
Finished Jul 14 07:28:04 PM PDT 24
Peak memory 574008 kb
Host smart-b89f7319-1f20-499b-80f5-1ec4972eed24
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263870095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.
263870095
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all.372775031
Short name T2622
Test name
Test status
Simulation time 1904462526 ps
CPU time 166.45 seconds
Started Jul 14 07:28:13 PM PDT 24
Finished Jul 14 07:31:00 PM PDT 24
Peak memory 575484 kb
Host smart-4cfd92aa-fa1a-4bda-97e6-870aaca8d429
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372775031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.372775031
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.178775938
Short name T1981
Test name
Test status
Simulation time 1865929212 ps
CPU time 150.79 seconds
Started Jul 14 07:28:15 PM PDT 24
Finished Jul 14 07:30:47 PM PDT 24
Peak memory 575468 kb
Host smart-7c45d16a-ab05-4ce8-bc8d-6177a8668465
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178775938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.178775938
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.2792137909
Short name T877
Test name
Test status
Simulation time 628543375 ps
CPU time 238 seconds
Started Jul 14 07:28:12 PM PDT 24
Finished Jul 14 07:32:10 PM PDT 24
Peak memory 575460 kb
Host smart-a8c41cbd-cac7-4e47-8fb8-513bd4631afd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792137909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_
with_rand_reset.2792137909
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.2896200082
Short name T2619
Test name
Test status
Simulation time 8232100120 ps
CPU time 756.64 seconds
Started Jul 14 07:28:14 PM PDT 24
Finished Jul 14 07:40:51 PM PDT 24
Peak memory 576604 kb
Host smart-4dfde531-ea7a-400d-b910-aff9f5906a32
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896200082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all
_with_reset_error.2896200082
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.1578738040
Short name T2714
Test name
Test status
Simulation time 1408584454 ps
CPU time 64.27 seconds
Started Jul 14 07:28:06 PM PDT 24
Finished Jul 14 07:29:11 PM PDT 24
Peak memory 575388 kb
Host smart-9df738da-556f-44c6-bb31-c9b8469a02c4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578738040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1578738040
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_access_same_device.268400211
Short name T2759
Test name
Test status
Simulation time 740348299 ps
CPU time 73.88 seconds
Started Jul 14 07:36:56 PM PDT 24
Finished Jul 14 07:38:10 PM PDT 24
Peak memory 575436 kb
Host smart-067c5eb4-cff3-4f47-b4de-045b34227012
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268400211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device.
268400211
Directory /workspace/50.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.275534562
Short name T541
Test name
Test status
Simulation time 36307018018 ps
CPU time 631.94 seconds
Started Jul 14 07:36:54 PM PDT 24
Finished Jul 14 07:47:26 PM PDT 24
Peak memory 575516 kb
Host smart-c3b9ff11-97c7-400d-ae4b-ec1acd3516fd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275534562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_d
evice_slow_rsp.275534562
Directory /workspace/50.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.2009930941
Short name T2531
Test name
Test status
Simulation time 136266899 ps
CPU time 17.26 seconds
Started Jul 14 07:36:53 PM PDT 24
Finished Jul 14 07:37:11 PM PDT 24
Peak memory 575284 kb
Host smart-b551eb2b-8953-428a-8754-a16eeca6f153
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009930941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add
r.2009930941
Directory /workspace/50.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_error_random.1649381851
Short name T2664
Test name
Test status
Simulation time 2204057207 ps
CPU time 77.75 seconds
Started Jul 14 07:36:53 PM PDT 24
Finished Jul 14 07:38:11 PM PDT 24
Peak memory 575428 kb
Host smart-7e90ee85-7353-4f9f-9a8c-b34724e37576
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649381851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.1649381851
Directory /workspace/50.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random.4250965731
Short name T2529
Test name
Test status
Simulation time 327355402 ps
CPU time 32.57 seconds
Started Jul 14 07:36:53 PM PDT 24
Finished Jul 14 07:37:26 PM PDT 24
Peak memory 575372 kb
Host smart-ce09c61a-6920-41dc-ad2b-e69f27ba5b50
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250965731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.4250965731
Directory /workspace/50.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.145194636
Short name T1873
Test name
Test status
Simulation time 10246897791 ps
CPU time 117.71 seconds
Started Jul 14 07:36:55 PM PDT 24
Finished Jul 14 07:38:53 PM PDT 24
Peak memory 575440 kb
Host smart-d40bbc97-b807-4c49-8816-09bb272891b4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145194636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.145194636
Directory /workspace/50.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.685974318
Short name T2392
Test name
Test status
Simulation time 41196457164 ps
CPU time 781.07 seconds
Started Jul 14 07:36:53 PM PDT 24
Finished Jul 14 07:49:55 PM PDT 24
Peak memory 575520 kb
Host smart-40f6b80e-fb1c-480c-97fa-9019757fad15
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685974318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.685974318
Directory /workspace/50.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.537747249
Short name T1552
Test name
Test status
Simulation time 35433138 ps
CPU time 6.03 seconds
Started Jul 14 07:37:00 PM PDT 24
Finished Jul 14 07:37:06 PM PDT 24
Peak memory 574048 kb
Host smart-954e4d53-9a4c-42cd-9311-e41027ab58aa
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537747249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_dela
ys.537747249
Directory /workspace/50.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_same_source.3428098973
Short name T1509
Test name
Test status
Simulation time 230021590 ps
CPU time 18.81 seconds
Started Jul 14 07:36:53 PM PDT 24
Finished Jul 14 07:37:12 PM PDT 24
Peak memory 575328 kb
Host smart-e151244e-b967-4497-8339-7ca7cc5b7d4f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428098973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.3428098973
Directory /workspace/50.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke.3014664305
Short name T2164
Test name
Test status
Simulation time 217691247 ps
CPU time 9.48 seconds
Started Jul 14 07:36:46 PM PDT 24
Finished Jul 14 07:36:56 PM PDT 24
Peak memory 573964 kb
Host smart-3963534a-392c-4e3b-afcc-9df309677501
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014664305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.3014664305
Directory /workspace/50.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.2698691072
Short name T1704
Test name
Test status
Simulation time 7879382546 ps
CPU time 87.3 seconds
Started Jul 14 07:36:45 PM PDT 24
Finished Jul 14 07:38:13 PM PDT 24
Peak memory 574160 kb
Host smart-56e06583-8a62-4afd-aeb0-77b10434bc9e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698691072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.2698691072
Directory /workspace/50.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.3193836207
Short name T1842
Test name
Test status
Simulation time 5280182959 ps
CPU time 95.74 seconds
Started Jul 14 07:36:47 PM PDT 24
Finished Jul 14 07:38:23 PM PDT 24
Peak memory 574128 kb
Host smart-bd46e273-8f79-46a7-abc1-cd67dc455e11
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193836207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.3193836207
Directory /workspace/50.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.2625655963
Short name T2322
Test name
Test status
Simulation time 45836624 ps
CPU time 6.05 seconds
Started Jul 14 07:36:46 PM PDT 24
Finished Jul 14 07:36:52 PM PDT 24
Peak memory 575248 kb
Host smart-24c22798-8e41-49c7-80a1-72d10ff0af34
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625655963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay
s.2625655963
Directory /workspace/50.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all.3624312631
Short name T2097
Test name
Test status
Simulation time 10333980469 ps
CPU time 388.68 seconds
Started Jul 14 07:36:52 PM PDT 24
Finished Jul 14 07:43:21 PM PDT 24
Peak memory 575536 kb
Host smart-edbbad05-6bd6-4ba0-8516-cf945af0a33e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624312631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.3624312631
Directory /workspace/50.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.2820398874
Short name T1894
Test name
Test status
Simulation time 212156684 ps
CPU time 98.09 seconds
Started Jul 14 07:36:55 PM PDT 24
Finished Jul 14 07:38:33 PM PDT 24
Peak memory 575424 kb
Host smart-d2bbaea8-cd6a-4d75-8daf-288f9cd101f2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820398874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all
_with_rand_reset.2820398874
Directory /workspace/50.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.1987564415
Short name T2636
Test name
Test status
Simulation time 4598722930 ps
CPU time 288.08 seconds
Started Jul 14 07:36:52 PM PDT 24
Finished Jul 14 07:41:41 PM PDT 24
Peak memory 575620 kb
Host smart-74341b85-cd8d-47ac-9d41-9b64482b23dd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987564415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al
l_with_reset_error.1987564415
Directory /workspace/50.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.1672354760
Short name T1369
Test name
Test status
Simulation time 671366838 ps
CPU time 32.73 seconds
Started Jul 14 07:36:52 PM PDT 24
Finished Jul 14 07:37:25 PM PDT 24
Peak memory 575412 kb
Host smart-ff77fa9f-ab82-49ac-a079-b56cb9d8e75c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672354760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.1672354760
Directory /workspace/50.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_access_same_device.2602833500
Short name T2707
Test name
Test status
Simulation time 2907811366 ps
CPU time 104.01 seconds
Started Jul 14 07:37:00 PM PDT 24
Finished Jul 14 07:38:44 PM PDT 24
Peak memory 575412 kb
Host smart-08e0967d-2f19-4138-9e6e-e5695777eb16
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602833500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device
.2602833500
Directory /workspace/51.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.845037089
Short name T2243
Test name
Test status
Simulation time 41553857543 ps
CPU time 810.75 seconds
Started Jul 14 07:36:56 PM PDT 24
Finished Jul 14 07:50:27 PM PDT 24
Peak memory 575532 kb
Host smart-72031b3a-3474-48cf-9273-3c848761902d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845037089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_d
evice_slow_rsp.845037089
Directory /workspace/51.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.570182863
Short name T1943
Test name
Test status
Simulation time 824405332 ps
CPU time 34.34 seconds
Started Jul 14 07:37:07 PM PDT 24
Finished Jul 14 07:37:42 PM PDT 24
Peak memory 575348 kb
Host smart-35757120-3623-4633-ac4c-e97101be2056
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570182863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_addr
.570182863
Directory /workspace/51.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_error_random.154157825
Short name T1541
Test name
Test status
Simulation time 876271272 ps
CPU time 32.45 seconds
Started Jul 14 07:36:58 PM PDT 24
Finished Jul 14 07:37:31 PM PDT 24
Peak memory 575336 kb
Host smart-078a657a-e4f9-43b4-9e4b-fd8ef7863db3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154157825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.154157825
Directory /workspace/51.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random.2646999657
Short name T609
Test name
Test status
Simulation time 1037252441 ps
CPU time 41.01 seconds
Started Jul 14 07:37:00 PM PDT 24
Finished Jul 14 07:37:42 PM PDT 24
Peak memory 575316 kb
Host smart-ad5302da-3962-47d4-b75b-e08c79a074c6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646999657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.2646999657
Directory /workspace/51.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.3426720345
Short name T2002
Test name
Test status
Simulation time 6645885881 ps
CPU time 72.98 seconds
Started Jul 14 07:36:59 PM PDT 24
Finished Jul 14 07:38:13 PM PDT 24
Peak memory 575436 kb
Host smart-50c7ef18-fb22-4a0f-9074-a069a729a81f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426720345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.3426720345
Directory /workspace/51.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.535650135
Short name T546
Test name
Test status
Simulation time 17226202816 ps
CPU time 290.86 seconds
Started Jul 14 07:36:59 PM PDT 24
Finished Jul 14 07:41:51 PM PDT 24
Peak memory 575416 kb
Host smart-efd25cbe-ae5a-4493-aea5-87ef875fa78f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535650135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.535650135
Directory /workspace/51.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.2178138307
Short name T1724
Test name
Test status
Simulation time 177262679 ps
CPU time 18.35 seconds
Started Jul 14 07:37:00 PM PDT 24
Finished Jul 14 07:37:19 PM PDT 24
Peak memory 575336 kb
Host smart-87deafcf-7956-4454-9366-21d46441e525
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178138307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del
ays.2178138307
Directory /workspace/51.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_same_source.2937915133
Short name T1820
Test name
Test status
Simulation time 1266679652 ps
CPU time 37.4 seconds
Started Jul 14 07:37:00 PM PDT 24
Finished Jul 14 07:37:38 PM PDT 24
Peak memory 575344 kb
Host smart-d624645c-7862-413b-a15c-3788190494c4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937915133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.2937915133
Directory /workspace/51.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke.1984313814
Short name T1405
Test name
Test status
Simulation time 48409453 ps
CPU time 6.73 seconds
Started Jul 14 07:36:52 PM PDT 24
Finished Jul 14 07:37:00 PM PDT 24
Peak memory 575344 kb
Host smart-1186da18-5df7-4522-a8ca-31799ae1892c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984313814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.1984313814
Directory /workspace/51.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.1338139779
Short name T2689
Test name
Test status
Simulation time 8676966100 ps
CPU time 98.77 seconds
Started Jul 14 07:37:02 PM PDT 24
Finished Jul 14 07:38:41 PM PDT 24
Peak memory 574128 kb
Host smart-0d1b7570-4b0e-4831-9358-86a5ccb0340f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338139779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.1338139779
Directory /workspace/51.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.2634865691
Short name T1916
Test name
Test status
Simulation time 6022138890 ps
CPU time 102.5 seconds
Started Jul 14 07:37:02 PM PDT 24
Finished Jul 14 07:38:45 PM PDT 24
Peak memory 574128 kb
Host smart-1e734633-8b7c-4926-92c0-321fb63b819a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634865691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.2634865691
Directory /workspace/51.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.161497514
Short name T2623
Test name
Test status
Simulation time 45906074 ps
CPU time 6.42 seconds
Started Jul 14 07:36:58 PM PDT 24
Finished Jul 14 07:37:05 PM PDT 24
Peak memory 575252 kb
Host smart-f451ddd7-40ea-4cb0-87f2-66731e62f6f2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161497514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delays
.161497514
Directory /workspace/51.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all.2749683513
Short name T834
Test name
Test status
Simulation time 2612680522 ps
CPU time 97.36 seconds
Started Jul 14 07:37:08 PM PDT 24
Finished Jul 14 07:38:46 PM PDT 24
Peak memory 575424 kb
Host smart-8dff6968-2f9a-4e4a-8815-9c87e236540b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749683513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.2749683513
Directory /workspace/51.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.2728654224
Short name T2801
Test name
Test status
Simulation time 4548566877 ps
CPU time 156.91 seconds
Started Jul 14 07:37:04 PM PDT 24
Finished Jul 14 07:39:41 PM PDT 24
Peak memory 575568 kb
Host smart-592651f6-1de4-4fc5-b68d-567c2d07021c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728654224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.2728654224
Directory /workspace/51.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.3820884694
Short name T2715
Test name
Test status
Simulation time 479296579 ps
CPU time 157.03 seconds
Started Jul 14 07:37:03 PM PDT 24
Finished Jul 14 07:39:41 PM PDT 24
Peak memory 575488 kb
Host smart-8f5abe90-ce15-4c01-bf09-e9d3c528bf52
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820884694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all
_with_rand_reset.3820884694
Directory /workspace/51.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.377090960
Short name T2418
Test name
Test status
Simulation time 6672431058 ps
CPU time 590.04 seconds
Started Jul 14 07:37:02 PM PDT 24
Finished Jul 14 07:46:53 PM PDT 24
Peak memory 575628 kb
Host smart-1a7e40fb-5b7d-4327-8287-ea682ae7d0e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377090960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all
_with_reset_error.377090960
Directory /workspace/51.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.3902182642
Short name T2700
Test name
Test status
Simulation time 1090117729 ps
CPU time 41.91 seconds
Started Jul 14 07:37:04 PM PDT 24
Finished Jul 14 07:37:47 PM PDT 24
Peak memory 575436 kb
Host smart-b651abf8-283b-49a5-b5a3-20ffe484222e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902182642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.3902182642
Directory /workspace/51.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_access_same_device.2272668228
Short name T2290
Test name
Test status
Simulation time 1801825078 ps
CPU time 83.94 seconds
Started Jul 14 07:37:07 PM PDT 24
Finished Jul 14 07:38:31 PM PDT 24
Peak memory 575396 kb
Host smart-c110cbe6-c30a-443f-8bda-e1e4bc949c28
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272668228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device
.2272668228
Directory /workspace/52.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.4022206472
Short name T2148
Test name
Test status
Simulation time 70691367095 ps
CPU time 1335.44 seconds
Started Jul 14 07:37:05 PM PDT 24
Finished Jul 14 07:59:21 PM PDT 24
Peak memory 575456 kb
Host smart-dd4684c2-0f2f-4d0c-9efa-692ea4c9202c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022206472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_
device_slow_rsp.4022206472
Directory /workspace/52.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.1639916810
Short name T1530
Test name
Test status
Simulation time 198371608 ps
CPU time 25.22 seconds
Started Jul 14 07:37:12 PM PDT 24
Finished Jul 14 07:37:38 PM PDT 24
Peak memory 575284 kb
Host smart-e5a9a717-2f3f-4dd4-83a2-4a0757b5a12a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639916810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add
r.1639916810
Directory /workspace/52.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_error_random.3676775878
Short name T2500
Test name
Test status
Simulation time 740769524 ps
CPU time 25.26 seconds
Started Jul 14 07:37:08 PM PDT 24
Finished Jul 14 07:37:34 PM PDT 24
Peak memory 575232 kb
Host smart-e02d1c98-6bbc-43b6-b6bb-d092ab5ab692
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676775878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.3676775878
Directory /workspace/52.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random.1180106905
Short name T1949
Test name
Test status
Simulation time 94412178 ps
CPU time 11.59 seconds
Started Jul 14 07:37:05 PM PDT 24
Finished Jul 14 07:37:17 PM PDT 24
Peak memory 575272 kb
Host smart-074098e0-f7f0-4a83-b9bc-8ef4d0bb4c97
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180106905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.1180106905
Directory /workspace/52.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.3540314074
Short name T536
Test name
Test status
Simulation time 107644986526 ps
CPU time 1378.7 seconds
Started Jul 14 07:37:02 PM PDT 24
Finished Jul 14 08:00:02 PM PDT 24
Peak memory 575488 kb
Host smart-08408e7d-bc03-43be-b58d-fe20421712a1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540314074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.3540314074
Directory /workspace/52.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.3399024215
Short name T2357
Test name
Test status
Simulation time 23332089891 ps
CPU time 395.34 seconds
Started Jul 14 07:37:04 PM PDT 24
Finished Jul 14 07:43:40 PM PDT 24
Peak memory 575444 kb
Host smart-ab99ff25-61ca-425e-8d11-1dbf997e4dc4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399024215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.3399024215
Directory /workspace/52.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.793993721
Short name T563
Test name
Test status
Simulation time 452884006 ps
CPU time 40.01 seconds
Started Jul 14 07:37:04 PM PDT 24
Finished Jul 14 07:37:45 PM PDT 24
Peak memory 575320 kb
Host smart-692dec96-fc4f-4d83-b571-bd25c0064f28
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793993721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_dela
ys.793993721
Directory /workspace/52.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_same_source.4129995923
Short name T646
Test name
Test status
Simulation time 2288366856 ps
CPU time 74.32 seconds
Started Jul 14 07:37:04 PM PDT 24
Finished Jul 14 07:38:19 PM PDT 24
Peak memory 575428 kb
Host smart-9e09236d-14b5-41c4-a33e-c36d3f997652
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129995923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.4129995923
Directory /workspace/52.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke.1827341059
Short name T2176
Test name
Test status
Simulation time 49722996 ps
CPU time 5.85 seconds
Started Jul 14 07:37:05 PM PDT 24
Finished Jul 14 07:37:11 PM PDT 24
Peak memory 574064 kb
Host smart-a3a2b3df-5541-4535-8c99-19b0932223d5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827341059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.1827341059
Directory /workspace/52.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.3334638800
Short name T2602
Test name
Test status
Simulation time 8728255148 ps
CPU time 90.83 seconds
Started Jul 14 07:37:05 PM PDT 24
Finished Jul 14 07:38:36 PM PDT 24
Peak memory 574176 kb
Host smart-270c6351-678d-46c9-83a6-47cc85c9f306
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334638800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.3334638800
Directory /workspace/52.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.1133400175
Short name T1993
Test name
Test status
Simulation time 3789918302 ps
CPU time 67.12 seconds
Started Jul 14 07:37:05 PM PDT 24
Finished Jul 14 07:38:12 PM PDT 24
Peak memory 575352 kb
Host smart-6fe7f5d9-882e-4abe-ad54-8a8f40cdd109
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133400175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.1133400175
Directory /workspace/52.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.606710546
Short name T637
Test name
Test status
Simulation time 40954518 ps
CPU time 6.45 seconds
Started Jul 14 07:37:03 PM PDT 24
Finished Jul 14 07:37:10 PM PDT 24
Peak memory 574176 kb
Host smart-93ed8aa3-0021-4649-a500-977086c65567
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606710546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delays
.606710546
Directory /workspace/52.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all.1618151197
Short name T581
Test name
Test status
Simulation time 1008094600 ps
CPU time 79.52 seconds
Started Jul 14 07:37:16 PM PDT 24
Finished Jul 14 07:38:36 PM PDT 24
Peak memory 575440 kb
Host smart-747055c9-ca22-4daf-88e4-6787af93bd89
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618151197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.1618151197
Directory /workspace/52.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.126445959
Short name T2143
Test name
Test status
Simulation time 15560146682 ps
CPU time 600.86 seconds
Started Jul 14 07:37:09 PM PDT 24
Finished Jul 14 07:47:10 PM PDT 24
Peak memory 575564 kb
Host smart-a21b4166-7472-49be-97b1-900b165b7a13
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126445959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.126445959
Directory /workspace/52.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.3055360610
Short name T873
Test name
Test status
Simulation time 405028255 ps
CPU time 190.52 seconds
Started Jul 14 07:37:11 PM PDT 24
Finished Jul 14 07:40:22 PM PDT 24
Peak memory 575464 kb
Host smart-f4fe5868-3124-48b9-8580-238ddf3acdcb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055360610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all
_with_rand_reset.3055360610
Directory /workspace/52.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.961302443
Short name T1951
Test name
Test status
Simulation time 443156801 ps
CPU time 119.3 seconds
Started Jul 14 07:37:11 PM PDT 24
Finished Jul 14 07:39:10 PM PDT 24
Peak memory 575440 kb
Host smart-c42d3df1-dfd6-41cf-99da-e82359b191ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961302443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all
_with_reset_error.961302443
Directory /workspace/52.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.2212178634
Short name T2491
Test name
Test status
Simulation time 886388828 ps
CPU time 38.28 seconds
Started Jul 14 07:37:12 PM PDT 24
Finished Jul 14 07:37:50 PM PDT 24
Peak memory 575440 kb
Host smart-3c9148a6-642f-497b-9b5b-37fd07bc71e2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212178634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.2212178634
Directory /workspace/52.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_access_same_device.2657606834
Short name T2398
Test name
Test status
Simulation time 884553467 ps
CPU time 71.34 seconds
Started Jul 14 07:37:18 PM PDT 24
Finished Jul 14 07:38:30 PM PDT 24
Peak memory 575308 kb
Host smart-0df3789d-2e6d-42a8-b941-dc94075abab5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657606834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device
.2657606834
Directory /workspace/53.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.3634112387
Short name T2344
Test name
Test status
Simulation time 21498397972 ps
CPU time 380.74 seconds
Started Jul 14 07:37:16 PM PDT 24
Finished Jul 14 07:43:37 PM PDT 24
Peak memory 575592 kb
Host smart-f933ef3c-5eea-48bd-bfc0-81d07ef97547
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634112387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_
device_slow_rsp.3634112387
Directory /workspace/53.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.1859415112
Short name T1345
Test name
Test status
Simulation time 175065372 ps
CPU time 16.69 seconds
Started Jul 14 07:37:20 PM PDT 24
Finished Jul 14 07:37:37 PM PDT 24
Peak memory 575324 kb
Host smart-e2301dd7-141a-448d-8eb0-cb62b8578be7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859415112 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add
r.1859415112
Directory /workspace/53.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_error_random.4226197677
Short name T1874
Test name
Test status
Simulation time 1390168004 ps
CPU time 49.27 seconds
Started Jul 14 07:37:16 PM PDT 24
Finished Jul 14 07:38:06 PM PDT 24
Peak memory 575296 kb
Host smart-df807b1e-477a-4389-bf6b-f0ff80091eeb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226197677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.4226197677
Directory /workspace/53.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random.3632251519
Short name T2353
Test name
Test status
Simulation time 330900005 ps
CPU time 28.41 seconds
Started Jul 14 07:37:10 PM PDT 24
Finished Jul 14 07:37:39 PM PDT 24
Peak memory 575384 kb
Host smart-af5bcd7f-3c42-4d7b-a89b-e174b9a8e9d1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632251519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.3632251519
Directory /workspace/53.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.3135551246
Short name T1377
Test name
Test status
Simulation time 6584493667 ps
CPU time 75.61 seconds
Started Jul 14 07:37:19 PM PDT 24
Finished Jul 14 07:38:34 PM PDT 24
Peak memory 575504 kb
Host smart-779897d7-f04c-43f5-a30e-7b8a09f0368a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135551246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.3135551246
Directory /workspace/53.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.2592816965
Short name T1824
Test name
Test status
Simulation time 40010270927 ps
CPU time 636.23 seconds
Started Jul 14 07:37:22 PM PDT 24
Finished Jul 14 07:47:59 PM PDT 24
Peak memory 575500 kb
Host smart-3504adc4-dca1-44a3-875a-d9a400fc25bf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592816965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.2592816965
Directory /workspace/53.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.1572673164
Short name T1992
Test name
Test status
Simulation time 427891016 ps
CPU time 41.7 seconds
Started Jul 14 07:37:22 PM PDT 24
Finished Jul 14 07:38:04 PM PDT 24
Peak memory 575344 kb
Host smart-fcdad2b8-5aeb-44e1-a6ef-c27fc29011e4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572673164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del
ays.1572673164
Directory /workspace/53.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_same_source.2516585881
Short name T2731
Test name
Test status
Simulation time 2630945383 ps
CPU time 79.94 seconds
Started Jul 14 07:37:18 PM PDT 24
Finished Jul 14 07:38:38 PM PDT 24
Peak memory 575400 kb
Host smart-22c92ac6-2979-4c55-9ef5-9c8c0c4fa8cf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516585881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.2516585881
Directory /workspace/53.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke.661273077
Short name T2065
Test name
Test status
Simulation time 46789737 ps
CPU time 6.04 seconds
Started Jul 14 07:37:16 PM PDT 24
Finished Jul 14 07:37:23 PM PDT 24
Peak memory 575236 kb
Host smart-32a648c5-613e-46da-88bc-711346d37ce1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661273077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.661273077
Directory /workspace/53.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.3944652881
Short name T2387
Test name
Test status
Simulation time 8861601851 ps
CPU time 100.71 seconds
Started Jul 14 07:37:17 PM PDT 24
Finished Jul 14 07:38:58 PM PDT 24
Peak memory 575420 kb
Host smart-2ad00590-228b-4ce8-9a41-d6a0bf00cc85
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944652881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.3944652881
Directory /workspace/53.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1419560532
Short name T1912
Test name
Test status
Simulation time 5675689727 ps
CPU time 93.32 seconds
Started Jul 14 07:37:11 PM PDT 24
Finished Jul 14 07:38:45 PM PDT 24
Peak memory 574144 kb
Host smart-5030eb36-390f-4a23-8abc-9d8fcc127a8d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419560532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.1419560532
Directory /workspace/53.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.4024052922
Short name T1412
Test name
Test status
Simulation time 45294609 ps
CPU time 6.25 seconds
Started Jul 14 07:37:11 PM PDT 24
Finished Jul 14 07:37:18 PM PDT 24
Peak memory 575276 kb
Host smart-589ea34d-77e0-43de-a740-0881c68f7a31
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024052922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delay
s.4024052922
Directory /workspace/53.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all.2474437048
Short name T520
Test name
Test status
Simulation time 3129026856 ps
CPU time 240.12 seconds
Started Jul 14 07:37:19 PM PDT 24
Finished Jul 14 07:41:20 PM PDT 24
Peak memory 575508 kb
Host smart-92b65795-6a75-4b2e-aa25-7e330bd2e106
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474437048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.2474437048
Directory /workspace/53.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.3327401058
Short name T688
Test name
Test status
Simulation time 7889840256 ps
CPU time 306.73 seconds
Started Jul 14 07:37:23 PM PDT 24
Finished Jul 14 07:42:30 PM PDT 24
Peak memory 575576 kb
Host smart-23129aca-1d2d-47f4-ba51-0433df3f2d28
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327401058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.3327401058
Directory /workspace/53.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.1702382492
Short name T1958
Test name
Test status
Simulation time 267315872 ps
CPU time 178.28 seconds
Started Jul 14 07:37:26 PM PDT 24
Finished Jul 14 07:40:25 PM PDT 24
Peak memory 575448 kb
Host smart-4af49f0b-10a8-41ac-8cec-215b6505d3d5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702382492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all
_with_rand_reset.1702382492
Directory /workspace/53.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.540855026
Short name T2177
Test name
Test status
Simulation time 105148485 ps
CPU time 49.17 seconds
Started Jul 14 07:37:23 PM PDT 24
Finished Jul 14 07:38:13 PM PDT 24
Peak memory 575236 kb
Host smart-0b20a54e-1cd3-4f84-a800-37b59513d963
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540855026 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all
_with_reset_error.540855026
Directory /workspace/53.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.2488541823
Short name T1833
Test name
Test status
Simulation time 1257212878 ps
CPU time 49.38 seconds
Started Jul 14 07:37:20 PM PDT 24
Finished Jul 14 07:38:10 PM PDT 24
Peak memory 575428 kb
Host smart-68ba8899-1f34-4730-9d3f-c0aaa1e3711a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488541823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.2488541823
Directory /workspace/53.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_access_same_device.3184927216
Short name T831
Test name
Test status
Simulation time 2410026944 ps
CPU time 91.8 seconds
Started Jul 14 07:37:29 PM PDT 24
Finished Jul 14 07:39:02 PM PDT 24
Peak memory 575632 kb
Host smart-afd77ee8-8b60-40a5-b548-53fca42653b0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184927216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device
.3184927216
Directory /workspace/54.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.1852907494
Short name T2527
Test name
Test status
Simulation time 25522644703 ps
CPU time 456.48 seconds
Started Jul 14 07:37:31 PM PDT 24
Finished Jul 14 07:45:08 PM PDT 24
Peak memory 575496 kb
Host smart-43b57554-90d5-4af2-80d6-ff5ad04b9b5c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852907494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_
device_slow_rsp.1852907494
Directory /workspace/54.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.1392058311
Short name T2537
Test name
Test status
Simulation time 311605251 ps
CPU time 14.51 seconds
Started Jul 14 07:37:37 PM PDT 24
Finished Jul 14 07:37:51 PM PDT 24
Peak memory 575320 kb
Host smart-96bbfa07-1c3b-443b-9152-ba3f2c138dc7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392058311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add
r.1392058311
Directory /workspace/54.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_error_random.1304071263
Short name T1558
Test name
Test status
Simulation time 1253966806 ps
CPU time 45.61 seconds
Started Jul 14 07:37:30 PM PDT 24
Finished Jul 14 07:38:16 PM PDT 24
Peak memory 575316 kb
Host smart-d52571fb-4186-4e4c-b889-9a5a107d8843
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304071263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.1304071263
Directory /workspace/54.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random.1864293229
Short name T627
Test name
Test status
Simulation time 454262896 ps
CPU time 18.8 seconds
Started Jul 14 07:37:23 PM PDT 24
Finished Jul 14 07:37:43 PM PDT 24
Peak memory 575316 kb
Host smart-506572aa-da00-4a1b-b246-78a908b39e20
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864293229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.1864293229
Directory /workspace/54.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.848210813
Short name T2061
Test name
Test status
Simulation time 19842403035 ps
CPU time 233.06 seconds
Started Jul 14 07:37:30 PM PDT 24
Finished Jul 14 07:41:23 PM PDT 24
Peak memory 575508 kb
Host smart-e7c6d1ae-bace-42b4-a095-2404e3a8c4f0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848210813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.848210813
Directory /workspace/54.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.1172862941
Short name T2001
Test name
Test status
Simulation time 15293159768 ps
CPU time 266 seconds
Started Jul 14 07:37:32 PM PDT 24
Finished Jul 14 07:41:58 PM PDT 24
Peak memory 575504 kb
Host smart-338e0a42-68ed-4c83-8b6e-e499831c0993
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172862941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.1172862941
Directory /workspace/54.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.2304348750
Short name T1695
Test name
Test status
Simulation time 311858229 ps
CPU time 25.32 seconds
Started Jul 14 07:37:30 PM PDT 24
Finished Jul 14 07:37:56 PM PDT 24
Peak memory 575284 kb
Host smart-caa44fd2-7d21-49ce-81d8-265313d21942
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304348750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del
ays.2304348750
Directory /workspace/54.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_same_source.3268046303
Short name T2324
Test name
Test status
Simulation time 524736028 ps
CPU time 38.46 seconds
Started Jul 14 07:37:29 PM PDT 24
Finished Jul 14 07:38:08 PM PDT 24
Peak memory 575348 kb
Host smart-4c19693c-7739-47ae-9629-0cb079ed0a9f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268046303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.3268046303
Directory /workspace/54.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke.2644368386
Short name T1886
Test name
Test status
Simulation time 242178399 ps
CPU time 10.56 seconds
Started Jul 14 07:37:23 PM PDT 24
Finished Jul 14 07:37:34 PM PDT 24
Peak memory 574048 kb
Host smart-88abfc6c-ac07-416c-a307-989941bfa49d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644368386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.2644368386
Directory /workspace/54.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.3638596614
Short name T1609
Test name
Test status
Simulation time 9718971169 ps
CPU time 109.13 seconds
Started Jul 14 07:37:23 PM PDT 24
Finished Jul 14 07:39:13 PM PDT 24
Peak memory 574172 kb
Host smart-74f089bc-b07b-4a54-a6d1-7674f9e2faae
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638596614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.3638596614
Directory /workspace/54.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.2903001878
Short name T2676
Test name
Test status
Simulation time 4293426885 ps
CPU time 76.8 seconds
Started Jul 14 07:37:25 PM PDT 24
Finished Jul 14 07:38:42 PM PDT 24
Peak memory 575396 kb
Host smart-c3402bf5-bf54-4715-ae0f-798d61e1a528
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903001878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.2903001878
Directory /workspace/54.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.793020609
Short name T2692
Test name
Test status
Simulation time 40954833 ps
CPU time 5.79 seconds
Started Jul 14 07:37:27 PM PDT 24
Finished Jul 14 07:37:33 PM PDT 24
Peak memory 573980 kb
Host smart-97c1dfdb-91fc-40e3-9277-be733617e52e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793020609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delays
.793020609
Directory /workspace/54.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all.3401765692
Short name T2851
Test name
Test status
Simulation time 274269720 ps
CPU time 23.29 seconds
Started Jul 14 07:37:39 PM PDT 24
Finished Jul 14 07:38:02 PM PDT 24
Peak memory 575388 kb
Host smart-34a15abb-40a1-430c-8122-7cf5c260c336
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401765692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.3401765692
Directory /workspace/54.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.1981584806
Short name T2016
Test name
Test status
Simulation time 13564598345 ps
CPU time 453.16 seconds
Started Jul 14 07:37:35 PM PDT 24
Finished Jul 14 07:45:09 PM PDT 24
Peak memory 575608 kb
Host smart-fd73d6d3-3ad2-4447-b98f-31074c0aaedc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981584806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.1981584806
Directory /workspace/54.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.1114095742
Short name T2192
Test name
Test status
Simulation time 80362793 ps
CPU time 58.88 seconds
Started Jul 14 07:37:39 PM PDT 24
Finished Jul 14 07:38:38 PM PDT 24
Peak memory 575436 kb
Host smart-57c55efb-02ed-4cdb-ac94-25a210943777
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114095742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all
_with_rand_reset.1114095742
Directory /workspace/54.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.1456611723
Short name T2072
Test name
Test status
Simulation time 3897901192 ps
CPU time 390.27 seconds
Started Jul 14 07:37:35 PM PDT 24
Finished Jul 14 07:44:06 PM PDT 24
Peak memory 575468 kb
Host smart-3760a002-3545-43c4-9e09-b39c27fa7536
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456611723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al
l_with_reset_error.1456611723
Directory /workspace/54.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.4076454504
Short name T560
Test name
Test status
Simulation time 340231920 ps
CPU time 35.31 seconds
Started Jul 14 07:37:30 PM PDT 24
Finished Jul 14 07:38:05 PM PDT 24
Peak memory 575432 kb
Host smart-2491e50f-37c5-4370-a105-a6a5ea126303
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076454504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.4076454504
Directory /workspace/54.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_access_same_device.1601270960
Short name T1768
Test name
Test status
Simulation time 725519611 ps
CPU time 33.54 seconds
Started Jul 14 07:37:37 PM PDT 24
Finished Jul 14 07:38:11 PM PDT 24
Peak memory 575328 kb
Host smart-12cb3766-7f1f-4610-a6d0-09087f6a3c44
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601270960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device
.1601270960
Directory /workspace/55.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.3520384470
Short name T1799
Test name
Test status
Simulation time 92893759389 ps
CPU time 1769.17 seconds
Started Jul 14 07:37:35 PM PDT 24
Finished Jul 14 08:07:05 PM PDT 24
Peak memory 575572 kb
Host smart-133fbc74-d3d8-480b-b8c5-cc5a656a9f3a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520384470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_
device_slow_rsp.3520384470
Directory /workspace/55.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.1176212048
Short name T2586
Test name
Test status
Simulation time 209041291 ps
CPU time 24.17 seconds
Started Jul 14 07:37:43 PM PDT 24
Finished Jul 14 07:38:08 PM PDT 24
Peak memory 575332 kb
Host smart-a2424016-256e-4a65-a1c5-43319a252f7a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176212048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_add
r.1176212048
Directory /workspace/55.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_error_random.3485349670
Short name T2615
Test name
Test status
Simulation time 195312157 ps
CPU time 19.14 seconds
Started Jul 14 07:37:41 PM PDT 24
Finished Jul 14 07:38:01 PM PDT 24
Peak memory 575324 kb
Host smart-af596733-02b4-40c7-a37a-0407f2a6ddde
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485349670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.3485349670
Directory /workspace/55.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random.2902460190
Short name T503
Test name
Test status
Simulation time 1515196881 ps
CPU time 53.39 seconds
Started Jul 14 07:37:39 PM PDT 24
Finished Jul 14 07:38:33 PM PDT 24
Peak memory 575348 kb
Host smart-282db2ff-139e-45b6-a7b6-7b7a64825f0a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902460190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.2902460190
Directory /workspace/55.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.506483774
Short name T2684
Test name
Test status
Simulation time 26052674698 ps
CPU time 286.84 seconds
Started Jul 14 07:37:40 PM PDT 24
Finished Jul 14 07:42:27 PM PDT 24
Peak memory 575460 kb
Host smart-aaf451f6-e3d8-43ef-b4b7-e33e932e6191
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506483774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.506483774
Directory /workspace/55.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.836271696
Short name T1789
Test name
Test status
Simulation time 42424340982 ps
CPU time 768.98 seconds
Started Jul 14 07:37:35 PM PDT 24
Finished Jul 14 07:50:25 PM PDT 24
Peak memory 575468 kb
Host smart-0e12b610-34c2-48e5-a048-363603915008
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836271696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.836271696
Directory /workspace/55.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.2678301903
Short name T604
Test name
Test status
Simulation time 178145166 ps
CPU time 17.12 seconds
Started Jul 14 07:37:38 PM PDT 24
Finished Jul 14 07:37:56 PM PDT 24
Peak memory 575324 kb
Host smart-4e5f276e-22b9-422b-acfa-6f1c68b78f20
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678301903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del
ays.2678301903
Directory /workspace/55.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_same_source.851512429
Short name T2442
Test name
Test status
Simulation time 455218293 ps
CPU time 30.81 seconds
Started Jul 14 07:37:46 PM PDT 24
Finished Jul 14 07:38:17 PM PDT 24
Peak memory 575352 kb
Host smart-20783595-ae71-420c-b82f-9280d95e7016
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851512429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.851512429
Directory /workspace/55.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke.132137622
Short name T1817
Test name
Test status
Simulation time 41067049 ps
CPU time 5.58 seconds
Started Jul 14 07:37:39 PM PDT 24
Finished Jul 14 07:37:45 PM PDT 24
Peak memory 573984 kb
Host smart-7b3f6aba-b0a0-4755-b4b5-18bdea576330
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132137622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.132137622
Directory /workspace/55.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.2340467452
Short name T1830
Test name
Test status
Simulation time 10150700580 ps
CPU time 118.36 seconds
Started Jul 14 07:37:36 PM PDT 24
Finished Jul 14 07:39:35 PM PDT 24
Peak memory 574196 kb
Host smart-4b4170d0-7bb1-48e9-b5cb-8f4f7d8e01ac
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340467452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.2340467452
Directory /workspace/55.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.1152390317
Short name T1999
Test name
Test status
Simulation time 3414239041 ps
CPU time 58.6 seconds
Started Jul 14 07:37:40 PM PDT 24
Finished Jul 14 07:38:39 PM PDT 24
Peak memory 574044 kb
Host smart-ff707d0c-4e7d-4e88-a57c-34c37fb467ee
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152390317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.1152390317
Directory /workspace/55.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.294556223
Short name T1503
Test name
Test status
Simulation time 53291540 ps
CPU time 6.81 seconds
Started Jul 14 07:37:35 PM PDT 24
Finished Jul 14 07:37:43 PM PDT 24
Peak memory 573996 kb
Host smart-867a9778-23bc-40c4-8523-b4ed5735b476
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294556223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delays
.294556223
Directory /workspace/55.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all.2652091644
Short name T1725
Test name
Test status
Simulation time 9622820404 ps
CPU time 370.91 seconds
Started Jul 14 07:37:41 PM PDT 24
Finished Jul 14 07:43:53 PM PDT 24
Peak memory 575604 kb
Host smart-845b10e0-ee3c-4a78-a08a-af434de27d05
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652091644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.2652091644
Directory /workspace/55.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.100025514
Short name T1496
Test name
Test status
Simulation time 1468593483 ps
CPU time 94.04 seconds
Started Jul 14 07:37:43 PM PDT 24
Finished Jul 14 07:39:17 PM PDT 24
Peak memory 575400 kb
Host smart-66456111-3389-45d0-a25c-3ec6ecc7081c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100025514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.100025514
Directory /workspace/55.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.3058400655
Short name T2137
Test name
Test status
Simulation time 23309448765 ps
CPU time 1025.81 seconds
Started Jul 14 07:37:44 PM PDT 24
Finished Jul 14 07:54:51 PM PDT 24
Peak memory 575596 kb
Host smart-8be93f2e-928e-4d15-b117-f0c94692fa62
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058400655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al
l_with_reset_error.3058400655
Directory /workspace/55.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.2427666956
Short name T641
Test name
Test status
Simulation time 872763173 ps
CPU time 32.19 seconds
Started Jul 14 07:37:41 PM PDT 24
Finished Jul 14 07:38:13 PM PDT 24
Peak memory 575376 kb
Host smart-6e811a2c-686e-41e5-8925-1cf13ca486dd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427666956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.2427666956
Directory /workspace/55.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_access_same_device.3403616225
Short name T2559
Test name
Test status
Simulation time 1241896933 ps
CPU time 55.32 seconds
Started Jul 14 07:37:50 PM PDT 24
Finished Jul 14 07:38:46 PM PDT 24
Peak memory 575360 kb
Host smart-b3a6c2b3-4db2-4314-bd99-cac52fb528ff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403616225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device
.3403616225
Directory /workspace/56.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.1277742670
Short name T1464
Test name
Test status
Simulation time 107424620090 ps
CPU time 2041.47 seconds
Started Jul 14 07:37:49 PM PDT 24
Finished Jul 14 08:11:52 PM PDT 24
Peak memory 575520 kb
Host smart-d9b6513e-832a-4445-bd06-5ecf7e765b23
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277742670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_
device_slow_rsp.1277742670
Directory /workspace/56.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.2649801703
Short name T1371
Test name
Test status
Simulation time 212550823 ps
CPU time 12.68 seconds
Started Jul 14 07:37:52 PM PDT 24
Finished Jul 14 07:38:05 PM PDT 24
Peak memory 575324 kb
Host smart-7705d88b-0e42-425b-b3d2-0ec4bd75755d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649801703 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add
r.2649801703
Directory /workspace/56.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_error_random.377117942
Short name T2898
Test name
Test status
Simulation time 130719549 ps
CPU time 8.17 seconds
Started Jul 14 07:37:48 PM PDT 24
Finished Jul 14 07:37:57 PM PDT 24
Peak memory 574032 kb
Host smart-19601508-34e0-4344-93e2-5f6b032984f7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377117942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.377117942
Directory /workspace/56.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random.1557321054
Short name T1770
Test name
Test status
Simulation time 94599720 ps
CPU time 7.26 seconds
Started Jul 14 07:37:43 PM PDT 24
Finished Jul 14 07:37:51 PM PDT 24
Peak memory 575312 kb
Host smart-244bf0fa-26ad-4e4d-b79b-647a165b7d0b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557321054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.1557321054
Directory /workspace/56.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.3987040998
Short name T2806
Test name
Test status
Simulation time 59466388963 ps
CPU time 683.37 seconds
Started Jul 14 07:37:47 PM PDT 24
Finished Jul 14 07:49:11 PM PDT 24
Peak memory 575460 kb
Host smart-53784db2-aa01-46aa-82d2-a59c6b9dc471
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987040998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.3987040998
Directory /workspace/56.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.1964304059
Short name T2096
Test name
Test status
Simulation time 35313377279 ps
CPU time 633.84 seconds
Started Jul 14 07:37:48 PM PDT 24
Finished Jul 14 07:48:23 PM PDT 24
Peak memory 575536 kb
Host smart-177539bb-e577-4bd5-9608-3ea019e30b35
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964304059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.1964304059
Directory /workspace/56.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.3218824698
Short name T2015
Test name
Test status
Simulation time 42409768 ps
CPU time 6.13 seconds
Started Jul 14 07:37:42 PM PDT 24
Finished Jul 14 07:37:49 PM PDT 24
Peak memory 574048 kb
Host smart-c930b93c-b019-4736-bfb3-68fe839e4095
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218824698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del
ays.3218824698
Directory /workspace/56.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_same_source.2172170285
Short name T2595
Test name
Test status
Simulation time 509994889 ps
CPU time 40.34 seconds
Started Jul 14 07:37:48 PM PDT 24
Finished Jul 14 07:38:29 PM PDT 24
Peak memory 575280 kb
Host smart-cb3a5c1d-28f2-4db0-b659-129e530e2520
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172170285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.2172170285
Directory /workspace/56.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke.2758666837
Short name T1399
Test name
Test status
Simulation time 200565346 ps
CPU time 8.51 seconds
Started Jul 14 07:37:44 PM PDT 24
Finished Jul 14 07:37:53 PM PDT 24
Peak memory 574056 kb
Host smart-916178f9-dde6-40d3-b9f3-fd33c8865478
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758666837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.2758666837
Directory /workspace/56.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.3531694748
Short name T1547
Test name
Test status
Simulation time 7306609159 ps
CPU time 78.14 seconds
Started Jul 14 07:37:43 PM PDT 24
Finished Jul 14 07:39:01 PM PDT 24
Peak memory 574220 kb
Host smart-9c404a9f-f642-4d3f-ae18-618c234c9325
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531694748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.3531694748
Directory /workspace/56.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.2507788612
Short name T1362
Test name
Test status
Simulation time 5241825191 ps
CPU time 91.31 seconds
Started Jul 14 07:37:42 PM PDT 24
Finished Jul 14 07:39:13 PM PDT 24
Peak memory 574144 kb
Host smart-f9264dfb-36b8-4664-9edd-8227ba722032
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507788612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.2507788612
Directory /workspace/56.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.3431811164
Short name T1466
Test name
Test status
Simulation time 45302955 ps
CPU time 6.03 seconds
Started Jul 14 07:37:42 PM PDT 24
Finished Jul 14 07:37:49 PM PDT 24
Peak memory 575272 kb
Host smart-0b7d3d2f-d2cc-47c5-b271-d78287e94ee1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431811164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay
s.3431811164
Directory /workspace/56.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all.1254577548
Short name T602
Test name
Test status
Simulation time 4078712431 ps
CPU time 360.32 seconds
Started Jul 14 07:37:48 PM PDT 24
Finished Jul 14 07:43:50 PM PDT 24
Peak memory 575524 kb
Host smart-4726b952-dd5f-40b1-9a32-94586cdd67a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254577548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.1254577548
Directory /workspace/56.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.2033675426
Short name T1784
Test name
Test status
Simulation time 7499791658 ps
CPU time 241.15 seconds
Started Jul 14 07:37:49 PM PDT 24
Finished Jul 14 07:41:51 PM PDT 24
Peak memory 575628 kb
Host smart-47f62683-bcd0-4770-9b44-dbcc184b8742
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033675426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.2033675426
Directory /workspace/56.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.3145689824
Short name T2080
Test name
Test status
Simulation time 587491540 ps
CPU time 140.52 seconds
Started Jul 14 07:37:50 PM PDT 24
Finished Jul 14 07:40:11 PM PDT 24
Peak memory 575488 kb
Host smart-29aaf676-6d77-4630-ab53-974c51e2b327
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145689824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al
l_with_reset_error.3145689824
Directory /workspace/56.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.2610052850
Short name T590
Test name
Test status
Simulation time 1137179381 ps
CPU time 48.29 seconds
Started Jul 14 07:37:50 PM PDT 24
Finished Jul 14 07:38:39 PM PDT 24
Peak memory 575436 kb
Host smart-19c3c7ef-a984-48a6-af30-697370469d29
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610052850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.2610052850
Directory /workspace/56.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_access_same_device.1052062613
Short name T1957
Test name
Test status
Simulation time 2547962414 ps
CPU time 101.22 seconds
Started Jul 14 07:37:57 PM PDT 24
Finished Jul 14 07:39:39 PM PDT 24
Peak memory 575416 kb
Host smart-5925d2a2-50a1-423c-863b-2b87c9c670d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052062613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device
.1052062613
Directory /workspace/57.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.896071879
Short name T2060
Test name
Test status
Simulation time 120785814822 ps
CPU time 2230.59 seconds
Started Jul 14 07:37:57 PM PDT 24
Finished Jul 14 08:15:09 PM PDT 24
Peak memory 575560 kb
Host smart-66062f17-8378-4121-b0b8-c098d1984f48
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896071879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_d
evice_slow_rsp.896071879
Directory /workspace/57.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.3624313302
Short name T1335
Test name
Test status
Simulation time 726724491 ps
CPU time 28.05 seconds
Started Jul 14 07:38:00 PM PDT 24
Finished Jul 14 07:38:29 PM PDT 24
Peak memory 575348 kb
Host smart-5b0e1e43-8049-487e-ac3c-7bfda68ef92a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624313302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add
r.3624313302
Directory /workspace/57.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_error_random.2807896733
Short name T2184
Test name
Test status
Simulation time 564921087 ps
CPU time 22.38 seconds
Started Jul 14 07:37:59 PM PDT 24
Finished Jul 14 07:38:23 PM PDT 24
Peak memory 575276 kb
Host smart-53648795-1ef5-4ea4-9748-6385b0377d9d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807896733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.2807896733
Directory /workspace/57.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random.1367658254
Short name T469
Test name
Test status
Simulation time 2148948696 ps
CPU time 80.27 seconds
Started Jul 14 07:37:56 PM PDT 24
Finished Jul 14 07:39:16 PM PDT 24
Peak memory 575420 kb
Host smart-ced40c47-ae5e-4e6c-b81d-a4757c118640
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367658254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.1367658254
Directory /workspace/57.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.3203875382
Short name T1669
Test name
Test status
Simulation time 106667313528 ps
CPU time 1259.45 seconds
Started Jul 14 07:37:55 PM PDT 24
Finished Jul 14 07:58:55 PM PDT 24
Peak memory 575428 kb
Host smart-51506ad0-21f0-4521-a046-83c92d3dd0d6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203875382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.3203875382
Directory /workspace/57.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.3760924648
Short name T1653
Test name
Test status
Simulation time 11586993143 ps
CPU time 208.16 seconds
Started Jul 14 07:37:54 PM PDT 24
Finished Jul 14 07:41:23 PM PDT 24
Peak memory 575516 kb
Host smart-cfc4b456-bbd5-4831-9a59-4ffd68c4849a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760924648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.3760924648
Directory /workspace/57.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.4070427028
Short name T2410
Test name
Test status
Simulation time 448805212 ps
CPU time 36.95 seconds
Started Jul 14 07:37:59 PM PDT 24
Finished Jul 14 07:38:37 PM PDT 24
Peak memory 575324 kb
Host smart-1c1bae65-d1ea-4f80-bc00-ea4509315b15
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070427028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del
ays.4070427028
Directory /workspace/57.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_same_source.3847847755
Short name T2222
Test name
Test status
Simulation time 285306069 ps
CPU time 18.84 seconds
Started Jul 14 07:38:03 PM PDT 24
Finished Jul 14 07:38:22 PM PDT 24
Peak memory 575352 kb
Host smart-9accaf5b-c6e3-45f2-9c06-d2dd47308e00
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847847755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.3847847755
Directory /workspace/57.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke.560148680
Short name T2565
Test name
Test status
Simulation time 49129046 ps
CPU time 6.84 seconds
Started Jul 14 07:37:53 PM PDT 24
Finished Jul 14 07:38:01 PM PDT 24
Peak memory 574064 kb
Host smart-9f9d4c91-5ca9-419f-ad2c-ee33f9891dad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560148680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.560148680
Directory /workspace/57.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.251435268
Short name T1367
Test name
Test status
Simulation time 5444276985 ps
CPU time 59.02 seconds
Started Jul 14 07:37:54 PM PDT 24
Finished Jul 14 07:38:54 PM PDT 24
Peak memory 574160 kb
Host smart-e865f65e-9d2d-4f7a-bb82-d2d705ce0fda
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251435268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.251435268
Directory /workspace/57.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.4119813620
Short name T1802
Test name
Test status
Simulation time 6521114509 ps
CPU time 111.02 seconds
Started Jul 14 07:37:53 PM PDT 24
Finished Jul 14 07:39:44 PM PDT 24
Peak memory 574232 kb
Host smart-6077fa44-6598-4920-b159-f21c7f72cd4a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119813620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.4119813620
Directory /workspace/57.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.668383380
Short name T2349
Test name
Test status
Simulation time 45879747 ps
CPU time 6.8 seconds
Started Jul 14 07:37:59 PM PDT 24
Finished Jul 14 07:38:07 PM PDT 24
Peak memory 575288 kb
Host smart-094b765d-801e-423e-8fc9-bfeb1942a249
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668383380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delays
.668383380
Directory /workspace/57.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all.2680193248
Short name T1872
Test name
Test status
Simulation time 13165280870 ps
CPU time 535.81 seconds
Started Jul 14 07:38:02 PM PDT 24
Finished Jul 14 07:46:58 PM PDT 24
Peak memory 575612 kb
Host smart-3292a6f4-5c03-47a9-bfd0-502b89d20518
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680193248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.2680193248
Directory /workspace/57.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.1797159811
Short name T2257
Test name
Test status
Simulation time 3934500151 ps
CPU time 288.73 seconds
Started Jul 14 07:37:59 PM PDT 24
Finished Jul 14 07:42:49 PM PDT 24
Peak memory 575584 kb
Host smart-c8622d61-5862-4997-9e2a-736a33deaa84
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797159811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.1797159811
Directory /workspace/57.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.1144148167
Short name T1866
Test name
Test status
Simulation time 243980435 ps
CPU time 94.32 seconds
Started Jul 14 07:37:59 PM PDT 24
Finished Jul 14 07:39:34 PM PDT 24
Peak memory 575404 kb
Host smart-483f05da-1ad8-43e4-80e0-60467e57d828
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144148167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all
_with_rand_reset.1144148167
Directory /workspace/57.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.2280791871
Short name T867
Test name
Test status
Simulation time 12138652126 ps
CPU time 721.11 seconds
Started Jul 14 07:37:59 PM PDT 24
Finished Jul 14 07:50:02 PM PDT 24
Peak memory 575604 kb
Host smart-443ff1be-6e2f-40a3-a2cd-9bd16fa45b62
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280791871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al
l_with_reset_error.2280791871
Directory /workspace/57.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.2545633615
Short name T1693
Test name
Test status
Simulation time 1203408074 ps
CPU time 49.35 seconds
Started Jul 14 07:38:00 PM PDT 24
Finished Jul 14 07:38:50 PM PDT 24
Peak memory 575400 kb
Host smart-1da6125a-6d3a-4fed-9701-c235cc4c6b3b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545633615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.2545633615
Directory /workspace/57.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_access_same_device.2693654949
Short name T1564
Test name
Test status
Simulation time 413266984 ps
CPU time 35.18 seconds
Started Jul 14 07:38:08 PM PDT 24
Finished Jul 14 07:38:43 PM PDT 24
Peak memory 575328 kb
Host smart-398fd672-2c30-4a91-af09-a2ab5dd7f3e6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693654949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device
.2693654949
Directory /workspace/58.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.4074186660
Short name T707
Test name
Test status
Simulation time 81891303379 ps
CPU time 1473.64 seconds
Started Jul 14 07:38:06 PM PDT 24
Finished Jul 14 08:02:40 PM PDT 24
Peak memory 575548 kb
Host smart-6c4c3744-6161-478d-995e-bb783a7582e8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074186660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_
device_slow_rsp.4074186660
Directory /workspace/58.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.1452884403
Short name T1860
Test name
Test status
Simulation time 570378322 ps
CPU time 24.58 seconds
Started Jul 14 07:38:13 PM PDT 24
Finished Jul 14 07:38:38 PM PDT 24
Peak memory 575348 kb
Host smart-abb66076-df3c-4f89-9da3-a7856165f08b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452884403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add
r.1452884403
Directory /workspace/58.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_error_random.2239372873
Short name T2753
Test name
Test status
Simulation time 2242950991 ps
CPU time 85.53 seconds
Started Jul 14 07:38:13 PM PDT 24
Finished Jul 14 07:39:40 PM PDT 24
Peak memory 575388 kb
Host smart-1d81037d-213d-41d4-970e-1bf6b339ef1c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239372873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.2239372873
Directory /workspace/58.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random.4167448814
Short name T519
Test name
Test status
Simulation time 1770077409 ps
CPU time 54.1 seconds
Started Jul 14 07:38:08 PM PDT 24
Finished Jul 14 07:39:02 PM PDT 24
Peak memory 575348 kb
Host smart-54e90c11-6972-4725-b6b4-4d734f6bbc37
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167448814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.4167448814
Directory /workspace/58.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.2369808172
Short name T1739
Test name
Test status
Simulation time 54217732656 ps
CPU time 616.44 seconds
Started Jul 14 07:38:07 PM PDT 24
Finished Jul 14 07:48:24 PM PDT 24
Peak memory 575504 kb
Host smart-9e2af743-b87f-4b7b-bd70-c03939f78621
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369808172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.2369808172
Directory /workspace/58.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.1083852716
Short name T570
Test name
Test status
Simulation time 55372366471 ps
CPU time 997.37 seconds
Started Jul 14 07:38:07 PM PDT 24
Finished Jul 14 07:54:45 PM PDT 24
Peak memory 575524 kb
Host smart-dba288a2-47a1-4565-b716-6e867a96190e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083852716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.1083852716
Directory /workspace/58.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.1478329976
Short name T2461
Test name
Test status
Simulation time 378834790 ps
CPU time 35.89 seconds
Started Jul 14 07:38:06 PM PDT 24
Finished Jul 14 07:38:42 PM PDT 24
Peak memory 575288 kb
Host smart-e52af92e-01cc-4739-b65d-47d5a4db66cc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478329976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del
ays.1478329976
Directory /workspace/58.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_same_source.2896459878
Short name T2790
Test name
Test status
Simulation time 523241521 ps
CPU time 44.23 seconds
Started Jul 14 07:38:12 PM PDT 24
Finished Jul 14 07:38:57 PM PDT 24
Peak memory 575348 kb
Host smart-ced4466e-cd17-4a46-8b0d-8f29aa301e0c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896459878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.2896459878
Directory /workspace/58.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke.2271078521
Short name T1727
Test name
Test status
Simulation time 39528034 ps
CPU time 6.15 seconds
Started Jul 14 07:37:59 PM PDT 24
Finished Jul 14 07:38:06 PM PDT 24
Peak memory 574036 kb
Host smart-6eda1b33-0fc3-45cc-88a4-6a132369e642
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271078521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.2271078521
Directory /workspace/58.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.3247037419
Short name T1339
Test name
Test status
Simulation time 9462329345 ps
CPU time 100.15 seconds
Started Jul 14 07:38:04 PM PDT 24
Finished Jul 14 07:39:45 PM PDT 24
Peak memory 574228 kb
Host smart-44bba801-1e90-46e8-a56e-8ed2f8f7fb76
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247037419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.3247037419
Directory /workspace/58.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.1769222767
Short name T2524
Test name
Test status
Simulation time 5339204630 ps
CPU time 98 seconds
Started Jul 14 07:38:05 PM PDT 24
Finished Jul 14 07:39:44 PM PDT 24
Peak memory 575432 kb
Host smart-98743d34-e96f-40e0-bd1d-87fe035a1520
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769222767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.1769222767
Directory /workspace/58.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.1066824905
Short name T2499
Test name
Test status
Simulation time 60135699 ps
CPU time 7.14 seconds
Started Jul 14 07:37:59 PM PDT 24
Finished Jul 14 07:38:07 PM PDT 24
Peak memory 575276 kb
Host smart-3da5fcdf-911d-4062-a3af-d133fd61901e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066824905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay
s.1066824905
Directory /workspace/58.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all.1441349603
Short name T2118
Test name
Test status
Simulation time 2217734204 ps
CPU time 149.11 seconds
Started Jul 14 07:38:11 PM PDT 24
Finished Jul 14 07:40:41 PM PDT 24
Peak memory 575568 kb
Host smart-ec2812e6-1bcb-4708-9abd-b2eba0919f62
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441349603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.1441349603
Directory /workspace/58.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.1310312295
Short name T2069
Test name
Test status
Simulation time 3203925315 ps
CPU time 114.37 seconds
Started Jul 14 07:38:12 PM PDT 24
Finished Jul 14 07:40:07 PM PDT 24
Peak memory 575464 kb
Host smart-d7eabbf1-0efe-4624-a590-9438b9a4616d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310312295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.1310312295
Directory /workspace/58.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.2772585911
Short name T863
Test name
Test status
Simulation time 3090023343 ps
CPU time 214.25 seconds
Started Jul 14 07:38:13 PM PDT 24
Finished Jul 14 07:41:48 PM PDT 24
Peak memory 575540 kb
Host smart-fea01a3c-74c0-4fe6-8a76-7ab44870ff90
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772585911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all
_with_rand_reset.2772585911
Directory /workspace/58.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.1708445708
Short name T1733
Test name
Test status
Simulation time 7507810145 ps
CPU time 239.92 seconds
Started Jul 14 07:38:14 PM PDT 24
Finished Jul 14 07:42:14 PM PDT 24
Peak memory 575596 kb
Host smart-a1f23908-e172-4e75-a2db-e116881e1db3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708445708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al
l_with_reset_error.1708445708
Directory /workspace/58.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.2686885923
Short name T1456
Test name
Test status
Simulation time 59680067 ps
CPU time 9.6 seconds
Started Jul 14 07:38:13 PM PDT 24
Finished Jul 14 07:38:23 PM PDT 24
Peak memory 575400 kb
Host smart-c88f982f-d5d9-4afd-86d4-072333aef638
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686885923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.2686885923
Directory /workspace/58.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_access_same_device.249627811
Short name T2360
Test name
Test status
Simulation time 3083625227 ps
CPU time 125.93 seconds
Started Jul 14 07:38:18 PM PDT 24
Finished Jul 14 07:40:24 PM PDT 24
Peak memory 575416 kb
Host smart-baf5b583-936d-44e8-8423-47050c869d70
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249627811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device.
249627811
Directory /workspace/59.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.1614304399
Short name T1661
Test name
Test status
Simulation time 375473436 ps
CPU time 16.37 seconds
Started Jul 14 07:38:22 PM PDT 24
Finished Jul 14 07:38:38 PM PDT 24
Peak memory 575096 kb
Host smart-e6845d0d-4745-4e6a-b5fd-a171a2c70695
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614304399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add
r.1614304399
Directory /workspace/59.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_error_random.2456944745
Short name T2740
Test name
Test status
Simulation time 260119882 ps
CPU time 11.82 seconds
Started Jul 14 07:38:20 PM PDT 24
Finished Jul 14 07:38:32 PM PDT 24
Peak memory 574048 kb
Host smart-9f2a033b-1e5c-4559-b968-4bbea9f1ed37
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456944745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.2456944745
Directory /workspace/59.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random.1489370513
Short name T1828
Test name
Test status
Simulation time 2092960388 ps
CPU time 73.7 seconds
Started Jul 14 07:38:15 PM PDT 24
Finished Jul 14 07:39:29 PM PDT 24
Peak memory 575372 kb
Host smart-bd0edac4-d1f1-4051-b514-3c8b1b3def41
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489370513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.1489370513
Directory /workspace/59.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.1875705949
Short name T2606
Test name
Test status
Simulation time 4538571000 ps
CPU time 50.04 seconds
Started Jul 14 07:38:20 PM PDT 24
Finished Jul 14 07:39:11 PM PDT 24
Peak memory 574360 kb
Host smart-698bb348-66b8-4503-b0a5-610fb77ed451
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875705949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.1875705949
Directory /workspace/59.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.684502701
Short name T2852
Test name
Test status
Simulation time 55162875705 ps
CPU time 1023.29 seconds
Started Jul 14 07:38:19 PM PDT 24
Finished Jul 14 07:55:23 PM PDT 24
Peak memory 575512 kb
Host smart-2400d197-53ef-4b63-803e-49e273866c76
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684502701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.684502701
Directory /workspace/59.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.934813698
Short name T1978
Test name
Test status
Simulation time 35257631 ps
CPU time 6.09 seconds
Started Jul 14 07:38:14 PM PDT 24
Finished Jul 14 07:38:20 PM PDT 24
Peak memory 574024 kb
Host smart-3bd79d50-7908-48eb-8c90-aeb30f5fada4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934813698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_dela
ys.934813698
Directory /workspace/59.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_same_source.1806644433
Short name T1945
Test name
Test status
Simulation time 197149998 ps
CPU time 16.4 seconds
Started Jul 14 07:38:22 PM PDT 24
Finished Jul 14 07:38:38 PM PDT 24
Peak memory 575344 kb
Host smart-d4e03935-7fbc-402a-aff9-16d97ab5bba1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806644433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.1806644433
Directory /workspace/59.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke.154990529
Short name T1563
Test name
Test status
Simulation time 183725516 ps
CPU time 8.2 seconds
Started Jul 14 07:38:13 PM PDT 24
Finished Jul 14 07:38:22 PM PDT 24
Peak memory 574036 kb
Host smart-af73bb7b-bab9-45ce-8cdd-c7bc84717e78
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154990529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.154990529
Directory /workspace/59.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.1487113230
Short name T1490
Test name
Test status
Simulation time 9275827905 ps
CPU time 103.17 seconds
Started Jul 14 07:38:13 PM PDT 24
Finished Jul 14 07:39:56 PM PDT 24
Peak memory 574204 kb
Host smart-c987d3dc-7f7e-44a5-bb61-0c27fff7ef48
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487113230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.1487113230
Directory /workspace/59.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.1371988051
Short name T659
Test name
Test status
Simulation time 5016049377 ps
CPU time 92.02 seconds
Started Jul 14 07:38:16 PM PDT 24
Finished Jul 14 07:39:49 PM PDT 24
Peak memory 574164 kb
Host smart-3e43c5a0-ab16-4460-b744-d6b51b4fc02b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371988051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.1371988051
Directory /workspace/59.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.3978209889
Short name T2306
Test name
Test status
Simulation time 51559824 ps
CPU time 6.51 seconds
Started Jul 14 07:38:15 PM PDT 24
Finished Jul 14 07:38:22 PM PDT 24
Peak memory 575288 kb
Host smart-45d17606-73d0-42c9-94a6-dfc1b7199aa5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978209889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay
s.3978209889
Directory /workspace/59.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all.390605643
Short name T511
Test name
Test status
Simulation time 2718086877 ps
CPU time 184.38 seconds
Started Jul 14 07:38:20 PM PDT 24
Finished Jul 14 07:41:25 PM PDT 24
Peak memory 575536 kb
Host smart-eb507937-701f-459f-ab14-14be3f884163
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390605643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.390605643
Directory /workspace/59.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.361945839
Short name T2550
Test name
Test status
Simulation time 8771065240 ps
CPU time 345.46 seconds
Started Jul 14 07:38:20 PM PDT 24
Finished Jul 14 07:44:05 PM PDT 24
Peak memory 575572 kb
Host smart-7aa2f4e1-9755-4bdd-8ba1-d78b178239a8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361945839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.361945839
Directory /workspace/59.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3067968346
Short name T1379
Test name
Test status
Simulation time 7817799 ps
CPU time 32.02 seconds
Started Jul 14 07:38:21 PM PDT 24
Finished Jul 14 07:38:53 PM PDT 24
Peak memory 574020 kb
Host smart-c3621736-e85c-4a67-8b23-ff345b4aa2a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067968346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all
_with_rand_reset.3067968346
Directory /workspace/59.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.555708793
Short name T1662
Test name
Test status
Simulation time 18122558833 ps
CPU time 770.43 seconds
Started Jul 14 07:38:25 PM PDT 24
Finished Jul 14 07:51:16 PM PDT 24
Peak memory 575588 kb
Host smart-a8626aef-b9b1-4f47-b715-827f3df2277e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555708793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all
_with_reset_error.555708793
Directory /workspace/59.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.2403352642
Short name T1986
Test name
Test status
Simulation time 1424151419 ps
CPU time 64.13 seconds
Started Jul 14 07:38:18 PM PDT 24
Finished Jul 14 07:39:22 PM PDT 24
Peak memory 575344 kb
Host smart-29e9599c-110f-4539-8d93-e8741599fee9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403352642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.2403352642
Directory /workspace/59.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/6.chip_csr_rw.3306471458
Short name T383
Test name
Test status
Simulation time 4284247005 ps
CPU time 326.16 seconds
Started Jul 14 07:28:28 PM PDT 24
Finished Jul 14 07:33:55 PM PDT 24
Peak memory 597316 kb
Host smart-8574461d-99e3-4944-8367-3ea8a04676a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306471458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.3306471458
Directory /workspace/6.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.707557146
Short name T381
Test name
Test status
Simulation time 31188292491 ps
CPU time 3935.1 seconds
Started Jul 14 07:28:13 PM PDT 24
Finished Jul 14 08:33:49 PM PDT 24
Peak memory 593348 kb
Host smart-ce323937-50c2-4c8f-848d-5f9496bc58cb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707557146 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.chip_same_csr_outstanding.707557146
Directory /workspace/6.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.chip_tl_errors.2328431833
Short name T696
Test name
Test status
Simulation time 3410491735 ps
CPU time 215.13 seconds
Started Jul 14 07:28:14 PM PDT 24
Finished Jul 14 07:31:50 PM PDT 24
Peak memory 599720 kb
Host smart-5a946247-fe24-4367-9cc6-c51edc1f11ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328431833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.2328431833
Directory /workspace/6.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_access_same_device.2032426183
Short name T2874
Test name
Test status
Simulation time 899238091 ps
CPU time 42.38 seconds
Started Jul 14 07:28:17 PM PDT 24
Finished Jul 14 07:29:00 PM PDT 24
Peak memory 575284 kb
Host smart-ef84d2e1-5e66-4244-be91-b6c93e7dcb5d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032426183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.
2032426183
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.1681173587
Short name T1864
Test name
Test status
Simulation time 262827504 ps
CPU time 12.84 seconds
Started Jul 14 07:28:24 PM PDT 24
Finished Jul 14 07:28:38 PM PDT 24
Peak memory 575360 kb
Host smart-448527c1-4435-4200-b29d-a2759e063fa4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681173587 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr
.1681173587
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_error_random.159120440
Short name T2777
Test name
Test status
Simulation time 231139875 ps
CPU time 24.03 seconds
Started Jul 14 07:28:27 PM PDT 24
Finished Jul 14 07:28:52 PM PDT 24
Peak memory 575044 kb
Host smart-690a8f09-69f8-4581-8714-498d334db34d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159120440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.159120440
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random.4138975554
Short name T2417
Test name
Test status
Simulation time 457338755 ps
CPU time 42.08 seconds
Started Jul 14 07:28:18 PM PDT 24
Finished Jul 14 07:29:00 PM PDT 24
Peak memory 575332 kb
Host smart-fba113ed-31af-4917-ba07-47153071f487
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138975554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.4138975554
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.2511452446
Short name T610
Test name
Test status
Simulation time 60196689996 ps
CPU time 670.46 seconds
Started Jul 14 07:28:17 PM PDT 24
Finished Jul 14 07:39:28 PM PDT 24
Peak memory 575484 kb
Host smart-8b78db10-5fe6-4480-99ff-f78ff0f37556
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511452446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2511452446
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.2925132013
Short name T1592
Test name
Test status
Simulation time 55437218192 ps
CPU time 964.72 seconds
Started Jul 14 07:28:18 PM PDT 24
Finished Jul 14 07:44:23 PM PDT 24
Peak memory 575528 kb
Host smart-4265c54a-4b91-4a94-9fda-f2d60bed6a61
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925132013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2925132013
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.208010312
Short name T1788
Test name
Test status
Simulation time 254846378 ps
CPU time 21.42 seconds
Started Jul 14 07:28:18 PM PDT 24
Finished Jul 14 07:28:40 PM PDT 24
Peak memory 575316 kb
Host smart-71103a28-8748-4e2f-b1f0-54c8ed62a057
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208010312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delay
s.208010312
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_same_source.3349774840
Short name T2567
Test name
Test status
Simulation time 262360847 ps
CPU time 23.42 seconds
Started Jul 14 07:28:24 PM PDT 24
Finished Jul 14 07:28:48 PM PDT 24
Peak memory 575264 kb
Host smart-ede51605-77c9-4279-8ce8-35a4e1187c90
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349774840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3349774840
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke.3108243397
Short name T2383
Test name
Test status
Simulation time 46133300 ps
CPU time 6.31 seconds
Started Jul 14 07:28:17 PM PDT 24
Finished Jul 14 07:28:24 PM PDT 24
Peak memory 573996 kb
Host smart-d64f1f6c-c8bb-46c6-af7a-d31e3072bf28
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108243397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3108243397
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.2467838270
Short name T2226
Test name
Test status
Simulation time 6813203269 ps
CPU time 75.36 seconds
Started Jul 14 07:28:19 PM PDT 24
Finished Jul 14 07:29:35 PM PDT 24
Peak memory 574172 kb
Host smart-118df334-4447-4712-ba98-d42bd25311c6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467838270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2467838270
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.2211499789
Short name T1427
Test name
Test status
Simulation time 4943945569 ps
CPU time 83.37 seconds
Started Jul 14 07:28:16 PM PDT 24
Finished Jul 14 07:29:40 PM PDT 24
Peak memory 575432 kb
Host smart-cb4d88fe-fa27-46ae-9d96-fb02b7682835
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211499789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2211499789
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.3881071399
Short name T1435
Test name
Test status
Simulation time 49749240 ps
CPU time 6.11 seconds
Started Jul 14 07:28:17 PM PDT 24
Finished Jul 14 07:28:23 PM PDT 24
Peak memory 574040 kb
Host smart-3439d09c-a85d-4822-8927-9c09dce4ed80
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881071399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays
.3881071399
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all.61635162
Short name T1660
Test name
Test status
Simulation time 1309222209 ps
CPU time 110.12 seconds
Started Jul 14 07:28:24 PM PDT 24
Finished Jul 14 07:30:15 PM PDT 24
Peak memory 575508 kb
Host smart-aaa224af-becf-4846-a8a6-5543892b1d13
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61635162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.61635162
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.485187870
Short name T1948
Test name
Test status
Simulation time 708768061 ps
CPU time 55.12 seconds
Started Jul 14 07:28:28 PM PDT 24
Finished Jul 14 07:29:24 PM PDT 24
Peak memory 575436 kb
Host smart-cc4868bc-4226-4a38-9892-633cccf9c2e7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485187870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.485187870
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.183580839
Short name T2302
Test name
Test status
Simulation time 3354919902 ps
CPU time 308.39 seconds
Started Jul 14 07:28:22 PM PDT 24
Finished Jul 14 07:33:31 PM PDT 24
Peak memory 575508 kb
Host smart-f190c3d5-34cf-46da-94c4-8b6ff6cdc50d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183580839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_w
ith_rand_reset.183580839
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.2104107316
Short name T2561
Test name
Test status
Simulation time 53226939 ps
CPU time 36.54 seconds
Started Jul 14 07:28:30 PM PDT 24
Finished Jul 14 07:29:07 PM PDT 24
Peak memory 575440 kb
Host smart-ff4fd82f-6b9b-409f-ba81-e5eb0e76ce86
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104107316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all
_with_reset_error.2104107316
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.1540192640
Short name T2208
Test name
Test status
Simulation time 927285640 ps
CPU time 40.39 seconds
Started Jul 14 07:28:23 PM PDT 24
Finished Jul 14 07:29:04 PM PDT 24
Peak memory 575292 kb
Host smart-d92a869f-97c5-4838-95b0-16c5bef2bc82
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540192640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1540192640
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_access_same_device.193496137
Short name T2498
Test name
Test status
Simulation time 203523809 ps
CPU time 17.3 seconds
Started Jul 14 07:38:26 PM PDT 24
Finished Jul 14 07:38:44 PM PDT 24
Peak memory 575276 kb
Host smart-d4381dec-c4a1-43f6-ab7e-5a6233041e39
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193496137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device.
193496137
Directory /workspace/60.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.3408343843
Short name T1556
Test name
Test status
Simulation time 8637860201 ps
CPU time 164.44 seconds
Started Jul 14 07:38:30 PM PDT 24
Finished Jul 14 07:41:15 PM PDT 24
Peak memory 575472 kb
Host smart-5d53ecc1-ee5c-40c2-adad-6e78ee3b60e8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408343843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_
device_slow_rsp.3408343843
Directory /workspace/60.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.254288169
Short name T2358
Test name
Test status
Simulation time 85554309 ps
CPU time 9.89 seconds
Started Jul 14 07:38:33 PM PDT 24
Finished Jul 14 07:38:44 PM PDT 24
Peak memory 575292 kb
Host smart-fc145cec-25e4-4adf-b8b6-1f70a69b18be
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254288169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_addr
.254288169
Directory /workspace/60.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_error_random.3026397528
Short name T1414
Test name
Test status
Simulation time 218391544 ps
CPU time 18.04 seconds
Started Jul 14 07:38:32 PM PDT 24
Finished Jul 14 07:38:51 PM PDT 24
Peak memory 575296 kb
Host smart-e0100257-8575-4aa0-9bdb-61420ddb8ad6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026397528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.3026397528
Directory /workspace/60.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random.3382408208
Short name T1701
Test name
Test status
Simulation time 320314761 ps
CPU time 15.1 seconds
Started Jul 14 07:38:27 PM PDT 24
Finished Jul 14 07:38:42 PM PDT 24
Peak memory 575360 kb
Host smart-29a8dc5b-91ff-449b-bd6c-ee19a0ad50ad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382408208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.3382408208
Directory /workspace/60.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.39843133
Short name T1785
Test name
Test status
Simulation time 21146127712 ps
CPU time 258.33 seconds
Started Jul 14 07:38:26 PM PDT 24
Finished Jul 14 07:42:45 PM PDT 24
Peak memory 575484 kb
Host smart-0eaec362-7872-4955-99e0-52d5137d6f00
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39843133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.39843133
Directory /workspace/60.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.1567960991
Short name T2603
Test name
Test status
Simulation time 9066693882 ps
CPU time 160.2 seconds
Started Jul 14 07:38:27 PM PDT 24
Finished Jul 14 07:41:07 PM PDT 24
Peak memory 575504 kb
Host smart-bb664d55-1bb2-4c72-b445-26d5e460601f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567960991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.1567960991
Directory /workspace/60.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.3957141916
Short name T2460
Test name
Test status
Simulation time 148098159 ps
CPU time 15.12 seconds
Started Jul 14 07:38:26 PM PDT 24
Finished Jul 14 07:38:42 PM PDT 24
Peak memory 575344 kb
Host smart-651fec9c-925f-4948-93ba-53edee4982d5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957141916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del
ays.3957141916
Directory /workspace/60.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_same_source.1968672564
Short name T2695
Test name
Test status
Simulation time 2502413833 ps
CPU time 74.12 seconds
Started Jul 14 07:38:29 PM PDT 24
Finished Jul 14 07:39:43 PM PDT 24
Peak memory 575380 kb
Host smart-ca812b99-c012-41a1-acd4-0f4239e6a388
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968672564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.1968672564
Directory /workspace/60.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke.1880167268
Short name T1548
Test name
Test status
Simulation time 45980123 ps
CPU time 6.14 seconds
Started Jul 14 07:38:28 PM PDT 24
Finished Jul 14 07:38:35 PM PDT 24
Peak memory 575264 kb
Host smart-c03a5ebe-61a8-48c1-b56b-2ee05515a3a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880167268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.1880167268
Directory /workspace/60.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.3216276805
Short name T1623
Test name
Test status
Simulation time 5686119028 ps
CPU time 63.75 seconds
Started Jul 14 07:38:28 PM PDT 24
Finished Jul 14 07:39:32 PM PDT 24
Peak memory 574164 kb
Host smart-c4b44923-9984-4046-b1d1-127e7368aaff
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216276805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.3216276805
Directory /workspace/60.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.651203498
Short name T2316
Test name
Test status
Simulation time 3598419965 ps
CPU time 63.78 seconds
Started Jul 14 07:38:29 PM PDT 24
Finished Jul 14 07:39:33 PM PDT 24
Peak memory 575328 kb
Host smart-5efe80b4-1285-47b4-a847-9f633ab799fe
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651203498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.651203498
Directory /workspace/60.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.2360929977
Short name T2282
Test name
Test status
Simulation time 50965972 ps
CPU time 6.83 seconds
Started Jul 14 07:38:30 PM PDT 24
Finished Jul 14 07:38:37 PM PDT 24
Peak memory 575240 kb
Host smart-24f34620-2cb9-4911-8909-bf69ff80dc12
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360929977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay
s.2360929977
Directory /workspace/60.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all.1448857500
Short name T614
Test name
Test status
Simulation time 6700122092 ps
CPU time 281.84 seconds
Started Jul 14 07:38:35 PM PDT 24
Finished Jul 14 07:43:17 PM PDT 24
Peak memory 575592 kb
Host smart-eac27839-6cfd-43ae-9636-638bc20b1cef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448857500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.1448857500
Directory /workspace/60.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.2411853429
Short name T2443
Test name
Test status
Simulation time 1383152604 ps
CPU time 94.94 seconds
Started Jul 14 07:38:57 PM PDT 24
Finished Jul 14 07:40:33 PM PDT 24
Peak memory 575448 kb
Host smart-bdb3c219-9183-4b30-99ec-7d8d1edf9ac9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411853429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.2411853429
Directory /workspace/60.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.1624980962
Short name T2575
Test name
Test status
Simulation time 5892960161 ps
CPU time 524.52 seconds
Started Jul 14 07:38:33 PM PDT 24
Finished Jul 14 07:47:19 PM PDT 24
Peak memory 575628 kb
Host smart-da40c734-e057-46b7-9aa5-f3f4a77af0b2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624980962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all
_with_rand_reset.1624980962
Directory /workspace/60.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.1438148906
Short name T822
Test name
Test status
Simulation time 3048607735 ps
CPU time 185.52 seconds
Started Jul 14 07:38:34 PM PDT 24
Finished Jul 14 07:41:40 PM PDT 24
Peak memory 575516 kb
Host smart-a9fd1a4f-7d91-485e-b4ec-3b0fb6e21b17
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438148906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al
l_with_reset_error.1438148906
Directory /workspace/60.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.2778738178
Short name T1753
Test name
Test status
Simulation time 313419115 ps
CPU time 30.63 seconds
Started Jul 14 07:38:32 PM PDT 24
Finished Jul 14 07:39:03 PM PDT 24
Peak memory 575384 kb
Host smart-1aea9a83-8bc3-4fdd-8262-1c6edc7847fb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778738178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.2778738178
Directory /workspace/60.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_access_same_device.77641178
Short name T2751
Test name
Test status
Simulation time 2372119374 ps
CPU time 89.87 seconds
Started Jul 14 07:38:39 PM PDT 24
Finished Jul 14 07:40:09 PM PDT 24
Peak memory 575500 kb
Host smart-f4d4a05a-fbec-4478-8b4e-820f4b1bbbce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77641178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device.77641178
Directory /workspace/61.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.1297072062
Short name T2347
Test name
Test status
Simulation time 88997485954 ps
CPU time 1691.02 seconds
Started Jul 14 07:38:36 PM PDT 24
Finished Jul 14 08:06:48 PM PDT 24
Peak memory 575508 kb
Host smart-2891b647-3315-46b7-8399-43851b83db4c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297072062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_
device_slow_rsp.1297072062
Directory /workspace/61.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.1469120561
Short name T2301
Test name
Test status
Simulation time 321624436 ps
CPU time 14.99 seconds
Started Jul 14 07:38:37 PM PDT 24
Finished Jul 14 07:38:52 PM PDT 24
Peak memory 575336 kb
Host smart-204c03eb-cb01-4ea8-9734-3d821ccbb11d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469120561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add
r.1469120561
Directory /workspace/61.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_error_random.691994821
Short name T1741
Test name
Test status
Simulation time 1167386578 ps
CPU time 38.68 seconds
Started Jul 14 07:38:38 PM PDT 24
Finished Jul 14 07:39:17 PM PDT 24
Peak memory 575264 kb
Host smart-511d1790-da71-43fe-b4af-0783ed06424a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691994821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.691994821
Directory /workspace/61.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random.3405868882
Short name T2463
Test name
Test status
Simulation time 398563068 ps
CPU time 36.01 seconds
Started Jul 14 07:38:40 PM PDT 24
Finished Jul 14 07:39:16 PM PDT 24
Peak memory 575408 kb
Host smart-f43dcd3f-0dea-4bd2-8d43-4d2b39efd117
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405868882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.3405868882
Directory /workspace/61.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.2467922761
Short name T1514
Test name
Test status
Simulation time 13242527214 ps
CPU time 146.19 seconds
Started Jul 14 07:38:37 PM PDT 24
Finished Jul 14 07:41:04 PM PDT 24
Peak memory 575524 kb
Host smart-0b54b162-c62d-4653-b433-68833082d7e4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467922761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.2467922761
Directory /workspace/61.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.1656530418
Short name T2054
Test name
Test status
Simulation time 38515461808 ps
CPU time 658.12 seconds
Started Jul 14 07:38:38 PM PDT 24
Finished Jul 14 07:49:37 PM PDT 24
Peak memory 575696 kb
Host smart-9bd83d6b-d890-4d79-a344-8e259512933f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656530418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.1656530418
Directory /workspace/61.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.635474483
Short name T1821
Test name
Test status
Simulation time 355392658 ps
CPU time 34.2 seconds
Started Jul 14 07:38:42 PM PDT 24
Finished Jul 14 07:39:17 PM PDT 24
Peak memory 575304 kb
Host smart-1ebbf8df-676c-4fa6-b8c1-e2b2d4ce0b71
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635474483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_dela
ys.635474483
Directory /workspace/61.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_same_source.1540971895
Short name T2017
Test name
Test status
Simulation time 352375499 ps
CPU time 25.37 seconds
Started Jul 14 07:38:37 PM PDT 24
Finished Jul 14 07:39:03 PM PDT 24
Peak memory 575296 kb
Host smart-7109f6b4-418e-4edf-8654-787918bc9fd0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540971895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.1540971895
Directory /workspace/61.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke.1288663615
Short name T2733
Test name
Test status
Simulation time 207057776 ps
CPU time 8.94 seconds
Started Jul 14 07:38:38 PM PDT 24
Finished Jul 14 07:38:47 PM PDT 24
Peak memory 575248 kb
Host smart-72d7f368-e669-4bcc-975e-1e9521774afd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288663615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.1288663615
Directory /workspace/61.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.4129239411
Short name T1965
Test name
Test status
Simulation time 9296004312 ps
CPU time 102.08 seconds
Started Jul 14 07:38:42 PM PDT 24
Finished Jul 14 07:40:24 PM PDT 24
Peak memory 574140 kb
Host smart-ca1bd07e-d978-4a1b-8b4a-113460f6720a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129239411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.4129239411
Directory /workspace/61.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.500396378
Short name T1816
Test name
Test status
Simulation time 4764062232 ps
CPU time 84.12 seconds
Started Jul 14 07:38:37 PM PDT 24
Finished Jul 14 07:40:02 PM PDT 24
Peak memory 574196 kb
Host smart-a65c1cec-bf1f-44f0-975d-20d89d3b0380
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500396378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.500396378
Directory /workspace/61.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.536365635
Short name T1333
Test name
Test status
Simulation time 39456410 ps
CPU time 6 seconds
Started Jul 14 07:38:37 PM PDT 24
Finished Jul 14 07:38:43 PM PDT 24
Peak memory 573980 kb
Host smart-8e3bf907-0655-4573-beb0-cb14d92dc819
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536365635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delays
.536365635
Directory /workspace/61.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all.3087576807
Short name T1901
Test name
Test status
Simulation time 1651474128 ps
CPU time 123.18 seconds
Started Jul 14 07:38:45 PM PDT 24
Finished Jul 14 07:40:49 PM PDT 24
Peak memory 575460 kb
Host smart-5242dd00-90db-403a-bb4c-afeecde50c43
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087576807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.3087576807
Directory /workspace/61.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.4199573224
Short name T1398
Test name
Test status
Simulation time 211791105 ps
CPU time 21.21 seconds
Started Jul 14 07:38:48 PM PDT 24
Finished Jul 14 07:39:09 PM PDT 24
Peak memory 575332 kb
Host smart-9106bc87-5adc-4f62-95a5-208c318f39bd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199573224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.4199573224
Directory /workspace/61.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.3012211574
Short name T2127
Test name
Test status
Simulation time 116346199 ps
CPU time 65.47 seconds
Started Jul 14 07:38:44 PM PDT 24
Finished Jul 14 07:39:50 PM PDT 24
Peak memory 575468 kb
Host smart-d102f74e-204e-448c-a442-30dc86ca2e75
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012211574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all
_with_rand_reset.3012211574
Directory /workspace/61.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.2506579646
Short name T848
Test name
Test status
Simulation time 6467300429 ps
CPU time 443.08 seconds
Started Jul 14 07:38:45 PM PDT 24
Finished Jul 14 07:46:09 PM PDT 24
Peak memory 575612 kb
Host smart-406ccd4d-9b0c-414f-990b-8e9865410693
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506579646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al
l_with_reset_error.2506579646
Directory /workspace/61.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.2486176494
Short name T1793
Test name
Test status
Simulation time 207171681 ps
CPU time 24.65 seconds
Started Jul 14 07:38:37 PM PDT 24
Finished Jul 14 07:39:02 PM PDT 24
Peak memory 575396 kb
Host smart-b446e7a1-10bd-4bbe-995f-1d7bfb4474a4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486176494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.2486176494
Directory /workspace/61.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_access_same_device.629960125
Short name T2197
Test name
Test status
Simulation time 819088448 ps
CPU time 37.52 seconds
Started Jul 14 07:38:48 PM PDT 24
Finished Jul 14 07:39:26 PM PDT 24
Peak memory 575296 kb
Host smart-5550b6a4-4626-4c90-a6f6-4600798f265f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629960125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device.
629960125
Directory /workspace/62.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.1488756054
Short name T1510
Test name
Test status
Simulation time 53213218621 ps
CPU time 979.84 seconds
Started Jul 14 07:38:43 PM PDT 24
Finished Jul 14 07:55:04 PM PDT 24
Peak memory 575496 kb
Host smart-01e84c7b-cdd8-4c3f-be08-4fa484143b99
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488756054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_
device_slow_rsp.1488756054
Directory /workspace/62.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.818523769
Short name T2033
Test name
Test status
Simulation time 302001460 ps
CPU time 29.87 seconds
Started Jul 14 07:38:43 PM PDT 24
Finished Jul 14 07:39:14 PM PDT 24
Peak memory 575300 kb
Host smart-aa7be15f-7eba-46ad-b687-c9a31c59ef5c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818523769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_addr
.818523769
Directory /workspace/62.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_error_random.1935904764
Short name T671
Test name
Test status
Simulation time 188501002 ps
CPU time 16.7 seconds
Started Jul 14 07:38:42 PM PDT 24
Finished Jul 14 07:38:59 PM PDT 24
Peak memory 575300 kb
Host smart-eee30d4e-04a3-4849-b5a4-f32d9020859d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935904764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.1935904764
Directory /workspace/62.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random.3122470548
Short name T1682
Test name
Test status
Simulation time 1227330059 ps
CPU time 48.35 seconds
Started Jul 14 07:38:46 PM PDT 24
Finished Jul 14 07:39:35 PM PDT 24
Peak memory 575336 kb
Host smart-1cf0e7b6-d04e-460d-85d9-5c0fb44a9488
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122470548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.3122470548
Directory /workspace/62.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.951884900
Short name T2760
Test name
Test status
Simulation time 36515822158 ps
CPU time 425.14 seconds
Started Jul 14 07:38:46 PM PDT 24
Finished Jul 14 07:45:51 PM PDT 24
Peak memory 575452 kb
Host smart-611782b6-ddc2-4e0f-9a56-45e298f4639a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951884900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.951884900
Directory /workspace/62.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.647751318
Short name T1989
Test name
Test status
Simulation time 13808520819 ps
CPU time 252.06 seconds
Started Jul 14 07:38:45 PM PDT 24
Finished Jul 14 07:42:58 PM PDT 24
Peak memory 575520 kb
Host smart-7117c9cd-e27f-4c92-b88d-76c9ac213da9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647751318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.647751318
Directory /workspace/62.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.4164747357
Short name T2748
Test name
Test status
Simulation time 274862965 ps
CPU time 22.76 seconds
Started Jul 14 07:38:44 PM PDT 24
Finished Jul 14 07:39:07 PM PDT 24
Peak memory 575272 kb
Host smart-c7530d93-f653-4eba-9d80-24fe3e57c719
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164747357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del
ays.4164747357
Directory /workspace/62.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_same_source.2995630295
Short name T2441
Test name
Test status
Simulation time 2056499919 ps
CPU time 63.28 seconds
Started Jul 14 07:38:45 PM PDT 24
Finished Jul 14 07:39:48 PM PDT 24
Peak memory 575296 kb
Host smart-4b0a8dc3-0c99-4e1f-a37c-5a3574663231
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995630295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.2995630295
Directory /workspace/62.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke.1982818380
Short name T2286
Test name
Test status
Simulation time 51841469 ps
CPU time 6.37 seconds
Started Jul 14 07:38:45 PM PDT 24
Finished Jul 14 07:38:52 PM PDT 24
Peak memory 574004 kb
Host smart-7f9387ed-dad9-4557-b205-d6faf7a03d33
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982818380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.1982818380
Directory /workspace/62.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.4124199859
Short name T631
Test name
Test status
Simulation time 7746297404 ps
CPU time 88.08 seconds
Started Jul 14 07:38:45 PM PDT 24
Finished Jul 14 07:40:14 PM PDT 24
Peak memory 574132 kb
Host smart-918826b4-0ba5-4389-85c9-c0452df5a8c2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124199859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.4124199859
Directory /workspace/62.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.241024277
Short name T1336
Test name
Test status
Simulation time 3613940071 ps
CPU time 66.74 seconds
Started Jul 14 07:38:44 PM PDT 24
Finished Jul 14 07:39:51 PM PDT 24
Peak memory 574100 kb
Host smart-7ddf7662-373d-4a76-89ac-765cacf09ad4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241024277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.241024277
Directory /workspace/62.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.2646652926
Short name T1975
Test name
Test status
Simulation time 42741707 ps
CPU time 5.99 seconds
Started Jul 14 07:38:45 PM PDT 24
Finished Jul 14 07:38:52 PM PDT 24
Peak memory 574028 kb
Host smart-df67be34-4cd6-4024-ba00-6eca29604d7f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646652926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay
s.2646652926
Directory /workspace/62.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all.1066285077
Short name T2162
Test name
Test status
Simulation time 1560535624 ps
CPU time 127.99 seconds
Started Jul 14 07:38:52 PM PDT 24
Finished Jul 14 07:41:00 PM PDT 24
Peak memory 575508 kb
Host smart-38ae4524-1a27-415d-a40f-02b8fc29456a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066285077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.1066285077
Directory /workspace/62.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.4156848685
Short name T1575
Test name
Test status
Simulation time 6998906876 ps
CPU time 228.71 seconds
Started Jul 14 07:38:51 PM PDT 24
Finished Jul 14 07:42:40 PM PDT 24
Peak memory 575600 kb
Host smart-9c575e81-045f-4da0-848b-3be452901231
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156848685 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.4156848685
Directory /workspace/62.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.4255614730
Short name T1569
Test name
Test status
Simulation time 71968725 ps
CPU time 27.33 seconds
Started Jul 14 07:38:53 PM PDT 24
Finished Jul 14 07:39:21 PM PDT 24
Peak memory 575424 kb
Host smart-f8025d80-de1e-482e-a334-e5504970a3bb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255614730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all
_with_rand_reset.4255614730
Directory /workspace/62.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.3766725805
Short name T858
Test name
Test status
Simulation time 8762316465 ps
CPU time 586.81 seconds
Started Jul 14 07:38:51 PM PDT 24
Finished Jul 14 07:48:39 PM PDT 24
Peak memory 578652 kb
Host smart-03f8399f-6211-42dd-bfbc-10078ba1bf66
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766725805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al
l_with_reset_error.3766725805
Directory /workspace/62.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.76661762
Short name T2023
Test name
Test status
Simulation time 200371596 ps
CPU time 22.33 seconds
Started Jul 14 07:38:45 PM PDT 24
Finished Jul 14 07:39:08 PM PDT 24
Peak memory 575432 kb
Host smart-79b49755-e70f-475a-a5ef-a412934dce26
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76661762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.76661762
Directory /workspace/62.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_access_same_device.1092099497
Short name T2727
Test name
Test status
Simulation time 847011894 ps
CPU time 34.7 seconds
Started Jul 14 07:38:59 PM PDT 24
Finished Jul 14 07:39:35 PM PDT 24
Peak memory 575352 kb
Host smart-73a1e0c4-d879-4209-9e92-1cf87df73f39
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092099497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device
.1092099497
Directory /workspace/63.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.761407710
Short name T1953
Test name
Test status
Simulation time 76431220977 ps
CPU time 1463.65 seconds
Started Jul 14 07:38:57 PM PDT 24
Finished Jul 14 08:03:22 PM PDT 24
Peak memory 575528 kb
Host smart-960a5a08-a7ea-4e4f-a5bd-e10b6a65623b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761407710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_d
evice_slow_rsp.761407710
Directory /workspace/63.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.4040005751
Short name T2458
Test name
Test status
Simulation time 1400917489 ps
CPU time 52.97 seconds
Started Jul 14 07:38:56 PM PDT 24
Finished Jul 14 07:39:49 PM PDT 24
Peak memory 575072 kb
Host smart-341cfc14-5e68-4922-aac0-0f5e80b02275
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040005751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add
r.4040005751
Directory /workspace/63.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_error_random.778113835
Short name T1907
Test name
Test status
Simulation time 401288682 ps
CPU time 16.32 seconds
Started Jul 14 07:38:58 PM PDT 24
Finished Jul 14 07:39:15 PM PDT 24
Peak memory 575252 kb
Host smart-74eb133a-d027-40c2-82f1-39f51e84d81f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778113835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.778113835
Directory /workspace/63.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random.2269683393
Short name T656
Test name
Test status
Simulation time 157364315 ps
CPU time 16.3 seconds
Started Jul 14 07:38:52 PM PDT 24
Finished Jul 14 07:39:09 PM PDT 24
Peak memory 575336 kb
Host smart-3c5ffd52-d262-4d53-98da-a0b148e7f84b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269683393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.2269683393
Directory /workspace/63.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.3868156524
Short name T1445
Test name
Test status
Simulation time 49202856299 ps
CPU time 598.47 seconds
Started Jul 14 07:38:50 PM PDT 24
Finished Jul 14 07:48:49 PM PDT 24
Peak memory 575512 kb
Host smart-6cd3af73-f854-417f-a980-b84a9ff4f4cf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868156524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.3868156524
Directory /workspace/63.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.2551368415
Short name T2691
Test name
Test status
Simulation time 28774471701 ps
CPU time 471.14 seconds
Started Jul 14 07:38:55 PM PDT 24
Finished Jul 14 07:46:47 PM PDT 24
Peak memory 575532 kb
Host smart-9bba9b91-ef4a-4416-a9a4-43471fe997ca
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551368415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.2551368415
Directory /workspace/63.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.1240962244
Short name T1699
Test name
Test status
Simulation time 441413905 ps
CPU time 40.28 seconds
Started Jul 14 07:38:52 PM PDT 24
Finished Jul 14 07:39:33 PM PDT 24
Peak memory 575324 kb
Host smart-fc7b2edc-1f25-4c37-b51c-d704439b01b5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240962244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_del
ays.1240962244
Directory /workspace/63.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_same_source.2330173974
Short name T1463
Test name
Test status
Simulation time 568850203 ps
CPU time 37.08 seconds
Started Jul 14 07:38:56 PM PDT 24
Finished Jul 14 07:39:33 PM PDT 24
Peak memory 575252 kb
Host smart-d2579e1d-c891-49dc-bc18-d3c113692aea
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330173974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.2330173974
Directory /workspace/63.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke.188714606
Short name T623
Test name
Test status
Simulation time 221216107 ps
CPU time 9.23 seconds
Started Jul 14 07:38:52 PM PDT 24
Finished Jul 14 07:39:02 PM PDT 24
Peak memory 573968 kb
Host smart-6a93b387-c2f6-46bf-ada5-70041dcce7da
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188714606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.188714606
Directory /workspace/63.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.1282663544
Short name T2086
Test name
Test status
Simulation time 7816121618 ps
CPU time 86.34 seconds
Started Jul 14 07:38:52 PM PDT 24
Finished Jul 14 07:40:19 PM PDT 24
Peak memory 575384 kb
Host smart-81068cab-a58a-41bf-bc07-b82eb2f5551f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282663544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.1282663544
Directory /workspace/63.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.3771825678
Short name T2156
Test name
Test status
Simulation time 6244011125 ps
CPU time 114.43 seconds
Started Jul 14 07:40:06 PM PDT 24
Finished Jul 14 07:42:01 PM PDT 24
Peak memory 574196 kb
Host smart-b126641b-00a7-43f4-8a6a-14092cd2c05b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771825678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.3771825678
Directory /workspace/63.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.3561523398
Short name T1754
Test name
Test status
Simulation time 50508919 ps
CPU time 6.44 seconds
Started Jul 14 07:38:50 PM PDT 24
Finished Jul 14 07:38:57 PM PDT 24
Peak memory 574064 kb
Host smart-374ec470-96fd-4eea-9c35-c6d5b43d4287
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561523398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay
s.3561523398
Directory /workspace/63.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all.1595262677
Short name T1633
Test name
Test status
Simulation time 2742126316 ps
CPU time 227.92 seconds
Started Jul 14 07:38:57 PM PDT 24
Finished Jul 14 07:42:45 PM PDT 24
Peak memory 575544 kb
Host smart-3ac3f613-16ce-49cc-be36-01652287e018
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595262677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.1595262677
Directory /workspace/63.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.1289297794
Short name T1709
Test name
Test status
Simulation time 3061855430 ps
CPU time 226.86 seconds
Started Jul 14 07:38:57 PM PDT 24
Finished Jul 14 07:42:45 PM PDT 24
Peak memory 575552 kb
Host smart-64d6dce4-0a38-4470-ab39-f10ac60d9336
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289297794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.1289297794
Directory /workspace/63.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3151333383
Short name T2812
Test name
Test status
Simulation time 988141677 ps
CPU time 188.52 seconds
Started Jul 14 07:38:58 PM PDT 24
Finished Jul 14 07:42:08 PM PDT 24
Peak memory 575480 kb
Host smart-dfdd06cc-409b-47bf-a1d8-dfb30132f8b6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151333383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all
_with_rand_reset.3151333383
Directory /workspace/63.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.2871184536
Short name T2660
Test name
Test status
Simulation time 4624896815 ps
CPU time 296.03 seconds
Started Jul 14 07:38:59 PM PDT 24
Finished Jul 14 07:43:56 PM PDT 24
Peak memory 575316 kb
Host smart-9ccb08ae-c3c9-4a29-9d78-3afe5f39e3c4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871184536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al
l_with_reset_error.2871184536
Directory /workspace/63.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.3236227040
Short name T660
Test name
Test status
Simulation time 1347127728 ps
CPU time 53.42 seconds
Started Jul 14 07:38:57 PM PDT 24
Finished Jul 14 07:39:52 PM PDT 24
Peak memory 575408 kb
Host smart-fa2e2076-ed63-4602-b881-ca0c6ba10faf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236227040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.3236227040
Directory /workspace/63.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_access_same_device.2447648553
Short name T1481
Test name
Test status
Simulation time 866213577 ps
CPU time 31.72 seconds
Started Jul 14 07:39:03 PM PDT 24
Finished Jul 14 07:39:37 PM PDT 24
Peak memory 575368 kb
Host smart-97a5f44a-9854-4d4d-aa5c-8b7710d66725
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447648553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device
.2447648553
Directory /workspace/64.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.330477660
Short name T1961
Test name
Test status
Simulation time 13322505001 ps
CPU time 265.13 seconds
Started Jul 14 07:39:04 PM PDT 24
Finished Jul 14 07:43:31 PM PDT 24
Peak memory 575456 kb
Host smart-d5ec58c8-ffbf-4cd1-9772-8f3ea1156635
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330477660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_d
evice_slow_rsp.330477660
Directory /workspace/64.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.1256632402
Short name T2569
Test name
Test status
Simulation time 168157989 ps
CPU time 20.82 seconds
Started Jul 14 07:39:09 PM PDT 24
Finished Jul 14 07:39:30 PM PDT 24
Peak memory 575380 kb
Host smart-d23711c8-ff40-4391-98b8-a34749b6e066
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256632402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add
r.1256632402
Directory /workspace/64.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_error_random.4003420448
Short name T1540
Test name
Test status
Simulation time 2079925576 ps
CPU time 66.31 seconds
Started Jul 14 07:39:13 PM PDT 24
Finished Jul 14 07:40:20 PM PDT 24
Peak memory 575328 kb
Host smart-f3203d54-47b3-44d6-a78f-0c091850d51b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003420448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.4003420448
Directory /workspace/64.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random.2807254685
Short name T578
Test name
Test status
Simulation time 2566367005 ps
CPU time 95.17 seconds
Started Jul 14 07:39:03 PM PDT 24
Finished Jul 14 07:40:40 PM PDT 24
Peak memory 575348 kb
Host smart-48912fdd-c162-405f-995b-114b46e3ad3c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807254685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.2807254685
Directory /workspace/64.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.3107187848
Short name T2824
Test name
Test status
Simulation time 92174544087 ps
CPU time 1098.87 seconds
Started Jul 14 07:39:04 PM PDT 24
Finished Jul 14 07:57:24 PM PDT 24
Peak memory 575536 kb
Host smart-f94c1139-db4a-4975-b207-40973d7fda60
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107187848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.3107187848
Directory /workspace/64.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.782224364
Short name T2394
Test name
Test status
Simulation time 18395879827 ps
CPU time 305.67 seconds
Started Jul 14 07:39:03 PM PDT 24
Finished Jul 14 07:44:11 PM PDT 24
Peak memory 575440 kb
Host smart-2bdf13d5-771e-4497-b663-189c5a1d7df7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782224364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.782224364
Directory /workspace/64.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.3951840798
Short name T1497
Test name
Test status
Simulation time 443165623 ps
CPU time 41.16 seconds
Started Jul 14 07:39:03 PM PDT 24
Finished Jul 14 07:39:46 PM PDT 24
Peak memory 575344 kb
Host smart-7deba0d1-c1b7-4a09-b67c-95e2a153bd65
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951840798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del
ays.3951840798
Directory /workspace/64.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_same_source.2837620624
Short name T2386
Test name
Test status
Simulation time 523259420 ps
CPU time 36.58 seconds
Started Jul 14 07:39:13 PM PDT 24
Finished Jul 14 07:39:50 PM PDT 24
Peak memory 575340 kb
Host smart-bafd5e14-433e-44e4-abc9-813dd0866f53
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837620624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.2837620624
Directory /workspace/64.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke.3889608099
Short name T2629
Test name
Test status
Simulation time 189319474 ps
CPU time 9.19 seconds
Started Jul 14 07:38:57 PM PDT 24
Finished Jul 14 07:39:07 PM PDT 24
Peak memory 573976 kb
Host smart-003e3d1e-cd1f-47d0-aac4-ef2b5f40e6ad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889608099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.3889608099
Directory /workspace/64.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.1467297108
Short name T1863
Test name
Test status
Simulation time 7897953649 ps
CPU time 89.23 seconds
Started Jul 14 07:39:04 PM PDT 24
Finished Jul 14 07:40:35 PM PDT 24
Peak memory 574236 kb
Host smart-ed9d870a-fd7d-4ef8-a369-e56fb5031330
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467297108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.1467297108
Directory /workspace/64.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.1723508314
Short name T2743
Test name
Test status
Simulation time 5703849892 ps
CPU time 98.95 seconds
Started Jul 14 07:39:01 PM PDT 24
Finished Jul 14 07:40:42 PM PDT 24
Peak memory 574332 kb
Host smart-6b82bdb9-6fdb-4037-b4ad-3c0c37f51e66
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723508314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.1723508314
Directory /workspace/64.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.2240224617
Short name T2391
Test name
Test status
Simulation time 36460187 ps
CPU time 6.19 seconds
Started Jul 14 07:38:56 PM PDT 24
Finished Jul 14 07:39:02 PM PDT 24
Peak memory 574020 kb
Host smart-cc62034a-c108-4556-a5f5-e8582c83552b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240224617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay
s.2240224617
Directory /workspace/64.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all.1750327093
Short name T506
Test name
Test status
Simulation time 10946157795 ps
CPU time 388.99 seconds
Started Jul 14 07:39:11 PM PDT 24
Finished Jul 14 07:45:41 PM PDT 24
Peak memory 575564 kb
Host smart-25fa7915-9b89-4823-b38a-e1126b78a0c4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750327093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.1750327093
Directory /workspace/64.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.1438243198
Short name T1590
Test name
Test status
Simulation time 2084875355 ps
CPU time 63.15 seconds
Started Jul 14 07:39:12 PM PDT 24
Finished Jul 14 07:40:15 PM PDT 24
Peak memory 575336 kb
Host smart-2a9b432b-4802-4843-970a-a9667768a95e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438243198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.1438243198
Directory /workspace/64.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.520253250
Short name T1971
Test name
Test status
Simulation time 4059054096 ps
CPU time 312.01 seconds
Started Jul 14 07:39:11 PM PDT 24
Finished Jul 14 07:44:23 PM PDT 24
Peak memory 575496 kb
Host smart-21a4257c-02f5-4207-ad6c-fae17a1c6b33
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520253250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_
with_rand_reset.520253250
Directory /workspace/64.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3595174979
Short name T1955
Test name
Test status
Simulation time 422706305 ps
CPU time 92.87 seconds
Started Jul 14 07:39:13 PM PDT 24
Finished Jul 14 07:40:46 PM PDT 24
Peak memory 575200 kb
Host smart-6f64b597-5835-4cf9-816a-86215e476b00
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595174979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al
l_with_reset_error.3595174979
Directory /workspace/64.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.1763933299
Short name T2342
Test name
Test status
Simulation time 300447937 ps
CPU time 34.82 seconds
Started Jul 14 07:39:13 PM PDT 24
Finished Jul 14 07:39:48 PM PDT 24
Peak memory 575416 kb
Host smart-178a4bef-aa4e-460c-9902-2f05443ac139
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763933299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.1763933299
Directory /workspace/64.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_access_same_device.3446090447
Short name T533
Test name
Test status
Simulation time 1012893021 ps
CPU time 64.86 seconds
Started Jul 14 07:39:24 PM PDT 24
Finished Jul 14 07:40:30 PM PDT 24
Peak memory 575340 kb
Host smart-fdbb20e6-26e4-4239-9906-a3326f90bf75
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446090447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device
.3446090447
Directory /workspace/65.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.4048734551
Short name T2897
Test name
Test status
Simulation time 102734752981 ps
CPU time 2053.99 seconds
Started Jul 14 07:39:17 PM PDT 24
Finished Jul 14 08:13:32 PM PDT 24
Peak memory 575536 kb
Host smart-2a0c91d1-bb6e-4022-9ec1-967c780ca3e4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048734551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_
device_slow_rsp.4048734551
Directory /workspace/65.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.2121781105
Short name T2591
Test name
Test status
Simulation time 321779415 ps
CPU time 37.09 seconds
Started Jul 14 07:39:15 PM PDT 24
Finished Jul 14 07:39:53 PM PDT 24
Peak memory 575296 kb
Host smart-9f877f22-67b3-4cca-b282-18cebf1c7e17
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121781105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add
r.2121781105
Directory /workspace/65.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_error_random.3186453434
Short name T1351
Test name
Test status
Simulation time 464046914 ps
CPU time 36.24 seconds
Started Jul 14 07:39:19 PM PDT 24
Finished Jul 14 07:39:55 PM PDT 24
Peak memory 575336 kb
Host smart-8d658f74-f7d6-43c1-a5f4-1beed5813524
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186453434 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.3186453434
Directory /workspace/65.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random.4044877057
Short name T1938
Test name
Test status
Simulation time 2039093999 ps
CPU time 75.71 seconds
Started Jul 14 07:39:18 PM PDT 24
Finished Jul 14 07:40:34 PM PDT 24
Peak memory 575324 kb
Host smart-ecba61d1-0320-4253-9fbc-09f5263bb618
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044877057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.4044877057
Directory /workspace/65.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.400813744
Short name T1719
Test name
Test status
Simulation time 93189981227 ps
CPU time 1007.4 seconds
Started Jul 14 07:39:17 PM PDT 24
Finished Jul 14 07:56:05 PM PDT 24
Peak memory 575560 kb
Host smart-f7f28725-ad27-4348-85bb-0ec941c9d70e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400813744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.400813744
Directory /workspace/65.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.2526166853
Short name T1822
Test name
Test status
Simulation time 19953743906 ps
CPU time 387.32 seconds
Started Jul 14 07:39:14 PM PDT 24
Finished Jul 14 07:45:42 PM PDT 24
Peak memory 575512 kb
Host smart-c60ae97c-3902-4579-ae4e-f05c8d3ec79a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526166853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.2526166853
Directory /workspace/65.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.641783388
Short name T2323
Test name
Test status
Simulation time 399819545 ps
CPU time 34.56 seconds
Started Jul 14 07:39:16 PM PDT 24
Finished Jul 14 07:39:51 PM PDT 24
Peak memory 575340 kb
Host smart-901ac4bd-a9f5-482d-9556-915f010e9457
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641783388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_dela
ys.641783388
Directory /workspace/65.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_same_source.1969578439
Short name T1708
Test name
Test status
Simulation time 2407411019 ps
CPU time 67.35 seconds
Started Jul 14 07:39:24 PM PDT 24
Finished Jul 14 07:40:32 PM PDT 24
Peak memory 575408 kb
Host smart-d6da0c3b-ff7a-428d-9b75-0f27287f2aeb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969578439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.1969578439
Directory /workspace/65.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke.4140345252
Short name T2837
Test name
Test status
Simulation time 39723992 ps
CPU time 5.74 seconds
Started Jul 14 07:39:12 PM PDT 24
Finished Jul 14 07:39:18 PM PDT 24
Peak memory 575304 kb
Host smart-45ed6e69-c9ed-4692-8506-3bf4a9ba079a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140345252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.4140345252
Directory /workspace/65.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.3453134674
Short name T2879
Test name
Test status
Simulation time 7516670538 ps
CPU time 81.35 seconds
Started Jul 14 07:39:09 PM PDT 24
Finished Jul 14 07:40:31 PM PDT 24
Peak memory 574184 kb
Host smart-081a8416-668d-460b-b78f-43328953242f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453134674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.3453134674
Directory /workspace/65.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.793717920
Short name T1723
Test name
Test status
Simulation time 4908789492 ps
CPU time 86.61 seconds
Started Jul 14 07:39:16 PM PDT 24
Finished Jul 14 07:40:44 PM PDT 24
Peak memory 574100 kb
Host smart-00e520c6-a1b4-4314-80ca-4242397a6e87
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793717920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.793717920
Directory /workspace/65.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.2375575472
Short name T2254
Test name
Test status
Simulation time 40465035 ps
CPU time 6.14 seconds
Started Jul 14 07:39:11 PM PDT 24
Finished Jul 14 07:39:17 PM PDT 24
Peak memory 575208 kb
Host smart-cf79ce59-57f4-4c7f-9702-fcdafc00369a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375575472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay
s.2375575472
Directory /workspace/65.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all.2383900909
Short name T597
Test name
Test status
Simulation time 8491901187 ps
CPU time 369.1 seconds
Started Jul 14 07:39:16 PM PDT 24
Finished Jul 14 07:45:26 PM PDT 24
Peak memory 575588 kb
Host smart-61c55c23-186b-4bd6-b9c1-bf84ae3146b4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383900909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.2383900909
Directory /workspace/65.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.706325719
Short name T1679
Test name
Test status
Simulation time 6970438927 ps
CPU time 260.65 seconds
Started Jul 14 07:39:18 PM PDT 24
Finished Jul 14 07:43:39 PM PDT 24
Peak memory 575576 kb
Host smart-72428b5a-0106-40f5-a89f-98e661842ca0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706325719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.706325719
Directory /workspace/65.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.892653457
Short name T853
Test name
Test status
Simulation time 244836283 ps
CPU time 127.18 seconds
Started Jul 14 07:39:20 PM PDT 24
Finished Jul 14 07:41:28 PM PDT 24
Peak memory 575476 kb
Host smart-8abff0df-1251-4d00-b273-a9d6a48a09e3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892653457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_
with_rand_reset.892653457
Directory /workspace/65.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.4244284890
Short name T845
Test name
Test status
Simulation time 439144100 ps
CPU time 180.3 seconds
Started Jul 14 07:39:17 PM PDT 24
Finished Jul 14 07:42:18 PM PDT 24
Peak memory 575504 kb
Host smart-58796cc4-529a-48b5-ab52-70dd6d4b6552
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244284890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al
l_with_reset_error.4244284890
Directory /workspace/65.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.1351065167
Short name T2380
Test name
Test status
Simulation time 224324966 ps
CPU time 25.88 seconds
Started Jul 14 07:39:16 PM PDT 24
Finished Jul 14 07:39:43 PM PDT 24
Peak memory 575460 kb
Host smart-314f3f2a-ba3c-43e9-a34d-c72771bc446c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351065167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.1351065167
Directory /workspace/65.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_access_same_device.1376151452
Short name T843
Test name
Test status
Simulation time 309793222 ps
CPU time 31.34 seconds
Started Jul 14 07:39:26 PM PDT 24
Finished Jul 14 07:39:57 PM PDT 24
Peak memory 575396 kb
Host smart-58ad22d7-04d9-4f5b-8df6-155b7b8d64e5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376151452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device
.1376151452
Directory /workspace/66.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.227641170
Short name T2261
Test name
Test status
Simulation time 110955668096 ps
CPU time 2135.86 seconds
Started Jul 14 07:39:22 PM PDT 24
Finished Jul 14 08:14:59 PM PDT 24
Peak memory 575584 kb
Host smart-c004f6fc-656c-41be-a5c7-7594145595a1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227641170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_d
evice_slow_rsp.227641170
Directory /workspace/66.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.1405042980
Short name T2886
Test name
Test status
Simulation time 499471989 ps
CPU time 22.19 seconds
Started Jul 14 07:39:24 PM PDT 24
Finished Jul 14 07:39:46 PM PDT 24
Peak memory 575324 kb
Host smart-c35e4063-7340-48dc-8a15-bc6b60e2ac8c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405042980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add
r.1405042980
Directory /workspace/66.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_error_random.3572516217
Short name T2682
Test name
Test status
Simulation time 457311861 ps
CPU time 38.21 seconds
Started Jul 14 07:39:21 PM PDT 24
Finished Jul 14 07:39:59 PM PDT 24
Peak memory 575232 kb
Host smart-9a13a2dc-4347-40cb-9230-4908e29443c9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572516217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.3572516217
Directory /workspace/66.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random.2494156392
Short name T2235
Test name
Test status
Simulation time 343702886 ps
CPU time 34.2 seconds
Started Jul 14 07:39:16 PM PDT 24
Finished Jul 14 07:39:51 PM PDT 24
Peak memory 575368 kb
Host smart-44bc09e9-7b70-4c50-a158-e589fdd2636d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494156392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.2494156392
Directory /workspace/66.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.663072360
Short name T2869
Test name
Test status
Simulation time 72263461753 ps
CPU time 804.36 seconds
Started Jul 14 07:39:25 PM PDT 24
Finished Jul 14 07:52:51 PM PDT 24
Peak memory 575488 kb
Host smart-55dfd966-cc53-42e2-b634-66165d03e94f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663072360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.663072360
Directory /workspace/66.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.3901652421
Short name T2135
Test name
Test status
Simulation time 48693094821 ps
CPU time 922.91 seconds
Started Jul 14 07:39:21 PM PDT 24
Finished Jul 14 07:54:45 PM PDT 24
Peak memory 575516 kb
Host smart-94cc3ef3-9e44-46f7-bbea-d59a61e0c868
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901652421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.3901652421
Directory /workspace/66.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.935471841
Short name T1831
Test name
Test status
Simulation time 185945046 ps
CPU time 19.5 seconds
Started Jul 14 07:39:24 PM PDT 24
Finished Jul 14 07:39:44 PM PDT 24
Peak memory 575340 kb
Host smart-10a10fed-4bb4-4242-88be-eca8fa00ffe4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935471841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_dela
ys.935471841
Directory /workspace/66.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_same_source.510697156
Short name T1443
Test name
Test status
Simulation time 563890431 ps
CPU time 40.62 seconds
Started Jul 14 07:39:23 PM PDT 24
Finished Jul 14 07:40:04 PM PDT 24
Peak memory 575324 kb
Host smart-1eb5c3bb-18ed-468c-85a6-fb6b3368bc08
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510697156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.510697156
Directory /workspace/66.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke.273109620
Short name T1444
Test name
Test status
Simulation time 207499761 ps
CPU time 8.9 seconds
Started Jul 14 07:39:16 PM PDT 24
Finished Jul 14 07:39:25 PM PDT 24
Peak memory 575252 kb
Host smart-d609940d-7a8b-449d-9c6e-276deabbe9b2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273109620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.273109620
Directory /workspace/66.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.1343580676
Short name T1642
Test name
Test status
Simulation time 10916469943 ps
CPU time 123.63 seconds
Started Jul 14 07:39:16 PM PDT 24
Finished Jul 14 07:41:20 PM PDT 24
Peak memory 574160 kb
Host smart-5a5b0c09-9c35-4139-901a-99d36554690f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343580676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.1343580676
Directory /workspace/66.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.1997487553
Short name T608
Test name
Test status
Simulation time 4849713096 ps
CPU time 83.6 seconds
Started Jul 14 07:39:18 PM PDT 24
Finished Jul 14 07:40:42 PM PDT 24
Peak memory 574136 kb
Host smart-39eaad0a-2050-40aa-aabf-8d8aa060f208
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997487553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.1997487553
Directory /workspace/66.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.815104618
Short name T2564
Test name
Test status
Simulation time 41325800 ps
CPU time 6.1 seconds
Started Jul 14 07:39:18 PM PDT 24
Finished Jul 14 07:39:24 PM PDT 24
Peak memory 573996 kb
Host smart-26f415f8-4ef0-484a-ad3e-f0cfa5e30655
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815104618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delays
.815104618
Directory /workspace/66.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all.2645746556
Short name T1808
Test name
Test status
Simulation time 839274727 ps
CPU time 28.75 seconds
Started Jul 14 07:39:23 PM PDT 24
Finished Jul 14 07:39:52 PM PDT 24
Peak memory 575364 kb
Host smart-24d6109c-71b7-4cf2-a63e-5eb1c07539cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645746556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.2645746556
Directory /workspace/66.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.3407352758
Short name T1600
Test name
Test status
Simulation time 7317429303 ps
CPU time 226.11 seconds
Started Jul 14 07:39:30 PM PDT 24
Finished Jul 14 07:43:17 PM PDT 24
Peak memory 575560 kb
Host smart-0035b188-d2b6-49d0-a62a-061f777f7b1c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407352758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.3407352758
Directory /workspace/66.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.1472091826
Short name T864
Test name
Test status
Simulation time 708962096 ps
CPU time 172.02 seconds
Started Jul 14 07:39:30 PM PDT 24
Finished Jul 14 07:42:23 PM PDT 24
Peak memory 575208 kb
Host smart-4120ae3e-0bb7-4ea0-868a-e8deb6615442
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472091826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al
l_with_reset_error.1472091826
Directory /workspace/66.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.1896481033
Short name T1643
Test name
Test status
Simulation time 86241606 ps
CPU time 12.29 seconds
Started Jul 14 07:39:23 PM PDT 24
Finished Jul 14 07:39:36 PM PDT 24
Peak memory 575424 kb
Host smart-d0c6114f-6bb1-42bf-9d23-2ba4f0117a32
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896481033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.1896481033
Directory /workspace/66.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_access_same_device.2216700926
Short name T2560
Test name
Test status
Simulation time 2231394173 ps
CPU time 98.81 seconds
Started Jul 14 07:39:30 PM PDT 24
Finished Jul 14 07:41:10 PM PDT 24
Peak memory 575356 kb
Host smart-22d48829-6314-4425-956b-3c6770b19f7d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216700926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device
.2216700926
Directory /workspace/67.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.3340826278
Short name T2905
Test name
Test status
Simulation time 103071856734 ps
CPU time 1864.19 seconds
Started Jul 14 07:39:41 PM PDT 24
Finished Jul 14 08:10:46 PM PDT 24
Peak memory 575608 kb
Host smart-7a7f5442-0c78-4f26-83d1-ab8579ba47a7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340826278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_
device_slow_rsp.3340826278
Directory /workspace/67.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.4119179009
Short name T1462
Test name
Test status
Simulation time 170604791 ps
CPU time 18.29 seconds
Started Jul 14 07:39:35 PM PDT 24
Finished Jul 14 07:39:54 PM PDT 24
Peak memory 575304 kb
Host smart-1e14a853-1108-4fc6-be29-ede7484f6401
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119179009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add
r.4119179009
Directory /workspace/67.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_error_random.2269469394
Short name T2462
Test name
Test status
Simulation time 1039365550 ps
CPU time 38.69 seconds
Started Jul 14 07:39:36 PM PDT 24
Finished Jul 14 07:40:15 PM PDT 24
Peak memory 575348 kb
Host smart-c58b61b5-3fa2-4a94-8df6-6def36d5953c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269469394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.2269469394
Directory /workspace/67.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random.1694656382
Short name T1797
Test name
Test status
Simulation time 359354191 ps
CPU time 28.33 seconds
Started Jul 14 07:39:34 PM PDT 24
Finished Jul 14 07:40:02 PM PDT 24
Peak memory 575400 kb
Host smart-d0cd2ae2-088d-4431-9b00-6fd4713f7c69
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694656382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.1694656382
Directory /workspace/67.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.3914962778
Short name T2557
Test name
Test status
Simulation time 91895560364 ps
CPU time 1150.96 seconds
Started Jul 14 07:39:30 PM PDT 24
Finished Jul 14 07:58:41 PM PDT 24
Peak memory 575496 kb
Host smart-9364d442-05a7-4fe2-8726-7b333c674031
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914962778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.3914962778
Directory /workspace/67.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.2358133676
Short name T2825
Test name
Test status
Simulation time 65914612412 ps
CPU time 1144.3 seconds
Started Jul 14 07:39:31 PM PDT 24
Finished Jul 14 07:58:35 PM PDT 24
Peak memory 575432 kb
Host smart-e862a968-5fd5-482a-a423-ce1972572607
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358133676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.2358133676
Directory /workspace/67.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.1709653624
Short name T1798
Test name
Test status
Simulation time 588231387 ps
CPU time 49.03 seconds
Started Jul 14 07:39:34 PM PDT 24
Finished Jul 14 07:40:23 PM PDT 24
Peak memory 575372 kb
Host smart-31c0721d-d633-4390-9843-109d5b6fd8b3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709653624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del
ays.1709653624
Directory /workspace/67.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_same_source.284532542
Short name T2372
Test name
Test status
Simulation time 887566693 ps
CPU time 27.22 seconds
Started Jul 14 07:39:35 PM PDT 24
Finished Jul 14 07:40:03 PM PDT 24
Peak memory 575304 kb
Host smart-912aaa3e-ab96-4dcc-b01f-45ee9dcf2671
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284532542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.284532542
Directory /workspace/67.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke.2100287995
Short name T2452
Test name
Test status
Simulation time 186335803 ps
CPU time 8.82 seconds
Started Jul 14 07:39:32 PM PDT 24
Finished Jul 14 07:39:41 PM PDT 24
Peak memory 574044 kb
Host smart-8ba366c1-f7a5-41dc-9a97-21f9682f7b3e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100287995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.2100287995
Directory /workspace/67.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.3360076514
Short name T2308
Test name
Test status
Simulation time 7022114251 ps
CPU time 72.31 seconds
Started Jul 14 07:39:29 PM PDT 24
Finished Jul 14 07:40:42 PM PDT 24
Peak memory 575412 kb
Host smart-f8d9e6ff-dc34-4357-9b95-389a2874caf5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360076514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.3360076514
Directory /workspace/67.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.610787759
Short name T2083
Test name
Test status
Simulation time 5360418036 ps
CPU time 98.9 seconds
Started Jul 14 07:39:30 PM PDT 24
Finished Jul 14 07:41:09 PM PDT 24
Peak memory 574148 kb
Host smart-54f869d3-0931-4d78-86bc-a05ae5e38ab6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610787759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.610787759
Directory /workspace/67.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.2933307339
Short name T1903
Test name
Test status
Simulation time 39032525 ps
CPU time 6.25 seconds
Started Jul 14 07:39:30 PM PDT 24
Finished Jul 14 07:39:37 PM PDT 24
Peak memory 574060 kb
Host smart-c1548a64-5237-49ff-8042-ed5403e9753c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933307339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay
s.2933307339
Directory /workspace/67.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all.2708598112
Short name T2338
Test name
Test status
Simulation time 1140514084 ps
CPU time 40.6 seconds
Started Jul 14 07:39:41 PM PDT 24
Finished Jul 14 07:40:23 PM PDT 24
Peak memory 575472 kb
Host smart-8b95a525-29fa-4346-9437-66ab2769e7aa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708598112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.2708598112
Directory /workspace/67.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.3919087088
Short name T1440
Test name
Test status
Simulation time 3453560660 ps
CPU time 120.1 seconds
Started Jul 14 07:39:36 PM PDT 24
Finished Jul 14 07:41:36 PM PDT 24
Peak memory 575392 kb
Host smart-4170d3a3-a4de-4249-a2af-dc949f3c36a7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919087088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.3919087088
Directory /workspace/67.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.3262838030
Short name T2614
Test name
Test status
Simulation time 187865062 ps
CPU time 48.74 seconds
Started Jul 14 07:39:42 PM PDT 24
Finished Jul 14 07:40:31 PM PDT 24
Peak memory 575192 kb
Host smart-dcdeb705-4f35-4bfd-a251-54354273bb4f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262838030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al
l_with_reset_error.3262838030
Directory /workspace/67.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.2145027772
Short name T1806
Test name
Test status
Simulation time 1009863535 ps
CPU time 39.79 seconds
Started Jul 14 07:39:39 PM PDT 24
Finished Jul 14 07:40:19 PM PDT 24
Peak memory 575396 kb
Host smart-246d0578-1c34-409e-9b22-235472279660
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145027772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.2145027772
Directory /workspace/67.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_access_same_device.1064469982
Short name T2077
Test name
Test status
Simulation time 2166485210 ps
CPU time 78.83 seconds
Started Jul 14 07:39:43 PM PDT 24
Finished Jul 14 07:41:02 PM PDT 24
Peak memory 575380 kb
Host smart-a95b9d8c-e5d8-4908-aa46-5953f837bbd4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064469982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device
.1064469982
Directory /workspace/68.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.2287823476
Short name T1349
Test name
Test status
Simulation time 708331095 ps
CPU time 28.02 seconds
Started Jul 14 07:39:42 PM PDT 24
Finished Jul 14 07:40:10 PM PDT 24
Peak memory 575308 kb
Host smart-4d36b03e-f76f-4b29-9e1c-ef23ff95be82
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287823476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add
r.2287823476
Directory /workspace/68.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_error_random.1310669306
Short name T2121
Test name
Test status
Simulation time 2515362926 ps
CPU time 84.85 seconds
Started Jul 14 07:39:44 PM PDT 24
Finished Jul 14 07:41:09 PM PDT 24
Peak memory 575124 kb
Host smart-01472f56-60fe-43c5-873a-edc40eb1bef8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310669306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.1310669306
Directory /workspace/68.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random.609630298
Short name T1734
Test name
Test status
Simulation time 1095218277 ps
CPU time 36.54 seconds
Started Jul 14 07:39:50 PM PDT 24
Finished Jul 14 07:40:27 PM PDT 24
Peak memory 575380 kb
Host smart-ac28bd58-786e-45f7-8523-f0b32a799301
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609630298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.609630298
Directory /workspace/68.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.4053031100
Short name T1834
Test name
Test status
Simulation time 85512228568 ps
CPU time 1037.27 seconds
Started Jul 14 07:39:43 PM PDT 24
Finished Jul 14 07:57:00 PM PDT 24
Peak memory 575576 kb
Host smart-5a8dbafe-e60b-4e4a-a0ed-ec0349b98f87
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053031100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.4053031100
Directory /workspace/68.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.949182503
Short name T2466
Test name
Test status
Simulation time 55872900896 ps
CPU time 1013.41 seconds
Started Jul 14 07:39:44 PM PDT 24
Finished Jul 14 07:56:38 PM PDT 24
Peak memory 575516 kb
Host smart-14d472f3-15d8-4980-84eb-aee3baf269e8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949182503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.949182503
Directory /workspace/68.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.2166370143
Short name T645
Test name
Test status
Simulation time 184088862 ps
CPU time 16.57 seconds
Started Jul 14 07:39:45 PM PDT 24
Finished Jul 14 07:40:02 PM PDT 24
Peak memory 575280 kb
Host smart-fc380464-7a4e-4855-a137-81bf0e0b1dbf
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166370143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del
ays.2166370143
Directory /workspace/68.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_same_source.1734862267
Short name T1805
Test name
Test status
Simulation time 483140223 ps
CPU time 16.44 seconds
Started Jul 14 07:39:43 PM PDT 24
Finished Jul 14 07:40:00 PM PDT 24
Peak memory 575296 kb
Host smart-76c07344-d673-4842-b43c-b766f81d3c99
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734862267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.1734862267
Directory /workspace/68.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke.4140743188
Short name T2233
Test name
Test status
Simulation time 210787512 ps
CPU time 9.18 seconds
Started Jul 14 07:39:42 PM PDT 24
Finished Jul 14 07:39:52 PM PDT 24
Peak memory 574016 kb
Host smart-be8fe872-053d-4680-a664-071564b697cd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140743188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.4140743188
Directory /workspace/68.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.2308745157
Short name T1478
Test name
Test status
Simulation time 9372425491 ps
CPU time 105.72 seconds
Started Jul 14 07:39:37 PM PDT 24
Finished Jul 14 07:41:23 PM PDT 24
Peak memory 575472 kb
Host smart-03bc73db-6bd5-4e9d-82c1-ca9a80e5eddc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308745157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.2308745157
Directory /workspace/68.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.1960064169
Short name T2761
Test name
Test status
Simulation time 4411601088 ps
CPU time 76.39 seconds
Started Jul 14 07:39:36 PM PDT 24
Finished Jul 14 07:40:53 PM PDT 24
Peak memory 574132 kb
Host smart-d3a1d6cd-2e19-4117-a451-c9f316ea2610
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960064169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.1960064169
Directory /workspace/68.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.584426496
Short name T1343
Test name
Test status
Simulation time 47812005 ps
CPU time 6.47 seconds
Started Jul 14 07:39:35 PM PDT 24
Finished Jul 14 07:39:42 PM PDT 24
Peak memory 575260 kb
Host smart-5c2a6c13-6005-4b57-aa9a-964681cfa479
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584426496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delays
.584426496
Directory /workspace/68.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all.3849289776
Short name T2271
Test name
Test status
Simulation time 11372364514 ps
CPU time 395.1 seconds
Started Jul 14 07:39:44 PM PDT 24
Finished Jul 14 07:46:20 PM PDT 24
Peak memory 575640 kb
Host smart-32d28ebe-0c76-4023-9f8e-4be1dcd28523
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849289776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.3849289776
Directory /workspace/68.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.3669349427
Short name T2423
Test name
Test status
Simulation time 794113611 ps
CPU time 59.42 seconds
Started Jul 14 07:39:43 PM PDT 24
Finished Jul 14 07:40:43 PM PDT 24
Peak memory 575348 kb
Host smart-10946c9d-1de7-458f-ae8c-720ce569d205
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669349427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.3669349427
Directory /workspace/68.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3513548302
Short name T2057
Test name
Test status
Simulation time 168862666 ps
CPU time 71.81 seconds
Started Jul 14 07:39:44 PM PDT 24
Finished Jul 14 07:40:57 PM PDT 24
Peak memory 575460 kb
Host smart-d08d6f7a-828b-4b8f-9785-eabe59eacc70
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513548302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all
_with_rand_reset.3513548302
Directory /workspace/68.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.1132092383
Short name T1613
Test name
Test status
Simulation time 5462933133 ps
CPU time 261.98 seconds
Started Jul 14 07:39:44 PM PDT 24
Finished Jul 14 07:44:06 PM PDT 24
Peak memory 575612 kb
Host smart-19edc25a-176d-40f0-b0d4-387df079eb6d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132092383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al
l_with_reset_error.1132092383
Directory /workspace/68.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.2069454585
Short name T484
Test name
Test status
Simulation time 245182694 ps
CPU time 28.76 seconds
Started Jul 14 07:39:47 PM PDT 24
Finished Jul 14 07:40:16 PM PDT 24
Peak memory 575408 kb
Host smart-db0408b4-65c3-4872-aa02-af72a4ad83d5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069454585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.2069454585
Directory /workspace/68.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_access_same_device.1009073520
Short name T2264
Test name
Test status
Simulation time 1580807129 ps
CPU time 61.04 seconds
Started Jul 14 07:39:50 PM PDT 24
Finished Jul 14 07:40:52 PM PDT 24
Peak memory 575340 kb
Host smart-c28860f6-19ea-4b58-8b9e-1fb055def237
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009073520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device
.1009073520
Directory /workspace/69.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.3887305815
Short name T2648
Test name
Test status
Simulation time 5647542247 ps
CPU time 101.91 seconds
Started Jul 14 07:39:50 PM PDT 24
Finished Jul 14 07:41:32 PM PDT 24
Peak memory 575456 kb
Host smart-83e04947-aebe-4b69-8a75-f942ff75dc32
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887305815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_
device_slow_rsp.3887305815
Directory /workspace/69.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.2804785617
Short name T2762
Test name
Test status
Simulation time 186494376 ps
CPU time 21.38 seconds
Started Jul 14 07:39:49 PM PDT 24
Finished Jul 14 07:40:11 PM PDT 24
Peak memory 575444 kb
Host smart-200278ce-1e50-4600-90a7-1776c0c8e3b0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804785617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add
r.2804785617
Directory /workspace/69.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_error_random.3414317812
Short name T2672
Test name
Test status
Simulation time 653950223 ps
CPU time 21.15 seconds
Started Jul 14 07:39:48 PM PDT 24
Finished Jul 14 07:40:10 PM PDT 24
Peak memory 574988 kb
Host smart-6aff3b3d-b04e-429a-b1eb-3c71651fe46f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414317812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.3414317812
Directory /workspace/69.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random.2671478353
Short name T600
Test name
Test status
Simulation time 2293046913 ps
CPU time 90.59 seconds
Started Jul 14 07:39:42 PM PDT 24
Finished Jul 14 07:41:13 PM PDT 24
Peak memory 575412 kb
Host smart-911ba398-1f87-4504-9b69-0914008c37d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671478353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.2671478353
Directory /workspace/69.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.4023316114
Short name T1601
Test name
Test status
Simulation time 27756719799 ps
CPU time 316.06 seconds
Started Jul 14 07:39:52 PM PDT 24
Finished Jul 14 07:45:08 PM PDT 24
Peak memory 575472 kb
Host smart-da1c64e4-a398-4983-bfaf-65c7ff33edea
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023316114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.4023316114
Directory /workspace/69.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.4198191051
Short name T2775
Test name
Test status
Simulation time 46186134550 ps
CPU time 818 seconds
Started Jul 14 07:39:49 PM PDT 24
Finished Jul 14 07:53:28 PM PDT 24
Peak memory 575500 kb
Host smart-a8e94219-69dc-49e2-b468-7fbc34aed811
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198191051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.4198191051
Directory /workspace/69.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.161000431
Short name T1515
Test name
Test status
Simulation time 433100074 ps
CPU time 42.95 seconds
Started Jul 14 07:39:44 PM PDT 24
Finished Jul 14 07:40:28 PM PDT 24
Peak memory 575360 kb
Host smart-95b162f8-1995-470a-8b16-97a458d17184
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161000431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_dela
ys.161000431
Directory /workspace/69.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_same_source.1179609763
Short name T491
Test name
Test status
Simulation time 2020930746 ps
CPU time 62.07 seconds
Started Jul 14 07:39:54 PM PDT 24
Finished Jul 14 07:40:56 PM PDT 24
Peak memory 575316 kb
Host smart-48933528-a0c7-4fd9-9bc2-b7f43d583015
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179609763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.1179609763
Directory /workspace/69.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke.3126976441
Short name T2382
Test name
Test status
Simulation time 40591419 ps
CPU time 5.85 seconds
Started Jul 14 07:39:44 PM PDT 24
Finished Jul 14 07:39:51 PM PDT 24
Peak memory 574028 kb
Host smart-e8277765-1de5-4b02-a865-7251c8e4da88
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126976441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.3126976441
Directory /workspace/69.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.1854519959
Short name T706
Test name
Test status
Simulation time 5650036108 ps
CPU time 59.53 seconds
Started Jul 14 07:39:46 PM PDT 24
Finished Jul 14 07:40:45 PM PDT 24
Peak memory 575476 kb
Host smart-44b9c87c-2eab-4427-a31c-af2dfe4f82df
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854519959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.1854519959
Directory /workspace/69.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.3878195215
Short name T2034
Test name
Test status
Simulation time 3602026605 ps
CPU time 60.38 seconds
Started Jul 14 07:39:44 PM PDT 24
Finished Jul 14 07:40:45 PM PDT 24
Peak memory 575412 kb
Host smart-7c1404ad-099b-441d-a2f5-a523300a0593
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878195215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.3878195215
Directory /workspace/69.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.125137947
Short name T2670
Test name
Test status
Simulation time 49620176 ps
CPU time 6.68 seconds
Started Jul 14 07:39:43 PM PDT 24
Finished Jul 14 07:39:50 PM PDT 24
Peak memory 574040 kb
Host smart-cca096ca-6346-4992-830f-4de0d52ab337
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125137947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delays
.125137947
Directory /workspace/69.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all.249973088
Short name T2105
Test name
Test status
Simulation time 9745522748 ps
CPU time 380 seconds
Started Jul 14 07:39:54 PM PDT 24
Finished Jul 14 07:46:14 PM PDT 24
Peak memory 575588 kb
Host smart-022ded11-d90a-45d5-bd8f-26ff1b94130b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249973088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.249973088
Directory /workspace/69.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.1711517489
Short name T1430
Test name
Test status
Simulation time 5774170164 ps
CPU time 203.68 seconds
Started Jul 14 07:39:50 PM PDT 24
Finished Jul 14 07:43:15 PM PDT 24
Peak memory 575644 kb
Host smart-eddf5faa-e904-4ced-85bb-9e27054079af
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711517489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.1711517489
Directory /workspace/69.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.2041838028
Short name T2055
Test name
Test status
Simulation time 104370564 ps
CPU time 36.86 seconds
Started Jul 14 07:39:49 PM PDT 24
Finished Jul 14 07:40:27 PM PDT 24
Peak memory 575416 kb
Host smart-c83977a8-8c31-4d61-827d-a1cd3fd267cc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041838028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all
_with_rand_reset.2041838028
Directory /workspace/69.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.3024626663
Short name T2544
Test name
Test status
Simulation time 347046939 ps
CPU time 57.08 seconds
Started Jul 14 07:39:50 PM PDT 24
Finished Jul 14 07:40:48 PM PDT 24
Peak memory 575472 kb
Host smart-5e56800a-5140-4462-b1b5-ad990f36b53e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024626663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al
l_with_reset_error.3024626663
Directory /workspace/69.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.2263566332
Short name T2459
Test name
Test status
Simulation time 639155653 ps
CPU time 28.48 seconds
Started Jul 14 07:39:49 PM PDT 24
Finished Jul 14 07:40:18 PM PDT 24
Peak memory 575452 kb
Host smart-2824fd13-dc08-4cca-a386-f53a30892f0b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263566332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.2263566332
Directory /workspace/69.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/7.chip_csr_rw.2981907590
Short name T144
Test name
Test status
Simulation time 5273610726 ps
CPU time 580.86 seconds
Started Jul 14 07:28:45 PM PDT 24
Finished Jul 14 07:38:26 PM PDT 24
Peak memory 597444 kb
Host smart-d0cd3e9a-93e8-45ef-8dbb-d8f8dc105ba5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981907590 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.2981907590
Directory /workspace/7.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.3418835983
Short name T2425
Test name
Test status
Simulation time 14899605236 ps
CPU time 2460.76 seconds
Started Jul 14 07:28:29 PM PDT 24
Finished Jul 14 08:09:31 PM PDT 24
Peak memory 593116 kb
Host smart-81d194af-6b0c-4d38-9b6c-0c9c9b082146
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418835983 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.3418835983
Directory /workspace/7.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.chip_tl_errors.72929039
Short name T554
Test name
Test status
Simulation time 3690289598 ps
CPU time 303.32 seconds
Started Jul 14 07:28:34 PM PDT 24
Finished Jul 14 07:33:38 PM PDT 24
Peak memory 603776 kb
Host smart-2816e6be-1d81-43e7-a6c4-55b20f4f23bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72929039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.72929039
Directory /workspace/7.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_access_same_device.3440983010
Short name T1804
Test name
Test status
Simulation time 234872879 ps
CPU time 24.78 seconds
Started Jul 14 07:28:33 PM PDT 24
Finished Jul 14 07:28:58 PM PDT 24
Peak memory 575348 kb
Host smart-904c565f-4391-4e31-9e28-ade1b1104a57
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440983010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.
3440983010
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.1930704105
Short name T439
Test name
Test status
Simulation time 87146800223 ps
CPU time 1657.49 seconds
Started Jul 14 07:28:43 PM PDT 24
Finished Jul 14 07:56:21 PM PDT 24
Peak memory 575584 kb
Host smart-e2cecae9-40a9-49c3-b297-d4dfae9caae7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930704105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d
evice_slow_rsp.1930704105
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.1853466596
Short name T2319
Test name
Test status
Simulation time 288989086 ps
CPU time 15.58 seconds
Started Jul 14 07:28:44 PM PDT 24
Finished Jul 14 07:28:59 PM PDT 24
Peak memory 575332 kb
Host smart-40308170-3192-4755-8894-7cad450669b4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853466596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr
.1853466596
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_error_random.273440644
Short name T1680
Test name
Test status
Simulation time 124883088 ps
CPU time 13.19 seconds
Started Jul 14 07:28:40 PM PDT 24
Finished Jul 14 07:28:54 PM PDT 24
Peak memory 575244 kb
Host smart-bfc2a81a-d555-4257-8b01-8261c46163b8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273440644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.273440644
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random.1055285204
Short name T2558
Test name
Test status
Simulation time 357779693 ps
CPU time 36.98 seconds
Started Jul 14 07:28:34 PM PDT 24
Finished Jul 14 07:29:11 PM PDT 24
Peak memory 575320 kb
Host smart-0a14aef6-bc55-49a2-a098-431ec282e0bb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055285204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.1055285204
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.1568008093
Short name T1706
Test name
Test status
Simulation time 60537457025 ps
CPU time 666.59 seconds
Started Jul 14 07:28:35 PM PDT 24
Finished Jul 14 07:39:42 PM PDT 24
Peak memory 575508 kb
Host smart-bba80ca5-b832-4478-a0af-20e06d6ffcf3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568008093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1568008093
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.1553627702
Short name T2597
Test name
Test status
Simulation time 47307008961 ps
CPU time 848.7 seconds
Started Jul 14 07:28:35 PM PDT 24
Finished Jul 14 07:42:44 PM PDT 24
Peak memory 575496 kb
Host smart-1fb24ff7-2d87-45ce-88ad-fa2ba55b4232
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553627702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1553627702
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.97666356
Short name T2723
Test name
Test status
Simulation time 318137534 ps
CPU time 27.24 seconds
Started Jul 14 07:28:33 PM PDT 24
Finished Jul 14 07:29:01 PM PDT 24
Peak memory 575348 kb
Host smart-48d2055f-fa7c-495e-9cad-570a7be93096
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97666356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays
.97666356
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_same_source.221350169
Short name T513
Test name
Test status
Simulation time 2309898940 ps
CPU time 68.03 seconds
Started Jul 14 07:28:41 PM PDT 24
Finished Jul 14 07:29:49 PM PDT 24
Peak memory 575392 kb
Host smart-d9ab7145-791f-4f6a-81b5-3771d774d64b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221350169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.221350169
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke.1328861442
Short name T2848
Test name
Test status
Simulation time 38272357 ps
CPU time 6.15 seconds
Started Jul 14 07:28:31 PM PDT 24
Finished Jul 14 07:28:37 PM PDT 24
Peak memory 575252 kb
Host smart-985497be-eb73-43d9-98b4-a9524da24e75
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328861442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1328861442
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.976197304
Short name T1561
Test name
Test status
Simulation time 8187172009 ps
CPU time 90.57 seconds
Started Jul 14 07:28:29 PM PDT 24
Finished Jul 14 07:30:00 PM PDT 24
Peak memory 574136 kb
Host smart-7044e255-a1e8-4737-80f9-93c975975fc9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976197304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.976197304
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.1932326922
Short name T2130
Test name
Test status
Simulation time 4165525410 ps
CPU time 76.34 seconds
Started Jul 14 07:28:43 PM PDT 24
Finished Jul 14 07:29:59 PM PDT 24
Peak memory 574116 kb
Host smart-9dc54bf0-7923-41ec-b82c-73abc6f16600
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932326922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1932326922
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.482939279
Short name T2765
Test name
Test status
Simulation time 49492609 ps
CPU time 6.84 seconds
Started Jul 14 07:28:31 PM PDT 24
Finished Jul 14 07:28:39 PM PDT 24
Peak memory 573984 kb
Host smart-c1001b61-27f1-4fc7-9925-423d253e0eab
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482939279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.
482939279
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all.2296165918
Short name T512
Test name
Test status
Simulation time 5519634953 ps
CPU time 210.84 seconds
Started Jul 14 07:28:41 PM PDT 24
Finished Jul 14 07:32:12 PM PDT 24
Peak memory 575604 kb
Host smart-214520f7-57c6-43ef-a063-ccc8f9366c82
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296165918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2296165918
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.575858382
Short name T2868
Test name
Test status
Simulation time 869126934 ps
CPU time 62.63 seconds
Started Jul 14 07:28:45 PM PDT 24
Finished Jul 14 07:29:48 PM PDT 24
Peak memory 575408 kb
Host smart-d07ab98b-b8db-4860-a2b9-18a5680ee790
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575858382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.575858382
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.2726553316
Short name T870
Test name
Test status
Simulation time 2810932343 ps
CPU time 414.35 seconds
Started Jul 14 07:28:47 PM PDT 24
Finished Jul 14 07:35:42 PM PDT 24
Peak memory 575544 kb
Host smart-00ee4e65-8141-4463-b489-0e1e163db9b6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726553316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_
with_rand_reset.2726553316
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.1541669110
Short name T2641
Test name
Test status
Simulation time 4337510567 ps
CPU time 342.9 seconds
Started Jul 14 07:28:47 PM PDT 24
Finished Jul 14 07:34:30 PM PDT 24
Peak memory 575336 kb
Host smart-ba38f0ad-97f3-48cd-8f3c-cc2dac2a4285
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541669110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all
_with_reset_error.1541669110
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.3889795119
Short name T584
Test name
Test status
Simulation time 354598997 ps
CPU time 42.13 seconds
Started Jul 14 07:28:39 PM PDT 24
Finished Jul 14 07:29:22 PM PDT 24
Peak memory 575436 kb
Host smart-fa951fa0-2b9b-4e7e-bda0-ff15d25165a0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889795119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3889795119
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_access_same_device.858021114
Short name T2363
Test name
Test status
Simulation time 592277287 ps
CPU time 25.61 seconds
Started Jul 14 07:39:59 PM PDT 24
Finished Jul 14 07:40:25 PM PDT 24
Peak memory 575352 kb
Host smart-041499f5-70cb-4815-87f8-57005d3e0f8f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858021114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device.
858021114
Directory /workspace/70.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.65484275
Short name T547
Test name
Test status
Simulation time 75224560836 ps
CPU time 1488.63 seconds
Started Jul 14 07:39:57 PM PDT 24
Finished Jul 14 08:04:47 PM PDT 24
Peak memory 575520 kb
Host smart-dbd0e6eb-e4b1-42d0-8e1c-ef1b0052b29c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65484275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_de
vice_slow_rsp.65484275
Directory /workspace/70.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.1857464888
Short name T1786
Test name
Test status
Simulation time 333347840 ps
CPU time 34.3 seconds
Started Jul 14 07:39:54 PM PDT 24
Finished Jul 14 07:40:29 PM PDT 24
Peak memory 575316 kb
Host smart-1c9b5001-7b81-4327-85a5-2491faf590ff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857464888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add
r.1857464888
Directory /workspace/70.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_error_random.835485867
Short name T714
Test name
Test status
Simulation time 1824081708 ps
CPU time 63.51 seconds
Started Jul 14 07:39:53 PM PDT 24
Finished Jul 14 07:40:58 PM PDT 24
Peak memory 575304 kb
Host smart-964805c5-3468-47e6-8fce-fd2c6509c58c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835485867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.835485867
Directory /workspace/70.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random.2685208319
Short name T1406
Test name
Test status
Simulation time 170654689 ps
CPU time 17.87 seconds
Started Jul 14 07:39:49 PM PDT 24
Finished Jul 14 07:40:07 PM PDT 24
Peak memory 575376 kb
Host smart-5f8d87ba-3a3f-401a-8927-4cae80659006
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685208319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.2685208319
Directory /workspace/70.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.1375539230
Short name T526
Test name
Test status
Simulation time 83448566221 ps
CPU time 976 seconds
Started Jul 14 07:39:57 PM PDT 24
Finished Jul 14 07:56:13 PM PDT 24
Peak memory 575504 kb
Host smart-2a8371e0-33dd-4b16-a361-485e3bbfd6aa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375539230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.1375539230
Directory /workspace/70.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.2853869522
Short name T2809
Test name
Test status
Simulation time 21481713863 ps
CPU time 380.81 seconds
Started Jul 14 07:39:57 PM PDT 24
Finished Jul 14 07:46:19 PM PDT 24
Peak memory 575492 kb
Host smart-9fdbe8fa-0d63-40d6-98ef-7ca5de61a568
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853869522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.2853869522
Directory /workspace/70.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.655867985
Short name T2685
Test name
Test status
Simulation time 140335080 ps
CPU time 14.12 seconds
Started Jul 14 07:39:59 PM PDT 24
Finished Jul 14 07:40:14 PM PDT 24
Peak memory 575280 kb
Host smart-57c9caa6-2abe-49f9-ac21-9098ebc3e5ec
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655867985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_dela
ys.655867985
Directory /workspace/70.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_same_source.3216874199
Short name T2742
Test name
Test status
Simulation time 861386310 ps
CPU time 28.81 seconds
Started Jul 14 07:39:54 PM PDT 24
Finished Jul 14 07:40:24 PM PDT 24
Peak memory 575288 kb
Host smart-e64805f4-be51-4589-87ed-6377ffcd4ba2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216874199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.3216874199
Directory /workspace/70.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke.641921353
Short name T2563
Test name
Test status
Simulation time 44884334 ps
CPU time 6.6 seconds
Started Jul 14 07:39:51 PM PDT 24
Finished Jul 14 07:39:58 PM PDT 24
Peak memory 573916 kb
Host smart-ed7717f0-e076-4903-94d6-33eba449105d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641921353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.641921353
Directory /workspace/70.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.601843269
Short name T1891
Test name
Test status
Simulation time 7621597577 ps
CPU time 83.55 seconds
Started Jul 14 07:39:48 PM PDT 24
Finished Jul 14 07:41:12 PM PDT 24
Peak memory 574128 kb
Host smart-3225a6ac-c82e-4eed-9126-e3bdc98e6d69
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601843269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.601843269
Directory /workspace/70.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.2567737056
Short name T1420
Test name
Test status
Simulation time 5247758267 ps
CPU time 93.17 seconds
Started Jul 14 07:39:49 PM PDT 24
Finished Jul 14 07:41:23 PM PDT 24
Peak memory 574196 kb
Host smart-9fece07f-7167-4b99-875f-83c35b67c9d6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567737056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.2567737056
Directory /workspace/70.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.3565283148
Short name T1397
Test name
Test status
Simulation time 49403374 ps
CPU time 6.43 seconds
Started Jul 14 07:39:48 PM PDT 24
Finished Jul 14 07:39:55 PM PDT 24
Peak memory 573980 kb
Host smart-db06dff9-396c-4b06-a9fd-74844f2a38d0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565283148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay
s.3565283148
Directory /workspace/70.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all.1696762107
Short name T565
Test name
Test status
Simulation time 20553784152 ps
CPU time 837.78 seconds
Started Jul 14 07:39:56 PM PDT 24
Finished Jul 14 07:53:54 PM PDT 24
Peak memory 575560 kb
Host smart-514b7365-dd36-42d3-9ed7-005efdd3aed5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696762107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.1696762107
Directory /workspace/70.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.2392972454
Short name T1580
Test name
Test status
Simulation time 12976084120 ps
CPU time 496.21 seconds
Started Jul 14 07:40:02 PM PDT 24
Finished Jul 14 07:48:20 PM PDT 24
Peak memory 575608 kb
Host smart-238880ea-e0ea-4f6a-9396-88944b503f2b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392972454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.2392972454
Directory /workspace/70.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.1172469703
Short name T1781
Test name
Test status
Simulation time 16213160863 ps
CPU time 815.15 seconds
Started Jul 14 07:40:02 PM PDT 24
Finished Jul 14 07:53:38 PM PDT 24
Peak memory 575592 kb
Host smart-6d7ca21d-a949-45cf-b485-a0b97cd0c477
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172469703 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al
l_with_reset_error.1172469703
Directory /workspace/70.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.1519619037
Short name T1639
Test name
Test status
Simulation time 150008633 ps
CPU time 9.59 seconds
Started Jul 14 07:39:56 PM PDT 24
Finished Jul 14 07:40:06 PM PDT 24
Peak memory 575396 kb
Host smart-042113e1-f4bc-4e60-a10a-d71093d43930
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519619037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.1519619037
Directory /workspace/70.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_access_same_device.3829656196
Short name T1875
Test name
Test status
Simulation time 344224553 ps
CPU time 33.14 seconds
Started Jul 14 07:40:10 PM PDT 24
Finished Jul 14 07:40:44 PM PDT 24
Peak memory 575304 kb
Host smart-c488320c-bf84-4fe4-bc61-b37e07c27caa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829656196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device
.3829656196
Directory /workspace/71.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.345935333
Short name T2373
Test name
Test status
Simulation time 109609398199 ps
CPU time 2037.08 seconds
Started Jul 14 07:40:15 PM PDT 24
Finished Jul 14 08:14:12 PM PDT 24
Peak memory 575568 kb
Host smart-421cafa2-5137-47f2-a666-49cfbc919972
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345935333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_d
evice_slow_rsp.345935333
Directory /workspace/71.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.2583535572
Short name T1730
Test name
Test status
Simulation time 683284468 ps
CPU time 27.78 seconds
Started Jul 14 07:40:08 PM PDT 24
Finished Jul 14 07:40:37 PM PDT 24
Peak memory 575340 kb
Host smart-cd16e0c8-8f23-4c59-bb02-f7964fb7d46c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583535572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add
r.2583535572
Directory /workspace/71.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_error_random.1217692652
Short name T1926
Test name
Test status
Simulation time 157125617 ps
CPU time 14.74 seconds
Started Jul 14 07:40:14 PM PDT 24
Finished Jul 14 07:40:29 PM PDT 24
Peak memory 575268 kb
Host smart-bfc377a7-732c-4615-b049-f7075425ad2f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217692652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.1217692652
Directory /workspace/71.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random.2682291344
Short name T2504
Test name
Test status
Simulation time 187567817 ps
CPU time 10.11 seconds
Started Jul 14 07:40:02 PM PDT 24
Finished Jul 14 07:40:14 PM PDT 24
Peak memory 574068 kb
Host smart-d633cfa4-3956-4f8a-9a6e-d9035b182168
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682291344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.2682291344
Directory /workspace/71.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.1714043839
Short name T1698
Test name
Test status
Simulation time 85623279217 ps
CPU time 1044.87 seconds
Started Jul 14 07:40:09 PM PDT 24
Finished Jul 14 07:57:35 PM PDT 24
Peak memory 575720 kb
Host smart-96e468b1-71ba-492c-be14-c2d6ad48a0d9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714043839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.1714043839
Directory /workspace/71.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.2842353553
Short name T2655
Test name
Test status
Simulation time 28583983194 ps
CPU time 524.53 seconds
Started Jul 14 07:40:09 PM PDT 24
Finished Jul 14 07:48:54 PM PDT 24
Peak memory 575540 kb
Host smart-e2e13a99-093d-4f00-bac9-2549ab1a0bec
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842353553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.2842353553
Directory /workspace/71.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.2408278033
Short name T2549
Test name
Test status
Simulation time 627222734 ps
CPU time 53.48 seconds
Started Jul 14 07:40:08 PM PDT 24
Finished Jul 14 07:41:02 PM PDT 24
Peak memory 575244 kb
Host smart-f7855021-e7c9-48d1-8545-d8f1b86119b7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408278033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del
ays.2408278033
Directory /workspace/71.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_same_source.2553971107
Short name T2444
Test name
Test status
Simulation time 1939054731 ps
CPU time 58.73 seconds
Started Jul 14 07:40:10 PM PDT 24
Finished Jul 14 07:41:10 PM PDT 24
Peak memory 575336 kb
Host smart-0728a4ed-fc86-4eb3-9e59-afd41570529a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553971107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.2553971107
Directory /workspace/71.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke.2117280396
Short name T2901
Test name
Test status
Simulation time 206332344 ps
CPU time 8.33 seconds
Started Jul 14 07:40:02 PM PDT 24
Finished Jul 14 07:40:11 PM PDT 24
Peak memory 574032 kb
Host smart-2b7337d2-3d01-484a-910f-b9841bdd68e2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117280396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.2117280396
Directory /workspace/71.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.469511971
Short name T2116
Test name
Test status
Simulation time 6475096764 ps
CPU time 72.48 seconds
Started Jul 14 07:40:03 PM PDT 24
Finished Jul 14 07:41:17 PM PDT 24
Peak memory 575424 kb
Host smart-b715cbab-4838-4d2c-8c97-5dad05981239
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469511971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.469511971
Directory /workspace/71.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.2442229165
Short name T1525
Test name
Test status
Simulation time 6261792151 ps
CPU time 109.16 seconds
Started Jul 14 07:40:25 PM PDT 24
Finished Jul 14 07:42:15 PM PDT 24
Peak memory 574164 kb
Host smart-b18a35d6-fca5-44e0-9437-bfa85cc294ab
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442229165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.2442229165
Directory /workspace/71.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.464156078
Short name T1356
Test name
Test status
Simulation time 60811976 ps
CPU time 6.82 seconds
Started Jul 14 07:40:03 PM PDT 24
Finished Jul 14 07:40:11 PM PDT 24
Peak memory 575308 kb
Host smart-99f06753-d091-4115-9d6a-92c02f1e4d21
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464156078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delays
.464156078
Directory /workspace/71.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all.3108524725
Short name T2314
Test name
Test status
Simulation time 11740858265 ps
CPU time 442.81 seconds
Started Jul 14 07:40:11 PM PDT 24
Finished Jul 14 07:47:34 PM PDT 24
Peak memory 575536 kb
Host smart-cf6df258-2c99-4e2c-b2c8-9921f62cfe55
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108524725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.3108524725
Directory /workspace/71.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.1421809653
Short name T687
Test name
Test status
Simulation time 16386872251 ps
CPU time 611.46 seconds
Started Jul 14 07:40:10 PM PDT 24
Finished Jul 14 07:50:22 PM PDT 24
Peak memory 575624 kb
Host smart-1e683eb4-9fe7-4d5f-a74e-692bfe82ddb4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421809653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.1421809653
Directory /workspace/71.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.455841201
Short name T1694
Test name
Test status
Simulation time 364503785 ps
CPU time 94.27 seconds
Started Jul 14 07:40:14 PM PDT 24
Finished Jul 14 07:41:48 PM PDT 24
Peak memory 575468 kb
Host smart-7c25d10e-e729-4eec-95ca-65435c4f6025
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455841201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_
with_rand_reset.455841201
Directory /workspace/71.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.2879017051
Short name T2518
Test name
Test status
Simulation time 384729857 ps
CPU time 59.66 seconds
Started Jul 14 07:40:27 PM PDT 24
Finished Jul 14 07:41:27 PM PDT 24
Peak memory 575432 kb
Host smart-108aac43-dd6a-4253-aa3c-536e6cd901eb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879017051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al
l_with_reset_error.2879017051
Directory /workspace/71.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.4054570642
Short name T1933
Test name
Test status
Simulation time 883544305 ps
CPU time 39.15 seconds
Started Jul 14 07:40:07 PM PDT 24
Finished Jul 14 07:40:47 PM PDT 24
Peak memory 575392 kb
Host smart-33480616-f83a-4329-a940-ed0691e53b0e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054570642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.4054570642
Directory /workspace/71.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_access_same_device.3639335607
Short name T1647
Test name
Test status
Simulation time 976772774 ps
CPU time 77.73 seconds
Started Jul 14 07:40:27 PM PDT 24
Finished Jul 14 07:41:45 PM PDT 24
Peak memory 575392 kb
Host smart-2a8c030d-8263-4925-a346-4fe362fd5204
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639335607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device
.3639335607
Directory /workspace/72.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.712946721
Short name T2847
Test name
Test status
Simulation time 128809037 ps
CPU time 15.16 seconds
Started Jul 14 07:40:29 PM PDT 24
Finished Jul 14 07:40:44 PM PDT 24
Peak memory 575080 kb
Host smart-defcfeae-1eab-486e-9ac5-910600f7c9dc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712946721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_addr
.712946721
Directory /workspace/72.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_error_random.2217376612
Short name T2106
Test name
Test status
Simulation time 1369442527 ps
CPU time 44.47 seconds
Started Jul 14 07:40:28 PM PDT 24
Finished Jul 14 07:41:13 PM PDT 24
Peak memory 575336 kb
Host smart-e8941951-dff6-4ad1-8952-cbf2cc76cdbf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217376612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.2217376612
Directory /workspace/72.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random.593329937
Short name T2092
Test name
Test status
Simulation time 117516450 ps
CPU time 7.26 seconds
Started Jul 14 07:40:16 PM PDT 24
Finished Jul 14 07:40:24 PM PDT 24
Peak memory 574208 kb
Host smart-c681485a-0115-4b77-9c6e-67b6bcbe1a71
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593329937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.593329937
Directory /workspace/72.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.1757792897
Short name T2204
Test name
Test status
Simulation time 39201932165 ps
CPU time 440.32 seconds
Started Jul 14 07:40:16 PM PDT 24
Finished Jul 14 07:47:36 PM PDT 24
Peak memory 575448 kb
Host smart-c7c3b55c-864e-4e86-a7be-8005a889daa1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757792897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.1757792897
Directory /workspace/72.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.2506541258
Short name T2035
Test name
Test status
Simulation time 29137273239 ps
CPU time 568.31 seconds
Started Jul 14 07:40:18 PM PDT 24
Finished Jul 14 07:49:46 PM PDT 24
Peak memory 575476 kb
Host smart-a76ebe93-8aa6-4084-a8ca-7b5e825bcd25
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506541258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.2506541258
Directory /workspace/72.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.891271248
Short name T1513
Test name
Test status
Simulation time 89845414 ps
CPU time 10.98 seconds
Started Jul 14 07:40:15 PM PDT 24
Finished Jul 14 07:40:26 PM PDT 24
Peak memory 575280 kb
Host smart-3b26ce8b-6cec-43b4-a08a-4ce5f6dbfdd8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891271248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_dela
ys.891271248
Directory /workspace/72.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_same_source.3522148497
Short name T1985
Test name
Test status
Simulation time 2495475013 ps
CPU time 72.7 seconds
Started Jul 14 07:40:26 PM PDT 24
Finished Jul 14 07:41:39 PM PDT 24
Peak memory 575408 kb
Host smart-ddf82ba5-8c80-477c-95dd-a98a28101bb0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522148497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.3522148497
Directory /workspace/72.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke.1077622409
Short name T2613
Test name
Test status
Simulation time 189387520 ps
CPU time 9.56 seconds
Started Jul 14 07:40:14 PM PDT 24
Finished Jul 14 07:40:24 PM PDT 24
Peak memory 574080 kb
Host smart-b1c60503-9705-43fb-87f3-773a64eb2f58
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077622409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.1077622409
Directory /workspace/72.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.620903734
Short name T1545
Test name
Test status
Simulation time 8439854130 ps
CPU time 92.8 seconds
Started Jul 14 07:40:16 PM PDT 24
Finished Jul 14 07:41:49 PM PDT 24
Peak memory 575420 kb
Host smart-afb6f47f-9a2e-4b4c-8454-48467ee7e792
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620903734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.620903734
Directory /workspace/72.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.729884160
Short name T2902
Test name
Test status
Simulation time 4603656751 ps
CPU time 87.36 seconds
Started Jul 14 07:40:18 PM PDT 24
Finished Jul 14 07:41:46 PM PDT 24
Peak memory 574128 kb
Host smart-bfa6b86f-8667-48d5-889b-ab1f39b205f0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729884160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.729884160
Directory /workspace/72.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.1260608456
Short name T1918
Test name
Test status
Simulation time 47350722 ps
CPU time 6.26 seconds
Started Jul 14 07:40:27 PM PDT 24
Finished Jul 14 07:40:34 PM PDT 24
Peak memory 574044 kb
Host smart-4bce0288-3634-45ff-8a9e-a6ec96c28e14
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260608456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay
s.1260608456
Directory /workspace/72.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all.1520592972
Short name T468
Test name
Test status
Simulation time 5603503193 ps
CPU time 206.55 seconds
Started Jul 14 07:40:25 PM PDT 24
Finished Jul 14 07:43:52 PM PDT 24
Peak memory 575612 kb
Host smart-7d638edc-49e0-41c7-b3d8-eba61bd053af
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520592972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.1520592972
Directory /workspace/72.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.2869658373
Short name T2180
Test name
Test status
Simulation time 1039852596 ps
CPU time 78.02 seconds
Started Jul 14 07:40:24 PM PDT 24
Finished Jul 14 07:41:42 PM PDT 24
Peak memory 575504 kb
Host smart-69281ecf-ee16-42ff-bda0-f64d23d0cf53
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869658373 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.2869658373
Directory /workspace/72.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.4023788361
Short name T1637
Test name
Test status
Simulation time 156077782 ps
CPU time 55.7 seconds
Started Jul 14 07:40:26 PM PDT 24
Finished Jul 14 07:41:22 PM PDT 24
Peak memory 575484 kb
Host smart-dce00882-9eaf-4eaa-9afb-f4ebbb7e52ef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023788361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all
_with_rand_reset.4023788361
Directory /workspace/72.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.3109771865
Short name T1492
Test name
Test status
Simulation time 373139053 ps
CPU time 86.75 seconds
Started Jul 14 07:40:26 PM PDT 24
Finished Jul 14 07:41:53 PM PDT 24
Peak memory 575424 kb
Host smart-4d1f1f52-dc4a-4e11-84ed-ebe17e9e790f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109771865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al
l_with_reset_error.3109771865
Directory /workspace/72.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.4084608221
Short name T574
Test name
Test status
Simulation time 251695252 ps
CPU time 27.77 seconds
Started Jul 14 07:40:26 PM PDT 24
Finished Jul 14 07:40:54 PM PDT 24
Peak memory 575424 kb
Host smart-ca20844c-72f9-45f0-a7b3-48bafa36cdcc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084608221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.4084608221
Directory /workspace/72.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_access_same_device.1729307195
Short name T2805
Test name
Test status
Simulation time 818702348 ps
CPU time 42.39 seconds
Started Jul 14 07:40:31 PM PDT 24
Finished Jul 14 07:41:14 PM PDT 24
Peak memory 575312 kb
Host smart-d5298190-a9e5-49e0-b14f-54a9cb9b84a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729307195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device
.1729307195
Directory /workspace/73.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.1521350026
Short name T826
Test name
Test status
Simulation time 129009046147 ps
CPU time 2488.22 seconds
Started Jul 14 07:40:39 PM PDT 24
Finished Jul 14 08:22:08 PM PDT 24
Peak memory 575560 kb
Host smart-ccb8f791-7365-47ff-91f5-54657d6c7b78
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521350026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_
device_slow_rsp.1521350026
Directory /workspace/73.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.3667480238
Short name T1721
Test name
Test status
Simulation time 199715149 ps
CPU time 19.56 seconds
Started Jul 14 07:40:32 PM PDT 24
Finished Jul 14 07:40:53 PM PDT 24
Peak memory 575280 kb
Host smart-8765aa15-bcae-4c51-a6bf-f16803c69736
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667480238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add
r.3667480238
Directory /workspace/73.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_error_random.3784689465
Short name T2633
Test name
Test status
Simulation time 987508007 ps
CPU time 33.75 seconds
Started Jul 14 07:40:34 PM PDT 24
Finished Jul 14 07:41:08 PM PDT 24
Peak memory 575252 kb
Host smart-a49c94ab-8a09-4e62-8e07-ff0b651ae4b7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784689465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.3784689465
Directory /workspace/73.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random.1841336008
Short name T2501
Test name
Test status
Simulation time 227209146 ps
CPU time 11.19 seconds
Started Jul 14 07:40:33 PM PDT 24
Finished Jul 14 07:40:45 PM PDT 24
Peak memory 575324 kb
Host smart-cbd76902-6b5e-4518-8049-0604e89127dc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841336008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.1841336008
Directory /workspace/73.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.13322738
Short name T1928
Test name
Test status
Simulation time 37314383671 ps
CPU time 421 seconds
Started Jul 14 07:40:39 PM PDT 24
Finished Jul 14 07:47:41 PM PDT 24
Peak memory 575504 kb
Host smart-0c96b581-e0ce-4d42-9818-48a7b6def038
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13322738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.13322738
Directory /workspace/73.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.3710267740
Short name T1616
Test name
Test status
Simulation time 19491800033 ps
CPU time 325.02 seconds
Started Jul 14 07:40:32 PM PDT 24
Finished Jul 14 07:45:58 PM PDT 24
Peak memory 575504 kb
Host smart-211c937c-9cec-4063-8b6d-69e83746c2f5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710267740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.3710267740
Directory /workspace/73.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.2894229766
Short name T616
Test name
Test status
Simulation time 451270329 ps
CPU time 39.78 seconds
Started Jul 14 07:40:39 PM PDT 24
Finished Jul 14 07:41:19 PM PDT 24
Peak memory 575316 kb
Host smart-3b30175c-63d3-45bd-bc7e-c7c931cf02e7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894229766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del
ays.2894229766
Directory /workspace/73.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_same_source.2309324683
Short name T585
Test name
Test status
Simulation time 1612021954 ps
CPU time 55.45 seconds
Started Jul 14 07:40:35 PM PDT 24
Finished Jul 14 07:41:31 PM PDT 24
Peak memory 575304 kb
Host smart-76deb7e0-9a81-4530-a032-cfb3ea03e548
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309324683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.2309324683
Directory /workspace/73.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke.4293762082
Short name T1374
Test name
Test status
Simulation time 219244342 ps
CPU time 9.18 seconds
Started Jul 14 07:40:25 PM PDT 24
Finished Jul 14 07:40:35 PM PDT 24
Peak memory 573980 kb
Host smart-3f5744ab-02a0-4d31-879a-6d0f194539ee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293762082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.4293762082
Directory /workspace/73.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.1082179261
Short name T622
Test name
Test status
Simulation time 8582355803 ps
CPU time 95.34 seconds
Started Jul 14 07:40:28 PM PDT 24
Finished Jul 14 07:42:04 PM PDT 24
Peak memory 574160 kb
Host smart-8beee4c4-7edc-4655-a1df-ee665f730884
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082179261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.1082179261
Directory /workspace/73.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.74893727
Short name T580
Test name
Test status
Simulation time 4729850387 ps
CPU time 82.91 seconds
Started Jul 14 07:40:26 PM PDT 24
Finished Jul 14 07:41:49 PM PDT 24
Peak memory 574128 kb
Host smart-278d8aad-4f18-4117-9405-526c4396718f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74893727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.74893727
Directory /workspace/73.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.3158307736
Short name T654
Test name
Test status
Simulation time 47073479 ps
CPU time 6.47 seconds
Started Jul 14 07:40:27 PM PDT 24
Finished Jul 14 07:40:34 PM PDT 24
Peak memory 574000 kb
Host smart-cd0476d7-5867-4305-9955-d3e62b207ed9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158307736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay
s.3158307736
Directory /workspace/73.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all.1480777487
Short name T2624
Test name
Test status
Simulation time 4350418309 ps
CPU time 418.46 seconds
Started Jul 14 07:40:35 PM PDT 24
Finished Jul 14 07:47:34 PM PDT 24
Peak memory 575592 kb
Host smart-34e15779-eb6e-4834-bba9-5a0a776f958f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480777487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.1480777487
Directory /workspace/73.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.2005142485
Short name T1474
Test name
Test status
Simulation time 21624216780 ps
CPU time 902.28 seconds
Started Jul 14 07:40:32 PM PDT 24
Finished Jul 14 07:55:35 PM PDT 24
Peak memory 575616 kb
Host smart-a2b2027e-aba0-42ea-9c71-898f2449a907
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005142485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.2005142485
Directory /workspace/73.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.1753945773
Short name T509
Test name
Test status
Simulation time 989123400 ps
CPU time 358.19 seconds
Started Jul 14 07:40:34 PM PDT 24
Finished Jul 14 07:46:33 PM PDT 24
Peak memory 575440 kb
Host smart-2eca79b4-672a-478a-b38f-da508187d12f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753945773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all
_with_rand_reset.1753945773
Directory /workspace/73.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.835923445
Short name T2657
Test name
Test status
Simulation time 9591740868 ps
CPU time 448.01 seconds
Started Jul 14 07:40:38 PM PDT 24
Finished Jul 14 07:48:06 PM PDT 24
Peak memory 575560 kb
Host smart-c3fea3d6-b597-4cbc-ba59-d06f4bb0bb64
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835923445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all
_with_reset_error.835923445
Directory /workspace/73.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.1035444497
Short name T2129
Test name
Test status
Simulation time 367223475 ps
CPU time 16.16 seconds
Started Jul 14 07:40:34 PM PDT 24
Finished Jul 14 07:40:50 PM PDT 24
Peak memory 575420 kb
Host smart-ff7af0dd-f494-446d-8660-56e60f18c544
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035444497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.1035444497
Directory /workspace/73.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_access_same_device.3559645314
Short name T1755
Test name
Test status
Simulation time 1131840203 ps
CPU time 76.34 seconds
Started Jul 14 07:40:39 PM PDT 24
Finished Jul 14 07:41:56 PM PDT 24
Peak memory 575288 kb
Host smart-918a17c5-bbaa-4d42-9159-3719580f6705
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559645314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device
.3559645314
Directory /workspace/74.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.2527618341
Short name T2295
Test name
Test status
Simulation time 132819809485 ps
CPU time 2409.47 seconds
Started Jul 14 07:40:37 PM PDT 24
Finished Jul 14 08:20:47 PM PDT 24
Peak memory 575528 kb
Host smart-5547441b-9281-4982-8367-5965cec513af
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527618341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_
device_slow_rsp.2527618341
Directory /workspace/74.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.3133237999
Short name T1867
Test name
Test status
Simulation time 41831425 ps
CPU time 6.69 seconds
Started Jul 14 07:40:38 PM PDT 24
Finished Jul 14 07:40:46 PM PDT 24
Peak memory 574000 kb
Host smart-c300e377-d20a-4127-82ce-cfb0a5cdcf6d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133237999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add
r.3133237999
Directory /workspace/74.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_error_random.3865194129
Short name T1825
Test name
Test status
Simulation time 2137502828 ps
CPU time 69.92 seconds
Started Jul 14 07:40:39 PM PDT 24
Finished Jul 14 07:41:50 PM PDT 24
Peak memory 575316 kb
Host smart-34dde0be-2686-4043-b8df-b5a41d336666
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865194129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.3865194129
Directory /workspace/74.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random.3544417022
Short name T1746
Test name
Test status
Simulation time 2382461529 ps
CPU time 90.46 seconds
Started Jul 14 07:40:43 PM PDT 24
Finished Jul 14 07:42:14 PM PDT 24
Peak memory 575388 kb
Host smart-3f9a9836-a701-436d-9aa4-8cf4660e1e48
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544417022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.3544417022
Directory /workspace/74.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.2954385396
Short name T2665
Test name
Test status
Simulation time 32098619355 ps
CPU time 351.75 seconds
Started Jul 14 07:40:38 PM PDT 24
Finished Jul 14 07:46:30 PM PDT 24
Peak memory 575444 kb
Host smart-3c865da2-eea9-4dd6-a063-e18648b641f4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954385396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.2954385396
Directory /workspace/74.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.1526184177
Short name T2638
Test name
Test status
Simulation time 14026426535 ps
CPU time 245.28 seconds
Started Jul 14 07:40:39 PM PDT 24
Finished Jul 14 07:44:45 PM PDT 24
Peak memory 575536 kb
Host smart-912aebaa-a126-4657-8915-e20907b2eda2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526184177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.1526184177
Directory /workspace/74.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.1585421277
Short name T634
Test name
Test status
Simulation time 524365261 ps
CPU time 44.28 seconds
Started Jul 14 07:40:37 PM PDT 24
Finished Jul 14 07:41:22 PM PDT 24
Peak memory 575368 kb
Host smart-eb2dd561-d3d8-4741-b7a4-81a16cee66b2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585421277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del
ays.1585421277
Directory /workspace/74.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_same_source.4283977368
Short name T1748
Test name
Test status
Simulation time 511416218 ps
CPU time 17.9 seconds
Started Jul 14 07:40:42 PM PDT 24
Finished Jul 14 07:41:01 PM PDT 24
Peak memory 575260 kb
Host smart-4e6efce8-e621-4a88-a918-52ae204a5210
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283977368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.4283977368
Directory /workspace/74.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke.1578402691
Short name T2196
Test name
Test status
Simulation time 241637581 ps
CPU time 10.17 seconds
Started Jul 14 07:40:43 PM PDT 24
Finished Jul 14 07:40:54 PM PDT 24
Peak memory 574008 kb
Host smart-194d41be-528a-493f-a649-3370a6b772d9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578402691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.1578402691
Directory /workspace/74.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.4004794020
Short name T2368
Test name
Test status
Simulation time 6887137697 ps
CPU time 71.38 seconds
Started Jul 14 07:40:39 PM PDT 24
Finished Jul 14 07:41:50 PM PDT 24
Peak memory 574144 kb
Host smart-2fac2dd6-e491-4ca6-a72a-648e241e0f0e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004794020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.4004794020
Directory /workspace/74.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.3109438839
Short name T2063
Test name
Test status
Simulation time 5932519403 ps
CPU time 106.35 seconds
Started Jul 14 07:40:36 PM PDT 24
Finished Jul 14 07:42:22 PM PDT 24
Peak memory 574124 kb
Host smart-752e5460-c68b-484a-b6b6-67eaf21549ea
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109438839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.3109438839
Directory /workspace/74.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.3692696503
Short name T1346
Test name
Test status
Simulation time 43798247 ps
CPU time 5.92 seconds
Started Jul 14 07:40:39 PM PDT 24
Finished Jul 14 07:40:45 PM PDT 24
Peak memory 575268 kb
Host smart-313b9832-f313-4821-8aef-8a5def6b6e41
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692696503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay
s.3692696503
Directory /workspace/74.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all.2872314541
Short name T492
Test name
Test status
Simulation time 1942226251 ps
CPU time 169.62 seconds
Started Jul 14 07:40:46 PM PDT 24
Finished Jul 14 07:43:35 PM PDT 24
Peak memory 575500 kb
Host smart-df9ec4ee-6a21-43e3-a1fb-6091bd2c6c6a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872314541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.2872314541
Directory /workspace/74.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.99550311
Short name T2090
Test name
Test status
Simulation time 10672236763 ps
CPU time 399.51 seconds
Started Jul 14 07:40:43 PM PDT 24
Finished Jul 14 07:47:23 PM PDT 24
Peak memory 575604 kb
Host smart-7e957871-26b1-4b57-b8ba-17a7b3ed9667
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99550311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.99550311
Directory /workspace/74.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.4017089975
Short name T642
Test name
Test status
Simulation time 816926554 ps
CPU time 45.68 seconds
Started Jul 14 07:40:45 PM PDT 24
Finished Jul 14 07:41:31 PM PDT 24
Peak memory 575440 kb
Host smart-d4b5ae58-47cd-4810-ab47-659cba434d47
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017089975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all
_with_rand_reset.4017089975
Directory /workspace/74.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.1706495541
Short name T849
Test name
Test status
Simulation time 355083929 ps
CPU time 137.82 seconds
Started Jul 14 07:40:43 PM PDT 24
Finished Jul 14 07:43:02 PM PDT 24
Peak memory 575480 kb
Host smart-9b96e993-bcbe-4fd7-83dc-0095e259ab9a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706495541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al
l_with_reset_error.1706495541
Directory /workspace/74.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.2256600218
Short name T1417
Test name
Test status
Simulation time 39516123 ps
CPU time 7.46 seconds
Started Jul 14 07:40:44 PM PDT 24
Finished Jul 14 07:40:52 PM PDT 24
Peak memory 574116 kb
Host smart-150ebd21-b2b0-490d-82f7-3e2534fc95d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256600218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.2256600218
Directory /workspace/74.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_access_same_device.1127910509
Short name T1678
Test name
Test status
Simulation time 1091526476 ps
CPU time 46.81 seconds
Started Jul 14 07:40:47 PM PDT 24
Finished Jul 14 07:41:35 PM PDT 24
Peak memory 575320 kb
Host smart-8a7bc4a5-bf30-470b-8f97-cd894b4b83d1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127910509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device
.1127910509
Directory /workspace/75.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.1916280550
Short name T1988
Test name
Test status
Simulation time 441973851 ps
CPU time 21.45 seconds
Started Jul 14 07:41:00 PM PDT 24
Finished Jul 14 07:41:22 PM PDT 24
Peak memory 575036 kb
Host smart-357f4cd3-1974-4e24-909c-32e36b9c64fb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916280550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add
r.1916280550
Directory /workspace/75.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_error_random.71449238
Short name T1439
Test name
Test status
Simulation time 150110052 ps
CPU time 8.48 seconds
Started Jul 14 07:40:49 PM PDT 24
Finished Jul 14 07:40:58 PM PDT 24
Peak memory 575256 kb
Host smart-caa72c0b-bd92-4477-972f-7d67e8a99c89
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71449238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.71449238
Directory /workspace/75.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random.826517671
Short name T2838
Test name
Test status
Simulation time 874873914 ps
CPU time 30.43 seconds
Started Jul 14 07:40:45 PM PDT 24
Finished Jul 14 07:41:16 PM PDT 24
Peak memory 575308 kb
Host smart-5a047571-0ec1-4bf9-bb66-0cfc2e6ed8ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826517671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.826517671
Directory /workspace/75.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.3285801526
Short name T2903
Test name
Test status
Simulation time 74902475216 ps
CPU time 809.87 seconds
Started Jul 14 07:40:45 PM PDT 24
Finished Jul 14 07:54:16 PM PDT 24
Peak memory 575524 kb
Host smart-a0303243-4099-4996-bb9a-39dfa88406ce
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285801526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.3285801526
Directory /workspace/75.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.778094029
Short name T1640
Test name
Test status
Simulation time 37021414834 ps
CPU time 738.61 seconds
Started Jul 14 07:41:01 PM PDT 24
Finished Jul 14 07:53:20 PM PDT 24
Peak memory 575480 kb
Host smart-cad2a2b9-d01e-499f-9d79-de1097dc819f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778094029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.778094029
Directory /workspace/75.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.4171355064
Short name T2570
Test name
Test status
Simulation time 53453820 ps
CPU time 7.72 seconds
Started Jul 14 07:40:47 PM PDT 24
Finished Jul 14 07:40:55 PM PDT 24
Peak memory 575300 kb
Host smart-eb3b676e-3bb2-442c-b93b-098201375da6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171355064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del
ays.4171355064
Directory /workspace/75.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_same_source.2530681434
Short name T2737
Test name
Test status
Simulation time 2457899092 ps
CPU time 71.11 seconds
Started Jul 14 07:40:51 PM PDT 24
Finished Jul 14 07:42:02 PM PDT 24
Peak memory 575400 kb
Host smart-5af3b894-4309-46f7-9cb8-3ae8bb625cd9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530681434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.2530681434
Directory /workspace/75.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke.4027085357
Short name T1344
Test name
Test status
Simulation time 235907703 ps
CPU time 10.32 seconds
Started Jul 14 07:40:47 PM PDT 24
Finished Jul 14 07:40:58 PM PDT 24
Peak memory 574044 kb
Host smart-a88e95a9-97f3-4667-99a9-6023ed694b38
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027085357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.4027085357
Directory /workspace/75.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.174486297
Short name T2483
Test name
Test status
Simulation time 9364795297 ps
CPU time 103.01 seconds
Started Jul 14 07:40:43 PM PDT 24
Finished Jul 14 07:42:27 PM PDT 24
Peak memory 575436 kb
Host smart-682b01a8-639b-4191-a0f9-f87fb3fecca4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174486297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.174486297
Directory /workspace/75.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.1221807597
Short name T2858
Test name
Test status
Simulation time 4929832995 ps
CPU time 86.65 seconds
Started Jul 14 07:40:45 PM PDT 24
Finished Jul 14 07:42:12 PM PDT 24
Peak memory 574152 kb
Host smart-c6a82786-4b33-4fc7-9686-92e0d3ca6cd1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221807597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.1221807597
Directory /workspace/75.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.1418211820
Short name T2228
Test name
Test status
Simulation time 41980634 ps
CPU time 5.61 seconds
Started Jul 14 07:40:47 PM PDT 24
Finished Jul 14 07:40:52 PM PDT 24
Peak memory 574028 kb
Host smart-ec236c6f-9b45-4114-b5e2-3b87df4496ca
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418211820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay
s.1418211820
Directory /workspace/75.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all.1960927256
Short name T2375
Test name
Test status
Simulation time 4737539694 ps
CPU time 186.18 seconds
Started Jul 14 07:41:01 PM PDT 24
Finished Jul 14 07:44:07 PM PDT 24
Peak memory 575536 kb
Host smart-aca3c703-d4ac-420e-82ce-5f2a4499edf0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960927256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.1960927256
Directory /workspace/75.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.2938935954
Short name T1807
Test name
Test status
Simulation time 6145818584 ps
CPU time 205.15 seconds
Started Jul 14 07:41:00 PM PDT 24
Finished Jul 14 07:44:26 PM PDT 24
Peak memory 575568 kb
Host smart-a3b7e653-6f6a-4349-8ffb-24a26a48dd79
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938935954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.2938935954
Directory /workspace/75.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.3068548965
Short name T2609
Test name
Test status
Simulation time 11065607079 ps
CPU time 600.94 seconds
Started Jul 14 07:40:52 PM PDT 24
Finished Jul 14 07:50:53 PM PDT 24
Peak memory 575600 kb
Host smart-eeb7cb31-a8b1-4c1a-9fe7-ddfcdf8b8056
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068548965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all
_with_rand_reset.3068548965
Directory /workspace/75.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1191796399
Short name T865
Test name
Test status
Simulation time 6720717868 ps
CPU time 383.33 seconds
Started Jul 14 07:40:51 PM PDT 24
Finished Jul 14 07:47:15 PM PDT 24
Peak memory 575600 kb
Host smart-3d013549-7071-4cda-80a4-4ca6bc953e03
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191796399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al
l_with_reset_error.1191796399
Directory /workspace/75.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.1421259566
Short name T2040
Test name
Test status
Simulation time 864828586 ps
CPU time 37.83 seconds
Started Jul 14 07:41:01 PM PDT 24
Finished Jul 14 07:41:39 PM PDT 24
Peak memory 575384 kb
Host smart-76e2dbf6-1c04-48f7-b10b-72fadce05c4e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421259566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.1421259566
Directory /workspace/75.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_access_same_device.3927215116
Short name T493
Test name
Test status
Simulation time 1078981672 ps
CPU time 48.31 seconds
Started Jul 14 07:40:56 PM PDT 24
Finished Jul 14 07:41:45 PM PDT 24
Peak memory 575360 kb
Host smart-3fa8074a-1ab4-4341-956a-ebe4513f5b17
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927215116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device
.3927215116
Directory /workspace/76.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3715437170
Short name T2584
Test name
Test status
Simulation time 40526625923 ps
CPU time 784.09 seconds
Started Jul 14 07:40:55 PM PDT 24
Finished Jul 14 07:54:00 PM PDT 24
Peak memory 575504 kb
Host smart-45bd8cc0-9b5b-4e19-bb8a-eacd264842b8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715437170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_
device_slow_rsp.3715437170
Directory /workspace/76.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.1264786798
Short name T1468
Test name
Test status
Simulation time 889395990 ps
CPU time 35.56 seconds
Started Jul 14 07:40:57 PM PDT 24
Finished Jul 14 07:41:33 PM PDT 24
Peak memory 575328 kb
Host smart-3434cd02-8184-4e00-8616-3508567526f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264786798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add
r.1264786798
Directory /workspace/76.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_error_random.2198748725
Short name T2400
Test name
Test status
Simulation time 717361950 ps
CPU time 24.99 seconds
Started Jul 14 07:40:56 PM PDT 24
Finished Jul 14 07:41:21 PM PDT 24
Peak memory 575296 kb
Host smart-13e3d1a8-1cb3-424a-afae-c5238696374d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198748725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.2198748725
Directory /workspace/76.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random.652028195
Short name T1840
Test name
Test status
Simulation time 2320306065 ps
CPU time 82.92 seconds
Started Jul 14 07:40:48 PM PDT 24
Finished Jul 14 07:42:11 PM PDT 24
Peak memory 575456 kb
Host smart-946979a1-0beb-42b3-90e4-97fd63e76335
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652028195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.652028195
Directory /workspace/76.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.2164342450
Short name T1448
Test name
Test status
Simulation time 57365645495 ps
CPU time 710.52 seconds
Started Jul 14 07:40:57 PM PDT 24
Finished Jul 14 07:52:48 PM PDT 24
Peak memory 575508 kb
Host smart-6024394b-e4ec-4fa5-8748-5ca416f835dd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164342450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.2164342450
Directory /workspace/76.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.2990534286
Short name T1391
Test name
Test status
Simulation time 18704240638 ps
CPU time 346.08 seconds
Started Jul 14 07:40:55 PM PDT 24
Finished Jul 14 07:46:42 PM PDT 24
Peak memory 575492 kb
Host smart-1de55ce3-dd75-45a2-a4cb-b5e46aeec601
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990534286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.2990534286
Directory /workspace/76.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.2845522133
Short name T2084
Test name
Test status
Simulation time 282274902 ps
CPU time 24.04 seconds
Started Jul 14 07:40:57 PM PDT 24
Finished Jul 14 07:41:22 PM PDT 24
Peak memory 575316 kb
Host smart-80781f54-2dcb-452e-9d4d-aad32d604a55
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845522133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del
ays.2845522133
Directory /workspace/76.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_same_source.61302006
Short name T2229
Test name
Test status
Simulation time 330442229 ps
CPU time 12.05 seconds
Started Jul 14 07:40:57 PM PDT 24
Finished Jul 14 07:41:10 PM PDT 24
Peak memory 575296 kb
Host smart-7f12b660-3716-4dc8-af4f-2d0c4fc22843
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61302006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.61302006
Directory /workspace/76.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke.1486452679
Short name T1358
Test name
Test status
Simulation time 54595319 ps
CPU time 6.72 seconds
Started Jul 14 07:40:50 PM PDT 24
Finished Jul 14 07:40:57 PM PDT 24
Peak memory 573964 kb
Host smart-969dd7ca-1a52-44fd-9c08-d95d3279d463
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486452679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.1486452679
Directory /workspace/76.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.1193380140
Short name T124
Test name
Test status
Simulation time 7227027808 ps
CPU time 79.46 seconds
Started Jul 14 07:40:54 PM PDT 24
Finished Jul 14 07:42:14 PM PDT 24
Peak memory 574136 kb
Host smart-c8e68113-3469-4fdd-bbf0-19f6ca6abebe
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193380140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.1193380140
Directory /workspace/76.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.870562923
Short name T2456
Test name
Test status
Simulation time 4260297766 ps
CPU time 70.68 seconds
Started Jul 14 07:40:51 PM PDT 24
Finished Jul 14 07:42:01 PM PDT 24
Peak memory 575404 kb
Host smart-38aedd3c-ea84-42f8-b363-19d68de73904
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870562923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.870562923
Directory /workspace/76.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.2132994205
Short name T2658
Test name
Test status
Simulation time 43014362 ps
CPU time 6.61 seconds
Started Jul 14 07:40:50 PM PDT 24
Finished Jul 14 07:40:56 PM PDT 24
Peak memory 574048 kb
Host smart-600c5c3f-617e-412b-8229-732642847bbc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132994205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delay
s.2132994205
Directory /workspace/76.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all.690953189
Short name T517
Test name
Test status
Simulation time 6125647001 ps
CPU time 195.93 seconds
Started Jul 14 07:40:56 PM PDT 24
Finished Jul 14 07:44:13 PM PDT 24
Peak memory 575612 kb
Host smart-3d59fcf6-f848-4596-b6a9-24de9ca1b84e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690953189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.690953189
Directory /workspace/76.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.3504155968
Short name T2067
Test name
Test status
Simulation time 2811249826 ps
CPU time 210.85 seconds
Started Jul 14 07:40:56 PM PDT 24
Finished Jul 14 07:44:27 PM PDT 24
Peak memory 575524 kb
Host smart-4b8bbebc-07c0-4f4c-94d4-0322bec04ec9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504155968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.3504155968
Directory /workspace/76.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.254705156
Short name T2407
Test name
Test status
Simulation time 138811784 ps
CPU time 56.05 seconds
Started Jul 14 07:40:56 PM PDT 24
Finished Jul 14 07:41:53 PM PDT 24
Peak memory 575508 kb
Host smart-b9e1a8e2-daca-4aee-9b51-fdfd4a5e0d86
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254705156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_
with_rand_reset.254705156
Directory /workspace/76.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.1289839143
Short name T854
Test name
Test status
Simulation time 250825794 ps
CPU time 86.4 seconds
Started Jul 14 07:40:59 PM PDT 24
Finished Jul 14 07:42:26 PM PDT 24
Peak memory 575500 kb
Host smart-ea87b44d-8249-4a9b-9a9b-91b1972a85d5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289839143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al
l_with_reset_error.1289839143
Directory /workspace/76.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.1128672546
Short name T123
Test name
Test status
Simulation time 250576075 ps
CPU time 29.76 seconds
Started Jul 14 07:40:59 PM PDT 24
Finished Jul 14 07:41:30 PM PDT 24
Peak memory 575432 kb
Host smart-d27d543b-95c8-4a24-b404-8ffd7e05e4c1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128672546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.1128672546
Directory /workspace/76.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_access_same_device.2649875559
Short name T2220
Test name
Test status
Simulation time 294559524 ps
CPU time 21.34 seconds
Started Jul 14 07:41:05 PM PDT 24
Finished Jul 14 07:41:27 PM PDT 24
Peak memory 575380 kb
Host smart-0412ce5a-3264-4e65-8d28-cc3ec4505769
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649875559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device
.2649875559
Directory /workspace/77.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.4015567607
Short name T1855
Test name
Test status
Simulation time 49128169516 ps
CPU time 922.08 seconds
Started Jul 14 07:41:05 PM PDT 24
Finished Jul 14 07:56:28 PM PDT 24
Peak memory 575496 kb
Host smart-07653f46-0a54-48b8-b142-fa7f2a7b26e7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015567607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_
device_slow_rsp.4015567607
Directory /workspace/77.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.2942288704
Short name T1671
Test name
Test status
Simulation time 323066226 ps
CPU time 15.34 seconds
Started Jul 14 07:41:09 PM PDT 24
Finished Jul 14 07:41:25 PM PDT 24
Peak memory 575284 kb
Host smart-82a747c5-0c13-4ec1-965b-176980455bf6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942288704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add
r.2942288704
Directory /workspace/77.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_error_random.1141427747
Short name T1769
Test name
Test status
Simulation time 1459813733 ps
CPU time 45.9 seconds
Started Jul 14 07:41:03 PM PDT 24
Finished Jul 14 07:41:49 PM PDT 24
Peak memory 575280 kb
Host smart-9f565a93-a398-4be5-b91e-b964d6715c04
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141427747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.1141427747
Directory /workspace/77.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random.3610138066
Short name T592
Test name
Test status
Simulation time 1913884063 ps
CPU time 65.97 seconds
Started Jul 14 07:41:04 PM PDT 24
Finished Jul 14 07:42:11 PM PDT 24
Peak memory 575336 kb
Host smart-173f8442-0504-48b5-9aaa-423108a64c43
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610138066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.3610138066
Directory /workspace/77.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.3620792271
Short name T2484
Test name
Test status
Simulation time 65898583723 ps
CPU time 804.9 seconds
Started Jul 14 07:41:03 PM PDT 24
Finished Jul 14 07:54:29 PM PDT 24
Peak memory 575544 kb
Host smart-9d9c98c4-389b-4201-bb45-150673ee7fa9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620792271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.3620792271
Directory /workspace/77.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.2009029030
Short name T1717
Test name
Test status
Simulation time 18011039341 ps
CPU time 324.33 seconds
Started Jul 14 07:41:04 PM PDT 24
Finished Jul 14 07:46:29 PM PDT 24
Peak memory 575512 kb
Host smart-7787e000-2893-4c97-9c4f-f77167fd6128
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009029030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.2009029030
Directory /workspace/77.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.2477079438
Short name T2336
Test name
Test status
Simulation time 155983315 ps
CPU time 17.2 seconds
Started Jul 14 07:41:03 PM PDT 24
Finished Jul 14 07:41:21 PM PDT 24
Peak memory 575252 kb
Host smart-c72056c1-ea62-4f02-a617-79690a616231
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477079438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del
ays.2477079438
Directory /workspace/77.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_same_source.610761171
Short name T524
Test name
Test status
Simulation time 2281714236 ps
CPU time 66.68 seconds
Started Jul 14 07:41:02 PM PDT 24
Finished Jul 14 07:42:09 PM PDT 24
Peak memory 575352 kb
Host smart-1c0ea054-e90b-4ec2-be5d-8eddf7c1a38f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610761171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.610761171
Directory /workspace/77.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke.1476711068
Short name T2854
Test name
Test status
Simulation time 194926313 ps
CPU time 8.5 seconds
Started Jul 14 07:40:55 PM PDT 24
Finished Jul 14 07:41:04 PM PDT 24
Peak memory 574004 kb
Host smart-9dedd821-9c4f-4f55-813d-e32496c19bc8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476711068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.1476711068
Directory /workspace/77.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.1510154862
Short name T1936
Test name
Test status
Simulation time 9321579996 ps
CPU time 101.99 seconds
Started Jul 14 07:40:55 PM PDT 24
Finished Jul 14 07:42:38 PM PDT 24
Peak memory 575460 kb
Host smart-59997ab9-492d-4938-8e39-48397599f2c1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510154862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.1510154862
Directory /workspace/77.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.968001666
Short name T1672
Test name
Test status
Simulation time 5789575899 ps
CPU time 102.04 seconds
Started Jul 14 07:40:55 PM PDT 24
Finished Jul 14 07:42:38 PM PDT 24
Peak memory 574220 kb
Host smart-ca724e16-49da-4de6-b3b8-ebd7c6d4c9ea
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968001666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.968001666
Directory /workspace/77.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.1679167232
Short name T2485
Test name
Test status
Simulation time 44938252 ps
CPU time 6.38 seconds
Started Jul 14 07:40:59 PM PDT 24
Finished Jul 14 07:41:06 PM PDT 24
Peak memory 574076 kb
Host smart-28b00e1d-af0f-44cb-8091-6732764d7f90
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679167232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay
s.1679167232
Directory /workspace/77.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all.455857718
Short name T2388
Test name
Test status
Simulation time 523536086 ps
CPU time 45.91 seconds
Started Jul 14 07:41:10 PM PDT 24
Finished Jul 14 07:41:57 PM PDT 24
Peak memory 575464 kb
Host smart-314a571c-9111-4637-9420-c39eec255e2c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455857718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.455857718
Directory /workspace/77.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.730512709
Short name T2414
Test name
Test status
Simulation time 2707849077 ps
CPU time 183.8 seconds
Started Jul 14 07:41:10 PM PDT 24
Finished Jul 14 07:44:14 PM PDT 24
Peak memory 575460 kb
Host smart-9a12b948-cd46-4719-aabf-03df4d32d3c4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730512709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.730512709
Directory /workspace/77.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2052098084
Short name T2764
Test name
Test status
Simulation time 355994010 ps
CPU time 127.68 seconds
Started Jul 14 07:41:13 PM PDT 24
Finished Jul 14 07:43:21 PM PDT 24
Peak memory 575496 kb
Host smart-2102d1fb-b722-460e-a6ba-175604995800
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052098084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all
_with_rand_reset.2052098084
Directory /workspace/77.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.1384052226
Short name T522
Test name
Test status
Simulation time 1489668046 ps
CPU time 60.02 seconds
Started Jul 14 07:41:02 PM PDT 24
Finished Jul 14 07:42:02 PM PDT 24
Peak memory 575484 kb
Host smart-b20b0149-92f2-4956-a08f-736f236bade1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384052226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.1384052226
Directory /workspace/77.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_access_same_device.1506803214
Short name T1467
Test name
Test status
Simulation time 403423871 ps
CPU time 32.19 seconds
Started Jul 14 07:41:15 PM PDT 24
Finished Jul 14 07:41:48 PM PDT 24
Peak memory 575288 kb
Host smart-abe30f99-658f-4840-abc3-17a5b895c489
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506803214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device
.1506803214
Directory /workspace/78.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.3000728778
Short name T2207
Test name
Test status
Simulation time 147481655689 ps
CPU time 2811.03 seconds
Started Jul 14 07:41:15 PM PDT 24
Finished Jul 14 08:28:06 PM PDT 24
Peak memory 575596 kb
Host smart-cb6c355a-5d98-4421-a2dd-2bfee4b0da6b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000728778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_
device_slow_rsp.3000728778
Directory /workspace/78.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.557583653
Short name T2366
Test name
Test status
Simulation time 165665141 ps
CPU time 20.22 seconds
Started Jul 14 07:41:15 PM PDT 24
Finished Jul 14 07:41:36 PM PDT 24
Peak memory 575340 kb
Host smart-304b6ba1-5c8b-4cff-8d1f-04c0842eb816
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557583653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_addr
.557583653
Directory /workspace/78.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_error_random.1967469597
Short name T249
Test name
Test status
Simulation time 536123015 ps
CPU time 19.62 seconds
Started Jul 14 07:41:16 PM PDT 24
Finished Jul 14 07:41:36 PM PDT 24
Peak memory 575284 kb
Host smart-728ee32f-fff0-4e48-b7b3-ced4b68e5ec0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967469597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.1967469597
Directory /workspace/78.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random.3644383644
Short name T1795
Test name
Test status
Simulation time 515111326 ps
CPU time 19.92 seconds
Started Jul 14 07:41:09 PM PDT 24
Finished Jul 14 07:41:30 PM PDT 24
Peak memory 575368 kb
Host smart-a7518508-2a52-4a56-8163-40068009f053
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644383644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.3644383644
Directory /workspace/78.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.524761263
Short name T2710
Test name
Test status
Simulation time 13392290380 ps
CPU time 141.39 seconds
Started Jul 14 07:41:10 PM PDT 24
Finished Jul 14 07:43:32 PM PDT 24
Peak memory 575436 kb
Host smart-ace4fe6b-c5c4-4e91-8101-ffec65fb03dc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524761263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.524761263
Directory /workspace/78.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.645157566
Short name T1775
Test name
Test status
Simulation time 31722920147 ps
CPU time 569.51 seconds
Started Jul 14 07:41:17 PM PDT 24
Finished Jul 14 07:50:47 PM PDT 24
Peak memory 575464 kb
Host smart-f6e41157-0bf7-4638-9c44-c0e37338a9a1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645157566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.645157566
Directory /workspace/78.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.3041068474
Short name T1969
Test name
Test status
Simulation time 610429498 ps
CPU time 47.08 seconds
Started Jul 14 07:41:11 PM PDT 24
Finished Jul 14 07:41:59 PM PDT 24
Peak memory 575352 kb
Host smart-d6fcd07d-8c3f-449f-b7b0-6f3465773233
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041068474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del
ays.3041068474
Directory /workspace/78.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_same_source.2511714374
Short name T2348
Test name
Test status
Simulation time 1031425651 ps
CPU time 30.84 seconds
Started Jul 14 07:41:18 PM PDT 24
Finished Jul 14 07:41:49 PM PDT 24
Peak memory 575344 kb
Host smart-9a34a8a0-7a18-4abc-855a-81ded70ecfc4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511714374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.2511714374
Directory /workspace/78.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke.349878749
Short name T2313
Test name
Test status
Simulation time 211571872 ps
CPU time 9.27 seconds
Started Jul 14 07:41:09 PM PDT 24
Finished Jul 14 07:41:19 PM PDT 24
Peak memory 573976 kb
Host smart-3fefd316-4313-4d0e-a20a-506b6044fed3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349878749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.349878749
Directory /workspace/78.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.231533333
Short name T1553
Test name
Test status
Simulation time 8217288322 ps
CPU time 99.15 seconds
Started Jul 14 07:41:12 PM PDT 24
Finished Jul 14 07:42:51 PM PDT 24
Peak memory 574148 kb
Host smart-fbf6d95d-db68-47fa-b8ca-3289134545d5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231533333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.231533333
Directory /workspace/78.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.3707178295
Short name T1856
Test name
Test status
Simulation time 6869843161 ps
CPU time 118.96 seconds
Started Jul 14 07:41:12 PM PDT 24
Finished Jul 14 07:43:11 PM PDT 24
Peak memory 575444 kb
Host smart-ab872065-b081-435d-b4c6-ef55ede1bc8c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707178295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.3707178295
Directory /workspace/78.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.1452751237
Short name T2199
Test name
Test status
Simulation time 47417256 ps
CPU time 6.26 seconds
Started Jul 14 07:41:11 PM PDT 24
Finished Jul 14 07:41:18 PM PDT 24
Peak memory 575300 kb
Host smart-f9c8d423-a54c-4606-80bc-b3077c5c783f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452751237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay
s.1452751237
Directory /workspace/78.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all.1326195451
Short name T2046
Test name
Test status
Simulation time 8111455025 ps
CPU time 300.34 seconds
Started Jul 14 07:41:15 PM PDT 24
Finished Jul 14 07:46:16 PM PDT 24
Peak memory 575564 kb
Host smart-aac0b473-0816-45be-b44c-fe5424bab50f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326195451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.1326195451
Directory /workspace/78.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.143489429
Short name T1882
Test name
Test status
Simulation time 15388627917 ps
CPU time 611.76 seconds
Started Jul 14 07:41:15 PM PDT 24
Finished Jul 14 07:51:27 PM PDT 24
Peak memory 575596 kb
Host smart-1fe640f8-fb53-422f-bd39-7b992154f2df
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143489429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.143489429
Directory /workspace/78.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.4230729385
Short name T1906
Test name
Test status
Simulation time 313155026 ps
CPU time 127.21 seconds
Started Jul 14 07:41:16 PM PDT 24
Finished Jul 14 07:43:24 PM PDT 24
Peak memory 575508 kb
Host smart-0c220dbd-c5bb-4e5b-8d63-577809e308f1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230729385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all
_with_rand_reset.4230729385
Directory /workspace/78.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.384831629
Short name T2699
Test name
Test status
Simulation time 3676062281 ps
CPU time 322.91 seconds
Started Jul 14 07:41:16 PM PDT 24
Finished Jul 14 07:46:39 PM PDT 24
Peak memory 575580 kb
Host smart-c62c4a80-cc07-44c2-bdf3-072102a637eb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384831629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all
_with_reset_error.384831629
Directory /workspace/78.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.520689612
Short name T1486
Test name
Test status
Simulation time 1322646273 ps
CPU time 50.03 seconds
Started Jul 14 07:41:16 PM PDT 24
Finished Jul 14 07:42:06 PM PDT 24
Peak memory 575388 kb
Host smart-4678544c-d54e-4e8f-afcb-fbb77b45743a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520689612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.520689612
Directory /workspace/78.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_access_same_device.554711421
Short name T2822
Test name
Test status
Simulation time 2081736797 ps
CPU time 82.34 seconds
Started Jul 14 07:41:24 PM PDT 24
Finished Jul 14 07:42:46 PM PDT 24
Peak memory 575268 kb
Host smart-0785997a-578d-4137-a999-dc639f3f37ab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554711421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device.
554711421
Directory /workspace/79.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.3040591770
Short name T2773
Test name
Test status
Simulation time 56325033777 ps
CPU time 1147.04 seconds
Started Jul 14 07:41:21 PM PDT 24
Finished Jul 14 08:00:29 PM PDT 24
Peak memory 575524 kb
Host smart-767b0941-c4ca-4861-9bb8-39a640f47b60
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040591770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_
device_slow_rsp.3040591770
Directory /workspace/79.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.3087781932
Short name T1566
Test name
Test status
Simulation time 1192154127 ps
CPU time 43.56 seconds
Started Jul 14 07:41:34 PM PDT 24
Finished Jul 14 07:42:17 PM PDT 24
Peak memory 575340 kb
Host smart-ba3a6361-d3fe-4e1c-b0d1-b3e4dc78bfdf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087781932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add
r.3087781932
Directory /workspace/79.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_error_random.1414518311
Short name T1796
Test name
Test status
Simulation time 112566491 ps
CPU time 13.04 seconds
Started Jul 14 07:41:22 PM PDT 24
Finished Jul 14 07:41:35 PM PDT 24
Peak memory 575320 kb
Host smart-4b1bfabc-02e0-4f4e-8083-43547b855b5e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414518311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.1414518311
Directory /workspace/79.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random.3222298348
Short name T2163
Test name
Test status
Simulation time 355582019 ps
CPU time 31.28 seconds
Started Jul 14 07:41:21 PM PDT 24
Finished Jul 14 07:41:53 PM PDT 24
Peak memory 575320 kb
Host smart-46d0a38e-eaad-4fb8-8b16-e1c121f28f10
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222298348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.3222298348
Directory /workspace/79.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.2015157761
Short name T1428
Test name
Test status
Simulation time 111524496444 ps
CPU time 1357.52 seconds
Started Jul 14 07:41:23 PM PDT 24
Finished Jul 14 08:04:01 PM PDT 24
Peak memory 575572 kb
Host smart-2c2e9fb9-b5ea-42e2-8fbf-e7abfb40b3d6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015157761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.2015157761
Directory /workspace/79.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.1015759694
Short name T534
Test name
Test status
Simulation time 44747996273 ps
CPU time 867.11 seconds
Started Jul 14 07:41:24 PM PDT 24
Finished Jul 14 07:55:51 PM PDT 24
Peak memory 575520 kb
Host smart-d19d0a31-16e3-4b75-a8dd-54bc84d33baf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015759694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.1015759694
Directory /workspace/79.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.662590854
Short name T1506
Test name
Test status
Simulation time 391822692 ps
CPU time 33.86 seconds
Started Jul 14 07:41:23 PM PDT 24
Finished Jul 14 07:41:57 PM PDT 24
Peak memory 575300 kb
Host smart-d9358416-f64f-4533-8a9b-e8a4d2835a4a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662590854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_dela
ys.662590854
Directory /workspace/79.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_same_source.236341783
Short name T2300
Test name
Test status
Simulation time 862588549 ps
CPU time 27.77 seconds
Started Jul 14 07:41:23 PM PDT 24
Finished Jul 14 07:41:51 PM PDT 24
Peak memory 575312 kb
Host smart-e9e93257-c3b5-463f-8a2c-92423d4286a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236341783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.236341783
Directory /workspace/79.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke.264048016
Short name T1780
Test name
Test status
Simulation time 255045276 ps
CPU time 10.4 seconds
Started Jul 14 07:41:17 PM PDT 24
Finished Jul 14 07:41:28 PM PDT 24
Peak memory 574072 kb
Host smart-5e8139ae-8602-4867-b353-086f83bc1fa3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264048016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.264048016
Directory /workspace/79.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.3899921454
Short name T2362
Test name
Test status
Simulation time 5219318519 ps
CPU time 63.52 seconds
Started Jul 14 07:41:28 PM PDT 24
Finished Jul 14 07:42:32 PM PDT 24
Peak memory 574152 kb
Host smart-9fe3f970-2f75-482e-8ecf-7eb3e6b61ddf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899921454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.3899921454
Directory /workspace/79.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.3219218230
Short name T2724
Test name
Test status
Simulation time 4922892277 ps
CPU time 85.84 seconds
Started Jul 14 07:41:23 PM PDT 24
Finished Jul 14 07:42:49 PM PDT 24
Peak memory 574148 kb
Host smart-c2632d9f-dbfb-459e-bd2b-f31e2751efdf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219218230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.3219218230
Directory /workspace/79.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.1345694590
Short name T1538
Test name
Test status
Simulation time 45029530 ps
CPU time 6.45 seconds
Started Jul 14 07:41:14 PM PDT 24
Finished Jul 14 07:41:21 PM PDT 24
Peak memory 575284 kb
Host smart-616fefe5-8156-4446-b4cf-6a762b134cef
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345694590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay
s.1345694590
Directory /workspace/79.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all.2600838383
Short name T2275
Test name
Test status
Simulation time 2648356148 ps
CPU time 204.95 seconds
Started Jul 14 07:41:29 PM PDT 24
Finished Jul 14 07:44:55 PM PDT 24
Peak memory 575576 kb
Host smart-cffb7e51-9cb0-4cf6-aed5-62a9e3f0fbb7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600838383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.2600838383
Directory /workspace/79.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.3043017495
Short name T2326
Test name
Test status
Simulation time 3601902882 ps
CPU time 149.36 seconds
Started Jul 14 07:41:30 PM PDT 24
Finished Jul 14 07:44:00 PM PDT 24
Peak memory 575460 kb
Host smart-315c5d16-4604-452a-bdc3-25beb5f7b318
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043017495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.3043017495
Directory /workspace/79.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1418591058
Short name T871
Test name
Test status
Simulation time 2063732970 ps
CPU time 223.41 seconds
Started Jul 14 07:41:29 PM PDT 24
Finished Jul 14 07:45:13 PM PDT 24
Peak memory 575616 kb
Host smart-17dfdfac-6bb2-43da-8d59-af1d7c45930c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418591058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all
_with_rand_reset.1418591058
Directory /workspace/79.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.1196737395
Short name T2876
Test name
Test status
Simulation time 666056976 ps
CPU time 193.18 seconds
Started Jul 14 07:41:28 PM PDT 24
Finished Jul 14 07:44:42 PM PDT 24
Peak memory 575496 kb
Host smart-14061155-2df7-4e87-b11a-fb6d4d2df1de
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196737395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al
l_with_reset_error.1196737395
Directory /workspace/79.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.2403884981
Short name T2642
Test name
Test status
Simulation time 323976106 ps
CPU time 15.76 seconds
Started Jul 14 07:41:28 PM PDT 24
Finished Jul 14 07:41:44 PM PDT 24
Peak memory 575400 kb
Host smart-0c2eefe3-cda8-4eeb-9950-bb1a0c78d066
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403884981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.2403884981
Directory /workspace/79.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/8.chip_csr_rw.2477806712
Short name T473
Test name
Test status
Simulation time 3936758050 ps
CPU time 300.29 seconds
Started Jul 14 07:29:03 PM PDT 24
Finished Jul 14 07:34:04 PM PDT 24
Peak memory 596904 kb
Host smart-e71736fa-3fbc-4a90-81e0-f484d4608c7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477806712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.2477806712
Directory /workspace/8.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.chip_tl_errors.2366298976
Short name T561
Test name
Test status
Simulation time 4058258504 ps
CPU time 277.91 seconds
Started Jul 14 07:28:44 PM PDT 24
Finished Jul 14 07:33:22 PM PDT 24
Peak memory 603780 kb
Host smart-b14eb0e3-b6ae-4849-875f-81dd4122eb4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366298976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.2366298976
Directory /workspace/8.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_access_same_device.3396138690
Short name T2019
Test name
Test status
Simulation time 717061674 ps
CPU time 45.75 seconds
Started Jul 14 07:28:57 PM PDT 24
Finished Jul 14 07:29:43 PM PDT 24
Peak memory 575368 kb
Host smart-f0e1431e-5bd0-4f2d-ad63-192cdadf37b3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396138690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.
3396138690
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.3777982483
Short name T2195
Test name
Test status
Simulation time 137060539044 ps
CPU time 2576.61 seconds
Started Jul 14 07:28:57 PM PDT 24
Finished Jul 14 08:11:54 PM PDT 24
Peak memory 575524 kb
Host smart-d326652e-669c-4c61-a03d-3eaefe5ba7b8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777982483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_d
evice_slow_rsp.3777982483
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.1619016845
Short name T2320
Test name
Test status
Simulation time 102430686 ps
CPU time 13.16 seconds
Started Jul 14 07:28:56 PM PDT 24
Finished Jul 14 07:29:09 PM PDT 24
Peak memory 575260 kb
Host smart-0851ece6-9e8c-4348-a6f2-c9b3dec66b6c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619016845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr
.1619016845
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_error_random.3191340329
Short name T2110
Test name
Test status
Simulation time 2506216467 ps
CPU time 84.6 seconds
Started Jul 14 07:28:55 PM PDT 24
Finished Jul 14 07:30:20 PM PDT 24
Peak memory 575380 kb
Host smart-0699aa9b-a4de-4a2e-8b92-42d61093eea9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191340329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3191340329
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random.1420624844
Short name T1508
Test name
Test status
Simulation time 477496214 ps
CPU time 46.81 seconds
Started Jul 14 07:28:51 PM PDT 24
Finished Jul 14 07:29:38 PM PDT 24
Peak memory 575388 kb
Host smart-4ad62c12-4b54-42d1-89b1-a85d905777ae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420624844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.1420624844
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.1763779797
Short name T2022
Test name
Test status
Simulation time 58345469722 ps
CPU time 645.51 seconds
Started Jul 14 07:28:50 PM PDT 24
Finished Jul 14 07:39:36 PM PDT 24
Peak memory 575508 kb
Host smart-629778ea-607b-4e0d-a1af-c655234d9849
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763779797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1763779797
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.705653149
Short name T2036
Test name
Test status
Simulation time 52013658831 ps
CPU time 940.09 seconds
Started Jul 14 07:28:58 PM PDT 24
Finished Jul 14 07:44:38 PM PDT 24
Peak memory 575484 kb
Host smart-c50c70f0-b6fe-48b8-a20e-b961c25a8a4c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705653149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.705653149
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.1279930860
Short name T2219
Test name
Test status
Simulation time 250019839 ps
CPU time 21.03 seconds
Started Jul 14 07:28:50 PM PDT 24
Finished Jul 14 07:29:12 PM PDT 24
Peak memory 575288 kb
Host smart-5c16e2fc-852a-4e23-80a1-c5028b709596
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279930860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela
ys.1279930860
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_same_source.3270871201
Short name T504
Test name
Test status
Simulation time 1887044561 ps
CPU time 64.56 seconds
Started Jul 14 07:28:55 PM PDT 24
Finished Jul 14 07:30:00 PM PDT 24
Peak memory 575376 kb
Host smart-1cc93bce-01b8-496a-aa76-c087c10e3ed8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270871201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3270871201
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke.3904586118
Short name T1582
Test name
Test status
Simulation time 43591860 ps
CPU time 5.96 seconds
Started Jul 14 07:28:45 PM PDT 24
Finished Jul 14 07:28:51 PM PDT 24
Peak memory 574040 kb
Host smart-d2671dc6-d6b3-4db1-ba53-7f6bd9f937e8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904586118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3904586118
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.3895343273
Short name T2160
Test name
Test status
Simulation time 6219922556 ps
CPU time 66.3 seconds
Started Jul 14 07:28:52 PM PDT 24
Finished Jul 14 07:29:59 PM PDT 24
Peak memory 575376 kb
Host smart-0a23554c-1a91-4259-9d30-3e57c28061ba
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895343273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3895343273
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.4241231356
Short name T2878
Test name
Test status
Simulation time 4182459406 ps
CPU time 71.62 seconds
Started Jul 14 07:28:52 PM PDT 24
Finished Jul 14 07:30:04 PM PDT 24
Peak memory 574136 kb
Host smart-08355b33-f1b4-43f2-8c03-a040c1b8fc7a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241231356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.4241231356
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.2615357772
Short name T1383
Test name
Test status
Simulation time 43786471 ps
CPU time 6.41 seconds
Started Jul 14 07:28:47 PM PDT 24
Finished Jul 14 07:28:54 PM PDT 24
Peak memory 574020 kb
Host smart-3c04803f-a528-462c-acaa-e39e7911bf9a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615357772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays
.2615357772
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all.705899571
Short name T2126
Test name
Test status
Simulation time 17757993823 ps
CPU time 681.5 seconds
Started Jul 14 07:28:55 PM PDT 24
Finished Jul 14 07:40:17 PM PDT 24
Peak memory 575540 kb
Host smart-05218fdb-fd1a-4abb-a74f-f9eb245c5f93
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705899571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.705899571
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.2027089101
Short name T2479
Test name
Test status
Simulation time 19597335365 ps
CPU time 748.27 seconds
Started Jul 14 07:29:03 PM PDT 24
Finished Jul 14 07:41:31 PM PDT 24
Peak memory 575584 kb
Host smart-5ad58329-6b3a-42c8-ba14-606425329963
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027089101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2027089101
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.4073140073
Short name T2273
Test name
Test status
Simulation time 4764126033 ps
CPU time 626.57 seconds
Started Jul 14 07:28:57 PM PDT 24
Finished Jul 14 07:39:24 PM PDT 24
Peak memory 575596 kb
Host smart-79cd1626-f2df-496f-ad68-d6c2f1ca1ebb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073140073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_
with_rand_reset.4073140073
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.3868076410
Short name T2579
Test name
Test status
Simulation time 7214804 ps
CPU time 17.94 seconds
Started Jul 14 07:28:58 PM PDT 24
Finished Jul 14 07:29:17 PM PDT 24
Peak memory 574064 kb
Host smart-ef445a22-9752-496e-9966-2828373ed3ee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868076410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all
_with_reset_error.3868076410
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.1192642173
Short name T1841
Test name
Test status
Simulation time 1080847177 ps
CPU time 51.3 seconds
Started Jul 14 07:28:59 PM PDT 24
Finished Jul 14 07:29:51 PM PDT 24
Peak memory 575460 kb
Host smart-6f407410-c29e-4d5d-b76f-78190fa3df84
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192642173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1192642173
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_access_same_device.1856775471
Short name T1923
Test name
Test status
Simulation time 244715846 ps
CPU time 12 seconds
Started Jul 14 07:41:28 PM PDT 24
Finished Jul 14 07:41:41 PM PDT 24
Peak memory 574040 kb
Host smart-faa25cf3-64be-48b2-9bc8-2efb604a02a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856775471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device
.1856775471
Directory /workspace/80.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.2947820107
Short name T566
Test name
Test status
Simulation time 71777354006 ps
CPU time 1366.23 seconds
Started Jul 14 07:41:29 PM PDT 24
Finished Jul 14 08:04:16 PM PDT 24
Peak memory 575488 kb
Host smart-5cf45ddb-8143-4ebe-98c2-c980eedbc45f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947820107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_
device_slow_rsp.2947820107
Directory /workspace/80.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.1240720952
Short name T2221
Test name
Test status
Simulation time 490699644 ps
CPU time 20.23 seconds
Started Jul 14 07:41:35 PM PDT 24
Finished Jul 14 07:41:55 PM PDT 24
Peak memory 575308 kb
Host smart-2fa4fad7-8a11-4f70-bdc3-0071e7a9766e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240720952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add
r.1240720952
Directory /workspace/80.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_error_random.2699508940
Short name T2343
Test name
Test status
Simulation time 89051979 ps
CPU time 9.66 seconds
Started Jul 14 07:41:38 PM PDT 24
Finished Jul 14 07:41:48 PM PDT 24
Peak memory 575272 kb
Host smart-49a90e72-bcf0-4644-899a-2877f0722b21
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699508940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.2699508940
Directory /workspace/80.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random.3717329345
Short name T1512
Test name
Test status
Simulation time 619045083 ps
CPU time 50.66 seconds
Started Jul 14 07:41:29 PM PDT 24
Finished Jul 14 07:42:20 PM PDT 24
Peak memory 575412 kb
Host smart-b76916c2-92ab-4a6a-9f13-44121da6ef78
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717329345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.3717329345
Directory /workspace/80.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.3949990748
Short name T1760
Test name
Test status
Simulation time 97129972200 ps
CPU time 1191.95 seconds
Started Jul 14 07:41:34 PM PDT 24
Finished Jul 14 08:01:27 PM PDT 24
Peak memory 575528 kb
Host smart-53d91b94-2e77-4e55-989b-d1db59e3f8cd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949990748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.3949990748
Directory /workspace/80.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.2109462796
Short name T2311
Test name
Test status
Simulation time 61609157323 ps
CPU time 1249.02 seconds
Started Jul 14 07:41:28 PM PDT 24
Finished Jul 14 08:02:18 PM PDT 24
Peak memory 575524 kb
Host smart-812befa1-22c5-4fd3-a53a-88faa7f95be3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109462796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.2109462796
Directory /workspace/80.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.1821650589
Short name T1751
Test name
Test status
Simulation time 335673620 ps
CPU time 32.24 seconds
Started Jul 14 07:41:26 PM PDT 24
Finished Jul 14 07:41:59 PM PDT 24
Peak memory 575304 kb
Host smart-ba107826-cc67-4674-9e00-6bc733f96a49
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821650589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del
ays.1821650589
Directory /workspace/80.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_same_source.1205099154
Short name T624
Test name
Test status
Simulation time 1105893233 ps
CPU time 34.95 seconds
Started Jul 14 07:41:33 PM PDT 24
Finished Jul 14 07:42:08 PM PDT 24
Peak memory 575368 kb
Host smart-967a5a0a-0507-44bf-93ff-e35710eb3080
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205099154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.1205099154
Directory /workspace/80.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke.1254995802
Short name T2857
Test name
Test status
Simulation time 55167660 ps
CPU time 6.41 seconds
Started Jul 14 07:41:34 PM PDT 24
Finished Jul 14 07:41:41 PM PDT 24
Peak memory 575256 kb
Host smart-3c8bd00c-6711-4c99-8928-fde2268e2cb8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254995802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.1254995802
Directory /workspace/80.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.3451018805
Short name T1409
Test name
Test status
Simulation time 8337998289 ps
CPU time 94.17 seconds
Started Jul 14 07:41:28 PM PDT 24
Finished Jul 14 07:43:03 PM PDT 24
Peak memory 574160 kb
Host smart-ab304170-28d7-49a1-99a6-662741feec05
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451018805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.3451018805
Directory /workspace/80.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.1155803401
Short name T2103
Test name
Test status
Simulation time 4663294876 ps
CPU time 85.4 seconds
Started Jul 14 07:41:30 PM PDT 24
Finished Jul 14 07:42:56 PM PDT 24
Peak memory 575404 kb
Host smart-c3ff9ca2-ab51-4ac6-8b32-529f739e1536
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155803401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.1155803401
Directory /workspace/80.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.461424135
Short name T2644
Test name
Test status
Simulation time 40739909 ps
CPU time 5.46 seconds
Started Jul 14 07:41:28 PM PDT 24
Finished Jul 14 07:41:34 PM PDT 24
Peak memory 574000 kb
Host smart-9428d0d2-5c86-42c2-90fd-7efad87edfe1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461424135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delays
.461424135
Directory /workspace/80.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all.3893644973
Short name T2862
Test name
Test status
Simulation time 1847158825 ps
CPU time 157.96 seconds
Started Jul 14 07:41:35 PM PDT 24
Finished Jul 14 07:44:14 PM PDT 24
Peak memory 575484 kb
Host smart-f325269c-607e-4813-b250-d2196e03ef87
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893644973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.3893644973
Directory /workspace/80.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.3947255248
Short name T1930
Test name
Test status
Simulation time 225491830 ps
CPU time 12.29 seconds
Started Jul 14 07:41:34 PM PDT 24
Finished Jul 14 07:41:47 PM PDT 24
Peak memory 575324 kb
Host smart-a7b47742-a2a7-4771-87c3-12932491107f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947255248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.3947255248
Directory /workspace/80.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2281472320
Short name T2617
Test name
Test status
Simulation time 356885559 ps
CPU time 223.46 seconds
Started Jul 14 07:41:34 PM PDT 24
Finished Jul 14 07:45:18 PM PDT 24
Peak memory 575500 kb
Host smart-1b1a2d12-6422-4d20-89c0-8d4391cd959e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281472320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all
_with_rand_reset.2281472320
Directory /workspace/80.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.711494212
Short name T1941
Test name
Test status
Simulation time 86831904 ps
CPU time 52.8 seconds
Started Jul 14 07:41:34 PM PDT 24
Finished Jul 14 07:42:27 PM PDT 24
Peak memory 575216 kb
Host smart-3dec8a07-0048-4d09-b6ba-d849d75c505d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711494212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all
_with_reset_error.711494212
Directory /workspace/80.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.511579312
Short name T1413
Test name
Test status
Simulation time 125629496 ps
CPU time 17.7 seconds
Started Jul 14 07:41:36 PM PDT 24
Finished Jul 14 07:41:54 PM PDT 24
Peak memory 575368 kb
Host smart-40fcb375-94e4-411a-b9b8-aa8d60da8b4d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511579312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.511579312
Directory /workspace/80.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_access_same_device.368488295
Short name T2032
Test name
Test status
Simulation time 3437892812 ps
CPU time 146.79 seconds
Started Jul 14 07:41:42 PM PDT 24
Finished Jul 14 07:44:09 PM PDT 24
Peak memory 575408 kb
Host smart-a56e14c7-9e7a-46d1-858f-ba8ba089198d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368488295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device.
368488295
Directory /workspace/81.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.4202320568
Short name T2167
Test name
Test status
Simulation time 119148219389 ps
CPU time 2241 seconds
Started Jul 14 07:41:46 PM PDT 24
Finished Jul 14 08:19:07 PM PDT 24
Peak memory 575536 kb
Host smart-1be7884e-e14c-40e1-82fa-9769f4d46caf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202320568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_
device_slow_rsp.4202320568
Directory /workspace/81.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.3068166014
Short name T1931
Test name
Test status
Simulation time 290956179 ps
CPU time 28.65 seconds
Started Jul 14 07:41:41 PM PDT 24
Finished Jul 14 07:42:10 PM PDT 24
Peak memory 575332 kb
Host smart-aab29fb6-8db2-4abf-91b6-06df45a15c82
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068166014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add
r.3068166014
Directory /workspace/81.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_error_random.1814539553
Short name T1919
Test name
Test status
Simulation time 67822719 ps
CPU time 8.48 seconds
Started Jul 14 07:41:42 PM PDT 24
Finished Jul 14 07:41:51 PM PDT 24
Peak memory 575216 kb
Host smart-bb166c01-e187-430b-8b85-90a71db9ac7a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814539553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.1814539553
Directory /workspace/81.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random.591245079
Short name T2428
Test name
Test status
Simulation time 98341459 ps
CPU time 10.86 seconds
Started Jul 14 07:41:43 PM PDT 24
Finished Jul 14 07:41:54 PM PDT 24
Peak memory 575308 kb
Host smart-38c2c6ae-f2ac-4e5b-b514-f0c101c6c003
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591245079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.591245079
Directory /workspace/81.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.2636678996
Short name T2249
Test name
Test status
Simulation time 101929054709 ps
CPU time 1170.23 seconds
Started Jul 14 07:41:42 PM PDT 24
Finished Jul 14 08:01:13 PM PDT 24
Peak memory 575532 kb
Host smart-3d955360-5bc5-44ba-9bf9-7cbae404adf6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636678996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.2636678996
Directory /workspace/81.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.3200573480
Short name T1865
Test name
Test status
Simulation time 48598662877 ps
CPU time 954.9 seconds
Started Jul 14 07:41:41 PM PDT 24
Finished Jul 14 07:57:36 PM PDT 24
Peak memory 575564 kb
Host smart-5ec8b85f-fea4-48a2-a4d9-ceb91a44be47
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200573480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.3200573480
Directory /workspace/81.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.2738549362
Short name T1584
Test name
Test status
Simulation time 138729248 ps
CPU time 13.17 seconds
Started Jul 14 07:41:43 PM PDT 24
Finished Jul 14 07:41:56 PM PDT 24
Peak memory 575348 kb
Host smart-1f5f9c48-be1e-4b89-84af-4c78bd5fa63e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738549362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del
ays.2738549362
Directory /workspace/81.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_same_source.17291096
Short name T2532
Test name
Test status
Simulation time 388373827 ps
CPU time 14.64 seconds
Started Jul 14 07:41:41 PM PDT 24
Finished Jul 14 07:41:56 PM PDT 24
Peak memory 575268 kb
Host smart-a2dd2556-580d-46e2-9b56-248bd6942384
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17291096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.17291096
Directory /workspace/81.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke.3737892001
Short name T1905
Test name
Test status
Simulation time 53870030 ps
CPU time 7.09 seconds
Started Jul 14 07:41:33 PM PDT 24
Finished Jul 14 07:41:41 PM PDT 24
Peak memory 575316 kb
Host smart-0da39da5-2081-4e0e-95ae-c4607376b264
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737892001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.3737892001
Directory /workspace/81.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.2460074602
Short name T2049
Test name
Test status
Simulation time 7128945517 ps
CPU time 80.36 seconds
Started Jul 14 07:41:38 PM PDT 24
Finished Jul 14 07:42:58 PM PDT 24
Peak memory 575384 kb
Host smart-4398cfc6-874e-4983-b637-6ac157bd8ad5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460074602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.2460074602
Directory /workspace/81.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.1358922278
Short name T1403
Test name
Test status
Simulation time 5249643788 ps
CPU time 100.46 seconds
Started Jul 14 07:41:42 PM PDT 24
Finished Jul 14 07:43:23 PM PDT 24
Peak memory 574196 kb
Host smart-ad962a96-a627-4556-8770-e54143eeaeab
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358922278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.1358922278
Directory /workspace/81.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.3422317567
Short name T1577
Test name
Test status
Simulation time 36524852 ps
CPU time 5.9 seconds
Started Jul 14 07:41:35 PM PDT 24
Finished Jul 14 07:41:41 PM PDT 24
Peak memory 575244 kb
Host smart-642d275b-dfff-4e3c-9be0-94e167b80593
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422317567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay
s.3422317567
Directory /workspace/81.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all.1013149046
Short name T1791
Test name
Test status
Simulation time 695096122 ps
CPU time 32.02 seconds
Started Jul 14 07:41:48 PM PDT 24
Finished Jul 14 07:42:20 PM PDT 24
Peak memory 575456 kb
Host smart-779f600d-a2e9-4fe1-80a5-5314d47fd119
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013149046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.1013149046
Directory /workspace/81.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.2214690634
Short name T1524
Test name
Test status
Simulation time 10079460184 ps
CPU time 334.11 seconds
Started Jul 14 07:41:51 PM PDT 24
Finished Jul 14 07:47:26 PM PDT 24
Peak memory 575596 kb
Host smart-ea2e164c-53a8-4841-afb8-c1623add7f8f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214690634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.2214690634
Directory /workspace/81.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.480506618
Short name T527
Test name
Test status
Simulation time 2773073764 ps
CPU time 379.82 seconds
Started Jul 14 07:41:48 PM PDT 24
Finished Jul 14 07:48:09 PM PDT 24
Peak memory 575528 kb
Host smart-8b669f9c-a96b-47e7-bfa6-96a7172cd27b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480506618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_
with_rand_reset.480506618
Directory /workspace/81.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.2502797082
Short name T856
Test name
Test status
Simulation time 3662010185 ps
CPU time 396.68 seconds
Started Jul 14 07:41:48 PM PDT 24
Finished Jul 14 07:48:25 PM PDT 24
Peak memory 575520 kb
Host smart-8a771603-048e-44ed-be36-64ff233ca621
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502797082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al
l_with_reset_error.2502797082
Directory /workspace/81.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.1483441908
Short name T2826
Test name
Test status
Simulation time 1371901924 ps
CPU time 59.54 seconds
Started Jul 14 07:41:40 PM PDT 24
Finished Jul 14 07:42:40 PM PDT 24
Peak memory 575352 kb
Host smart-d2faae30-f4ef-49d5-b561-8e7d91d509de
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483441908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.1483441908
Directory /workspace/81.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_access_same_device.1476080397
Short name T1946
Test name
Test status
Simulation time 693795269 ps
CPU time 35.66 seconds
Started Jul 14 07:41:58 PM PDT 24
Finished Jul 14 07:42:34 PM PDT 24
Peak memory 575308 kb
Host smart-24647361-7ba8-47cf-97f1-f4314142590f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476080397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device
.1476080397
Directory /workspace/82.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.2372193519
Short name T2508
Test name
Test status
Simulation time 24041928814 ps
CPU time 441.73 seconds
Started Jul 14 07:41:55 PM PDT 24
Finished Jul 14 07:49:18 PM PDT 24
Peak memory 575512 kb
Host smart-7de766bd-f458-4430-9e9e-0eb8496ed06e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372193519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_
device_slow_rsp.2372193519
Directory /workspace/82.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.4117267227
Short name T2087
Test name
Test status
Simulation time 690199706 ps
CPU time 26.94 seconds
Started Jul 14 07:41:58 PM PDT 24
Finished Jul 14 07:42:25 PM PDT 24
Peak memory 575320 kb
Host smart-7ba2cd99-d880-425d-a39c-122504a122fa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117267227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add
r.4117267227
Directory /workspace/82.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_error_random.314791749
Short name T1896
Test name
Test status
Simulation time 293526793 ps
CPU time 23.97 seconds
Started Jul 14 07:41:55 PM PDT 24
Finished Jul 14 07:42:20 PM PDT 24
Peak memory 575328 kb
Host smart-91e05479-42d8-4ca8-87fd-838458550f2c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314791749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.314791749
Directory /workspace/82.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random.368844565
Short name T1956
Test name
Test status
Simulation time 353013666 ps
CPU time 30.54 seconds
Started Jul 14 07:41:48 PM PDT 24
Finished Jul 14 07:42:19 PM PDT 24
Peak memory 575336 kb
Host smart-8de6ab23-717a-4b04-b606-149e114c15d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368844565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.368844565
Directory /workspace/82.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.4210982415
Short name T2883
Test name
Test status
Simulation time 82738565332 ps
CPU time 980.82 seconds
Started Jul 14 07:41:49 PM PDT 24
Finished Jul 14 07:58:10 PM PDT 24
Peak memory 575656 kb
Host smart-d3a3590f-b1e7-4d73-8a7d-a572ea3b1f0e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210982415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.4210982415
Directory /workspace/82.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.2181766509
Short name T2779
Test name
Test status
Simulation time 7629906131 ps
CPU time 134.59 seconds
Started Jul 14 07:41:56 PM PDT 24
Finished Jul 14 07:44:12 PM PDT 24
Peak memory 575488 kb
Host smart-b9fbd53a-5a4b-45b6-be29-fba85450e4e2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181766509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.2181766509
Directory /workspace/82.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.1143058468
Short name T1812
Test name
Test status
Simulation time 627626472 ps
CPU time 56.27 seconds
Started Jul 14 07:41:48 PM PDT 24
Finished Jul 14 07:42:45 PM PDT 24
Peak memory 575352 kb
Host smart-b785d266-f225-445b-872e-115d9901cf21
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143058468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del
ays.1143058468
Directory /workspace/82.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_same_source.1069113545
Short name T535
Test name
Test status
Simulation time 2107035727 ps
CPU time 59.41 seconds
Started Jul 14 07:41:56 PM PDT 24
Finished Jul 14 07:42:56 PM PDT 24
Peak memory 575336 kb
Host smart-794d102d-d08d-483a-8c27-5ef4d1633443
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069113545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.1069113545
Directory /workspace/82.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke.3846791645
Short name T1835
Test name
Test status
Simulation time 202584401 ps
CPU time 9.26 seconds
Started Jul 14 07:41:50 PM PDT 24
Finished Jul 14 07:42:00 PM PDT 24
Peak memory 574024 kb
Host smart-220fe9cb-57ac-40cf-b047-1156eea1ae87
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846791645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.3846791645
Directory /workspace/82.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.2185493720
Short name T1499
Test name
Test status
Simulation time 4829443260 ps
CPU time 54.05 seconds
Started Jul 14 07:41:50 PM PDT 24
Finished Jul 14 07:42:44 PM PDT 24
Peak memory 574156 kb
Host smart-9fb6217c-923d-476d-bb00-f424d8924a9e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185493720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.2185493720
Directory /workspace/82.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.2027279354
Short name T1385
Test name
Test status
Simulation time 6107418187 ps
CPU time 110.95 seconds
Started Jul 14 07:41:49 PM PDT 24
Finished Jul 14 07:43:40 PM PDT 24
Peak memory 574156 kb
Host smart-e09c518f-26c1-4a41-a381-a19ad014f101
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027279354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.2027279354
Directory /workspace/82.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.2076312664
Short name T2189
Test name
Test status
Simulation time 48527427 ps
CPU time 5.91 seconds
Started Jul 14 07:41:49 PM PDT 24
Finished Jul 14 07:41:55 PM PDT 24
Peak memory 574032 kb
Host smart-5dc09534-d101-4051-a322-b011cc69fcee
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076312664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delay
s.2076312664
Directory /workspace/82.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all.418472781
Short name T1631
Test name
Test status
Simulation time 9679526271 ps
CPU time 398.12 seconds
Started Jul 14 07:41:55 PM PDT 24
Finished Jul 14 07:48:34 PM PDT 24
Peak memory 575548 kb
Host smart-609a2149-96cf-4889-b0db-108ba2c4e09b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418472781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.418472781
Directory /workspace/82.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.622062773
Short name T2217
Test name
Test status
Simulation time 3015587074 ps
CPU time 102.56 seconds
Started Jul 14 07:41:57 PM PDT 24
Finished Jul 14 07:43:40 PM PDT 24
Peak memory 575500 kb
Host smart-174179ca-ab45-4853-b714-dc6bc2f159c8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622062773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.622062773
Directory /workspace/82.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.3807251305
Short name T2183
Test name
Test status
Simulation time 3895345440 ps
CPU time 550.46 seconds
Started Jul 14 07:41:57 PM PDT 24
Finished Jul 14 07:51:08 PM PDT 24
Peak memory 575532 kb
Host smart-5332acdb-57c7-480d-b63c-60a7d9f00171
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807251305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all
_with_rand_reset.3807251305
Directory /workspace/82.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.1687767667
Short name T851
Test name
Test status
Simulation time 9955150368 ps
CPU time 417.11 seconds
Started Jul 14 07:41:56 PM PDT 24
Finished Jul 14 07:48:54 PM PDT 24
Peak memory 575584 kb
Host smart-bd562bc8-1407-43ee-85d5-8c1b4176bf42
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687767667 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al
l_with_reset_error.1687767667
Directory /workspace/82.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.2612421466
Short name T1853
Test name
Test status
Simulation time 140936641 ps
CPU time 20 seconds
Started Jul 14 07:41:55 PM PDT 24
Finished Jul 14 07:42:15 PM PDT 24
Peak memory 575344 kb
Host smart-3dd56bae-2242-4127-9936-3d06ada53b3d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612421466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.2612421466
Directory /workspace/82.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_access_same_device.1922173487
Short name T2334
Test name
Test status
Simulation time 156489047 ps
CPU time 11.68 seconds
Started Jul 14 07:42:03 PM PDT 24
Finished Jul 14 07:42:16 PM PDT 24
Peak memory 575292 kb
Host smart-5739c36b-481b-4317-9053-fae8de28d0a6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922173487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device
.1922173487
Directory /workspace/83.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.2615082792
Short name T2752
Test name
Test status
Simulation time 124961526071 ps
CPU time 2478.57 seconds
Started Jul 14 07:42:03 PM PDT 24
Finished Jul 14 08:23:22 PM PDT 24
Peak memory 575564 kb
Host smart-735a846e-e87f-4c4d-a8c3-9626df1294a9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615082792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_
device_slow_rsp.2615082792
Directory /workspace/83.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.391986784
Short name T1578
Test name
Test status
Simulation time 22703299 ps
CPU time 5.27 seconds
Started Jul 14 07:42:05 PM PDT 24
Finished Jul 14 07:42:11 PM PDT 24
Peak memory 573900 kb
Host smart-5baa7b34-81c9-4dc7-bd5e-6dca320e8129
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391986784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_addr
.391986784
Directory /workspace/83.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_error_random.3319857220
Short name T2028
Test name
Test status
Simulation time 2394419298 ps
CPU time 96.46 seconds
Started Jul 14 07:42:04 PM PDT 24
Finished Jul 14 07:43:42 PM PDT 24
Peak memory 575388 kb
Host smart-0349728b-bef8-4816-b288-e4b417a286ad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319857220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.3319857220
Directory /workspace/83.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random.2796244354
Short name T1847
Test name
Test status
Simulation time 1980976805 ps
CPU time 70.76 seconds
Started Jul 14 07:42:04 PM PDT 24
Finished Jul 14 07:43:16 PM PDT 24
Peak memory 575292 kb
Host smart-57149a73-d971-47ec-b3df-08aeca524f36
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796244354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.2796244354
Directory /workspace/83.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.1295870363
Short name T2248
Test name
Test status
Simulation time 67627067581 ps
CPU time 811.83 seconds
Started Jul 14 07:42:02 PM PDT 24
Finished Jul 14 07:55:34 PM PDT 24
Peak memory 575492 kb
Host smart-955ec1b6-6b2b-4ccc-adc8-e2e20e684e9c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295870363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.1295870363
Directory /workspace/83.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.1148052670
Short name T1583
Test name
Test status
Simulation time 26701944482 ps
CPU time 443.82 seconds
Started Jul 14 07:42:04 PM PDT 24
Finished Jul 14 07:49:28 PM PDT 24
Peak memory 575432 kb
Host smart-c1e925ad-362e-4a1d-b326-c560f84b21ff
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148052670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.1148052670
Directory /workspace/83.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.2074546126
Short name T2875
Test name
Test status
Simulation time 216980730 ps
CPU time 20.46 seconds
Started Jul 14 07:42:03 PM PDT 24
Finished Jul 14 07:42:25 PM PDT 24
Peak memory 575300 kb
Host smart-69e24f67-54b6-46ef-8eaa-81df225e9ff6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074546126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del
ays.2074546126
Directory /workspace/83.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_same_source.1069322493
Short name T2745
Test name
Test status
Simulation time 351657025 ps
CPU time 13.61 seconds
Started Jul 14 07:42:04 PM PDT 24
Finished Jul 14 07:42:19 PM PDT 24
Peak memory 575264 kb
Host smart-76985355-a6f1-4ffb-b348-440225a47607
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069322493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.1069322493
Directory /workspace/83.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke.4265275266
Short name T1332
Test name
Test status
Simulation time 39903854 ps
CPU time 6.27 seconds
Started Jul 14 07:41:56 PM PDT 24
Finished Jul 14 07:42:03 PM PDT 24
Peak memory 574024 kb
Host smart-36fa01f7-80bb-47b0-9220-75c99088699c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265275266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.4265275266
Directory /workspace/83.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.440807299
Short name T1402
Test name
Test status
Simulation time 6607817350 ps
CPU time 72.05 seconds
Started Jul 14 07:42:03 PM PDT 24
Finished Jul 14 07:43:16 PM PDT 24
Peak memory 575428 kb
Host smart-8d040d1d-57b9-4efc-9a45-6b1172cbaa5d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440807299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.440807299
Directory /workspace/83.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.717972618
Short name T2646
Test name
Test status
Simulation time 5253940861 ps
CPU time 90.16 seconds
Started Jul 14 07:42:08 PM PDT 24
Finished Jul 14 07:43:38 PM PDT 24
Peak memory 574168 kb
Host smart-d9c6e221-60c0-4932-98b1-063cd4f4f959
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717972618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.717972618
Directory /workspace/83.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.2679791703
Short name T1854
Test name
Test status
Simulation time 42203725 ps
CPU time 6.11 seconds
Started Jul 14 07:42:02 PM PDT 24
Finished Jul 14 07:42:09 PM PDT 24
Peak memory 574000 kb
Host smart-a1428946-d90f-4a74-b670-93c86b92f68b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679791703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay
s.2679791703
Directory /workspace/83.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all.1390978329
Short name T2735
Test name
Test status
Simulation time 3878512670 ps
CPU time 289.35 seconds
Started Jul 14 07:42:06 PM PDT 24
Finished Jul 14 07:46:56 PM PDT 24
Peak memory 575496 kb
Host smart-f801a0ce-8d13-4d25-bfbc-8808618fa9f9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390978329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.1390978329
Directory /workspace/83.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.3034293431
Short name T1423
Test name
Test status
Simulation time 4791323402 ps
CPU time 164.95 seconds
Started Jul 14 07:42:08 PM PDT 24
Finished Jul 14 07:44:53 PM PDT 24
Peak memory 575612 kb
Host smart-008c6413-b31b-4c8f-a672-856fba0ecd78
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034293431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.3034293431
Directory /workspace/83.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3097047385
Short name T632
Test name
Test status
Simulation time 207644793 ps
CPU time 62.68 seconds
Started Jul 14 07:42:03 PM PDT 24
Finished Jul 14 07:43:06 PM PDT 24
Peak memory 575448 kb
Host smart-28681a6f-7584-47b6-9cfc-205a729ef5cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097047385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all
_with_rand_reset.3097047385
Directory /workspace/83.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.293453596
Short name T1522
Test name
Test status
Simulation time 2727026227 ps
CPU time 191.09 seconds
Started Jul 14 07:42:03 PM PDT 24
Finished Jul 14 07:45:15 PM PDT 24
Peak memory 575264 kb
Host smart-27401c38-71c2-4ac8-9410-2ed3ebb18b4a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293453596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all
_with_reset_error.293453596
Directory /workspace/83.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.3787052340
Short name T2027
Test name
Test status
Simulation time 1414925342 ps
CPU time 62.46 seconds
Started Jul 14 07:42:03 PM PDT 24
Finished Jul 14 07:43:06 PM PDT 24
Peak memory 575388 kb
Host smart-b8142e37-8a61-46b2-822d-35af97f79b0c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787052340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.3787052340
Directory /workspace/83.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_access_same_device.3541762772
Short name T2698
Test name
Test status
Simulation time 1501038576 ps
CPU time 65.6 seconds
Started Jul 14 07:42:10 PM PDT 24
Finished Jul 14 07:43:16 PM PDT 24
Peak memory 575380 kb
Host smart-1aeeabc9-e4a6-4921-b3d8-c4e4ed8ee326
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541762772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device
.3541762772
Directory /workspace/84.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2170945187
Short name T2066
Test name
Test status
Simulation time 106549763002 ps
CPU time 1961.65 seconds
Started Jul 14 07:42:12 PM PDT 24
Finished Jul 14 08:14:55 PM PDT 24
Peak memory 575568 kb
Host smart-a57083a6-5e5c-4e52-af03-ae81fb9b633b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170945187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_
device_slow_rsp.2170945187
Directory /workspace/84.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.3605685659
Short name T2720
Test name
Test status
Simulation time 630844939 ps
CPU time 24.91 seconds
Started Jul 14 07:42:11 PM PDT 24
Finished Jul 14 07:42:36 PM PDT 24
Peak memory 575284 kb
Host smart-edf3b5bd-585a-44a8-8880-836ac0ca0002
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605685659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add
r.3605685659
Directory /workspace/84.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_error_random.1776972035
Short name T2332
Test name
Test status
Simulation time 1554558896 ps
CPU time 47.93 seconds
Started Jul 14 07:42:09 PM PDT 24
Finished Jul 14 07:42:58 PM PDT 24
Peak memory 575328 kb
Host smart-128447bb-dff5-4b8f-a01a-1bdd46b9a6bd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776972035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.1776972035
Directory /workspace/84.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random.1219882261
Short name T2604
Test name
Test status
Simulation time 331457991 ps
CPU time 30.63 seconds
Started Jul 14 07:42:09 PM PDT 24
Finished Jul 14 07:42:40 PM PDT 24
Peak memory 575364 kb
Host smart-c9517e01-7de1-4f04-b409-6fb0f90cb741
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219882261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.1219882261
Directory /workspace/84.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.1315592310
Short name T1664
Test name
Test status
Simulation time 103922873677 ps
CPU time 1208.93 seconds
Started Jul 14 07:42:10 PM PDT 24
Finished Jul 14 08:02:20 PM PDT 24
Peak memory 575468 kb
Host smart-d516a376-8e85-4b4a-bfad-04281431f361
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315592310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.1315592310
Directory /workspace/84.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.240275450
Short name T1898
Test name
Test status
Simulation time 16212473501 ps
CPU time 271.67 seconds
Started Jul 14 07:42:15 PM PDT 24
Finished Jul 14 07:46:47 PM PDT 24
Peak memory 575504 kb
Host smart-66ba3123-e5d6-44ff-ba0e-a643dab6108e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240275450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.240275450
Directory /workspace/84.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.300926999
Short name T586
Test name
Test status
Simulation time 624365886 ps
CPU time 47.48 seconds
Started Jul 14 07:42:11 PM PDT 24
Finished Jul 14 07:42:59 PM PDT 24
Peak memory 575300 kb
Host smart-192654d3-4f60-47e7-b05b-8f55dcbf15d9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300926999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_dela
ys.300926999
Directory /workspace/84.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_same_source.1923232907
Short name T1744
Test name
Test status
Simulation time 329994445 ps
CPU time 23.67 seconds
Started Jul 14 07:42:11 PM PDT 24
Finished Jul 14 07:42:35 PM PDT 24
Peak memory 575284 kb
Host smart-edd694d8-866b-4fc6-90f5-200bb3866fbb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923232907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.1923232907
Directory /workspace/84.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke.2003763578
Short name T1954
Test name
Test status
Simulation time 136339779 ps
CPU time 7.36 seconds
Started Jul 14 07:42:03 PM PDT 24
Finished Jul 14 07:42:12 PM PDT 24
Peak memory 575312 kb
Host smart-216f30e9-08a0-4bc6-ac5e-7e784a3dadf2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003763578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.2003763578
Directory /workspace/84.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.1556108432
Short name T2855
Test name
Test status
Simulation time 9345339030 ps
CPU time 100.58 seconds
Started Jul 14 07:42:04 PM PDT 24
Finished Jul 14 07:43:46 PM PDT 24
Peak memory 574204 kb
Host smart-77fdbae0-17c0-4932-9910-2a60a0e2d1df
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556108432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.1556108432
Directory /workspace/84.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.3989192937
Short name T615
Test name
Test status
Simulation time 4655805855 ps
CPU time 82.41 seconds
Started Jul 14 07:42:10 PM PDT 24
Finished Jul 14 07:43:33 PM PDT 24
Peak memory 574144 kb
Host smart-7701e979-a355-494e-b5c7-8e287ae9c99b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989192937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.3989192937
Directory /workspace/84.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.3669393596
Short name T1372
Test name
Test status
Simulation time 46146527 ps
CPU time 6.49 seconds
Started Jul 14 07:42:02 PM PDT 24
Finished Jul 14 07:42:09 PM PDT 24
Peak memory 574048 kb
Host smart-e98a62f1-f207-42ad-b466-06ab7337a064
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669393596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay
s.3669393596
Directory /workspace/84.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all.3346367397
Short name T1929
Test name
Test status
Simulation time 9442641544 ps
CPU time 428.26 seconds
Started Jul 14 07:42:10 PM PDT 24
Finished Jul 14 07:49:19 PM PDT 24
Peak memory 575544 kb
Host smart-a67de0db-b6c8-420a-ad31-3f5a0f7487c5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346367397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.3346367397
Directory /workspace/84.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.365503807
Short name T1581
Test name
Test status
Simulation time 1367508293 ps
CPU time 100.97 seconds
Started Jul 14 07:42:17 PM PDT 24
Finished Jul 14 07:43:59 PM PDT 24
Peak memory 575416 kb
Host smart-dbeb1eaa-715c-492b-ba8a-d48f45ba5aeb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365503807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.365503807
Directory /workspace/84.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.889981701
Short name T872
Test name
Test status
Simulation time 651648893 ps
CPU time 209.89 seconds
Started Jul 14 07:42:18 PM PDT 24
Finished Jul 14 07:45:49 PM PDT 24
Peak memory 575476 kb
Host smart-5f4824a0-c598-47b3-a196-33cd24cd049d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889981701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_
with_rand_reset.889981701
Directory /workspace/84.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.4250457395
Short name T2778
Test name
Test status
Simulation time 90670067 ps
CPU time 36.47 seconds
Started Jul 14 07:42:18 PM PDT 24
Finished Jul 14 07:42:55 PM PDT 24
Peak memory 575208 kb
Host smart-2f7f91ca-623d-47f8-8444-858c32a4df35
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250457395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al
l_with_reset_error.4250457395
Directory /workspace/84.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.1624787060
Short name T2495
Test name
Test status
Simulation time 302511211 ps
CPU time 33.68 seconds
Started Jul 14 07:42:11 PM PDT 24
Finished Jul 14 07:42:45 PM PDT 24
Peak memory 575440 kb
Host smart-d521d72a-080c-48b8-9ab5-9e477e8ed393
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624787060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.1624787060
Directory /workspace/84.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_access_same_device.2388123824
Short name T2214
Test name
Test status
Simulation time 1133158499 ps
CPU time 49.5 seconds
Started Jul 14 07:42:25 PM PDT 24
Finished Jul 14 07:43:15 PM PDT 24
Peak memory 575368 kb
Host smart-979dca6c-0a22-4157-aceb-79eddf22dd87
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388123824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device
.2388123824
Directory /workspace/85.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.2770946356
Short name T839
Test name
Test status
Simulation time 58329556913 ps
CPU time 1174.05 seconds
Started Jul 14 07:42:23 PM PDT 24
Finished Jul 14 08:01:58 PM PDT 24
Peak memory 575596 kb
Host smart-6380b873-f994-40bd-a7b8-974580dd55c6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770946356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_
device_slow_rsp.2770946356
Directory /workspace/85.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.3002746814
Short name T1880
Test name
Test status
Simulation time 1319874943 ps
CPU time 48.56 seconds
Started Jul 14 07:42:24 PM PDT 24
Finished Jul 14 07:43:13 PM PDT 24
Peak memory 575084 kb
Host smart-00193ad2-91f6-4fd3-8731-96ae50698254
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002746814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add
r.3002746814
Directory /workspace/85.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_error_random.1270533120
Short name T2158
Test name
Test status
Simulation time 2149126053 ps
CPU time 79.51 seconds
Started Jul 14 07:42:25 PM PDT 24
Finished Jul 14 07:43:45 PM PDT 24
Peak memory 575368 kb
Host smart-e608cbce-c946-409c-9780-f75780873332
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270533120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.1270533120
Directory /workspace/85.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random.162044116
Short name T2798
Test name
Test status
Simulation time 1020761447 ps
CPU time 35.22 seconds
Started Jul 14 07:42:23 PM PDT 24
Finished Jul 14 07:42:59 PM PDT 24
Peak memory 575300 kb
Host smart-69a2aec9-eea2-4922-aee0-6cacf7c3ee56
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162044116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.162044116
Directory /workspace/85.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.2173258821
Short name T569
Test name
Test status
Simulation time 57497732083 ps
CPU time 636.21 seconds
Started Jul 14 07:42:16 PM PDT 24
Finished Jul 14 07:52:53 PM PDT 24
Peak memory 575512 kb
Host smart-5034b377-b4d5-4a57-959a-9c675234a93e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173258821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.2173258821
Directory /workspace/85.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.4226279844
Short name T1851
Test name
Test status
Simulation time 57347793993 ps
CPU time 989.47 seconds
Started Jul 14 07:42:23 PM PDT 24
Finished Jul 14 07:58:54 PM PDT 24
Peak memory 575552 kb
Host smart-74c49822-4b82-4c36-8090-5f8488999992
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226279844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.4226279844
Directory /workspace/85.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.2860467808
Short name T2011
Test name
Test status
Simulation time 494011327 ps
CPU time 48.21 seconds
Started Jul 14 07:42:17 PM PDT 24
Finished Jul 14 07:43:05 PM PDT 24
Peak memory 575336 kb
Host smart-4c8bca23-a151-44ed-bfe2-e9869dbb2650
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860467808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del
ays.2860467808
Directory /workspace/85.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_same_source.3761663851
Short name T1881
Test name
Test status
Simulation time 2384362217 ps
CPU time 72.81 seconds
Started Jul 14 07:42:24 PM PDT 24
Finished Jul 14 07:43:37 PM PDT 24
Peak memory 575328 kb
Host smart-68ca56e6-62c0-4009-8cd3-37db5d643054
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761663851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.3761663851
Directory /workspace/85.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke.2763257696
Short name T2701
Test name
Test status
Simulation time 57119716 ps
CPU time 6.93 seconds
Started Jul 14 07:42:16 PM PDT 24
Finished Jul 14 07:42:23 PM PDT 24
Peak memory 574028 kb
Host smart-27bb8bbe-1d03-4769-b39b-25fb7d72c7d5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763257696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.2763257696
Directory /workspace/85.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.52458892
Short name T2797
Test name
Test status
Simulation time 9621750245 ps
CPU time 104.87 seconds
Started Jul 14 07:42:23 PM PDT 24
Finished Jul 14 07:44:09 PM PDT 24
Peak memory 574180 kb
Host smart-ac3a0b1f-b971-4650-9ec6-2b85b3e8baa9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52458892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.52458892
Directory /workspace/85.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.2760992231
Short name T2823
Test name
Test status
Simulation time 5869335129 ps
CPU time 96.41 seconds
Started Jul 14 07:42:16 PM PDT 24
Finished Jul 14 07:43:53 PM PDT 24
Peak memory 574152 kb
Host smart-95339af8-d9ff-4e10-b0f5-131f223dbf91
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760992231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.2760992231
Directory /workspace/85.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.3579493011
Short name T2154
Test name
Test status
Simulation time 56551755 ps
CPU time 7.01 seconds
Started Jul 14 07:42:18 PM PDT 24
Finished Jul 14 07:42:26 PM PDT 24
Peak memory 574000 kb
Host smart-c83e0ace-c089-4dfd-aa7a-34b3de2e945a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579493011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay
s.3579493011
Directory /workspace/85.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all.2600800971
Short name T2856
Test name
Test status
Simulation time 2256785505 ps
CPU time 176.03 seconds
Started Jul 14 07:42:25 PM PDT 24
Finished Jul 14 07:45:21 PM PDT 24
Peak memory 575556 kb
Host smart-cf70af70-6a8e-4acd-8ffe-dd31f585bade
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600800971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.2600800971
Directory /workspace/85.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.3317010568
Short name T2397
Test name
Test status
Simulation time 3761449468 ps
CPU time 139.44 seconds
Started Jul 14 07:42:23 PM PDT 24
Finished Jul 14 07:44:43 PM PDT 24
Peak memory 575532 kb
Host smart-e6791304-d72e-4487-8534-9f7350bc9a18
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317010568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.3317010568
Directory /workspace/85.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.1336565615
Short name T859
Test name
Test status
Simulation time 748221143 ps
CPU time 152.08 seconds
Started Jul 14 07:42:23 PM PDT 24
Finished Jul 14 07:44:56 PM PDT 24
Peak memory 575352 kb
Host smart-1ad60795-0d53-45fb-b3ac-dabdbe40c759
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336565615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all
_with_rand_reset.1336565615
Directory /workspace/85.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.2536830856
Short name T855
Test name
Test status
Simulation time 2335555040 ps
CPU time 209.9 seconds
Started Jul 14 07:42:21 PM PDT 24
Finished Jul 14 07:45:51 PM PDT 24
Peak memory 575552 kb
Host smart-56728230-85ca-4645-87d8-29cb0430c665
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536830856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al
l_with_reset_error.2536830856
Directory /workspace/85.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.380608381
Short name T2047
Test name
Test status
Simulation time 378168569 ps
CPU time 16.56 seconds
Started Jul 14 07:42:25 PM PDT 24
Finished Jul 14 07:42:42 PM PDT 24
Peak memory 575368 kb
Host smart-dfdc17b4-743e-4310-a865-0891d962687f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380608381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.380608381
Directory /workspace/85.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_access_same_device.3182900422
Short name T824
Test name
Test status
Simulation time 3121114618 ps
CPU time 131.85 seconds
Started Jul 14 07:42:32 PM PDT 24
Finished Jul 14 07:44:44 PM PDT 24
Peak memory 575416 kb
Host smart-05e7bdfa-b90d-4340-8bb8-1a4eb6f0505d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182900422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device
.3182900422
Directory /workspace/86.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.4181418228
Short name T2024
Test name
Test status
Simulation time 318358606 ps
CPU time 31.41 seconds
Started Jul 14 07:42:30 PM PDT 24
Finished Jul 14 07:43:02 PM PDT 24
Peak memory 575332 kb
Host smart-549b9015-5a2f-457b-b6fc-bf7508d6dae0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181418228 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add
r.4181418228
Directory /workspace/86.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_error_random.1661175586
Short name T2694
Test name
Test status
Simulation time 327796269 ps
CPU time 25.66 seconds
Started Jul 14 07:42:31 PM PDT 24
Finished Jul 14 07:42:57 PM PDT 24
Peak memory 575264 kb
Host smart-bf105be0-ef51-4b06-b9af-8f95717b4bf3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661175586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.1661175586
Directory /workspace/86.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random.581617896
Short name T2620
Test name
Test status
Simulation time 39725875 ps
CPU time 6.44 seconds
Started Jul 14 07:42:30 PM PDT 24
Finished Jul 14 07:42:37 PM PDT 24
Peak memory 574036 kb
Host smart-c01eb2a0-9e03-4002-8c1e-624cb5ac30bc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581617896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.581617896
Directory /workspace/86.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.727258730
Short name T2651
Test name
Test status
Simulation time 39747961863 ps
CPU time 461.66 seconds
Started Jul 14 07:42:30 PM PDT 24
Finished Jul 14 07:50:12 PM PDT 24
Peak memory 575488 kb
Host smart-8cf9b9bc-8b9b-4611-b088-c84a6798d405
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727258730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.727258730
Directory /workspace/86.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.437776786
Short name T516
Test name
Test status
Simulation time 41782493177 ps
CPU time 834.97 seconds
Started Jul 14 07:42:31 PM PDT 24
Finished Jul 14 07:56:27 PM PDT 24
Peak memory 575548 kb
Host smart-d8b2154d-92fa-46cb-8ca1-57eec3ab16a8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437776786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.437776786
Directory /workspace/86.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.1397066185
Short name T2656
Test name
Test status
Simulation time 254924493 ps
CPU time 21.04 seconds
Started Jul 14 07:42:31 PM PDT 24
Finished Jul 14 07:42:53 PM PDT 24
Peak memory 575308 kb
Host smart-1af5b75b-9d8e-40b6-9473-bd6e33faae59
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397066185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del
ays.1397066185
Directory /workspace/86.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_same_source.3347438345
Short name T2030
Test name
Test status
Simulation time 207091689 ps
CPU time 9.1 seconds
Started Jul 14 07:42:33 PM PDT 24
Finished Jul 14 07:42:43 PM PDT 24
Peak memory 574056 kb
Host smart-55645ac3-61c8-4a20-a03d-e5ac44e096df
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347438345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.3347438345
Directory /workspace/86.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke.1700813096
Short name T1483
Test name
Test status
Simulation time 39728151 ps
CPU time 6.39 seconds
Started Jul 14 07:42:23 PM PDT 24
Finished Jul 14 07:42:30 PM PDT 24
Peak memory 574028 kb
Host smart-dd6173b4-75dd-411f-bcfa-d0ccc7b7cb66
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700813096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.1700813096
Directory /workspace/86.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.2691765271
Short name T248
Test name
Test status
Simulation time 8330144454 ps
CPU time 83.07 seconds
Started Jul 14 07:42:24 PM PDT 24
Finished Jul 14 07:43:48 PM PDT 24
Peak memory 574152 kb
Host smart-ef36265d-0a7e-46f9-9600-4dbbb7a5bec8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691765271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.2691765271
Directory /workspace/86.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.2534939613
Short name T1529
Test name
Test status
Simulation time 3438642659 ps
CPU time 62.86 seconds
Started Jul 14 07:42:31 PM PDT 24
Finished Jul 14 07:43:35 PM PDT 24
Peak memory 575304 kb
Host smart-a15dc61e-4f7f-4cfc-b232-07aa2f14e407
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534939613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.2534939613
Directory /workspace/86.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.4114576714
Short name T2519
Test name
Test status
Simulation time 52241270 ps
CPU time 6.57 seconds
Started Jul 14 07:42:23 PM PDT 24
Finished Jul 14 07:42:30 PM PDT 24
Peak memory 574044 kb
Host smart-f24ce6c2-91b1-4dc2-9a22-5d73ba114db8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114576714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay
s.4114576714
Directory /workspace/86.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all.1464980740
Short name T505
Test name
Test status
Simulation time 2185544897 ps
CPU time 191.01 seconds
Started Jul 14 07:42:33 PM PDT 24
Finished Jul 14 07:45:44 PM PDT 24
Peak memory 575516 kb
Host smart-4ed16d0c-e654-459a-bb9e-394c8989ccba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464980740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.1464980740
Directory /workspace/86.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.3012811786
Short name T2900
Test name
Test status
Simulation time 12873399604 ps
CPU time 521.81 seconds
Started Jul 14 07:42:31 PM PDT 24
Finished Jul 14 07:51:14 PM PDT 24
Peak memory 575600 kb
Host smart-d915c2a3-b202-4a95-9946-f1230330e783
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012811786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.3012811786
Directory /workspace/86.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.965326842
Short name T1501
Test name
Test status
Simulation time 96231868 ps
CPU time 51.38 seconds
Started Jul 14 07:42:33 PM PDT 24
Finished Jul 14 07:43:25 PM PDT 24
Peak memory 575468 kb
Host smart-d4be92ae-f87e-4dd9-81c9-a450d4e7b2ad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965326842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_
with_rand_reset.965326842
Directory /workspace/86.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.4067703995
Short name T2125
Test name
Test status
Simulation time 2963168093 ps
CPU time 322.81 seconds
Started Jul 14 07:42:30 PM PDT 24
Finished Jul 14 07:47:53 PM PDT 24
Peak memory 575252 kb
Host smart-98662d53-54d4-49ec-8919-bb2f9e17f151
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067703995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al
l_with_reset_error.4067703995
Directory /workspace/86.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.1995365680
Short name T1909
Test name
Test status
Simulation time 264169333 ps
CPU time 30.28 seconds
Started Jul 14 07:42:32 PM PDT 24
Finished Jul 14 07:43:03 PM PDT 24
Peak memory 575412 kb
Host smart-b484d072-56f7-4e3d-8c77-1a6b3337590e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995365680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.1995365680
Directory /workspace/86.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_access_same_device.2794552614
Short name T1890
Test name
Test status
Simulation time 934069436 ps
CPU time 59.82 seconds
Started Jul 14 07:42:39 PM PDT 24
Finished Jul 14 07:43:40 PM PDT 24
Peak memory 575336 kb
Host smart-4d67256d-4d5d-47de-8a38-0b0daa2b1124
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794552614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device
.2794552614
Directory /workspace/87.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.1364860023
Short name T2713
Test name
Test status
Simulation time 124621619967 ps
CPU time 2406.92 seconds
Started Jul 14 07:42:43 PM PDT 24
Finished Jul 14 08:22:51 PM PDT 24
Peak memory 575604 kb
Host smart-5f1549fd-dcb4-499a-a5b9-2a62c0446df2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364860023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_
device_slow_rsp.1364860023
Directory /workspace/87.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.22995093
Short name T683
Test name
Test status
Simulation time 77932451 ps
CPU time 6.67 seconds
Started Jul 14 07:42:37 PM PDT 24
Finished Jul 14 07:42:44 PM PDT 24
Peak memory 573992 kb
Host smart-adb83c71-2dd4-4c7f-9071-69c8b53ca561
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22995093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_addr.22995093
Directory /workspace/87.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_error_random.2973251069
Short name T2640
Test name
Test status
Simulation time 249162314 ps
CPU time 11.37 seconds
Started Jul 14 07:42:39 PM PDT 24
Finished Jul 14 07:42:51 PM PDT 24
Peak memory 575296 kb
Host smart-967ee71c-8933-499a-8a68-7ad151ea4092
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973251069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.2973251069
Directory /workspace/87.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random.522914385
Short name T662
Test name
Test status
Simulation time 535043960 ps
CPU time 42.73 seconds
Started Jul 14 07:42:30 PM PDT 24
Finished Jul 14 07:43:13 PM PDT 24
Peak memory 575384 kb
Host smart-a383aa15-95ae-49b7-8b86-b19d9fbe583b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522914385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.522914385
Directory /workspace/87.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.4053489900
Short name T2377
Test name
Test status
Simulation time 54610291008 ps
CPU time 665.29 seconds
Started Jul 14 07:42:37 PM PDT 24
Finished Jul 14 07:53:43 PM PDT 24
Peak memory 575424 kb
Host smart-3ac4a264-245a-4b52-b7fe-c6bc09271cd2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053489900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.4053489900
Directory /workspace/87.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.2067288736
Short name T1610
Test name
Test status
Simulation time 7651052545 ps
CPU time 137.91 seconds
Started Jul 14 07:42:38 PM PDT 24
Finished Jul 14 07:44:56 PM PDT 24
Peak memory 575480 kb
Host smart-8d7a4af8-b993-4cf0-9fb5-412d5b62387d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067288736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.2067288736
Directory /workspace/87.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.4194074823
Short name T2553
Test name
Test status
Simulation time 531024549 ps
CPU time 44.79 seconds
Started Jul 14 07:42:30 PM PDT 24
Finished Jul 14 07:43:15 PM PDT 24
Peak memory 575344 kb
Host smart-439dbf87-0ef5-4a86-9267-6d85cc96f09c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194074823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del
ays.4194074823
Directory /workspace/87.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_same_source.3548667271
Short name T1713
Test name
Test status
Simulation time 1983091158 ps
CPU time 60.12 seconds
Started Jul 14 07:42:36 PM PDT 24
Finished Jul 14 07:43:37 PM PDT 24
Peak memory 575340 kb
Host smart-a151ffad-a5c7-4f4b-81f4-e3049a3de96f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548667271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.3548667271
Directory /workspace/87.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke.2473174031
Short name T2621
Test name
Test status
Simulation time 237742981 ps
CPU time 9.86 seconds
Started Jul 14 07:42:31 PM PDT 24
Finished Jul 14 07:42:42 PM PDT 24
Peak memory 574044 kb
Host smart-b7b9ac1b-5c27-4125-bf99-e2f0b5ef2385
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473174031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.2473174031
Directory /workspace/87.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.1488736474
Short name T2312
Test name
Test status
Simulation time 7267689859 ps
CPU time 82.26 seconds
Started Jul 14 07:42:30 PM PDT 24
Finished Jul 14 07:43:53 PM PDT 24
Peak memory 574160 kb
Host smart-fc218bb1-6884-4dbd-a6f3-1d9d68d4f79a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488736474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.1488736474
Directory /workspace/87.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.204601153
Short name T1684
Test name
Test status
Simulation time 5242357816 ps
CPU time 98.47 seconds
Started Jul 14 07:42:32 PM PDT 24
Finished Jul 14 07:44:11 PM PDT 24
Peak memory 575408 kb
Host smart-25e9c4bc-38d8-45c4-af8a-1d9de98b7a69
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204601153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.204601153
Directory /workspace/87.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.3778481110
Short name T1790
Test name
Test status
Simulation time 42229883 ps
CPU time 5.78 seconds
Started Jul 14 07:42:34 PM PDT 24
Finished Jul 14 07:42:40 PM PDT 24
Peak memory 575260 kb
Host smart-817806b7-97fe-4f2e-9db7-8b1f365ed05d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778481110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay
s.3778481110
Directory /workspace/87.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all.2576489506
Short name T2112
Test name
Test status
Simulation time 12352232584 ps
CPU time 483.87 seconds
Started Jul 14 07:42:36 PM PDT 24
Finished Jul 14 07:50:41 PM PDT 24
Peak memory 575612 kb
Host smart-bacac710-8775-464d-b442-d1e388940c30
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576489506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.2576489506
Directory /workspace/87.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.1987389222
Short name T2305
Test name
Test status
Simulation time 1989157677 ps
CPU time 71.03 seconds
Started Jul 14 07:42:37 PM PDT 24
Finished Jul 14 07:43:49 PM PDT 24
Peak memory 575412 kb
Host smart-bd4effd2-6f19-48ee-aba7-5947dcdccd3d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987389222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.1987389222
Directory /workspace/87.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.3891228308
Short name T2872
Test name
Test status
Simulation time 1560984259 ps
CPU time 180.24 seconds
Started Jul 14 07:42:38 PM PDT 24
Finished Jul 14 07:45:39 PM PDT 24
Peak memory 575428 kb
Host smart-1cad8abf-8625-42b5-8af4-7e546d59d24f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891228308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all
_with_rand_reset.3891228308
Directory /workspace/87.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3420453795
Short name T2796
Test name
Test status
Simulation time 356187949 ps
CPU time 58.42 seconds
Started Jul 14 07:42:38 PM PDT 24
Finished Jul 14 07:43:37 PM PDT 24
Peak memory 575484 kb
Host smart-c7186a6e-f141-4b37-8cb9-8c90201fbde8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420453795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al
l_with_reset_error.3420453795
Directory /workspace/87.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.940777294
Short name T2427
Test name
Test status
Simulation time 1084459237 ps
CPU time 49.36 seconds
Started Jul 14 07:42:39 PM PDT 24
Finished Jul 14 07:43:29 PM PDT 24
Peak memory 575340 kb
Host smart-c38545a4-5338-4842-899d-87e181f86dd1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940777294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.940777294
Directory /workspace/87.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_access_same_device.3140989921
Short name T2891
Test name
Test status
Simulation time 2888344574 ps
CPU time 115.88 seconds
Started Jul 14 07:42:44 PM PDT 24
Finished Jul 14 07:44:41 PM PDT 24
Peak memory 575444 kb
Host smart-e7b882cc-5ceb-44cb-935e-4b57b0acbdc9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140989921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device
.3140989921
Directory /workspace/88.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.4251449636
Short name T1520
Test name
Test status
Simulation time 122480495574 ps
CPU time 2322.44 seconds
Started Jul 14 07:42:43 PM PDT 24
Finished Jul 14 08:21:27 PM PDT 24
Peak memory 575432 kb
Host smart-029d9d0e-8a22-4870-949c-4da13f4feec5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251449636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_
device_slow_rsp.4251449636
Directory /workspace/88.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.3963088090
Short name T2266
Test name
Test status
Simulation time 329366686 ps
CPU time 32.84 seconds
Started Jul 14 07:42:44 PM PDT 24
Finished Jul 14 07:43:18 PM PDT 24
Peak memory 575300 kb
Host smart-2c7a59b1-913d-4591-9098-dfe8f10f0bcc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963088090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add
r.3963088090
Directory /workspace/88.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_error_random.1475232103
Short name T2074
Test name
Test status
Simulation time 2172233259 ps
CPU time 68.21 seconds
Started Jul 14 07:42:45 PM PDT 24
Finished Jul 14 07:43:54 PM PDT 24
Peak memory 575364 kb
Host smart-23a14af1-d407-41a8-ab2b-c1f99bb79f53
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475232103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.1475232103
Directory /workspace/88.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random.3454754030
Short name T2718
Test name
Test status
Simulation time 36395772 ps
CPU time 6.26 seconds
Started Jul 14 07:42:43 PM PDT 24
Finished Jul 14 07:42:51 PM PDT 24
Peak memory 574084 kb
Host smart-037daca1-df6c-4127-b5f2-cfab3eadf18b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454754030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.3454754030
Directory /workspace/88.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.2678663489
Short name T2297
Test name
Test status
Simulation time 35308452208 ps
CPU time 407.26 seconds
Started Jul 14 07:42:45 PM PDT 24
Finished Jul 14 07:49:33 PM PDT 24
Peak memory 575520 kb
Host smart-d24be3c5-49b2-47de-88b4-c6d60be4501e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678663489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.2678663489
Directory /workspace/88.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.4053770326
Short name T1921
Test name
Test status
Simulation time 66951671216 ps
CPU time 1265.96 seconds
Started Jul 14 07:42:43 PM PDT 24
Finished Jul 14 08:03:50 PM PDT 24
Peak memory 575460 kb
Host smart-1087c8ea-b80a-4913-99e6-3bb746e7295b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053770326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.4053770326
Directory /workspace/88.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.2862138935
Short name T1857
Test name
Test status
Simulation time 372823501 ps
CPU time 31.29 seconds
Started Jul 14 07:42:40 PM PDT 24
Finished Jul 14 07:43:11 PM PDT 24
Peak memory 575308 kb
Host smart-06cf483f-1f48-4530-8247-6c5fdf90a47c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862138935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del
ays.2862138935
Directory /workspace/88.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_same_source.1060158394
Short name T2599
Test name
Test status
Simulation time 236945874 ps
CPU time 20.62 seconds
Started Jul 14 07:42:48 PM PDT 24
Finished Jul 14 07:43:09 PM PDT 24
Peak memory 575324 kb
Host smart-241879ac-0311-4bc2-9b03-0dbf7c1f59ea
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060158394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.1060158394
Directory /workspace/88.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke.2467976360
Short name T2020
Test name
Test status
Simulation time 50560989 ps
CPU time 6.29 seconds
Started Jul 14 07:42:37 PM PDT 24
Finished Jul 14 07:42:44 PM PDT 24
Peak memory 575212 kb
Host smart-024a8cac-8d5e-4caf-b664-ea20aa7ffac0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467976360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.2467976360
Directory /workspace/88.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.1184771087
Short name T2181
Test name
Test status
Simulation time 7965344871 ps
CPU time 84.87 seconds
Started Jul 14 07:42:39 PM PDT 24
Finished Jul 14 07:44:04 PM PDT 24
Peak memory 574172 kb
Host smart-65062c38-a86a-45c2-b752-8e8dc8456b04
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184771087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.1184771087
Directory /workspace/88.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.3133555819
Short name T1757
Test name
Test status
Simulation time 5312470708 ps
CPU time 91.12 seconds
Started Jul 14 07:42:36 PM PDT 24
Finished Jul 14 07:44:08 PM PDT 24
Peak memory 574188 kb
Host smart-57b45df5-026a-402d-b8d3-32f34e8dc896
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133555819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.3133555819
Directory /workspace/88.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.3545752717
Short name T1394
Test name
Test status
Simulation time 52495534 ps
CPU time 6.46 seconds
Started Jul 14 07:42:43 PM PDT 24
Finished Jul 14 07:42:51 PM PDT 24
Peak memory 575316 kb
Host smart-b8bcbab7-09af-4529-b442-83b9159e719a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545752717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay
s.3545752717
Directory /workspace/88.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all.3067359094
Short name T502
Test name
Test status
Simulation time 4344543105 ps
CPU time 350.8 seconds
Started Jul 14 07:42:45 PM PDT 24
Finished Jul 14 07:48:37 PM PDT 24
Peak memory 575612 kb
Host smart-d1caee36-e0b7-4596-8c9a-e14b86d06376
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067359094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.3067359094
Directory /workspace/88.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.100746354
Short name T2420
Test name
Test status
Simulation time 1836836637 ps
CPU time 144.21 seconds
Started Jul 14 07:42:45 PM PDT 24
Finished Jul 14 07:45:10 PM PDT 24
Peak memory 575492 kb
Host smart-950f915e-2dc6-4610-96cb-e30ca6021eba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100746354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.100746354
Directory /workspace/88.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.3025107597
Short name T2678
Test name
Test status
Simulation time 729714103 ps
CPU time 351.1 seconds
Started Jul 14 07:42:45 PM PDT 24
Finished Jul 14 07:48:37 PM PDT 24
Peak memory 575452 kb
Host smart-74383262-7aaf-4805-aef3-e0114da4640a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025107597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all
_with_rand_reset.3025107597
Directory /workspace/88.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.1983602437
Short name T689
Test name
Test status
Simulation time 3979088535 ps
CPU time 491.46 seconds
Started Jul 14 07:42:47 PM PDT 24
Finished Jul 14 07:50:58 PM PDT 24
Peak memory 575272 kb
Host smart-fb67fedc-a6b6-40c0-adf0-9fda4302db2a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983602437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al
l_with_reset_error.1983602437
Directory /workspace/88.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.2503541948
Short name T2726
Test name
Test status
Simulation time 240400173 ps
CPU time 28.6 seconds
Started Jul 14 07:42:45 PM PDT 24
Finished Jul 14 07:43:14 PM PDT 24
Peak memory 575416 kb
Host smart-0c5e19f5-15c7-4269-bd26-e7807e6a107c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503541948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.2503541948
Directory /workspace/88.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.1838791383
Short name T2865
Test name
Test status
Simulation time 15422281947 ps
CPU time 249.05 seconds
Started Jul 14 07:42:52 PM PDT 24
Finished Jul 14 07:47:01 PM PDT 24
Peak memory 575404 kb
Host smart-7115b545-74cd-4087-8cdc-167ad2a33b09
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838791383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_
device_slow_rsp.1838791383
Directory /workspace/89.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.1088025103
Short name T2675
Test name
Test status
Simulation time 284890276 ps
CPU time 30.21 seconds
Started Jul 14 07:42:52 PM PDT 24
Finished Jul 14 07:43:23 PM PDT 24
Peak memory 575308 kb
Host smart-5557a7e1-e4f2-4459-aa27-99ea8db90830
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088025103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add
r.1088025103
Directory /workspace/89.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_error_random.3847869632
Short name T2216
Test name
Test status
Simulation time 489448951 ps
CPU time 34.79 seconds
Started Jul 14 07:42:51 PM PDT 24
Finished Jul 14 07:43:26 PM PDT 24
Peak memory 575296 kb
Host smart-ea5af4dc-b15b-4244-b423-f67545a48768
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847869632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.3847869632
Directory /workspace/89.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random.3283694081
Short name T2089
Test name
Test status
Simulation time 1807427959 ps
CPU time 71.3 seconds
Started Jul 14 07:42:53 PM PDT 24
Finished Jul 14 07:44:05 PM PDT 24
Peak memory 575264 kb
Host smart-dde2fc17-c56f-4443-931c-d47c31941820
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283694081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.3283694081
Directory /workspace/89.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.4719999
Short name T2605
Test name
Test status
Simulation time 18914051303 ps
CPU time 206.64 seconds
Started Jul 14 07:42:52 PM PDT 24
Finished Jul 14 07:46:19 PM PDT 24
Peak memory 575468 kb
Host smart-877a84cc-7a02-4a03-b459-e58942b3dad7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4719999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.4719999
Directory /workspace/89.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.3653837462
Short name T644
Test name
Test status
Simulation time 26850071353 ps
CPU time 461.74 seconds
Started Jul 14 07:42:52 PM PDT 24
Finished Jul 14 07:50:34 PM PDT 24
Peak memory 575488 kb
Host smart-6bfc9cc9-df44-4dc9-b63d-a98763a182ad
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653837462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.3653837462
Directory /workspace/89.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.253803988
Short name T1635
Test name
Test status
Simulation time 236140632 ps
CPU time 22.46 seconds
Started Jul 14 07:42:49 PM PDT 24
Finished Jul 14 07:43:12 PM PDT 24
Peak memory 575280 kb
Host smart-2fbf05a5-c8b6-44c0-9bf5-69816f166f0b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253803988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_dela
ys.253803988
Directory /workspace/89.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_same_source.2198862021
Short name T1630
Test name
Test status
Simulation time 1689909321 ps
CPU time 55.93 seconds
Started Jul 14 07:42:53 PM PDT 24
Finished Jul 14 07:43:49 PM PDT 24
Peak memory 575316 kb
Host smart-c506916a-e0fa-43a9-a48e-1e62a2e0bb02
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198862021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.2198862021
Directory /workspace/89.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke.1109547165
Short name T2732
Test name
Test status
Simulation time 33881916 ps
CPU time 5.47 seconds
Started Jul 14 07:42:45 PM PDT 24
Finished Jul 14 07:42:51 PM PDT 24
Peak memory 574084 kb
Host smart-933a6565-dafb-44d1-aa13-4b368e1fb3e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109547165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.1109547165
Directory /workspace/89.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.206485442
Short name T633
Test name
Test status
Simulation time 4535179863 ps
CPU time 49.12 seconds
Started Jul 14 07:42:50 PM PDT 24
Finished Jul 14 07:43:40 PM PDT 24
Peak memory 574168 kb
Host smart-483ea677-1bd1-4dca-9507-c45b5f08f1a7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206485442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.206485442
Directory /workspace/89.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.1548583937
Short name T1436
Test name
Test status
Simulation time 6660633899 ps
CPU time 120.55 seconds
Started Jul 14 07:42:52 PM PDT 24
Finished Jul 14 07:44:53 PM PDT 24
Peak memory 575408 kb
Host smart-84d2f343-6768-4b7d-a617-6f2d31734832
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548583937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.1548583937
Directory /workspace/89.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.2354648605
Short name T1531
Test name
Test status
Simulation time 42244079 ps
CPU time 5.98 seconds
Started Jul 14 07:42:51 PM PDT 24
Finished Jul 14 07:42:57 PM PDT 24
Peak memory 575308 kb
Host smart-c04ffcb7-634c-4b85-9d99-fc381088e538
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354648605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay
s.2354648605
Directory /workspace/89.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all.3092333742
Short name T531
Test name
Test status
Simulation time 9020519025 ps
CPU time 351.81 seconds
Started Jul 14 07:42:59 PM PDT 24
Finished Jul 14 07:48:52 PM PDT 24
Peak memory 575600 kb
Host smart-2c965925-f769-466c-8fe4-bd9b77313312
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092333742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.3092333742
Directory /workspace/89.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.4237653310
Short name T2859
Test name
Test status
Simulation time 10104314853 ps
CPU time 340.69 seconds
Started Jul 14 07:42:58 PM PDT 24
Finished Jul 14 07:48:40 PM PDT 24
Peak memory 575580 kb
Host smart-c2059a2b-d664-4207-a528-96f363f34f45
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237653310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.4237653310
Directory /workspace/89.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.2186193876
Short name T2776
Test name
Test status
Simulation time 498196235 ps
CPU time 155.97 seconds
Started Jul 14 07:42:59 PM PDT 24
Finished Jul 14 07:45:35 PM PDT 24
Peak memory 575484 kb
Host smart-7084ef33-eecd-4980-aa3c-678b95384f21
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186193876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all
_with_rand_reset.2186193876
Directory /workspace/89.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.979237204
Short name T2667
Test name
Test status
Simulation time 2413123458 ps
CPU time 101.02 seconds
Started Jul 14 07:42:55 PM PDT 24
Finished Jul 14 07:44:37 PM PDT 24
Peak memory 575556 kb
Host smart-c29174c2-5884-4a29-bfa9-ef5ceaa2bbb7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979237204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all
_with_reset_error.979237204
Directory /workspace/89.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.2518560568
Short name T1960
Test name
Test status
Simulation time 719063657 ps
CPU time 30.42 seconds
Started Jul 14 07:42:52 PM PDT 24
Finished Jul 14 07:43:23 PM PDT 24
Peak memory 575348 kb
Host smart-8dc17ea3-108d-4056-8143-64d4138a324b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518560568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.2518560568
Directory /workspace/89.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/9.chip_csr_rw.3822246831
Short name T2003
Test name
Test status
Simulation time 5613936906 ps
CPU time 534.32 seconds
Started Jul 14 07:29:20 PM PDT 24
Finished Jul 14 07:38:15 PM PDT 24
Peak memory 598908 kb
Host smart-923db062-f909-4870-9289-51319e4dc317
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822246831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.3822246831
Directory /workspace/9.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.966124041
Short name T2042
Test name
Test status
Simulation time 15388465873 ps
CPU time 2278.24 seconds
Started Jul 14 07:29:01 PM PDT 24
Finished Jul 14 08:07:00 PM PDT 24
Peak memory 593224 kb
Host smart-85ded03c-0eb5-495a-a58d-bea9fbef8d02
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966124041 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.chip_same_csr_outstanding.966124041
Directory /workspace/9.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.chip_tl_errors.4111486990
Short name T2232
Test name
Test status
Simulation time 3476467095 ps
CPU time 192.44 seconds
Started Jul 14 07:29:06 PM PDT 24
Finished Jul 14 07:32:19 PM PDT 24
Peak memory 603012 kb
Host smart-c8f6cd3f-7e2f-4306-b04b-e01f60f9089a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111486990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.4111486990
Directory /workspace/9.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_access_same_device.164682192
Short name T2574
Test name
Test status
Simulation time 654600326 ps
CPU time 58.96 seconds
Started Jul 14 07:29:12 PM PDT 24
Finished Jul 14 07:30:11 PM PDT 24
Peak memory 575332 kb
Host smart-d5477352-4e80-4835-8834-996f8719de26
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164682192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.164682192
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.3532417610
Short name T1767
Test name
Test status
Simulation time 87440035395 ps
CPU time 1671.74 seconds
Started Jul 14 07:29:11 PM PDT 24
Finished Jul 14 07:57:03 PM PDT 24
Peak memory 575512 kb
Host smart-22ab3d6c-6d60-4995-baee-017818abe065
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532417610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d
evice_slow_rsp.3532417610
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.3087885857
Short name T2331
Test name
Test status
Simulation time 1127684323 ps
CPU time 45.45 seconds
Started Jul 14 07:29:16 PM PDT 24
Finished Jul 14 07:30:02 PM PDT 24
Peak memory 575348 kb
Host smart-5296043d-f9e3-42cd-8f61-211aa726d89e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087885857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr
.3087885857
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_error_random.1474378841
Short name T1800
Test name
Test status
Simulation time 1946285256 ps
CPU time 70.36 seconds
Started Jul 14 07:29:15 PM PDT 24
Finished Jul 14 07:30:26 PM PDT 24
Peak memory 575308 kb
Host smart-57f05c14-4c3b-4984-99c4-77fd723a5af2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474378841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1474378841
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random.289039878
Short name T2488
Test name
Test status
Simulation time 376610306 ps
CPU time 15.66 seconds
Started Jul 14 07:29:12 PM PDT 24
Finished Jul 14 07:29:28 PM PDT 24
Peak memory 575356 kb
Host smart-6e307220-140e-4876-a03b-875024e8730d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289039878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.289039878
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.2322892537
Short name T2744
Test name
Test status
Simulation time 84300726454 ps
CPU time 925.68 seconds
Started Jul 14 07:29:11 PM PDT 24
Finished Jul 14 07:44:37 PM PDT 24
Peak memory 575536 kb
Host smart-d1fac8ce-60d6-4ed2-9634-a4e51f9b80db
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322892537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.2322892537
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.3541007294
Short name T1829
Test name
Test status
Simulation time 13093731894 ps
CPU time 237.11 seconds
Started Jul 14 07:29:16 PM PDT 24
Finished Jul 14 07:33:14 PM PDT 24
Peak memory 575452 kb
Host smart-bd6b333b-fa5f-4a19-97b0-3eff2ca8df6e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541007294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3541007294
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.3819463623
Short name T2650
Test name
Test status
Simulation time 343835522 ps
CPU time 33.89 seconds
Started Jul 14 07:29:14 PM PDT 24
Finished Jul 14 07:29:48 PM PDT 24
Peak memory 575268 kb
Host smart-0e79b689-5ae0-47d1-ad6b-3888f8db783b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819463623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela
ys.3819463623
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_same_source.4138214959
Short name T2821
Test name
Test status
Simulation time 806632627 ps
CPU time 27.97 seconds
Started Jul 14 07:29:14 PM PDT 24
Finished Jul 14 07:29:42 PM PDT 24
Peak memory 575264 kb
Host smart-ab3bea2c-e3ca-4261-80bb-7097d86e687b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138214959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.4138214959
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke.4202288827
Short name T1735
Test name
Test status
Simulation time 231651489 ps
CPU time 9.96 seconds
Started Jul 14 07:29:06 PM PDT 24
Finished Jul 14 07:29:16 PM PDT 24
Peak memory 574068 kb
Host smart-5e4e4f14-a1fe-4b89-a10c-7c80b9ae190f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202288827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.4202288827
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.2278562924
Short name T635
Test name
Test status
Simulation time 8512505696 ps
CPU time 90.19 seconds
Started Jul 14 07:29:06 PM PDT 24
Finished Jul 14 07:30:36 PM PDT 24
Peak memory 574104 kb
Host smart-fadaab6f-d7c4-4654-8b47-ce0a2597778e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278562924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2278562924
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.3235011840
Short name T1388
Test name
Test status
Simulation time 5333102171 ps
CPU time 90.08 seconds
Started Jul 14 07:29:13 PM PDT 24
Finished Jul 14 07:30:43 PM PDT 24
Peak memory 574168 kb
Host smart-09c6b663-681f-451c-8566-73a44e45c468
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235011840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3235011840
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.3877880984
Short name T2450
Test name
Test status
Simulation time 48603287 ps
CPU time 6.78 seconds
Started Jul 14 07:29:06 PM PDT 24
Finished Jul 14 07:29:13 PM PDT 24
Peak memory 574068 kb
Host smart-615dc77d-25e0-4971-9625-6c4cb0151e82
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877880984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays
.3877880984
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all.3175689391
Short name T596
Test name
Test status
Simulation time 5898781923 ps
CPU time 225.64 seconds
Started Jul 14 07:29:16 PM PDT 24
Finished Jul 14 07:33:02 PM PDT 24
Peak memory 575584 kb
Host smart-fdbd3bab-aaa6-4ce3-9429-150c437a6dd9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175689391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3175689391
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.3199223318
Short name T1607
Test name
Test status
Simulation time 3162595611 ps
CPU time 98.44 seconds
Started Jul 14 07:29:15 PM PDT 24
Finished Jul 14 07:30:54 PM PDT 24
Peak memory 575444 kb
Host smart-aa196c9e-615b-48f5-9ca5-7463eb6a7b7d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199223318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3199223318
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.3905891210
Short name T829
Test name
Test status
Simulation time 701464959 ps
CPU time 220.93 seconds
Started Jul 14 07:29:15 PM PDT 24
Finished Jul 14 07:32:57 PM PDT 24
Peak memory 575492 kb
Host smart-af314942-ab50-4e1a-b924-4148555c9466
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905891210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all
_with_reset_error.3905891210
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.3629418089
Short name T2668
Test name
Test status
Simulation time 296595786 ps
CPU time 36.88 seconds
Started Jul 14 07:29:16 PM PDT 24
Finished Jul 14 07:29:53 PM PDT 24
Peak memory 575368 kb
Host smart-1ef3ca75-1567-4775-8355-8e0ef4792aff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629418089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3629418089
Directory /workspace/9.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_access_same_device.324932120
Short name T1638
Test name
Test status
Simulation time 123170120 ps
CPU time 14.05 seconds
Started Jul 14 07:43:00 PM PDT 24
Finished Jul 14 07:43:14 PM PDT 24
Peak memory 575308 kb
Host smart-8cee6182-a93b-489c-aaf3-6135aa20ab9f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324932120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device.
324932120
Directory /workspace/90.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.291232920
Short name T1620
Test name
Test status
Simulation time 40405079679 ps
CPU time 771.39 seconds
Started Jul 14 07:42:56 PM PDT 24
Finished Jul 14 07:55:48 PM PDT 24
Peak memory 575456 kb
Host smart-4836e263-b557-4945-9e31-baf89e9709b7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291232920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_d
evice_slow_rsp.291232920
Directory /workspace/90.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.3300345738
Short name T2810
Test name
Test status
Simulation time 1282774550 ps
CPU time 49.53 seconds
Started Jul 14 07:42:58 PM PDT 24
Finished Jul 14 07:43:49 PM PDT 24
Peak memory 575304 kb
Host smart-bcf62a4f-6d34-4246-9f09-4c31f6e95e1b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300345738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add
r.3300345738
Directory /workspace/90.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_error_random.4062780498
Short name T1736
Test name
Test status
Simulation time 822029625 ps
CPU time 28.02 seconds
Started Jul 14 07:42:57 PM PDT 24
Finished Jul 14 07:43:25 PM PDT 24
Peak memory 575308 kb
Host smart-5a32cbab-60a1-498b-ab2d-9fc8fc21cc7e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062780498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.4062780498
Directory /workspace/90.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random.1994775263
Short name T2209
Test name
Test status
Simulation time 37580523 ps
CPU time 6.48 seconds
Started Jul 14 07:42:58 PM PDT 24
Finished Jul 14 07:43:05 PM PDT 24
Peak memory 574004 kb
Host smart-b6eab5c8-d6b3-4871-8399-ba78e0da913b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994775263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.1994775263
Directory /workspace/90.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.2618413254
Short name T1489
Test name
Test status
Simulation time 77589909379 ps
CPU time 1011.65 seconds
Started Jul 14 07:43:00 PM PDT 24
Finished Jul 14 07:59:52 PM PDT 24
Peak memory 575476 kb
Host smart-c2e2e291-c17d-4c9d-8cf6-b363ba358758
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618413254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.2618413254
Directory /workspace/90.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.308351281
Short name T1758
Test name
Test status
Simulation time 11302116206 ps
CPU time 213.27 seconds
Started Jul 14 07:42:57 PM PDT 24
Finished Jul 14 07:46:31 PM PDT 24
Peak memory 575520 kb
Host smart-aaa27ae8-e504-4be1-b778-19244402617e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308351281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.308351281
Directory /workspace/90.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.3951052568
Short name T1518
Test name
Test status
Simulation time 466630185 ps
CPU time 37.1 seconds
Started Jul 14 07:42:58 PM PDT 24
Finished Jul 14 07:43:35 PM PDT 24
Peak memory 575344 kb
Host smart-06959510-69b8-436d-8344-f74429c64b3a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951052568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del
ays.3951052568
Directory /workspace/90.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_same_source.2615376188
Short name T2364
Test name
Test status
Simulation time 143538183 ps
CPU time 13.4 seconds
Started Jul 14 07:42:57 PM PDT 24
Finished Jul 14 07:43:11 PM PDT 24
Peak memory 575304 kb
Host smart-56676868-700b-4a07-8caf-c053fbb806a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615376188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.2615376188
Directory /workspace/90.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke.1461001969
Short name T2234
Test name
Test status
Simulation time 216171845 ps
CPU time 8.86 seconds
Started Jul 14 07:42:57 PM PDT 24
Finished Jul 14 07:43:07 PM PDT 24
Peak memory 574048 kb
Host smart-47444e42-25b6-4631-8ed9-00f68b0ef02d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461001969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.1461001969
Directory /workspace/90.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.7668104
Short name T1838
Test name
Test status
Simulation time 8130591028 ps
CPU time 88.33 seconds
Started Jul 14 07:42:57 PM PDT 24
Finished Jul 14 07:44:26 PM PDT 24
Peak memory 574124 kb
Host smart-aebf6fb5-aa90-41fc-98d8-be5db9994ccd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7668104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.7668104
Directory /workspace/90.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.468714267
Short name T1479
Test name
Test status
Simulation time 6464170589 ps
CPU time 117.44 seconds
Started Jul 14 07:42:59 PM PDT 24
Finished Jul 14 07:44:57 PM PDT 24
Peak memory 574132 kb
Host smart-3723386a-a00d-4788-9c53-ff5c0cba3960
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468714267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.468714267
Directory /workspace/90.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.1712700783
Short name T601
Test name
Test status
Simulation time 43004365 ps
CPU time 6.35 seconds
Started Jul 14 07:42:57 PM PDT 24
Finished Jul 14 07:43:04 PM PDT 24
Peak memory 573976 kb
Host smart-04cde8da-df59-4d89-923e-36d9239e1d1d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712700783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay
s.1712700783
Directory /workspace/90.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all.2399530209
Short name T1810
Test name
Test status
Simulation time 9676808263 ps
CPU time 350.27 seconds
Started Jul 14 07:43:04 PM PDT 24
Finished Jul 14 07:48:55 PM PDT 24
Peak memory 575592 kb
Host smart-9b26ed22-51b8-4e09-9543-f0a00ea5dead
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399530209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.2399530209
Directory /workspace/90.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.2902088827
Short name T1447
Test name
Test status
Simulation time 7848023314 ps
CPU time 272.21 seconds
Started Jul 14 07:43:05 PM PDT 24
Finished Jul 14 07:47:38 PM PDT 24
Peak memory 575572 kb
Host smart-3bc817bb-9873-425b-b49e-cc93ae25d998
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902088827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.2902088827
Directory /workspace/90.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.794189469
Short name T2269
Test name
Test status
Simulation time 186909825 ps
CPU time 85.87 seconds
Started Jul 14 07:43:04 PM PDT 24
Finished Jul 14 07:44:30 PM PDT 24
Peak memory 575432 kb
Host smart-24c4185a-a91b-4f73-9c29-b6b319467de7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794189469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_
with_rand_reset.794189469
Directory /workspace/90.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.736046530
Short name T2571
Test name
Test status
Simulation time 117459484 ps
CPU time 73.41 seconds
Started Jul 14 07:43:04 PM PDT 24
Finished Jul 14 07:44:18 PM PDT 24
Peak memory 575192 kb
Host smart-d1790739-8118-4918-afc2-4f30184a2912
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736046530 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all
_with_reset_error.736046530
Directory /workspace/90.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.3550301915
Short name T652
Test name
Test status
Simulation time 107734203 ps
CPU time 11.99 seconds
Started Jul 14 07:42:56 PM PDT 24
Finished Jul 14 07:43:09 PM PDT 24
Peak memory 575456 kb
Host smart-6af0890c-b17b-4038-9276-2382b8150f88
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550301915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.3550301915
Directory /workspace/90.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_access_same_device.304052212
Short name T2120
Test name
Test status
Simulation time 165554087 ps
CPU time 16.46 seconds
Started Jul 14 07:43:08 PM PDT 24
Finished Jul 14 07:43:25 PM PDT 24
Peak memory 575396 kb
Host smart-6069b98f-35aa-4281-a280-d07f3faff086
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304052212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device.
304052212
Directory /workspace/91.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.869654266
Short name T2292
Test name
Test status
Simulation time 98380938219 ps
CPU time 2124.77 seconds
Started Jul 14 07:43:11 PM PDT 24
Finished Jul 14 08:18:36 PM PDT 24
Peak memory 575564 kb
Host smart-ec11b5da-d9c2-430f-aceb-1a10ee98199f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869654266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_d
evice_slow_rsp.869654266
Directory /workspace/91.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.1566934170
Short name T2780
Test name
Test status
Simulation time 59210147 ps
CPU time 5.83 seconds
Started Jul 14 07:43:10 PM PDT 24
Finished Jul 14 07:43:16 PM PDT 24
Peak memory 575288 kb
Host smart-200f76b3-f119-470d-a95f-b70cd81f0dcf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566934170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add
r.1566934170
Directory /workspace/91.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_error_random.1579957339
Short name T2555
Test name
Test status
Simulation time 187608261 ps
CPU time 15.54 seconds
Started Jul 14 07:43:11 PM PDT 24
Finished Jul 14 07:43:27 PM PDT 24
Peak memory 575336 kb
Host smart-9434a300-0de9-45fc-8539-da579f711f44
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579957339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.1579957339
Directory /workspace/91.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random.3123713048
Short name T2892
Test name
Test status
Simulation time 344276498 ps
CPU time 29.82 seconds
Started Jul 14 07:43:06 PM PDT 24
Finished Jul 14 07:43:36 PM PDT 24
Peak memory 575320 kb
Host smart-5044b932-dcd6-4104-b42a-e30c77a7645d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123713048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.3123713048
Directory /workspace/91.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.2752235749
Short name T1528
Test name
Test status
Simulation time 8730303295 ps
CPU time 104.2 seconds
Started Jul 14 07:43:06 PM PDT 24
Finished Jul 14 07:44:50 PM PDT 24
Peak memory 575416 kb
Host smart-3d7b5fba-d4ec-43ca-a979-950ffc1fc8b1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752235749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.2752235749
Directory /workspace/91.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.49473567
Short name T1740
Test name
Test status
Simulation time 13992927932 ps
CPU time 250.49 seconds
Started Jul 14 07:43:06 PM PDT 24
Finished Jul 14 07:47:17 PM PDT 24
Peak memory 575444 kb
Host smart-6e5b6a2f-cc8c-43c7-bbf7-59d164d3675a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49473567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.49473567
Directory /workspace/91.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.1946070162
Short name T2068
Test name
Test status
Simulation time 480644255 ps
CPU time 40.24 seconds
Started Jul 14 07:43:04 PM PDT 24
Finished Jul 14 07:43:45 PM PDT 24
Peak memory 575352 kb
Host smart-5cc7cb6e-1d0d-47e1-a440-8f568d4610dd
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946070162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del
ays.1946070162
Directory /workspace/91.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_same_source.1375981095
Short name T2476
Test name
Test status
Simulation time 945432954 ps
CPU time 27.86 seconds
Started Jul 14 07:43:11 PM PDT 24
Finished Jul 14 07:43:39 PM PDT 24
Peak memory 575336 kb
Host smart-86e6555d-aee6-43b3-87a0-59f4729e8948
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375981095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.1375981095
Directory /workspace/91.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke.161686064
Short name T2594
Test name
Test status
Simulation time 170118757 ps
CPU time 8.86 seconds
Started Jul 14 07:43:05 PM PDT 24
Finished Jul 14 07:43:14 PM PDT 24
Peak memory 573956 kb
Host smart-727aea9a-0ed0-42d3-81ea-3232285308cd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161686064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.161686064
Directory /workspace/91.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.1839462703
Short name T1934
Test name
Test status
Simulation time 9513431532 ps
CPU time 112.16 seconds
Started Jul 14 07:43:06 PM PDT 24
Finished Jul 14 07:44:59 PM PDT 24
Peak memory 574144 kb
Host smart-83200c71-0b20-440c-a1cf-4198fc9e3f4d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839462703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.1839462703
Directory /workspace/91.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.3357432993
Short name T2318
Test name
Test status
Simulation time 3906544391 ps
CPU time 69.02 seconds
Started Jul 14 07:43:03 PM PDT 24
Finished Jul 14 07:44:13 PM PDT 24
Peak memory 574108 kb
Host smart-89004021-10a3-489e-9ae6-ad6d1f528cb4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357432993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.3357432993
Directory /workspace/91.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.425885763
Short name T1924
Test name
Test status
Simulation time 58263645 ps
CPU time 7.1 seconds
Started Jul 14 07:43:06 PM PDT 24
Finished Jul 14 07:43:14 PM PDT 24
Peak memory 575296 kb
Host smart-75a2ac7c-787f-4631-af0f-9de698b6d01c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425885763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delays
.425885763
Directory /workspace/91.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all.3926101088
Short name T2293
Test name
Test status
Simulation time 11433935474 ps
CPU time 452.04 seconds
Started Jul 14 07:43:10 PM PDT 24
Finished Jul 14 07:50:44 PM PDT 24
Peak memory 575588 kb
Host smart-04fe45fa-4580-42d7-a0f4-8451e2da2c8d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926101088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.3926101088
Directory /workspace/91.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.3487731807
Short name T1491
Test name
Test status
Simulation time 974136937 ps
CPU time 69.72 seconds
Started Jul 14 07:43:09 PM PDT 24
Finished Jul 14 07:44:19 PM PDT 24
Peak memory 575324 kb
Host smart-08a234ba-7e91-402c-92f2-7e872d65b1f7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487731807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.3487731807
Directory /workspace/91.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.3774613417
Short name T1692
Test name
Test status
Simulation time 83113484 ps
CPU time 16 seconds
Started Jul 14 07:43:10 PM PDT 24
Finished Jul 14 07:43:26 PM PDT 24
Peak memory 574164 kb
Host smart-0fbc7636-158d-492b-9422-8c4ca91b2b63
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774613417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all
_with_rand_reset.3774613417
Directory /workspace/91.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.958998600
Short name T2010
Test name
Test status
Simulation time 539781107 ps
CPU time 142.1 seconds
Started Jul 14 07:43:10 PM PDT 24
Finished Jul 14 07:45:33 PM PDT 24
Peak memory 575180 kb
Host smart-4bee4269-2668-40d6-a746-f67938e5bed5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958998600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all
_with_reset_error.958998600
Directory /workspace/91.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.357757369
Short name T2846
Test name
Test status
Simulation time 804670862 ps
CPU time 35.36 seconds
Started Jul 14 07:43:11 PM PDT 24
Finished Jul 14 07:43:47 PM PDT 24
Peak memory 575444 kb
Host smart-2f3a52fb-19af-4df0-b483-6d2ce2ee99bc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357757369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.357757369
Directory /workspace/91.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_access_same_device.1306570764
Short name T830
Test name
Test status
Simulation time 1341333331 ps
CPU time 87.54 seconds
Started Jul 14 07:43:16 PM PDT 24
Finished Jul 14 07:44:44 PM PDT 24
Peak memory 575324 kb
Host smart-4317babb-00a8-447d-bcc0-8da8624c7e47
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306570764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device
.1306570764
Directory /workspace/92.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.1344909384
Short name T2631
Test name
Test status
Simulation time 175722979180 ps
CPU time 3086.8 seconds
Started Jul 14 07:43:18 PM PDT 24
Finished Jul 14 08:34:45 PM PDT 24
Peak memory 575456 kb
Host smart-f2c82630-114e-4a6a-9bd0-89c1b411efe3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344909384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_
device_slow_rsp.1344909384
Directory /workspace/92.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.3855109825
Short name T2507
Test name
Test status
Simulation time 194910007 ps
CPU time 20.84 seconds
Started Jul 14 07:43:24 PM PDT 24
Finished Jul 14 07:43:46 PM PDT 24
Peak memory 575340 kb
Host smart-8c52664f-a48d-4b2c-89ba-06e21407fcd3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855109825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add
r.3855109825
Directory /workspace/92.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_error_random.1710495933
Short name T2754
Test name
Test status
Simulation time 444951824 ps
CPU time 34.32 seconds
Started Jul 14 07:43:17 PM PDT 24
Finished Jul 14 07:43:52 PM PDT 24
Peak memory 575308 kb
Host smart-890bee27-634c-42f4-ae84-1d3c3c15f898
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710495933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.1710495933
Directory /workspace/92.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random.913606351
Short name T1732
Test name
Test status
Simulation time 2145358732 ps
CPU time 76.48 seconds
Started Jul 14 07:43:15 PM PDT 24
Finished Jul 14 07:44:32 PM PDT 24
Peak memory 575400 kb
Host smart-7c7f7364-20e0-4e88-a7fe-5912a26adcfd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913606351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.913606351
Directory /workspace/92.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.614322679
Short name T557
Test name
Test status
Simulation time 52544960140 ps
CPU time 592.34 seconds
Started Jul 14 07:43:17 PM PDT 24
Finished Jul 14 07:53:10 PM PDT 24
Peak memory 575496 kb
Host smart-f077338b-d0ba-4a00-9a34-11954e6dc482
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614322679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.614322679
Directory /workspace/92.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.3846790235
Short name T1416
Test name
Test status
Simulation time 12447473099 ps
CPU time 217.81 seconds
Started Jul 14 07:43:16 PM PDT 24
Finished Jul 14 07:46:55 PM PDT 24
Peak memory 575532 kb
Host smart-88ec2320-cc4e-46fb-8b9b-87a81b47bd2b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846790235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.3846790235
Directory /workspace/92.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.3123393182
Short name T2280
Test name
Test status
Simulation time 496033505 ps
CPU time 44.51 seconds
Started Jul 14 07:43:19 PM PDT 24
Finished Jul 14 07:44:04 PM PDT 24
Peak memory 575304 kb
Host smart-74881672-347a-4a1a-bd42-a902035a04fc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123393182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del
ays.3123393182
Directory /workspace/92.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_same_source.478769118
Short name T2770
Test name
Test status
Simulation time 2633454568 ps
CPU time 72.31 seconds
Started Jul 14 07:43:17 PM PDT 24
Finished Jul 14 07:44:30 PM PDT 24
Peak memory 575352 kb
Host smart-d8bda4cc-7934-4ed6-8327-2972f3c682aa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478769118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.478769118
Directory /workspace/92.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke.932357132
Short name T2528
Test name
Test status
Simulation time 141902219 ps
CPU time 7.64 seconds
Started Jul 14 07:43:11 PM PDT 24
Finished Jul 14 07:43:19 PM PDT 24
Peak memory 575316 kb
Host smart-ad9a8b87-3c13-456d-ac32-ce69db9d0257
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932357132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.932357132
Directory /workspace/92.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.342915535
Short name T1543
Test name
Test status
Simulation time 8257319963 ps
CPU time 96.24 seconds
Started Jul 14 07:43:16 PM PDT 24
Finished Jul 14 07:44:53 PM PDT 24
Peak memory 574136 kb
Host smart-21edc602-ce6a-443b-b309-575f01b49b88
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342915535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.342915535
Directory /workspace/92.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.2453676961
Short name T1559
Test name
Test status
Simulation time 5425674240 ps
CPU time 95.14 seconds
Started Jul 14 07:43:21 PM PDT 24
Finished Jul 14 07:44:57 PM PDT 24
Peak memory 574204 kb
Host smart-8172df29-c702-455a-a217-846091ec6302
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453676961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.2453676961
Directory /workspace/92.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.1114077929
Short name T1340
Test name
Test status
Simulation time 50418866 ps
CPU time 6.51 seconds
Started Jul 14 07:43:16 PM PDT 24
Finished Jul 14 07:43:23 PM PDT 24
Peak memory 574032 kb
Host smart-3a3e9582-3c17-439c-b98d-c82a49a6f76a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114077929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay
s.1114077929
Directory /workspace/92.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all.3064034592
Short name T1968
Test name
Test status
Simulation time 2112113058 ps
CPU time 167.16 seconds
Started Jul 14 07:43:26 PM PDT 24
Finished Jul 14 07:46:14 PM PDT 24
Peak memory 575524 kb
Host smart-0bf969b0-f111-4f38-ae62-d7451b9579a6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064034592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.3064034592
Directory /workspace/92.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.1958145251
Short name T1434
Test name
Test status
Simulation time 2331953529 ps
CPU time 186.49 seconds
Started Jul 14 07:43:25 PM PDT 24
Finished Jul 14 07:46:32 PM PDT 24
Peak memory 575532 kb
Host smart-b5c367a4-f0bb-4e16-a5fc-17016ecfbefa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958145251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.1958145251
Directory /workspace/92.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.931276438
Short name T2422
Test name
Test status
Simulation time 211541248 ps
CPU time 116.67 seconds
Started Jul 14 07:43:23 PM PDT 24
Finished Jul 14 07:45:20 PM PDT 24
Peak memory 575432 kb
Host smart-1b402122-d59b-4672-95a9-a30daca2bcbc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931276438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_
with_rand_reset.931276438
Directory /workspace/92.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.145004214
Short name T850
Test name
Test status
Simulation time 6035444073 ps
CPU time 343.84 seconds
Started Jul 14 07:43:21 PM PDT 24
Finished Jul 14 07:49:06 PM PDT 24
Peak memory 575528 kb
Host smart-d6ea9271-0844-4376-b425-35e4d898127b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145004214 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all
_with_reset_error.145004214
Directory /workspace/92.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.4232500183
Short name T2802
Test name
Test status
Simulation time 1130307883 ps
CPU time 48.74 seconds
Started Jul 14 07:43:23 PM PDT 24
Finished Jul 14 07:44:13 PM PDT 24
Peak memory 575340 kb
Host smart-8dbb5fe0-9d96-4f97-85b9-809ff22f748d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232500183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.4232500183
Directory /workspace/92.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_access_same_device.3353986495
Short name T844
Test name
Test status
Simulation time 3412941059 ps
CPU time 130.37 seconds
Started Jul 14 07:43:33 PM PDT 24
Finished Jul 14 07:45:44 PM PDT 24
Peak memory 575344 kb
Host smart-a6f2842d-2e5d-4917-b767-61c076c7165a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353986495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device
.3353986495
Directory /workspace/93.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.1467758037
Short name T1370
Test name
Test status
Simulation time 910483623 ps
CPU time 36.17 seconds
Started Jul 14 07:43:32 PM PDT 24
Finished Jul 14 07:44:08 PM PDT 24
Peak memory 575348 kb
Host smart-7169a052-3975-4f39-98e2-8ae061683aef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467758037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add
r.1467758037
Directory /workspace/93.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_error_random.2970034832
Short name T1681
Test name
Test status
Simulation time 1985525160 ps
CPU time 72.53 seconds
Started Jul 14 07:43:29 PM PDT 24
Finished Jul 14 07:44:42 PM PDT 24
Peak memory 575296 kb
Host smart-2a9dca60-2c36-4f2c-946a-6aad7fca4ca2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970034832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.2970034832
Directory /workspace/93.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random.394424460
Short name T2094
Test name
Test status
Simulation time 218099122 ps
CPU time 24.47 seconds
Started Jul 14 07:43:24 PM PDT 24
Finished Jul 14 07:43:49 PM PDT 24
Peak memory 575304 kb
Host smart-b2b0fa5d-be75-45e7-9cf7-6440dd991330
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394424460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.394424460
Directory /workspace/93.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.2433510056
Short name T1606
Test name
Test status
Simulation time 56410689264 ps
CPU time 707.86 seconds
Started Jul 14 07:43:24 PM PDT 24
Finished Jul 14 07:55:13 PM PDT 24
Peak memory 575456 kb
Host smart-f177f488-1361-4480-bb45-c9403f35243d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433510056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.2433510056
Directory /workspace/93.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.1503923384
Short name T567
Test name
Test status
Simulation time 28601830437 ps
CPU time 490.05 seconds
Started Jul 14 07:43:24 PM PDT 24
Finished Jul 14 07:51:35 PM PDT 24
Peak memory 575528 kb
Host smart-0791fe8e-dd4d-481a-92ef-008716b6a19f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503923384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.1503923384
Directory /workspace/93.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.1334206936
Short name T1803
Test name
Test status
Simulation time 38163546 ps
CPU time 6.64 seconds
Started Jul 14 07:43:25 PM PDT 24
Finished Jul 14 07:43:32 PM PDT 24
Peak memory 574052 kb
Host smart-95af99b4-d405-4291-9fea-323c44feda3e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334206936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del
ays.1334206936
Directory /workspace/93.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_same_source.924044768
Short name T2487
Test name
Test status
Simulation time 2433954602 ps
CPU time 68.03 seconds
Started Jul 14 07:43:30 PM PDT 24
Finished Jul 14 07:44:38 PM PDT 24
Peak memory 575300 kb
Host smart-5655eb2f-bbd1-47af-bb08-15205c408c4d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924044768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.924044768
Directory /workspace/93.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke.1054951849
Short name T1836
Test name
Test status
Simulation time 245389487 ps
CPU time 9.4 seconds
Started Jul 14 07:43:24 PM PDT 24
Finished Jul 14 07:43:33 PM PDT 24
Peak memory 575268 kb
Host smart-8f8b3f29-0a77-4ce7-a65a-7c76042fddd2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054951849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.1054951849
Directory /workspace/93.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.2860517042
Short name T1979
Test name
Test status
Simulation time 7567726011 ps
CPU time 89.76 seconds
Started Jul 14 07:43:22 PM PDT 24
Finished Jul 14 07:44:52 PM PDT 24
Peak memory 574136 kb
Host smart-9e6f13d3-127a-4196-9bcc-76ddb3101f0d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860517042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.2860517042
Directory /workspace/93.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.1146857919
Short name T2309
Test name
Test status
Simulation time 6053318516 ps
CPU time 107.06 seconds
Started Jul 14 07:43:26 PM PDT 24
Finished Jul 14 07:45:14 PM PDT 24
Peak memory 575440 kb
Host smart-2f6a76c7-ebf3-4732-b96e-b41a935e744f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146857919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.1146857919
Directory /workspace/93.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.1370788566
Short name T1611
Test name
Test status
Simulation time 49723838 ps
CPU time 6.93 seconds
Started Jul 14 07:43:24 PM PDT 24
Finished Jul 14 07:43:31 PM PDT 24
Peak memory 574040 kb
Host smart-520f918c-47db-4290-b0e9-386fe4335afb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370788566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay
s.1370788566
Directory /workspace/93.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.4155839142
Short name T833
Test name
Test status
Simulation time 7777502026 ps
CPU time 276.13 seconds
Started Jul 14 07:43:30 PM PDT 24
Finished Jul 14 07:48:06 PM PDT 24
Peak memory 575612 kb
Host smart-472f7ab4-58f5-43fe-b3ee-6d4107d67fe8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155839142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.4155839142
Directory /workspace/93.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.3199823528
Short name T2281
Test name
Test status
Simulation time 1636304515 ps
CPU time 375.55 seconds
Started Jul 14 07:43:33 PM PDT 24
Finished Jul 14 07:49:49 PM PDT 24
Peak memory 575488 kb
Host smart-fa26e6e2-79ce-4c60-8898-470020800406
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199823528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all
_with_rand_reset.3199823528
Directory /workspace/93.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.3402469942
Short name T1883
Test name
Test status
Simulation time 236411154 ps
CPU time 129.31 seconds
Started Jul 14 07:43:29 PM PDT 24
Finished Jul 14 07:45:38 PM PDT 24
Peak memory 575444 kb
Host smart-614d1c4a-a62d-48f7-8e08-e08886676967
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402469942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al
l_with_reset_error.3402469942
Directory /workspace/93.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.1337112292
Short name T2355
Test name
Test status
Simulation time 867526760 ps
CPU time 38.63 seconds
Started Jul 14 07:43:35 PM PDT 24
Finished Jul 14 07:44:14 PM PDT 24
Peak memory 575392 kb
Host smart-dfa6cfe3-4b55-48e7-9e85-ad020e74a19f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337112292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.1337112292
Directory /workspace/93.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_access_same_device.4172750477
Short name T1749
Test name
Test status
Simulation time 410755840 ps
CPU time 49.94 seconds
Started Jul 14 07:43:35 PM PDT 24
Finished Jul 14 07:44:26 PM PDT 24
Peak memory 575344 kb
Host smart-f60063d2-0e27-4b22-a4c4-cc1d09da3e64
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172750477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device
.4172750477
Directory /workspace/94.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.666256341
Short name T1818
Test name
Test status
Simulation time 62123990779 ps
CPU time 1293.18 seconds
Started Jul 14 07:43:37 PM PDT 24
Finished Jul 14 08:05:11 PM PDT 24
Peak memory 575604 kb
Host smart-2a565dab-85b9-4edb-b70c-3a681654a2b8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666256341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_d
evice_slow_rsp.666256341
Directory /workspace/94.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.1230218771
Short name T1595
Test name
Test status
Simulation time 171704690 ps
CPU time 18.24 seconds
Started Jul 14 07:43:38 PM PDT 24
Finished Jul 14 07:43:56 PM PDT 24
Peak memory 575352 kb
Host smart-25b487f2-38c8-4175-851f-aac607600624
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230218771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add
r.1230218771
Directory /workspace/94.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_error_random.227307572
Short name T2703
Test name
Test status
Simulation time 2008824046 ps
CPU time 76.81 seconds
Started Jul 14 07:43:35 PM PDT 24
Finished Jul 14 07:44:53 PM PDT 24
Peak memory 575040 kb
Host smart-8933f525-dde9-47b5-a7a9-995fb8378913
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227307572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.227307572
Directory /workspace/94.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random.141911338
Short name T501
Test name
Test status
Simulation time 204876905 ps
CPU time 18.66 seconds
Started Jul 14 07:43:30 PM PDT 24
Finished Jul 14 07:43:49 PM PDT 24
Peak memory 575392 kb
Host smart-7a1ae41e-dfba-4edd-82ad-a0c2b31d2973
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141911338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.141911338
Directory /workspace/94.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.1196374710
Short name T1987
Test name
Test status
Simulation time 85036226936 ps
CPU time 967.25 seconds
Started Jul 14 07:43:30 PM PDT 24
Finished Jul 14 07:59:38 PM PDT 24
Peak memory 575540 kb
Host smart-f6a8088b-9b3e-4068-bc13-253f4615ae47
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196374710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.1196374710
Directory /workspace/94.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.3359495094
Short name T2182
Test name
Test status
Simulation time 48038420739 ps
CPU time 952.05 seconds
Started Jul 14 07:43:38 PM PDT 24
Finished Jul 14 07:59:30 PM PDT 24
Peak memory 575472 kb
Host smart-91e04777-4693-4948-aae5-64663480d3b9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359495094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.3359495094
Directory /workspace/94.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.4220703482
Short name T2242
Test name
Test status
Simulation time 619697162 ps
CPU time 53.93 seconds
Started Jul 14 07:43:29 PM PDT 24
Finished Jul 14 07:44:23 PM PDT 24
Peak memory 575316 kb
Host smart-6f6e9c82-cd92-4542-8d3b-aa22f6c8a21d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220703482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del
ays.4220703482
Directory /workspace/94.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_same_source.748667099
Short name T1858
Test name
Test status
Simulation time 1463795498 ps
CPU time 44.86 seconds
Started Jul 14 07:43:35 PM PDT 24
Finished Jul 14 07:44:20 PM PDT 24
Peak memory 575288 kb
Host smart-03e66b3a-33ae-45b3-972c-320a29e2dea1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748667099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.748667099
Directory /workspace/94.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke.1230692259
Short name T1849
Test name
Test status
Simulation time 193727994 ps
CPU time 9.4 seconds
Started Jul 14 07:43:35 PM PDT 24
Finished Jul 14 07:43:45 PM PDT 24
Peak memory 575252 kb
Host smart-287d1853-66ee-4492-8722-bf54afda23c2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230692259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.1230692259
Directory /workspace/94.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.2384279910
Short name T1650
Test name
Test status
Simulation time 9374281200 ps
CPU time 104.53 seconds
Started Jul 14 07:43:33 PM PDT 24
Finished Jul 14 07:45:18 PM PDT 24
Peak memory 574188 kb
Host smart-bbcdb8c0-c94d-43e5-819c-5c0fecb25665
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384279910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.2384279910
Directory /workspace/94.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.3988413811
Short name T2050
Test name
Test status
Simulation time 4376900480 ps
CPU time 78.21 seconds
Started Jul 14 07:43:30 PM PDT 24
Finished Jul 14 07:44:48 PM PDT 24
Peak memory 574164 kb
Host smart-0b2f1601-da7e-43f3-bd20-6a8c78bb864a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988413811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.3988413811
Directory /workspace/94.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.320553454
Short name T1632
Test name
Test status
Simulation time 40894889 ps
CPU time 5.72 seconds
Started Jul 14 07:43:29 PM PDT 24
Finished Jul 14 07:43:35 PM PDT 24
Peak memory 574036 kb
Host smart-019ec368-2bd7-4238-a63f-06ca72e1d198
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320553454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delays
.320553454
Directory /workspace/94.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all.1372004707
Short name T2402
Test name
Test status
Simulation time 3789186688 ps
CPU time 132.31 seconds
Started Jul 14 07:43:36 PM PDT 24
Finished Jul 14 07:45:49 PM PDT 24
Peak memory 575468 kb
Host smart-805377f4-5ec1-4a8b-9505-928fcb025143
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372004707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.1372004707
Directory /workspace/94.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.2822215558
Short name T1603
Test name
Test status
Simulation time 1501220502 ps
CPU time 121.71 seconds
Started Jul 14 07:43:46 PM PDT 24
Finished Jul 14 07:45:48 PM PDT 24
Peak memory 575516 kb
Host smart-6a8bece5-bb2f-4833-96ca-50711dd5b1ee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822215558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.2822215558
Directory /workspace/94.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.3002673150
Short name T1656
Test name
Test status
Simulation time 2381835720 ps
CPU time 256.01 seconds
Started Jul 14 07:43:36 PM PDT 24
Finished Jul 14 07:47:52 PM PDT 24
Peak memory 575544 kb
Host smart-3e057149-dca2-4e20-b1ba-9341439f8394
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002673150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all
_with_rand_reset.3002673150
Directory /workspace/94.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.556268222
Short name T2661
Test name
Test status
Simulation time 578109227 ps
CPU time 25.21 seconds
Started Jul 14 07:43:37 PM PDT 24
Finished Jul 14 07:44:03 PM PDT 24
Peak memory 575356 kb
Host smart-9fbac3b1-f666-4fb0-b65b-5674181bef8c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556268222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.556268222
Directory /workspace/94.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_access_same_device.162324807
Short name T2663
Test name
Test status
Simulation time 3414461975 ps
CPU time 123.73 seconds
Started Jul 14 07:43:47 PM PDT 24
Finished Jul 14 07:45:51 PM PDT 24
Peak memory 575388 kb
Host smart-12922163-04bc-4f5e-91cc-27516f39cfb3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162324807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device.
162324807
Directory /workspace/95.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.566882167
Short name T835
Test name
Test status
Simulation time 24532095680 ps
CPU time 473.4 seconds
Started Jul 14 07:43:53 PM PDT 24
Finished Jul 14 07:51:48 PM PDT 24
Peak memory 575504 kb
Host smart-be39515a-d0f1-4692-b5f6-8d34cdfc125d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566882167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_d
evice_slow_rsp.566882167
Directory /workspace/95.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.1765909659
Short name T2359
Test name
Test status
Simulation time 116742478 ps
CPU time 7.29 seconds
Started Jul 14 07:43:53 PM PDT 24
Finished Jul 14 07:44:01 PM PDT 24
Peak memory 575332 kb
Host smart-429ae94e-a24d-4e8a-a81f-a5c0558d9214
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765909659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add
r.1765909659
Directory /workspace/95.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_error_random.4133572115
Short name T1589
Test name
Test status
Simulation time 2140799127 ps
CPU time 72.46 seconds
Started Jul 14 07:43:48 PM PDT 24
Finished Jul 14 07:45:00 PM PDT 24
Peak memory 575348 kb
Host smart-b3b455a8-8ad9-46e8-b7ad-f412c9728c55
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133572115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.4133572115
Directory /workspace/95.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random.2241411854
Short name T1476
Test name
Test status
Simulation time 484390524 ps
CPU time 18.29 seconds
Started Jul 14 07:43:42 PM PDT 24
Finished Jul 14 07:44:01 PM PDT 24
Peak memory 575376 kb
Host smart-d38ee77a-2a2a-434a-addf-2bce272144d9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241411854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.2241411854
Directory /workspace/95.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.229034835
Short name T2113
Test name
Test status
Simulation time 82475518718 ps
CPU time 915.66 seconds
Started Jul 14 07:43:43 PM PDT 24
Finished Jul 14 07:58:59 PM PDT 24
Peak memory 575492 kb
Host smart-6a5638e1-f4c5-4e6f-939e-f8d3ae96a4b9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229034835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.229034835
Directory /workspace/95.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.3453632590
Short name T1431
Test name
Test status
Simulation time 7205186231 ps
CPU time 127.44 seconds
Started Jul 14 07:43:54 PM PDT 24
Finished Jul 14 07:46:02 PM PDT 24
Peak memory 575468 kb
Host smart-d246e48d-cec3-4877-ab1e-63ce895fa3cf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453632590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.3453632590
Directory /workspace/95.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.1284774574
Short name T2178
Test name
Test status
Simulation time 494198330 ps
CPU time 48.55 seconds
Started Jul 14 07:43:42 PM PDT 24
Finished Jul 14 07:44:31 PM PDT 24
Peak memory 575260 kb
Host smart-b47b8286-c6f2-4df0-b02f-ca4795974825
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284774574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del
ays.1284774574
Directory /workspace/95.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_same_source.565235679
Short name T544
Test name
Test status
Simulation time 2179297827 ps
CPU time 67.45 seconds
Started Jul 14 07:43:49 PM PDT 24
Finished Jul 14 07:44:56 PM PDT 24
Peak memory 575432 kb
Host smart-4865690a-1270-493f-ba1a-4428d9540e8b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565235679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.565235679
Directory /workspace/95.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke.2010746867
Short name T2200
Test name
Test status
Simulation time 212166539 ps
CPU time 9.68 seconds
Started Jul 14 07:43:43 PM PDT 24
Finished Jul 14 07:43:53 PM PDT 24
Peak memory 575260 kb
Host smart-8b716652-5358-49d4-9c17-b846f162a5ab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010746867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.2010746867
Directory /workspace/95.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.1935967183
Short name T1668
Test name
Test status
Simulation time 7689028326 ps
CPU time 85.19 seconds
Started Jul 14 07:43:42 PM PDT 24
Finished Jul 14 07:45:07 PM PDT 24
Peak memory 574124 kb
Host smart-7060409e-1a94-497e-80bc-744c233a9d50
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935967183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.1935967183
Directory /workspace/95.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.1714647993
Short name T2445
Test name
Test status
Simulation time 5513575865 ps
CPU time 102.61 seconds
Started Jul 14 07:43:43 PM PDT 24
Finished Jul 14 07:45:26 PM PDT 24
Peak memory 574176 kb
Host smart-317d682f-8b3a-41f7-b331-6e64715da0a7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714647993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.1714647993
Directory /workspace/95.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.3176802034
Short name T2486
Test name
Test status
Simulation time 55389769 ps
CPU time 6.32 seconds
Started Jul 14 07:43:42 PM PDT 24
Finished Jul 14 07:43:48 PM PDT 24
Peak memory 574016 kb
Host smart-15a0f49b-72b7-42ff-a24c-f5174c3fb9c8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176802034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay
s.3176802034
Directory /workspace/95.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all.1177001670
Short name T2007
Test name
Test status
Simulation time 2832945469 ps
CPU time 98.82 seconds
Started Jul 14 07:43:50 PM PDT 24
Finished Jul 14 07:45:29 PM PDT 24
Peak memory 575492 kb
Host smart-82d23945-6289-447a-b8b7-0d17c233dedb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177001670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.1177001670
Directory /workspace/95.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.639035326
Short name T2335
Test name
Test status
Simulation time 239126242 ps
CPU time 22.52 seconds
Started Jul 14 07:43:48 PM PDT 24
Finished Jul 14 07:44:10 PM PDT 24
Peak memory 575396 kb
Host smart-22917d74-6103-4a25-9ff4-454f8a692cce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639035326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.639035326
Directory /workspace/95.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.3040087671
Short name T1554
Test name
Test status
Simulation time 1840231173 ps
CPU time 249.18 seconds
Started Jul 14 07:43:51 PM PDT 24
Finished Jul 14 07:48:00 PM PDT 24
Peak memory 575508 kb
Host smart-5dfdc8d7-03c5-4976-aa1f-84f39c52b8d7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040087671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all
_with_rand_reset.3040087671
Directory /workspace/95.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.3506625270
Short name T2245
Test name
Test status
Simulation time 116007279 ps
CPU time 45.16 seconds
Started Jul 14 07:43:50 PM PDT 24
Finished Jul 14 07:44:35 PM PDT 24
Peak memory 575156 kb
Host smart-c2dbea94-b367-4ca0-9325-b564d9547312
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506625270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al
l_with_reset_error.3506625270
Directory /workspace/95.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.1721602885
Short name T1710
Test name
Test status
Simulation time 1346544134 ps
CPU time 52.25 seconds
Started Jul 14 07:43:49 PM PDT 24
Finished Jul 14 07:44:42 PM PDT 24
Peak memory 575412 kb
Host smart-3881fe9a-749e-457f-a091-dee04127fe10
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721602885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.1721602885
Directory /workspace/95.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_access_same_device.2776053106
Short name T2457
Test name
Test status
Simulation time 648040573 ps
CPU time 67.47 seconds
Started Jul 14 07:43:53 PM PDT 24
Finished Jul 14 07:45:02 PM PDT 24
Peak memory 575376 kb
Host smart-c988830a-95b2-4fdb-8570-c1dd65a3cfcb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776053106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device
.2776053106
Directory /workspace/96.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.1964294599
Short name T2339
Test name
Test status
Simulation time 31078609298 ps
CPU time 612.53 seconds
Started Jul 14 07:43:55 PM PDT 24
Finished Jul 14 07:54:08 PM PDT 24
Peak memory 575480 kb
Host smart-c5c3f97f-f16c-4132-a789-9bb0aec7a713
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964294599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_
device_slow_rsp.1964294599
Directory /workspace/96.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.1979746041
Short name T2906
Test name
Test status
Simulation time 269786125 ps
CPU time 12.97 seconds
Started Jul 14 07:43:54 PM PDT 24
Finished Jul 14 07:44:08 PM PDT 24
Peak memory 575304 kb
Host smart-cc48041a-8e10-4f0f-b4bc-9468ba548bba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979746041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add
r.1979746041
Directory /workspace/96.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_error_random.1227830255
Short name T2299
Test name
Test status
Simulation time 96045709 ps
CPU time 10.35 seconds
Started Jul 14 07:43:56 PM PDT 24
Finished Jul 14 07:44:06 PM PDT 24
Peak memory 575348 kb
Host smart-a04b0aac-478d-4a1f-95ef-a438f6f71e8a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227830255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.1227830255
Directory /workspace/96.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random.1458230547
Short name T2815
Test name
Test status
Simulation time 513063516 ps
CPU time 43 seconds
Started Jul 14 07:43:51 PM PDT 24
Finished Jul 14 07:44:34 PM PDT 24
Peak memory 575380 kb
Host smart-3f192af0-1931-4f7c-9e41-eb7e6de4cec8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458230547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.1458230547
Directory /workspace/96.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.2583196208
Short name T1665
Test name
Test status
Simulation time 15766712725 ps
CPU time 172.88 seconds
Started Jul 14 07:43:53 PM PDT 24
Finished Jul 14 07:46:46 PM PDT 24
Peak memory 575620 kb
Host smart-25a91567-d292-4a63-9ca6-53e362d7c877
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583196208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.2583196208
Directory /workspace/96.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.947370997
Short name T2253
Test name
Test status
Simulation time 2118320459 ps
CPU time 35.2 seconds
Started Jul 14 07:43:53 PM PDT 24
Finished Jul 14 07:44:29 PM PDT 24
Peak memory 574104 kb
Host smart-4b8f480d-c254-4045-be83-ea5bacb0011c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947370997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.947370997
Directory /workspace/96.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.2440472592
Short name T2786
Test name
Test status
Simulation time 120144193 ps
CPU time 12.46 seconds
Started Jul 14 07:43:51 PM PDT 24
Finished Jul 14 07:44:03 PM PDT 24
Peak memory 575304 kb
Host smart-9a52b2d8-22b9-474a-87f5-109923f04cdd
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440472592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del
ays.2440472592
Directory /workspace/96.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_same_source.756033522
Short name T2818
Test name
Test status
Simulation time 778354413 ps
CPU time 25.75 seconds
Started Jul 14 07:43:55 PM PDT 24
Finished Jul 14 07:44:21 PM PDT 24
Peak memory 575344 kb
Host smart-a1a831c1-0dd9-4290-bdec-6e4ff9bddaa5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756033522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.756033522
Directory /workspace/96.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke.4055901216
Short name T2704
Test name
Test status
Simulation time 197977951 ps
CPU time 8.68 seconds
Started Jul 14 07:43:51 PM PDT 24
Finished Jul 14 07:44:01 PM PDT 24
Peak memory 575284 kb
Host smart-045fa330-b218-4fd3-b358-1be6865322b7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055901216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.4055901216
Directory /workspace/96.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.889206077
Short name T2480
Test name
Test status
Simulation time 8642122103 ps
CPU time 89.86 seconds
Started Jul 14 07:43:50 PM PDT 24
Finished Jul 14 07:45:20 PM PDT 24
Peak memory 574136 kb
Host smart-6f3c38f3-c255-4498-b948-d25b79c94c0a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889206077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.889206077
Directory /workspace/96.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.4156348290
Short name T1557
Test name
Test status
Simulation time 5156334887 ps
CPU time 84.61 seconds
Started Jul 14 07:43:51 PM PDT 24
Finished Jul 14 07:45:17 PM PDT 24
Peak memory 574120 kb
Host smart-d1679d5c-b3f9-4cd1-a0a8-7bb194489ddf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156348290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.4156348290
Directory /workspace/96.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.2650245507
Short name T2095
Test name
Test status
Simulation time 54953568 ps
CPU time 7.01 seconds
Started Jul 14 07:43:49 PM PDT 24
Finished Jul 14 07:43:56 PM PDT 24
Peak memory 575316 kb
Host smart-a8075059-59d9-4c1b-b33c-204cec33fe42
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650245507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay
s.2650245507
Directory /workspace/96.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all.1612193858
Short name T500
Test name
Test status
Simulation time 10419960643 ps
CPU time 410.49 seconds
Started Jul 14 07:44:00 PM PDT 24
Finished Jul 14 07:50:52 PM PDT 24
Peak memory 575628 kb
Host smart-95c7c3da-7111-4ab9-958d-92f3f02ac547
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612193858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.1612193858
Directory /workspace/96.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.543860914
Short name T2122
Test name
Test status
Simulation time 7670885806 ps
CPU time 289.95 seconds
Started Jul 14 07:44:03 PM PDT 24
Finished Jul 14 07:48:53 PM PDT 24
Peak memory 575572 kb
Host smart-81f41907-eb05-415a-9489-f467ada667f0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543860914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.543860914
Directory /workspace/96.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.854528931
Short name T2817
Test name
Test status
Simulation time 277058186 ps
CPU time 95.73 seconds
Started Jul 14 07:44:02 PM PDT 24
Finished Jul 14 07:45:38 PM PDT 24
Peak memory 575448 kb
Host smart-f55ab4f4-2c70-4e88-9017-f2c8b4cdf5cf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854528931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_
with_rand_reset.854528931
Directory /workspace/96.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.2276042742
Short name T2471
Test name
Test status
Simulation time 10629110 ps
CPU time 28.1 seconds
Started Jul 14 07:44:02 PM PDT 24
Finished Jul 14 07:44:30 PM PDT 24
Peak memory 575424 kb
Host smart-f203d792-fe87-484a-88ca-79185af41ea2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276042742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al
l_with_reset_error.2276042742
Directory /workspace/96.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.815268690
Short name T2813
Test name
Test status
Simulation time 18046876 ps
CPU time 5.43 seconds
Started Jul 14 07:43:55 PM PDT 24
Finished Jul 14 07:44:01 PM PDT 24
Peak memory 574040 kb
Host smart-1520b235-1eb3-4e61-a1a4-4c854cfb15c7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815268690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.815268690
Directory /workspace/96.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_access_same_device.433049702
Short name T507
Test name
Test status
Simulation time 1126536596 ps
CPU time 96.75 seconds
Started Jul 14 07:44:06 PM PDT 24
Finished Jul 14 07:45:43 PM PDT 24
Peak memory 575348 kb
Host smart-bff6e551-9f0e-4b1d-8cdf-b161248348a8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433049702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device.
433049702
Directory /workspace/97.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.3420601033
Short name T498
Test name
Test status
Simulation time 111811636627 ps
CPU time 2242.46 seconds
Started Jul 14 07:44:07 PM PDT 24
Finished Jul 14 08:21:30 PM PDT 24
Peak memory 575552 kb
Host smart-a213d23c-5067-4cc0-8880-5964637b37f3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420601033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_
device_slow_rsp.3420601033
Directory /workspace/97.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.2324833425
Short name T1565
Test name
Test status
Simulation time 148332544 ps
CPU time 18.41 seconds
Started Jul 14 07:44:09 PM PDT 24
Finished Jul 14 07:44:27 PM PDT 24
Peak memory 575292 kb
Host smart-cf4f13fb-8677-48de-b597-b1091e8e71ab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324833425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add
r.2324833425
Directory /workspace/97.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_error_random.2410615657
Short name T2287
Test name
Test status
Simulation time 2360816707 ps
CPU time 85.52 seconds
Started Jul 14 07:44:09 PM PDT 24
Finished Jul 14 07:45:35 PM PDT 24
Peak memory 575360 kb
Host smart-4a024441-7009-4979-bc22-31421ef486f3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410615657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.2410615657
Directory /workspace/97.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random.107687990
Short name T1980
Test name
Test status
Simulation time 272390599 ps
CPU time 13.39 seconds
Started Jul 14 07:44:06 PM PDT 24
Finished Jul 14 07:44:20 PM PDT 24
Peak memory 575320 kb
Host smart-a1308fd9-88e3-4fb6-b463-d9aa685cf8f5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107687990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.107687990
Directory /workspace/97.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.2068362668
Short name T2583
Test name
Test status
Simulation time 50848022840 ps
CPU time 585.55 seconds
Started Jul 14 07:44:07 PM PDT 24
Finished Jul 14 07:53:53 PM PDT 24
Peak memory 575464 kb
Host smart-57b63f1d-72aa-48c4-9ed9-107a6af93c41
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068362668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.2068362668
Directory /workspace/97.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.3943536464
Short name T2187
Test name
Test status
Simulation time 55886385063 ps
CPU time 1072.26 seconds
Started Jul 14 07:44:06 PM PDT 24
Finished Jul 14 08:01:59 PM PDT 24
Peak memory 575536 kb
Host smart-ddb91247-a282-4eee-a951-22884930fa4d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943536464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.3943536464
Directory /workspace/97.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.1541622823
Short name T1750
Test name
Test status
Simulation time 173757396 ps
CPU time 17.71 seconds
Started Jul 14 07:44:07 PM PDT 24
Finished Jul 14 07:44:25 PM PDT 24
Peak memory 575324 kb
Host smart-da2291a1-c353-4e1a-bf6a-b9b027ac0965
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541622823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del
ays.1541622823
Directory /workspace/97.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_same_source.1449790869
Short name T1597
Test name
Test status
Simulation time 2547232785 ps
CPU time 72.66 seconds
Started Jul 14 07:44:07 PM PDT 24
Finished Jul 14 07:45:20 PM PDT 24
Peak memory 575376 kb
Host smart-234ad40a-fe09-43dc-bd77-6c290fe6c2f8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449790869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.1449790869
Directory /workspace/97.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke.2387690338
Short name T1690
Test name
Test status
Simulation time 237255259 ps
CPU time 10.35 seconds
Started Jul 14 07:44:00 PM PDT 24
Finished Jul 14 07:44:11 PM PDT 24
Peak memory 574056 kb
Host smart-6e1ac380-6928-4e4d-8a82-85e2b7aaefaa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387690338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.2387690338
Directory /workspace/97.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.870417999
Short name T1852
Test name
Test status
Simulation time 7098433526 ps
CPU time 75.13 seconds
Started Jul 14 07:44:00 PM PDT 24
Finished Jul 14 07:45:16 PM PDT 24
Peak memory 574196 kb
Host smart-5f9f7d46-1514-47c2-9b80-b1815c1c3bfa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870417999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.870417999
Directory /workspace/97.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.1871103093
Short name T2746
Test name
Test status
Simulation time 2956024890 ps
CPU time 54.39 seconds
Started Jul 14 07:44:00 PM PDT 24
Finished Jul 14 07:44:55 PM PDT 24
Peak memory 574048 kb
Host smart-7f57dc30-3345-4808-a7e5-e46ceb13697b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871103093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.1871103093
Directory /workspace/97.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.2522907770
Short name T1567
Test name
Test status
Simulation time 52394105 ps
CPU time 6.17 seconds
Started Jul 14 07:44:00 PM PDT 24
Finished Jul 14 07:44:07 PM PDT 24
Peak memory 574000 kb
Host smart-f2613833-003e-4dc3-9be5-a0f49b9305bd
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522907770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay
s.2522907770
Directory /workspace/97.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all.3973902249
Short name T2406
Test name
Test status
Simulation time 3682033315 ps
CPU time 284.55 seconds
Started Jul 14 07:44:10 PM PDT 24
Finished Jul 14 07:48:55 PM PDT 24
Peak memory 575552 kb
Host smart-480dbfa3-21ad-402a-9300-1dbcee125d92
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973902249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.3973902249
Directory /workspace/97.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.828738348
Short name T2008
Test name
Test status
Simulation time 16065674537 ps
CPU time 620.96 seconds
Started Jul 14 07:44:05 PM PDT 24
Finished Jul 14 07:54:27 PM PDT 24
Peak memory 575592 kb
Host smart-45ae2b00-dcaa-4913-bbee-d24b93ebddc6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828738348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.828738348
Directory /workspace/97.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.1549165411
Short name T2146
Test name
Test status
Simulation time 275776785 ps
CPU time 97.89 seconds
Started Jul 14 07:44:06 PM PDT 24
Finished Jul 14 07:45:45 PM PDT 24
Peak memory 575428 kb
Host smart-0dc66750-59d9-401d-8073-433f2a291d05
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549165411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all
_with_rand_reset.1549165411
Directory /workspace/97.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.667935790
Short name T1401
Test name
Test status
Simulation time 447132311 ps
CPU time 121.69 seconds
Started Jul 14 07:44:12 PM PDT 24
Finished Jul 14 07:46:14 PM PDT 24
Peak memory 575488 kb
Host smart-fdf85644-abac-4972-b4c4-737f0a8f0e8d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667935790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all
_with_reset_error.667935790
Directory /workspace/97.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.870915380
Short name T2317
Test name
Test status
Simulation time 1294522268 ps
CPU time 53.55 seconds
Started Jul 14 07:44:09 PM PDT 24
Finished Jul 14 07:45:03 PM PDT 24
Peak memory 575308 kb
Host smart-e8f780ba-3a4f-4645-8210-d45a68a8011b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870915380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.870915380
Directory /workspace/97.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_access_same_device.1461516132
Short name T2572
Test name
Test status
Simulation time 2886621899 ps
CPU time 125.93 seconds
Started Jul 14 07:44:14 PM PDT 24
Finished Jul 14 07:46:20 PM PDT 24
Peak memory 575536 kb
Host smart-7e18a86e-f443-4c72-8920-0a2611986aa0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461516132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device
.1461516132
Directory /workspace/98.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.3109873357
Short name T1471
Test name
Test status
Simulation time 141275506824 ps
CPU time 2635.76 seconds
Started Jul 14 07:44:13 PM PDT 24
Finished Jul 14 08:28:09 PM PDT 24
Peak memory 575564 kb
Host smart-f5545e12-54e7-4e3d-947b-5cba770e0397
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109873357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_
device_slow_rsp.3109873357
Directory /workspace/98.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.3965333370
Short name T1608
Test name
Test status
Simulation time 315120344 ps
CPU time 33.04 seconds
Started Jul 14 07:44:21 PM PDT 24
Finished Jul 14 07:44:55 PM PDT 24
Peak memory 575308 kb
Host smart-4b664ebb-5e77-4247-8741-dd96cde216e5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965333370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add
r.3965333370
Directory /workspace/98.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_error_random.4149385415
Short name T1848
Test name
Test status
Simulation time 163922798 ps
CPU time 15.79 seconds
Started Jul 14 07:44:37 PM PDT 24
Finished Jul 14 07:44:53 PM PDT 24
Peak memory 575268 kb
Host smart-562ef5e6-0a2d-4fdc-ae82-d7f5ffc61ecd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149385415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.4149385415
Directory /workspace/98.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random.1479525154
Short name T2680
Test name
Test status
Simulation time 1824515455 ps
CPU time 64.9 seconds
Started Jul 14 07:44:14 PM PDT 24
Finished Jul 14 07:45:20 PM PDT 24
Peak memory 575332 kb
Host smart-8281828f-013c-4159-8716-ff5f2c8e2c20
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479525154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.1479525154
Directory /workspace/98.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.2585788273
Short name T1899
Test name
Test status
Simulation time 53011162584 ps
CPU time 639.43 seconds
Started Jul 14 07:44:13 PM PDT 24
Finished Jul 14 07:54:53 PM PDT 24
Peak memory 575424 kb
Host smart-db52bc7b-6ca3-46a5-b595-3484f0a35de7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585788273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.2585788273
Directory /workspace/98.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.3770040331
Short name T2756
Test name
Test status
Simulation time 35719558815 ps
CPU time 681.92 seconds
Started Jul 14 07:44:12 PM PDT 24
Finished Jul 14 07:55:34 PM PDT 24
Peak memory 575512 kb
Host smart-58f3beeb-de17-40bd-a5ed-2561c5cd1ad0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770040331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.3770040331
Directory /workspace/98.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.937797736
Short name T2634
Test name
Test status
Simulation time 288756404 ps
CPU time 24.68 seconds
Started Jul 14 07:44:12 PM PDT 24
Finished Jul 14 07:44:37 PM PDT 24
Peak memory 575264 kb
Host smart-9e20104e-2b3f-4e08-aa33-e0f97cc10f48
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937797736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_dela
ys.937797736
Directory /workspace/98.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_same_source.213606713
Short name T2138
Test name
Test status
Simulation time 493250115 ps
CPU time 37.18 seconds
Started Jul 14 07:44:19 PM PDT 24
Finished Jul 14 07:44:56 PM PDT 24
Peak memory 575308 kb
Host smart-e7b3e524-3b7a-457f-9ce3-ad387e43170e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213606713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.213606713
Directory /workspace/98.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke.2415922498
Short name T2709
Test name
Test status
Simulation time 40946224 ps
CPU time 6.04 seconds
Started Jul 14 07:44:13 PM PDT 24
Finished Jul 14 07:44:19 PM PDT 24
Peak memory 574072 kb
Host smart-db268f48-6e0c-412e-974c-1d3e1ad3b5b2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415922498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.2415922498
Directory /workspace/98.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.3036264746
Short name T1902
Test name
Test status
Simulation time 10282072847 ps
CPU time 116.21 seconds
Started Jul 14 07:44:13 PM PDT 24
Finished Jul 14 07:46:10 PM PDT 24
Peak memory 574216 kb
Host smart-fa5c1f6a-da4a-4c06-97a7-db6ec833ef00
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036264746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.3036264746
Directory /workspace/98.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.1303655298
Short name T1935
Test name
Test status
Simulation time 6555089813 ps
CPU time 118.7 seconds
Started Jul 14 07:44:14 PM PDT 24
Finished Jul 14 07:46:13 PM PDT 24
Peak memory 574176 kb
Host smart-2510d2e9-b2fe-49c2-bf9f-79374b26fe7c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303655298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.1303655298
Directory /workspace/98.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.4233309260
Short name T2346
Test name
Test status
Simulation time 42691882 ps
CPU time 6.14 seconds
Started Jul 14 07:44:12 PM PDT 24
Finished Jul 14 07:44:19 PM PDT 24
Peak memory 575316 kb
Host smart-c201d875-66ba-4c18-bc47-1ebd62563263
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233309260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay
s.4233309260
Directory /workspace/98.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all.3352172563
Short name T588
Test name
Test status
Simulation time 3390570407 ps
CPU time 152.08 seconds
Started Jul 14 07:44:20 PM PDT 24
Finished Jul 14 07:46:52 PM PDT 24
Peak memory 575484 kb
Host smart-e00e58b6-9d7c-4856-8a38-121aec970392
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352172563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.3352172563
Directory /workspace/98.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.80814833
Short name T2545
Test name
Test status
Simulation time 9761131953 ps
CPU time 364.31 seconds
Started Jul 14 07:44:19 PM PDT 24
Finished Jul 14 07:50:24 PM PDT 24
Peak memory 575556 kb
Host smart-e9af224d-e6d6-4b3c-b549-82ca83a628f7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80814833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.80814833
Directory /workspace/98.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.3219899796
Short name T2201
Test name
Test status
Simulation time 316993402 ps
CPU time 103.57 seconds
Started Jul 14 07:44:23 PM PDT 24
Finished Jul 14 07:46:07 PM PDT 24
Peak memory 575436 kb
Host smart-7f72e466-2838-4044-b8e0-304be22e1aca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219899796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all
_with_rand_reset.3219899796
Directory /workspace/98.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.197841975
Short name T875
Test name
Test status
Simulation time 3801014927 ps
CPU time 434.96 seconds
Started Jul 14 07:44:23 PM PDT 24
Finished Jul 14 07:51:38 PM PDT 24
Peak memory 575568 kb
Host smart-bda21c34-dcea-4d0c-a1bb-43b178b530e7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197841975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all
_with_reset_error.197841975
Directory /workspace/98.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.1113512515
Short name T1407
Test name
Test status
Simulation time 392960701 ps
CPU time 20.31 seconds
Started Jul 14 07:44:20 PM PDT 24
Finished Jul 14 07:44:41 PM PDT 24
Peak memory 575424 kb
Host smart-bebc3e7b-6c7c-432f-978d-c49ee900d72a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113512515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.1113512515
Directory /workspace/98.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_access_same_device.2663132442
Short name T1473
Test name
Test status
Simulation time 70652644 ps
CPU time 7.98 seconds
Started Jul 14 07:44:20 PM PDT 24
Finished Jul 14 07:44:29 PM PDT 24
Peak memory 574040 kb
Host smart-79a33927-c701-4d5f-a064-2483fa72f836
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663132442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device
.2663132442
Directory /workspace/99.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.2204856417
Short name T2768
Test name
Test status
Simulation time 21526061010 ps
CPU time 339.58 seconds
Started Jul 14 07:44:25 PM PDT 24
Finished Jul 14 07:50:05 PM PDT 24
Peak memory 575416 kb
Host smart-e3ce6911-0dc3-4b62-8293-179cbb27768e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204856417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_
device_slow_rsp.2204856417
Directory /workspace/99.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.547211843
Short name T1947
Test name
Test status
Simulation time 112041011 ps
CPU time 13.8 seconds
Started Jul 14 07:44:26 PM PDT 24
Finished Jul 14 07:44:40 PM PDT 24
Peak memory 575296 kb
Host smart-cb11abf7-69ba-4288-bac5-5aa4a9fa90f0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547211843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_addr
.547211843
Directory /workspace/99.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_error_random.3141092098
Short name T1815
Test name
Test status
Simulation time 212429351 ps
CPU time 17.56 seconds
Started Jul 14 07:44:22 PM PDT 24
Finished Jul 14 07:44:40 PM PDT 24
Peak memory 575336 kb
Host smart-5219f2bf-1875-49b5-b2ae-8edeb98f6579
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141092098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.3141092098
Directory /workspace/99.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random.1432374529
Short name T2690
Test name
Test status
Simulation time 511501870 ps
CPU time 37.89 seconds
Started Jul 14 07:44:20 PM PDT 24
Finished Jul 14 07:44:58 PM PDT 24
Peak memory 575328 kb
Host smart-b520e1da-37d1-46be-ab14-ccb2da858fd3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432374529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.1432374529
Directory /workspace/99.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.4265610356
Short name T2044
Test name
Test status
Simulation time 5395151011 ps
CPU time 62.24 seconds
Started Jul 14 07:44:22 PM PDT 24
Finished Jul 14 07:45:25 PM PDT 24
Peak memory 574240 kb
Host smart-6a3ea806-1623-4fe3-9b0c-fcd1d4aa4e7a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265610356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.4265610356
Directory /workspace/99.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.1430798612
Short name T2258
Test name
Test status
Simulation time 50191361581 ps
CPU time 1078.85 seconds
Started Jul 14 07:44:20 PM PDT 24
Finished Jul 14 08:02:20 PM PDT 24
Peak memory 575448 kb
Host smart-9480b612-f6a0-4130-a9c3-ec201186c763
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430798612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.1430798612
Directory /workspace/99.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.3605444307
Short name T2170
Test name
Test status
Simulation time 182978630 ps
CPU time 18.4 seconds
Started Jul 14 07:44:21 PM PDT 24
Finished Jul 14 07:44:39 PM PDT 24
Peak memory 575348 kb
Host smart-7f97792b-4f62-4766-b021-cdc3321559cb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605444307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del
ays.3605444307
Directory /workspace/99.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_same_source.1751333095
Short name T1523
Test name
Test status
Simulation time 1920836139 ps
CPU time 59.06 seconds
Started Jul 14 07:44:25 PM PDT 24
Finished Jul 14 07:45:25 PM PDT 24
Peak memory 575380 kb
Host smart-e635e0c7-c1f7-49ea-9198-01681c198921
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751333095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.1751333095
Directory /workspace/99.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke.1971287322
Short name T1460
Test name
Test status
Simulation time 52295246 ps
CPU time 6.26 seconds
Started Jul 14 07:44:26 PM PDT 24
Finished Jul 14 07:44:32 PM PDT 24
Peak memory 574048 kb
Host smart-9ff4478b-9032-4503-b277-0c0184ecda40
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971287322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.1971287322
Directory /workspace/99.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.3655095510
Short name T1576
Test name
Test status
Simulation time 8307762016 ps
CPU time 86.55 seconds
Started Jul 14 07:44:25 PM PDT 24
Finished Jul 14 07:45:51 PM PDT 24
Peak memory 574120 kb
Host smart-a0f96317-189e-4a12-9c5b-a168c9ea2b9f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655095510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.3655095510
Directory /workspace/99.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.2207150187
Short name T2593
Test name
Test status
Simulation time 6560658095 ps
CPU time 122.75 seconds
Started Jul 14 07:44:24 PM PDT 24
Finished Jul 14 07:46:27 PM PDT 24
Peak memory 575436 kb
Host smart-1c8a6f1a-be7f-49b9-99f5-9ddcc9bd7234
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207150187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.2207150187
Directory /workspace/99.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.928734098
Short name T582
Test name
Test status
Simulation time 47725273 ps
CPU time 5.91 seconds
Started Jul 14 07:44:20 PM PDT 24
Finished Jul 14 07:44:26 PM PDT 24
Peak memory 575256 kb
Host smart-83fada5e-94c2-4eff-b2fe-f3f13a27311b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928734098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delays
.928734098
Directory /workspace/99.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all.1927460208
Short name T538
Test name
Test status
Simulation time 13468102701 ps
CPU time 613.13 seconds
Started Jul 14 07:44:27 PM PDT 24
Finished Jul 14 07:54:40 PM PDT 24
Peak memory 575600 kb
Host smart-189682a3-faf7-47a7-bea5-f00ba0097900
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927460208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.1927460208
Directory /workspace/99.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.278406567
Short name T2203
Test name
Test status
Simulation time 3738110990 ps
CPU time 298 seconds
Started Jul 14 07:44:25 PM PDT 24
Finished Jul 14 07:49:23 PM PDT 24
Peak memory 575464 kb
Host smart-23853bcb-0654-4aa5-b08d-2aa884b369cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278406567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.278406567
Directory /workspace/99.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.2369255916
Short name T2578
Test name
Test status
Simulation time 295576980 ps
CPU time 88.14 seconds
Started Jul 14 07:44:27 PM PDT 24
Finished Jul 14 07:45:55 PM PDT 24
Peak memory 575484 kb
Host smart-91f7fd6c-1f30-4427-acb4-7f255809043c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369255916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all
_with_rand_reset.2369255916
Directory /workspace/99.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.2410364335
Short name T2522
Test name
Test status
Simulation time 6469810135 ps
CPU time 364.94 seconds
Started Jul 14 07:44:27 PM PDT 24
Finished Jul 14 07:50:32 PM PDT 24
Peak memory 575612 kb
Host smart-42940dd0-4631-4d24-a741-ae594132401c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410364335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_al
l_with_reset_error.2410364335
Directory /workspace/99.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.3353580490
Short name T2454
Test name
Test status
Simulation time 290414570 ps
CPU time 36.21 seconds
Started Jul 14 07:44:19 PM PDT 24
Finished Jul 14 07:44:56 PM PDT 24
Peak memory 575396 kb
Host smart-ec5d28f8-a3e2-470a-9ee9-5276e9139669
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353580490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.3353580490
Directory /workspace/99.xbar_unmapped_addr/latest

Test location /workspace/coverage/default/0.chip_jtag_csr_rw.3067705380
Short name T88
Test name
Test status
Simulation time 10291584975 ps
CPU time 1115.93 seconds
Started Jul 14 07:46:05 PM PDT 24
Finished Jul 14 08:04:41 PM PDT 24
Peak memory 607300 kb
Host smart-1a54710d-1eba-41b0-98b7-e004dc0ca330
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067705380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c
hip_jtag_csr_rw.3067705380
Directory /workspace/0.chip_jtag_csr_rw/latest

Test location /workspace/coverage/default/0.chip_jtag_mem_access.3820184925
Short name T79
Test name
Test status
Simulation time 12977370610 ps
CPU time 1572.89 seconds
Started Jul 14 07:46:04 PM PDT 24
Finished Jul 14 08:12:18 PM PDT 24
Peak memory 607276 kb
Host smart-324e773c-ed1f-4f9a-9cd4-2827ddaa4d3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820184925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_
mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.3
820184925
Directory /workspace/0.chip_jtag_mem_access/latest

Test location /workspace/coverage/default/0.chip_sival_flash_info_access.841198485
Short name T1006
Test name
Test status
Simulation time 3709572860 ps
CPU time 376.21 seconds
Started Jul 14 07:52:07 PM PDT 24
Finished Jul 14 07:58:24 PM PDT 24
Peak memory 608700 kb
Host smart-b8cec0ce-3217-4d41-9b44-3fe0c753ba49
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=841198485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.841198485
Directory /workspace/0.chip_sival_flash_info_access/latest

Test location /workspace/coverage/default/0.chip_sw_aes_enc.1331362060
Short name T994
Test name
Test status
Simulation time 2807994976 ps
CPU time 305.37 seconds
Started Jul 14 07:52:15 PM PDT 24
Finished Jul 14 07:57:22 PM PDT 24
Peak memory 608656 kb
Host smart-069a8c46-9c29-44f9-8d71-83c4d1fe49e3
User root
Command /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331362060 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.1331362060
Directory /workspace/0.chip_sw_aes_enc/latest

Test location /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.4122599430
Short name T1309
Test name
Test status
Simulation time 3172901557 ps
CPU time 230.61 seconds
Started Jul 14 07:54:04 PM PDT 24
Finished Jul 14 07:57:55 PM PDT 24
Peak memory 608692 kb
Host smart-e744b4d2-7aea-40d2-810d-5cd0094ff4d5
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122
599430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.4122599430
Directory /workspace/0.chip_sw_aes_enc_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.499852496
Short name T1028
Test name
Test status
Simulation time 3689536439 ps
CPU time 328.3 seconds
Started Jul 14 08:00:58 PM PDT 24
Finished Jul 14 08:06:28 PM PDT 24
Peak memory 609172 kb
Host smart-a70b84fc-f6b8-49e0-808c-07f177fb2fdb
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=499852496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.499852496
Directory /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_aes_entropy.3026945283
Short name T979
Test name
Test status
Simulation time 3010735200 ps
CPU time 250.31 seconds
Started Jul 14 07:54:28 PM PDT 24
Finished Jul 14 07:58:39 PM PDT 24
Peak memory 608648 kb
Host smart-23fa7057-575d-449d-a188-e92889b8b122
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026945283 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.3026945283
Directory /workspace/0.chip_sw_aes_entropy/latest

Test location /workspace/coverage/default/0.chip_sw_aes_idle.1398827465
Short name T1173
Test name
Test status
Simulation time 2063057948 ps
CPU time 190.04 seconds
Started Jul 14 07:52:05 PM PDT 24
Finished Jul 14 07:55:16 PM PDT 24
Peak memory 608604 kb
Host smart-ccca7f32-cd69-4763-9b72-d5bf7d473e3f
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398827465 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.1398827465
Directory /workspace/0.chip_sw_aes_idle/latest

Test location /workspace/coverage/default/0.chip_sw_aes_masking_off.4092498251
Short name T296
Test name
Test status
Simulation time 3135875272 ps
CPU time 356.92 seconds
Started Jul 14 07:53:15 PM PDT 24
Finished Jul 14 07:59:12 PM PDT 24
Peak memory 609640 kb
Host smart-30ce2998-4916-4f63-8b83-eb5b437ab02a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092498251 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.4092498251
Directory /workspace/0.chip_sw_aes_masking_off/latest

Test location /workspace/coverage/default/0.chip_sw_aes_smoketest.3953429010
Short name T1131
Test name
Test status
Simulation time 3127370400 ps
CPU time 286.73 seconds
Started Jul 14 07:57:32 PM PDT 24
Finished Jul 14 08:02:19 PM PDT 24
Peak memory 609220 kb
Host smart-3713d256-aca5-48d6-afb0-79f6143e0650
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953429010 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_aes_smoketest.3953429010
Directory /workspace/0.chip_sw_aes_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_entropy.362805135
Short name T159
Test name
Test status
Simulation time 3176560192 ps
CPU time 230.48 seconds
Started Jul 14 07:53:29 PM PDT 24
Finished Jul 14 07:57:20 PM PDT 24
Peak memory 609232 kb
Host smart-568af98c-4fc5-4628-8822-256805e25d1c
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=362805135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.362805135
Directory /workspace/0.chip_sw_alert_handler_entropy/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_escalation.670105915
Short name T1164
Test name
Test status
Simulation time 4796821104 ps
CPU time 499.93 seconds
Started Jul 14 07:52:38 PM PDT 24
Finished Jul 14 08:00:58 PM PDT 24
Peak memory 618764 kb
Host smart-76328112-7e8d-4ab5-8101-6494179bbaa6
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=670105915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.670105915
Directory /workspace/0.chip_sw_alert_handler_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2739429466
Short name T404
Test name
Test status
Simulation time 7292531250 ps
CPU time 1876.81 seconds
Started Jul 14 07:55:34 PM PDT 24
Finished Jul 14 08:26:52 PM PDT 24
Peak memory 609672 kb
Host smart-1ac51ec7-5948-41b1-8394-5f9c79435386
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2739429466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.2739429466
Directory /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.33767677
Short name T1231
Test name
Test status
Simulation time 6968970696 ps
CPU time 1539.01 seconds
Started Jul 14 07:52:31 PM PDT 24
Finished Jul 14 08:18:11 PM PDT 24
Peak memory 609504 kb
Host smart-7c026110-4e2a-4f1f-9269-b0ba4d348b9d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=33767677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_toggle.33767677
Directory /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.2055587502
Short name T1258
Test name
Test status
Simulation time 8015345708 ps
CPU time 1448.41 seconds
Started Jul 14 07:54:45 PM PDT 24
Finished Jul 14 08:18:55 PM PDT 24
Peak memory 608636 kb
Host smart-1f4d3887-d5cd-421c-8b4a-05592c74b63a
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=2055587502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.2055587502
Directory /workspace/0.chip_sw_alert_handler_ping_ok/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.4291795167
Short name T750
Test name
Test status
Simulation time 5098937182 ps
CPU time 532.22 seconds
Started Jul 14 07:54:21 PM PDT 24
Finished Jul 14 08:03:14 PM PDT 24
Peak memory 609796 kb
Host smart-966b3ecb-5f9e-4b6c-a517-a364d9371440
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4291795167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.4291795167
Directory /workspace/0.chip_sw_alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3633687541
Short name T102
Test name
Test status
Simulation time 256090613184 ps
CPU time 13660.1 seconds
Started Jul 14 07:53:57 PM PDT 24
Finished Jul 14 11:41:39 PM PDT 24
Peak memory 609900 kb
Host smart-a2f2e585-8985-4f22-a1ee-1b0144f07b2c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633687541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3633687541
Directory /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location /workspace/coverage/default/0.chip_sw_alert_test.4040726291
Short name T67
Test name
Test status
Simulation time 2831400786 ps
CPU time 364.97 seconds
Started Jul 14 07:56:05 PM PDT 24
Finished Jul 14 08:02:10 PM PDT 24
Peak memory 608680 kb
Host smart-b4bbd5f9-ed15-46f9-bfd9-726875647b5e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040726291 -assert nopostproc +UVM_TESTNAME=chip_ba
se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.chip_sw_alert_test.4040726291
Directory /workspace/0.chip_sw_alert_test/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_irq.504253583
Short name T344
Test name
Test status
Simulation time 3819870262 ps
CPU time 441.65 seconds
Started Jul 14 07:53:17 PM PDT 24
Finished Jul 14 08:00:39 PM PDT 24
Peak memory 608708 kb
Host smart-6d0dc27a-8c84-4e3b-9d59-b1a6fb6f1192
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504253583 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.504253583
Directory /workspace/0.chip_sw_aon_timer_irq/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3538291272
Short name T1142
Test name
Test status
Simulation time 7083455480 ps
CPU time 513.5 seconds
Started Jul 14 07:55:38 PM PDT 24
Finished Jul 14 08:04:12 PM PDT 24
Peak memory 608624 kb
Host smart-89a8b234-f5af-4e9d-bc2b-84e19c141cc5
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3538291272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3538291272
Directory /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3264870180
Short name T1082
Test name
Test status
Simulation time 3348192776 ps
CPU time 405.76 seconds
Started Jul 14 07:56:36 PM PDT 24
Finished Jul 14 08:03:22 PM PDT 24
Peak memory 609028 kb
Host smart-106d3bd1-63a8-4f33-8f50-aff57617e71d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264870180 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.chip_sw_aon_timer_smoketest.3264870180
Directory /workspace/0.chip_sw_aon_timer_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.68182427
Short name T903
Test name
Test status
Simulation time 9261869080 ps
CPU time 919.43 seconds
Started Jul 14 07:54:09 PM PDT 24
Finished Jul 14 08:09:29 PM PDT 24
Peak memory 609984 kb
Host smart-124c9913-7c8e-4396-83d9-8b20e806ec8f
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
68182427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.68182427
Directory /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest

Test location /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3261346357
Short name T1174
Test name
Test status
Simulation time 5394545768 ps
CPU time 674.32 seconds
Started Jul 14 07:53:20 PM PDT 24
Finished Jul 14 08:04:35 PM PDT 24
Peak memory 610172 kb
Host smart-684e77c1-5c8c-4ea0-ba42-ca5c295cb1ba
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3261346357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.3261346357
Directory /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location /workspace/coverage/default/0.chip_sw_ast_clk_outputs.2559968987
Short name T737
Test name
Test status
Simulation time 8576996132 ps
CPU time 1129.66 seconds
Started Jul 14 07:53:15 PM PDT 24
Finished Jul 14 08:12:05 PM PDT 24
Peak memory 616556 kb
Host smart-ca34c891-95de-4428-92a7-6403320fdac4
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559968987 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.2559968987
Directory /workspace/0.chip_sw_ast_clk_outputs/latest

Test location /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.240393083
Short name T136
Test name
Test status
Simulation time 19823428051 ps
CPU time 3062.86 seconds
Started Jul 14 08:02:32 PM PDT 24
Finished Jul 14 08:53:36 PM PDT 24
Peak memory 609972 kb
Host smart-4b34c830-42e1-4cae-a153-4c6d1556d653
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240393083 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.240393083
Directory /workspace/0.chip_sw_ast_clk_rst_inputs/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2450208771
Short name T314
Test name
Test status
Simulation time 12596234824 ps
CPU time 806.82 seconds
Started Jul 14 07:53:53 PM PDT 24
Finished Jul 14 08:07:21 PM PDT 24
Peak memory 621176 kb
Host smart-7cd0ec08-0979-4f09-b1ae-90c5abb49def
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=2450208771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.2450208771
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2821950791
Short name T1103
Test name
Test status
Simulation time 3716527430 ps
CPU time 682.86 seconds
Started Jul 14 07:54:17 PM PDT 24
Finished Jul 14 08:05:40 PM PDT 24
Peak memory 612316 kb
Host smart-0d00f002-108b-4b27-8634-e6ae52fa1fdf
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821950791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_dev.2821950791
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4134887441
Short name T118
Test name
Test status
Simulation time 3843705880 ps
CPU time 644.07 seconds
Started Jul 14 07:55:59 PM PDT 24
Finished Jul 14 08:06:44 PM PDT 24
Peak memory 612068 kb
Host smart-48c5d65b-b75e-4e86-a365-e44435579487
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134887441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4134887441
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.545931589
Short name T1141
Test name
Test status
Simulation time 4078329580 ps
CPU time 691.46 seconds
Started Jul 14 07:53:16 PM PDT 24
Finished Jul 14 08:04:49 PM PDT 24
Peak memory 611120 kb
Host smart-160d77c6-6725-42b7-b378-e6d499fd3cee
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545931589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl
kmgr_external_clk_src_for_sw_slow_dev.545931589
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2639305571
Short name T893
Test name
Test status
Simulation time 4534355850 ps
CPU time 625.56 seconds
Started Jul 14 07:54:19 PM PDT 24
Finished Jul 14 08:04:45 PM PDT 24
Peak memory 612360 kb
Host smart-129dd498-ec21-4bb6-a270-a0fb9c13dda5
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639305571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_rma.2639305571
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2943040950
Short name T1195
Test name
Test status
Simulation time 4838685640 ps
CPU time 769.47 seconds
Started Jul 14 07:54:12 PM PDT 24
Finished Jul 14 08:07:03 PM PDT 24
Peak memory 612060 kb
Host smart-969fe974-cd71-4acd-b1ba-e611d094f206
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943040950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2943040950
Directory /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_jitter.637914732
Short name T883
Test name
Test status
Simulation time 3650264724 ps
CPU time 266.35 seconds
Started Jul 14 07:54:59 PM PDT 24
Finished Jul 14 07:59:26 PM PDT 24
Peak memory 608680 kb
Host smart-e83bb8ed-3651-4e17-879a-1495c91436d7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637914732 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_clkmgr_jitter.637914732
Directory /workspace/0.chip_sw_clkmgr_jitter/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1923897200
Short name T880
Test name
Test status
Simulation time 2805694780 ps
CPU time 337.31 seconds
Started Jul 14 07:55:49 PM PDT 24
Finished Jul 14 08:01:27 PM PDT 24
Peak memory 609192 kb
Host smart-ea1bb347-e8f6-433e-8398-8a2acc7f0f95
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923897200 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.1923897200
Directory /workspace/0.chip_sw_clkmgr_jitter_frequency/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1409910716
Short name T922
Test name
Test status
Simulation time 3400505955 ps
CPU time 234.15 seconds
Started Jul 14 07:56:14 PM PDT 24
Finished Jul 14 08:00:09 PM PDT 24
Peak memory 608660 kb
Host smart-f74bd641-a9a5-49db-b6e2-99b00cfe1766
User root
Command /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409910716 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.1409910716
Directory /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3896690884
Short name T954
Test name
Test status
Simulation time 3577888440 ps
CPU time 358.35 seconds
Started Jul 14 07:55:08 PM PDT 24
Finished Jul 14 08:01:07 PM PDT 24
Peak memory 608700 kb
Host smart-e8d0f034-d314-4a44-9d8c-3ae730065133
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896690884 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.3896690884
Directory /workspace/0.chip_sw_clkmgr_off_aes_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2405539746
Short name T1127
Test name
Test status
Simulation time 4837315208 ps
CPU time 354.31 seconds
Started Jul 14 07:56:00 PM PDT 24
Finished Jul 14 08:01:55 PM PDT 24
Peak memory 609720 kb
Host smart-5de0b51b-99fd-4350-8f6c-b60e01af7049
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405539746 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.2405539746
Directory /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1718356197
Short name T1044
Test name
Test status
Simulation time 4659729168 ps
CPU time 536.86 seconds
Started Jul 14 08:01:07 PM PDT 24
Finished Jul 14 08:10:05 PM PDT 24
Peak memory 608516 kb
Host smart-38b91d74-b126-464f-9569-3395098d2682
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718356197 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.1718356197
Directory /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.264683394
Short name T1050
Test name
Test status
Simulation time 5682162718 ps
CPU time 562.57 seconds
Started Jul 14 07:58:09 PM PDT 24
Finished Jul 14 08:07:32 PM PDT 24
Peak memory 609724 kb
Host smart-3087cc2e-a24a-4ca9-83f4-9428436093e4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264683394 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.264683394
Directory /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1008319996
Short name T105
Test name
Test status
Simulation time 10804773502 ps
CPU time 1407.99 seconds
Started Jul 14 07:55:10 PM PDT 24
Finished Jul 14 08:18:40 PM PDT 24
Peak memory 610064 kb
Host smart-019827ea-a8f0-43aa-9400-2d8ba00184a3
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008319996
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.1008319996
Directory /workspace/0.chip_sw_clkmgr_off_peri/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1560930273
Short name T1286
Test name
Test status
Simulation time 3042858028 ps
CPU time 442.2 seconds
Started Jul 14 07:54:48 PM PDT 24
Finished Jul 14 08:02:11 PM PDT 24
Peak memory 609232 kb
Host smart-7b1432f7-b004-410b-951e-e910ee546e02
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560930273 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.1560930273
Directory /workspace/0.chip_sw_clkmgr_reset_frequency/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3030043548
Short name T1136
Test name
Test status
Simulation time 4444244656 ps
CPU time 628.31 seconds
Started Jul 14 07:55:58 PM PDT 24
Finished Jul 14 08:06:27 PM PDT 24
Peak memory 609564 kb
Host smart-68d12a98-7685-433a-9a82-c55315c3a2f0
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030043548 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.3030043548
Directory /workspace/0.chip_sw_clkmgr_sleep_frequency/latest

Test location /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2953531744
Short name T1240
Test name
Test status
Simulation time 2378233590 ps
CPU time 153.8 seconds
Started Jul 14 07:54:39 PM PDT 24
Finished Jul 14 07:57:14 PM PDT 24
Peak memory 609152 kb
Host smart-e843797d-87ef-48ae-9bf6-5f131007a130
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953531744 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.chip_sw_clkmgr_smoketest.2953531744
Directory /workspace/0.chip_sw_clkmgr_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_coremark.2700448731
Short name T985
Test name
Test status
Simulation time 71998019224 ps
CPU time 14543.2 seconds
Started Jul 14 07:53:58 PM PDT 24
Finished Jul 14 11:56:24 PM PDT 24
Peak memory 609464 kb
Host smart-de4e5eaf-05ff-4dc9-9eec-5dc10916fdd2
User root
Command /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2700448731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.2700448731
Directory /workspace/0.chip_sw_coremark/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3771170901
Short name T1079
Test name
Test status
Simulation time 23284688160 ps
CPU time 5115.77 seconds
Started Jul 14 07:57:00 PM PDT 24
Finished Jul 14 09:22:18 PM PDT 24
Peak memory 609996 kb
Host smart-072884b1-0d6a-4076-9949-565d50c262c3
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c
oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771170901 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.3771170901
Directory /workspace/0.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1202189984
Short name T184
Test name
Test status
Simulation time 4726005100 ps
CPU time 585.75 seconds
Started Jul 14 07:56:26 PM PDT 24
Finished Jul 14 08:06:13 PM PDT 24
Peak memory 608776 kb
Host smart-94a251c4-e527-45fe-82a2-faf34c54cdf6
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12021
89984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.1202189984
Directory /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_kat_test.3331459745
Short name T1219
Test name
Test status
Simulation time 2547559288 ps
CPU time 247.31 seconds
Started Jul 14 07:52:19 PM PDT 24
Finished Jul 14 07:56:27 PM PDT 24
Peak memory 608676 kb
Host smart-7346f7f3-82c6-4ff2-a144-a5965d3bc6bc
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331459745 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.3331459745
Directory /workspace/0.chip_sw_csrng_kat_test/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2006111479
Short name T1025
Test name
Test status
Simulation time 8165805770 ps
CPU time 878.42 seconds
Started Jul 14 07:54:33 PM PDT 24
Finished Jul 14 08:09:14 PM PDT 24
Peak memory 610688 kb
Host smart-f680976b-2eb7-4896-a31c-975d2a0febcf
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima
ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006111479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_
lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr
ng_lc_hw_debug_en_test.2006111479
Directory /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location /workspace/coverage/default/0.chip_sw_csrng_smoketest.2107003791
Short name T993
Test name
Test status
Simulation time 2690872660 ps
CPU time 239.94 seconds
Started Jul 14 07:57:30 PM PDT 24
Finished Jul 14 08:01:31 PM PDT 24
Peak memory 609004 kb
Host smart-ea8c4ec5-25ea-4319-819b-817926948e1d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107003791 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.chip_sw_csrng_smoketest.2107003791
Directory /workspace/0.chip_sw_csrng_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_data_integrity_escalation.193514425
Short name T277
Test name
Test status
Simulation time 5834821842 ps
CPU time 894.58 seconds
Started Jul 14 07:54:47 PM PDT 24
Finished Jul 14 08:09:43 PM PDT 24
Peak memory 610276 kb
Host smart-fe4e1229-e51d-4509-a7e8-e7e4b82775c8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=193514425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.193514425
Directory /workspace/0.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2082590274
Short name T1020
Test name
Test status
Simulation time 7229714340 ps
CPU time 1027.03 seconds
Started Jul 14 07:56:05 PM PDT 24
Finished Jul 14 08:13:13 PM PDT 24
Peak memory 610156 kb
Host smart-892f3e57-56d0-4f75-b4b7-49f0eb9eafb4
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed
n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2082590274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.2082590274
Directory /workspace/0.chip_sw_edn_entropy_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_edn_kat.3248338830
Short name T669
Test name
Test status
Simulation time 3605727720 ps
CPU time 752.97 seconds
Started Jul 14 07:54:08 PM PDT 24
Finished Jul 14 08:06:42 PM PDT 24
Peak memory 615032 kb
Host smart-d85eff3b-0cda-4506-9ec1-68b7ff729bbb
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag
es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248338830 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_edn_kat.3248338830
Directory /workspace/0.chip_sw_edn_kat/latest

Test location /workspace/coverage/default/0.chip_sw_edn_sw_mode.2661092202
Short name T403
Test name
Test status
Simulation time 9031347986 ps
CPU time 2124.43 seconds
Started Jul 14 07:56:02 PM PDT 24
Finished Jul 14 08:31:27 PM PDT 24
Peak memory 608676 kb
Host smart-0e199fc1-5855-47ac-90e9-e6f4db629e78
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661092202 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.2661092202
Directory /workspace/0.chip_sw_edn_sw_mode/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2201165969
Short name T1296
Test name
Test status
Simulation time 2994362008 ps
CPU time 263.29 seconds
Started Jul 14 07:55:48 PM PDT 24
Finished Jul 14 08:00:12 PM PDT 24
Peak memory 608680 kb
Host smart-4d954338-3a20-4ebb-9ff0-f73235913fff
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22
01165969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.2201165969
Directory /workspace/0.chip_sw_entropy_src_ast_rng_req/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_csrng.1740832235
Short name T331
Test name
Test status
Simulation time 8014170496 ps
CPU time 2103.66 seconds
Started Jul 14 07:53:25 PM PDT 24
Finished Jul 14 08:28:30 PM PDT 24
Peak memory 609928 kb
Host smart-0e3dd64d-002d-401f-b9cf-c878dd217bb9
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_
csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1740832235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.1740832235
Directory /workspace/0.chip_sw_entropy_src_csrng/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2927886721
Short name T1151
Test name
Test status
Simulation time 2715803000 ps
CPU time 303.42 seconds
Started Jul 14 07:54:08 PM PDT 24
Finished Jul 14 07:59:12 PM PDT 24
Peak memory 608652 kb
Host smart-c49228c6-d310-4861-a8fb-f0272562b846
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927886721
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.2927886721
Directory /workspace/0.chip_sw_entropy_src_kat_test/latest

Test location /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1977329000
Short name T1167
Test name
Test status
Simulation time 3282138492 ps
CPU time 443.89 seconds
Started Jul 14 07:57:13 PM PDT 24
Finished Jul 14 08:04:37 PM PDT 24
Peak memory 608676 kb
Host smart-fa3303ed-58b0-4c99-adb3-b7e56fb03322
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1977329000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.1977329000
Directory /workspace/0.chip_sw_entropy_src_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_example_concurrency.789387534
Short name T311
Test name
Test status
Simulation time 3299524264 ps
CPU time 268.06 seconds
Started Jul 14 07:51:29 PM PDT 24
Finished Jul 14 07:55:58 PM PDT 24
Peak memory 609104 kb
Host smart-ab44193a-f87d-4a5b-94ea-2e09c0343fa0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789387534 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_example_concurrency.789387534
Directory /workspace/0.chip_sw_example_concurrency/latest

Test location /workspace/coverage/default/0.chip_sw_example_flash.1459109118
Short name T1074
Test name
Test status
Simulation time 3159332116 ps
CPU time 277.71 seconds
Started Jul 14 07:54:24 PM PDT 24
Finished Jul 14 07:59:03 PM PDT 24
Peak memory 609292 kb
Host smart-7e615d02-0300-4ca6-894d-1d397099c2ba
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459109118 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_example_flash.1459109118
Directory /workspace/0.chip_sw_example_flash/latest

Test location /workspace/coverage/default/0.chip_sw_example_manufacturer.1661289191
Short name T1121
Test name
Test status
Simulation time 2748717888 ps
CPU time 239.1 seconds
Started Jul 14 07:53:02 PM PDT 24
Finished Jul 14 07:57:02 PM PDT 24
Peak memory 608676 kb
Host smart-55b4572a-65e4-4d28-9a16-a5e12ff2fbee
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661289191 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_example_manufacturer.1661289191
Directory /workspace/0.chip_sw_example_manufacturer/latest

Test location /workspace/coverage/default/0.chip_sw_example_rom.2821736949
Short name T899
Test name
Test status
Simulation time 1954369480 ps
CPU time 120.91 seconds
Started Jul 14 07:51:16 PM PDT 24
Finished Jul 14 07:53:18 PM PDT 24
Peak memory 608816 kb
Host smart-4b982398-80fd-4c72-9850-92068dff8b6f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821736949 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_example_rom.2821736949
Directory /workspace/0.chip_sw_example_rom/latest

Test location /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.925363681
Short name T142
Test name
Test status
Simulation time 58393665626 ps
CPU time 11626.4 seconds
Started Jul 14 07:53:03 PM PDT 24
Finished Jul 14 11:06:51 PM PDT 24
Peak memory 624236 kb
Host smart-15963d5d-26eb-4ec0-ad67-a152bd662f61
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=925363681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.925363681
Directory /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest

Test location /workspace/coverage/default/0.chip_sw_flash_crash_alert.4170460823
Short name T320
Test name
Test status
Simulation time 5268265440 ps
CPU time 555.29 seconds
Started Jul 14 07:54:53 PM PDT 24
Finished Jul 14 08:04:09 PM PDT 24
Peak memory 610456 kb
Host smart-e5f51413-6f7c-4456-8b87-7cea55e448e1
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:
new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=4170460823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.4170460823
Directory /workspace/0.chip_sw_flash_crash_alert/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3982205657
Short name T1039
Test name
Test status
Simulation time 6437277304 ps
CPU time 1158 seconds
Started Jul 14 07:51:41 PM PDT 24
Finished Jul 14 08:10:59 PM PDT 24
Peak memory 608672 kb
Host smart-9522bf64-a054-41b6-8833-e26906e04ed9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982205657 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.chip_sw_flash_ctrl_access.3982205657
Directory /workspace/0.chip_sw_flash_ctrl_access/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.800658957
Short name T422
Test name
Test status
Simulation time 6311695273 ps
CPU time 1102.44 seconds
Started Jul 14 07:51:29 PM PDT 24
Finished Jul 14 08:09:52 PM PDT 24
Peak memory 608692 kb
Host smart-e7132323-c25e-4251-a324-f4dec4632c51
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800658957 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.800658957
Directory /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.591790272
Short name T1169
Test name
Test status
Simulation time 6710438316 ps
CPU time 891.45 seconds
Started Jul 14 07:53:33 PM PDT 24
Finished Jul 14 08:08:25 PM PDT 24
Peak memory 608672 kb
Host smart-feeab4fe-2dd4-4e73-b06c-cfe0a5a6048c
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591790272 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.591790272
Directory /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2008170447
Short name T1116
Test name
Test status
Simulation time 5881934132 ps
CPU time 1159.81 seconds
Started Jul 14 07:54:45 PM PDT 24
Finished Jul 14 08:14:06 PM PDT 24
Peak memory 609424 kb
Host smart-b6cb2d98-152c-4fbc-b1f9-3af5f2b7339d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008170447 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.2008170447
Directory /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.4058318627
Short name T1203
Test name
Test status
Simulation time 3033936710 ps
CPU time 352.17 seconds
Started Jul 14 07:55:38 PM PDT 24
Finished Jul 14 08:01:32 PM PDT 24
Peak memory 609160 kb
Host smart-cfbd91ab-0cbf-4963-8bdd-1d195022d22f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058318627 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.4058318627
Directory /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.4120558300
Short name T463
Test name
Test status
Simulation time 5683507560 ps
CPU time 582.96 seconds
Started Jul 14 07:51:58 PM PDT 24
Finished Jul 14 08:01:42 PM PDT 24
Peak memory 610068 kb
Host smart-dd239791-58da-42eb-8274-6d28c8afe5af
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41
20558300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.4120558300
Directory /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2321894014
Short name T999
Test name
Test status
Simulation time 5761990996 ps
CPU time 1203.31 seconds
Started Jul 14 07:59:59 PM PDT 24
Finished Jul 14 08:20:03 PM PDT 24
Peak memory 609496 kb
Host smart-e7603e77-5684-4c31-b3df-43120a4a2d64
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321894014 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.2321894014
Directory /workspace/0.chip_sw_flash_ctrl_mem_protection/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1803706555
Short name T1216
Test name
Test status
Simulation time 3947633415 ps
CPU time 697.48 seconds
Started Jul 14 07:53:48 PM PDT 24
Finished Jul 14 08:05:27 PM PDT 24
Peak memory 609464 kb
Host smart-ffbbe281-c1b2-48b3-a362-3bf14da4d1fa
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1803706555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.1803706555
Directory /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1984696709
Short name T348
Test name
Test status
Simulation time 5266067708 ps
CPU time 795.77 seconds
Started Jul 14 07:55:37 PM PDT 24
Finished Jul 14 08:08:54 PM PDT 24
Peak memory 609868 kb
Host smart-79828585-5c55-45df-9a76-ddb31661db39
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_
rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1984696709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1984696709
Directory /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1322014183
Short name T430
Test name
Test status
Simulation time 2956526040 ps
CPU time 358.07 seconds
Started Jul 14 07:57:50 PM PDT 24
Finished Jul 14 08:03:49 PM PDT 24
Peak memory 607812 kb
Host smart-1a5fe0ce-cdaa-4576-9fe6-4cad9e4cde1e
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322014
183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.1322014183
Directory /workspace/0.chip_sw_flash_ctrl_write_clear/latest

Test location /workspace/coverage/default/0.chip_sw_flash_init.1020543378
Short name T229
Test name
Test status
Simulation time 20561746177 ps
CPU time 2052.12 seconds
Started Jul 14 07:51:00 PM PDT 24
Finished Jul 14 08:25:13 PM PDT 24
Peak memory 611764 kb
Host smart-5694cf5e-45ad-4c9f-8bed-f7450fa477c1
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020543378 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.1020543378
Directory /workspace/0.chip_sw_flash_init/latest

Test location /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3236821347
Short name T1011
Test name
Test status
Simulation time 2666734524 ps
CPU time 217.86 seconds
Started Jul 14 08:00:04 PM PDT 24
Finished Jul 14 08:03:42 PM PDT 24
Peak memory 609020 kb
Host smart-a90ad50e-4a32-416c-b8d9-c8b07cc28a7f
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket
est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3236821347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.3236821347
Directory /workspace/0.chip_sw_flash_scrambling_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_gpio_smoketest.4147074122
Short name T94
Test name
Test status
Simulation time 3193396651 ps
CPU time 238.6 seconds
Started Jul 14 07:57:45 PM PDT 24
Finished Jul 14 08:01:44 PM PDT 24
Peak memory 609580 kb
Host smart-963f0fd8-8767-46ac-9bf0-938c1cb21f79
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147074122 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_sw_gpio_smoketest.4147074122
Directory /workspace/0.chip_sw_gpio_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc_idle.2183553310
Short name T929
Test name
Test status
Simulation time 3326082712 ps
CPU time 328.32 seconds
Started Jul 14 07:54:00 PM PDT 24
Finished Jul 14 07:59:28 PM PDT 24
Peak memory 609184 kb
Host smart-4929950f-e3b8-4c17-892a-d801431afd25
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183553310 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_hmac_enc_idle.2183553310
Directory /workspace/0.chip_sw_hmac_enc_idle/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.601399571
Short name T1143
Test name
Test status
Simulation time 3415647635 ps
CPU time 266.67 seconds
Started Jul 14 07:53:46 PM PDT 24
Finished Jul 14 07:58:13 PM PDT 24
Peak memory 608696 kb
Host smart-f0047734-3577-4e18-b3be-35af16ef8a0b
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601399571 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.601399571
Directory /workspace/0.chip_sw_hmac_enc_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1207129274
Short name T312
Test name
Test status
Simulation time 3511517100 ps
CPU time 287.53 seconds
Started Jul 14 07:57:14 PM PDT 24
Finished Jul 14 08:02:03 PM PDT 24
Peak memory 608664 kb
Host smart-7df2fdec-e985-468d-8a54-610aa394d63f
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207129274 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.1207129274
Directory /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_multistream.2437989331
Short name T704
Test name
Test status
Simulation time 8184483216 ps
CPU time 1961.33 seconds
Started Jul 14 07:57:05 PM PDT 24
Finished Jul 14 08:29:47 PM PDT 24
Peak memory 608296 kb
Host smart-bf82c113-5416-4c04-aa8c-f40cd95ae16f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437989331 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.chip_sw_hmac_multistream.2437989331
Directory /workspace/0.chip_sw_hmac_multistream/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_oneshot.1758099890
Short name T1108
Test name
Test status
Simulation time 2810613788 ps
CPU time 348.59 seconds
Started Jul 14 07:57:19 PM PDT 24
Finished Jul 14 08:03:08 PM PDT 24
Peak memory 609012 kb
Host smart-3a0bf82f-3045-41b8-bbf7-5753cbaed480
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758099890 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_hmac_oneshot.1758099890
Directory /workspace/0.chip_sw_hmac_oneshot/latest

Test location /workspace/coverage/default/0.chip_sw_hmac_smoketest.1023927695
Short name T424
Test name
Test status
Simulation time 3495963400 ps
CPU time 411.1 seconds
Started Jul 14 07:57:17 PM PDT 24
Finished Jul 14 08:04:09 PM PDT 24
Peak memory 608984 kb
Host smart-3bf747b1-112a-470c-93a2-87ddbe16d355
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023927695 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.chip_sw_hmac_smoketest.1023927695
Directory /workspace/0.chip_sw_hmac_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3209680145
Short name T340
Test name
Test status
Simulation time 3693380520 ps
CPU time 560.53 seconds
Started Jul 14 07:52:45 PM PDT 24
Finished Jul 14 08:02:07 PM PDT 24
Peak memory 609220 kb
Host smart-e4071ef0-9bba-4a81-a83e-4ee650f2823a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209680145 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.3209680145
Directory /workspace/0.chip_sw_i2c_device_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_inject_scramble_seed.641527929
Short name T201
Test name
Test status
Simulation time 64545381774 ps
CPU time 12001.3 seconds
Started Jul 14 07:53:45 PM PDT 24
Finished Jul 14 11:13:50 PM PDT 24
Peak memory 623836 kb
Host smart-721173c7-4535-42e0-ba88-ec1d469b9004
User root
Command /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=641527929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.641527929
Directory /workspace/0.chip_sw_inject_scramble_seed/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1715479308
Short name T1047
Test name
Test status
Simulation time 10676578084 ps
CPU time 2190.99 seconds
Started Jul 14 07:54:17 PM PDT 24
Finished Jul 14 08:30:50 PM PDT 24
Peak memory 616164 kb
Host smart-f0f85f9f-5c40-4976-937b-4717e8384945
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715
479308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.1715479308
Directory /workspace/0.chip_sw_keymgr_key_derivation/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.4262021479
Short name T113
Test name
Test status
Simulation time 6869375175 ps
CPU time 1238.55 seconds
Started Jul 14 07:55:58 PM PDT 24
Finished Jul 14 08:16:37 PM PDT 24
Peak memory 616512 kb
Host smart-40c85fa4-8592-4453-a106-cd7a4659daf1
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4262021479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.4262021479
Directory /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.402717455
Short name T1126
Test name
Test status
Simulation time 12705363922 ps
CPU time 2181.33 seconds
Started Jul 14 07:59:15 PM PDT 24
Finished Jul 14 08:35:37 PM PDT 24
Peak memory 617248 kb
Host smart-67032d91-8ba0-4433-ab07-250bbf11ee92
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=402717455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en_
reduced_freq.402717455
Directory /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1559825033
Short name T454
Test name
Test status
Simulation time 8832155912 ps
CPU time 1915.84 seconds
Started Jul 14 07:54:52 PM PDT 24
Finished Jul 14 08:26:49 PM PDT 24
Peak memory 617216 kb
Host smart-faba211c-689a-454e-a308-5afef1e1c31a
User root
Command /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1559825033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.1559825033
Directory /workspace/0.chip_sw_keymgr_key_derivation_prod/latest

Test location /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3593898054
Short name T453
Test name
Test status
Simulation time 10923322140 ps
CPU time 2305.36 seconds
Started Jul 14 07:52:11 PM PDT 24
Finished Jul 14 08:30:38 PM PDT 24
Peak memory 610396 kb
Host smart-89d048cc-17c0-4599-9ada-aee6c1855ba4
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35938
98054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.3593898054
Directory /workspace/0.chip_sw_keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_app_rom.1180777132
Short name T1085
Test name
Test status
Simulation time 2479535960 ps
CPU time 230.5 seconds
Started Jul 14 07:55:00 PM PDT 24
Finished Jul 14 07:58:51 PM PDT 24
Peak memory 609208 kb
Host smart-530ed116-99d0-48ca-ab5a-5a54f1d24e33
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180777132 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_kmac_app_rom.1180777132
Directory /workspace/0.chip_sw_kmac_app_rom/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_entropy.1357504961
Short name T1080
Test name
Test status
Simulation time 2897418224 ps
CPU time 237.21 seconds
Started Jul 14 07:55:34 PM PDT 24
Finished Jul 14 07:59:32 PM PDT 24
Peak memory 608004 kb
Host smart-22a62de8-8fd0-4eef-9a10-177e9a11380b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357504961 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_kmac_entropy.1357504961
Directory /workspace/0.chip_sw_kmac_entropy/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1040005876
Short name T1182
Test name
Test status
Simulation time 3399516840 ps
CPU time 259.7 seconds
Started Jul 14 07:54:30 PM PDT 24
Finished Jul 14 07:58:50 PM PDT 24
Peak memory 609260 kb
Host smart-de6af5cb-513a-48e1-9978-c08357e2da86
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040005876 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.chip_sw_kmac_mode_cshake.1040005876
Directory /workspace/0.chip_sw_kmac_mode_cshake/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.4063497493
Short name T1279
Test name
Test status
Simulation time 3841007520 ps
CPU time 422.22 seconds
Started Jul 14 07:55:03 PM PDT 24
Finished Jul 14 08:02:06 PM PDT 24
Peak memory 607940 kb
Host smart-1d973735-cf9e-4a16-8242-5b965d76e48e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063497493 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.chip_sw_kmac_mode_kmac.4063497493
Directory /workspace/0.chip_sw_kmac_mode_kmac/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2921390642
Short name T906
Test name
Test status
Simulation time 3157722489 ps
CPU time 311.58 seconds
Started Jul 14 07:53:58 PM PDT 24
Finished Jul 14 07:59:11 PM PDT 24
Peak memory 608664 kb
Host smart-98fc992e-6166-4531-a9ce-ffca8247b36c
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921390642 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.2921390642
Directory /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.800346932
Short name T933
Test name
Test status
Simulation time 3060235481 ps
CPU time 323.09 seconds
Started Jul 14 08:01:31 PM PDT 24
Finished Jul 14 08:06:56 PM PDT 24
Peak memory 608656 kb
Host smart-b5d4a42f-afe1-4177-a0f5-d3088f37f23d
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80034693
2 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.800346932
Directory /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_kmac_smoketest.581087975
Short name T1271
Test name
Test status
Simulation time 2691929200 ps
CPU time 243.46 seconds
Started Jul 14 07:56:44 PM PDT 24
Finished Jul 14 08:00:48 PM PDT 24
Peak memory 609056 kb
Host smart-47afe166-574f-4a30-bbcd-b8e61e595026
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581087975 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_kmac_smoketest.581087975
Directory /workspace/0.chip_sw_kmac_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2734812250
Short name T1243
Test name
Test status
Simulation time 3362926142 ps
CPU time 363.19 seconds
Started Jul 14 07:54:22 PM PDT 24
Finished Jul 14 08:00:26 PM PDT 24
Peak memory 609132 kb
Host smart-1dc29cb0-3a47-4664-9e78-8bdbbc8eff6c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734812250 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.2734812250
Directory /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3302634905
Short name T681
Test name
Test status
Simulation time 3442933458 ps
CPU time 131.75 seconds
Started Jul 14 07:54:26 PM PDT 24
Finished Jul 14 07:56:38 PM PDT 24
Peak memory 619572 kb
Host smart-d93fe066-464f-4e73-845a-46a064f2a151
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33026349
05 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.3302634905
Directory /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.358027364
Short name T682
Test name
Test status
Simulation time 3387927101 ps
CPU time 156.73 seconds
Started Jul 14 07:53:44 PM PDT 24
Finished Jul 14 07:56:22 PM PDT 24
Peak memory 619404 kb
Host smart-d66a2008-5752-482a-8326-16c487a2b32f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules
,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=358027364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.358027364
Directory /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1538549707
Short name T174
Test name
Test status
Simulation time 4138018924 ps
CPU time 313.96 seconds
Started Jul 14 07:54:18 PM PDT 24
Finished Jul 14 07:59:34 PM PDT 24
Peak memory 620340 kb
Host smart-a67137fa-2f10-421d-9360-241ae396bc99
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules
,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1538549707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.1538549707
Directory /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2626218932
Short name T679
Test name
Test status
Simulation time 2354779370 ps
CPU time 139.74 seconds
Started Jul 14 08:00:19 PM PDT 24
Finished Jul 14 08:02:40 PM PDT 24
Peak memory 614400 kb
Host smart-16c3be4a-2f39-4041-907d-d934ee876272
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes
t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2626218932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.2626218932
Directory /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2022056937
Short name T1217
Test name
Test status
Simulation time 2450530175 ps
CPU time 119.84 seconds
Started Jul 14 07:54:06 PM PDT 24
Finished Jul 14 07:56:07 PM PDT 24
Peak memory 617240 kb
Host smart-f9858543-a735-42c1-bb99-d223b836e28f
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s
im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022056937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2022056937
Directory /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.170807466
Short name T1310
Test name
Test status
Simulation time 48705248184 ps
CPU time 6001.79 seconds
Started Jul 14 07:53:40 PM PDT 24
Finished Jul 14 09:33:43 PM PDT 24
Peak memory 619860 kb
Host smart-71bf5d00-c61d-48f9-a323-0aa2d91c7400
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170807466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch
ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_
sw_lc_walkthrough_dev.170807466
Directory /workspace/0.chip_sw_lc_walkthrough_dev/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1743543382
Short name T1263
Test name
Test status
Simulation time 50638661028 ps
CPU time 6049.92 seconds
Started Jul 14 07:53:16 PM PDT 24
Finished Jul 14 09:34:07 PM PDT 24
Peak memory 619576 kb
Host smart-2b7814e0-1a07-4eec-913a-167b139a8a54
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d
evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743543382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi
p_sw_lc_walkthrough_prod.1743543382
Directory /workspace/0.chip_sw_lc_walkthrough_prod/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3328088307
Short name T931
Test name
Test status
Simulation time 9938430245 ps
CPU time 1210.02 seconds
Started Jul 14 07:53:00 PM PDT 24
Finished Jul 14 08:13:11 PM PDT 24
Peak memory 619380 kb
Host smart-7e557c6e-e6ae-4e06-b866-709d31acbb57
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa
lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328088307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.3328088307
Directory /workspace/0.chip_sw_lc_walkthrough_prodend/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3710021931
Short name T1205
Test name
Test status
Simulation time 46007189836 ps
CPU time 5500.87 seconds
Started Jul 14 07:53:01 PM PDT 24
Finished Jul 14 09:24:43 PM PDT 24
Peak memory 619580 kb
Host smart-ac18ba74-d2ae-4243-b8c8-ba504b3939f6
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710021931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip
_sw_lc_walkthrough_rma.3710021931
Directory /workspace/0.chip_sw_lc_walkthrough_rma/latest

Test location /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.103701715
Short name T1097
Test name
Test status
Simulation time 31194399190 ps
CPU time 1969.66 seconds
Started Jul 14 07:52:29 PM PDT 24
Finished Jul 14 08:25:20 PM PDT 24
Peak memory 620240 kb
Host smart-87cc687a-e114-43f0-af3a-12469367fb60
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks
_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=103701715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testunl
ocks.103701715
Directory /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2477965277
Short name T1213
Test name
Test status
Simulation time 18206692038 ps
CPU time 3703.4 seconds
Started Jul 14 07:54:08 PM PDT 24
Finished Jul 14 08:55:52 PM PDT 24
Peak memory 609748 kb
Host smart-316faea5-e50a-4f82-8367-c646e8cdbece
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne
w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2477965277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2477965277
Directory /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4096624876
Short name T668
Test name
Test status
Simulation time 24930841338 ps
CPU time 4401.37 seconds
Started Jul 14 07:58:00 PM PDT 24
Finished Jul 14 09:11:22 PM PDT 24
Peak memory 609896 kb
Host smart-ea253af3-f9d7-4527-8e73-161d752b8cd7
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e
cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096624876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu
ced_freq.4096624876
Directory /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2313260834
Short name T1257
Test name
Test status
Simulation time 3099237688 ps
CPU time 509.58 seconds
Started Jul 14 07:53:38 PM PDT 24
Finished Jul 14 08:02:08 PM PDT 24
Peak memory 609412 kb
Host smart-7efcabba-0ad0-47f6-9fb4-c9f657137e39
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn
_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313260834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.2313260834
Directory /workspace/0.chip_sw_otbn_mem_scramble/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_randomness.1965324325
Short name T121
Test name
Test status
Simulation time 5860393388 ps
CPU time 933.84 seconds
Started Jul 14 07:52:30 PM PDT 24
Finished Jul 14 08:08:04 PM PDT 24
Peak memory 610004 kb
Host smart-b52b16f0-6abc-4de3-a052-809965cdbf75
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1965324325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.1965324325
Directory /workspace/0.chip_sw_otbn_randomness/latest

Test location /workspace/coverage/default/0.chip_sw_otbn_smoketest.622267553
Short name T1260
Test name
Test status
Simulation time 10164573416 ps
CPU time 2571.32 seconds
Started Jul 14 07:56:00 PM PDT 24
Finished Jul 14 08:38:53 PM PDT 24
Peak memory 609544 kb
Host smart-8faffd8f-ae35-4af7-9e2f-6431616266bd
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622267553 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.chip_sw_otbn_smoketest.622267553
Directory /workspace/0.chip_sw_otbn_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2226550891
Short name T1120
Test name
Test status
Simulation time 27922710080 ps
CPU time 5836.73 seconds
Started Jul 14 07:53:47 PM PDT 24
Finished Jul 14 09:31:05 PM PDT 24
Peak memory 610052 kb
Host smart-2c93a986-ae09-4691-adc8-17f0ccca6d88
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222655
0891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.2226550891
Directory /workspace/0.chip_sw_otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.134135552
Short name T920
Test name
Test status
Simulation time 3044009328 ps
CPU time 312.81 seconds
Started Jul 14 07:52:46 PM PDT 24
Finished Jul 14 07:58:00 PM PDT 24
Peak memory 609500 kb
Host smart-e86388e4-5dee-4fd7-9a11-cd1efa17fc56
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134135552 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.134135552
Directory /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1814731166
Short name T164
Test name
Test status
Simulation time 5603719820 ps
CPU time 589.07 seconds
Started Jul 14 07:53:39 PM PDT 24
Finished Jul 14 08:03:28 PM PDT 24
Peak memory 610424 kb
Host smart-7d502233-104b-430c-a700-da84f5aef812
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1814731166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.1814731166
Directory /workspace/0.chip_sw_otp_ctrl_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2853139836
Short name T223
Test name
Test status
Simulation time 9651683600 ps
CPU time 1673.72 seconds
Started Jul 14 07:59:26 PM PDT 24
Finished Jul 14 08:27:21 PM PDT 24
Peak memory 609708 kb
Host smart-ca404b61-3711-4f0c-a831-903ec09050ea
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2853139836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.2853139836
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.937847049
Short name T911
Test name
Test status
Simulation time 8533414488 ps
CPU time 1622.22 seconds
Started Jul 14 07:51:58 PM PDT 24
Finished Jul 14 08:19:01 PM PDT 24
Peak memory 609916 kb
Host smart-3a85281b-7244-44d4-9cc5-9c3c4c662562
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=937847049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.937847049
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1754147021
Short name T218
Test name
Test status
Simulation time 7611866524 ps
CPU time 1373.85 seconds
Started Jul 14 07:51:41 PM PDT 24
Finished Jul 14 08:14:35 PM PDT 24
Peak memory 609924 kb
Host smart-0f4b0890-9efe-4286-bea9-3f9aa9699e0a
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1754147021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.1754147021
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2380228677
Short name T946
Test name
Test status
Simulation time 4047450912 ps
CPU time 647.41 seconds
Started Jul 14 07:54:59 PM PDT 24
Finished Jul 14 08:05:47 PM PDT 24
Peak memory 608652 kb
Host smart-9a75e813-4388-4abe-913e-a60ba683e5a4
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=2380228677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2380228677
Directory /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1564628446
Short name T897
Test name
Test status
Simulation time 3550767696 ps
CPU time 278.08 seconds
Started Jul 14 07:58:47 PM PDT 24
Finished Jul 14 08:03:26 PM PDT 24
Peak memory 609220 kb
Host smart-ef7c6671-84ca-450a-a016-fcfb6f27c8a0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564628446 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_otp_ctrl_smoketest.1564628446
Directory /workspace/0.chip_sw_otp_ctrl_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_power_idle_load.1542887827
Short name T1181
Test name
Test status
Simulation time 3829065738 ps
CPU time 742.03 seconds
Started Jul 14 07:58:44 PM PDT 24
Finished Jul 14 08:11:07 PM PDT 24
Peak memory 608456 kb
Host smart-24a7d0a9-3d58-4ff7-b8ef-24026d6f115c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542887827 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.1542887827
Directory /workspace/0.chip_sw_power_idle_load/latest

Test location /workspace/coverage/default/0.chip_sw_power_sleep_load.2800322281
Short name T148
Test name
Test status
Simulation time 11398676872 ps
CPU time 666.77 seconds
Started Jul 14 07:54:47 PM PDT 24
Finished Jul 14 08:05:54 PM PDT 24
Peak memory 609940 kb
Host smart-46ab0641-180c-4db4-a510-54bc79abf860
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800322281 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.2800322281
Directory /workspace/0.chip_sw_power_sleep_load/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3026566065
Short name T20
Test name
Test status
Simulation time 32575040755 ps
CPU time 1943.38 seconds
Started Jul 14 07:55:46 PM PDT 24
Finished Jul 14 08:28:10 PM PDT 24
Peak memory 609896 kb
Host smart-85c02a25-1688-428c-8383-9bfa83ea78b6
User root
Command /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302
6566065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.3026566065
Directory /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1088834587
Short name T317
Test name
Test status
Simulation time 17225714550 ps
CPU time 1665.47 seconds
Started Jul 14 07:53:17 PM PDT 24
Finished Jul 14 08:21:03 PM PDT 24
Peak memory 610680 kb
Host smart-c401d712-4316-4aa3-83fd-3f2d101715d3
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1088834587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1088834587
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1794718006
Short name T15
Test name
Test status
Simulation time 20385929312 ps
CPU time 1535.65 seconds
Started Jul 14 07:54:36 PM PDT 24
Finished Jul 14 08:20:13 PM PDT 24
Peak memory 610212 kb
Host smart-e1f3ceea-7304-4c58-86d7-954f469decb0
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1794718006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1794718006
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1261965239
Short name T1237
Test name
Test status
Simulation time 8982701040 ps
CPU time 692.39 seconds
Started Jul 14 07:54:17 PM PDT 24
Finished Jul 14 08:05:50 PM PDT 24
Peak memory 609140 kb
Host smart-e3b1db2c-327d-4dda-a10a-b68174ae48a8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261965239 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.1261965239
Directory /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2549036675
Short name T1292
Test name
Test status
Simulation time 4444299976 ps
CPU time 520.52 seconds
Started Jul 14 07:53:47 PM PDT 24
Finished Jul 14 08:02:29 PM PDT 24
Peak memory 615520 kb
Host smart-dc9803d1-f2d6-4fa5-b37d-1ed5c438a764
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2549036675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.2549036675
Directory /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1390600018
Short name T369
Test name
Test status
Simulation time 11030936115 ps
CPU time 1342.41 seconds
Started Jul 14 07:53:17 PM PDT 24
Finished Jul 14 08:15:41 PM PDT 24
Peak memory 610352 kb
Host smart-c160d31a-bbb5-40af-b5cc-1e7e3527472f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390600018 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1390600018
Directory /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3255798772
Short name T438
Test name
Test status
Simulation time 7712522676 ps
CPU time 537.07 seconds
Started Jul 14 07:55:04 PM PDT 24
Finished Jul 14 08:04:02 PM PDT 24
Peak memory 609832 kb
Host smart-f73abbd6-1d07-45c0-b0a4-568eba04d3c6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255798772 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3255798772
Directory /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3629776828
Short name T709
Test name
Test status
Simulation time 6296559744 ps
CPU time 632.6 seconds
Started Jul 14 07:55:49 PM PDT 24
Finished Jul 14 08:06:23 PM PDT 24
Peak memory 609120 kb
Host smart-3b32bc37-27a2-4dff-9dae-c3b82577f149
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629776828 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.3629776828
Directory /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3001488409
Short name T973
Test name
Test status
Simulation time 28994313305 ps
CPU time 3011.56 seconds
Started Jul 14 07:56:00 PM PDT 24
Finished Jul 14 08:46:13 PM PDT 24
Peak memory 610624 kb
Host smart-34af0b54-97a1-416f-97f0-80c6c1987e67
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3001488409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3001488409
Directory /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3126834464
Short name T1095
Test name
Test status
Simulation time 31411226540 ps
CPU time 2691.12 seconds
Started Jul 14 07:53:01 PM PDT 24
Finished Jul 14 08:37:53 PM PDT 24
Peak memory 611256 kb
Host smart-f3505e75-60e3-4190-84bf-1f6af3448b9a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power
_glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126834464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit
ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s
leep_power_glitch_reset.3126834464
Directory /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2713121417
Short name T95
Test name
Test status
Simulation time 2848956990 ps
CPU time 356.37 seconds
Started Jul 14 07:54:44 PM PDT 24
Finished Jul 14 08:00:42 PM PDT 24
Peak memory 609060 kb
Host smart-23fb103a-98bc-4767-b480-dafb8752689f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713121417 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.2713121417
Directory /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3431270753
Short name T974
Test name
Test status
Simulation time 6126448958 ps
CPU time 522.34 seconds
Started Jul 14 07:54:39 PM PDT 24
Finished Jul 14 08:03:22 PM PDT 24
Peak memory 615644 kb
Host smart-593c5615-bb6e-4e3b-8f1c-ba9f135beeef
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=3431270753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.3431270753
Directory /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1877243400
Short name T1152
Test name
Test status
Simulation time 7533619568 ps
CPU time 616.9 seconds
Started Jul 14 07:53:20 PM PDT 24
Finished Jul 14 08:03:37 PM PDT 24
Peak memory 610168 kb
Host smart-0c11a0af-2c19-4587-a079-6ddd2655c28b
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1877243400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.1877243400
Directory /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.91959857
Short name T1037
Test name
Test status
Simulation time 5857198428 ps
CPU time 390.43 seconds
Started Jul 14 07:58:12 PM PDT 24
Finished Jul 14 08:04:43 PM PDT 24
Peak memory 609720 kb
Host smart-410799c7-0add-4a6b-82be-d027b3c70163
User root
Command /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91959857 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.91959857
Directory /workspace/0.chip_sw_pwrmgr_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2795747906
Short name T487
Test name
Test status
Simulation time 7438784067 ps
CPU time 1447.82 seconds
Started Jul 14 07:54:55 PM PDT 24
Finished Jul 14 08:19:04 PM PDT 24
Peak memory 609908 kb
Host smart-66cf01b9-0bb5-49bd-999a-9060309f75ed
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795747906 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.2795747906
Directory /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.85796865
Short name T1269
Test name
Test status
Simulation time 5561506534 ps
CPU time 511.37 seconds
Started Jul 14 07:52:39 PM PDT 24
Finished Jul 14 08:01:10 PM PDT 24
Peak memory 609736 kb
Host smart-7ef3b7ed-76fd-402e-b48b-85a3d9d3ab41
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85796865 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.85796865
Directory /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.4153570442
Short name T84
Test name
Test status
Simulation time 4370805420 ps
CPU time 372.56 seconds
Started Jul 14 08:00:41 PM PDT 24
Finished Jul 14 08:06:55 PM PDT 24
Peak memory 609660 kb
Host smart-57e987cf-0d7d-4d79-8efb-21f9ca7dd7fa
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153570442 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.4153570442
Directory /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1003870691
Short name T1302
Test name
Test status
Simulation time 4121697760 ps
CPU time 614.32 seconds
Started Jul 14 07:53:19 PM PDT 24
Finished Jul 14 08:03:35 PM PDT 24
Peak memory 608732 kb
Host smart-34931df8-fa5a-4298-9da2-c7245c950556
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100
3870691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.1003870691
Directory /workspace/0.chip_sw_pwrmgr_wdog_reset/latest

Test location /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2895559630
Short name T274
Test name
Test status
Simulation time 8297876706 ps
CPU time 441.67 seconds
Started Jul 14 07:54:13 PM PDT 24
Finished Jul 14 08:01:35 PM PDT 24
Peak memory 624092 kb
Host smart-578e9564-08a2-48d8-9b6e-9180c2393adf
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895559630 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.2895559630
Directory /workspace/0.chip_sw_rom_ctrl_integrity_check/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3836879310
Short name T261
Test name
Test status
Simulation time 6374861076 ps
CPU time 601.02 seconds
Started Jul 14 07:52:49 PM PDT 24
Finished Jul 14 08:02:51 PM PDT 24
Peak memory 609812 kb
Host smart-320c88cc-8594-48d2-a2b7-1b5d09f5ee45
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836879310 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.3836879310
Directory /workspace/0.chip_sw_rstmgr_cpu_info/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3937714427
Short name T733
Test name
Test status
Simulation time 4836138616 ps
CPU time 493.38 seconds
Started Jul 14 07:53:09 PM PDT 24
Finished Jul 14 08:01:22 PM PDT 24
Peak memory 640644 kb
Host smart-5eb0028a-fbfc-4baa-8cf6-044d092c1323
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3937714427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.3937714427
Directory /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.4102762882
Short name T441
Test name
Test status
Simulation time 2271959440 ps
CPU time 252.95 seconds
Started Jul 14 07:57:57 PM PDT 24
Finished Jul 14 08:02:11 PM PDT 24
Peak memory 609104 kb
Host smart-acff0d65-b408-40df-a753-c9be014a0a7a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102762882 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.chip_sw_rstmgr_smoketest.4102762882
Directory /workspace/0.chip_sw_rstmgr_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2687155144
Short name T1266
Test name
Test status
Simulation time 5361425544 ps
CPU time 529.11 seconds
Started Jul 14 07:53:00 PM PDT 24
Finished Jul 14 08:01:50 PM PDT 24
Peak memory 609392 kb
Host smart-637ee489-3e78-47dd-8176-d42bade8ec1f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687155144 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.chip_sw_rstmgr_sw_req.2687155144
Directory /workspace/0.chip_sw_rstmgr_sw_req/latest

Test location /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1846899084
Short name T385
Test name
Test status
Simulation time 2984794260 ps
CPU time 302.31 seconds
Started Jul 14 07:53:12 PM PDT 24
Finished Jul 14 07:58:15 PM PDT 24
Peak memory 609272 kb
Host smart-455c6c1f-54aa-4816-b4a0-3f49f55c61da
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846899084 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.1846899084
Directory /workspace/0.chip_sw_rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1448823686
Short name T302
Test name
Test status
Simulation time 3095708001 ps
CPU time 243.75 seconds
Started Jul 14 07:53:45 PM PDT 24
Finished Jul 14 07:57:49 PM PDT 24
Peak memory 609552 kb
Host smart-bfc51975-a4b1-426b-840f-1896e1b306a5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448823686 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.1448823686
Directory /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2245179220
Short name T1301
Test name
Test status
Simulation time 5331788024 ps
CPU time 1090.23 seconds
Started Jul 14 07:55:52 PM PDT 24
Finished Jul 14 08:14:03 PM PDT 24
Peak memory 608648 kb
Host smart-e8434c74-1270-4f19-a76a-841dd4126767
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2245179220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.2245179220
Directory /workspace/0.chip_sw_rv_core_ibex_rnd/latest

Test location /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.990270956
Short name T676
Test name
Test status
Simulation time 5075780572 ps
CPU time 737.63 seconds
Started Jul 14 07:54:10 PM PDT 24
Finished Jul 14 08:06:28 PM PDT 24
Peak memory 623488 kb
Host smart-afe65294-4169-4af4-84ac-40d131a28a9d
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990270956 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.990270956
Directory /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1911103815
Short name T907
Test name
Test status
Simulation time 5865525482 ps
CPU time 478.17 seconds
Started Jul 14 07:53:59 PM PDT 24
Finished Jul 14 08:01:58 PM PDT 24
Peak memory 619396 kb
Host smart-d3889b34-fe96-46e5-a43d-790dd4b1a715
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911103815 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.1911103815
Directory /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest

Test location /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2417455462
Short name T373
Test name
Test status
Simulation time 5453987896 ps
CPU time 541.35 seconds
Started Jul 14 07:53:21 PM PDT 24
Finished Jul 14 08:02:24 PM PDT 24
Peak memory 619696 kb
Host smart-575c8226-a2a0-4a68-bdde-079b58a89a22
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241745
5462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2417455462
Directory /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.936214433
Short name T1201
Test name
Test status
Simulation time 3402553136 ps
CPU time 352.08 seconds
Started Jul 14 07:57:22 PM PDT 24
Finished Jul 14 08:03:15 PM PDT 24
Peak memory 609272 kb
Host smart-d84bd0df-6122-4449-a449-d358e83427d6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936214433 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.chip_sw_rv_plic_smoketest.936214433
Directory /workspace/0.chip_sw_rv_plic_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_rv_timer_irq.339716836
Short name T1197
Test name
Test status
Simulation time 3617631800 ps
CPU time 249.33 seconds
Started Jul 14 07:52:00 PM PDT 24
Finished Jul 14 07:56:10 PM PDT 24
Peak memory 607972 kb
Host smart-b52d1841-0e95-482c-a80d-a50f570bd226
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339716836 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_rv_timer_irq.339716836
Directory /workspace/0.chip_sw_rv_timer_irq/latest

Test location /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.754395354
Short name T253
Test name
Test status
Simulation time 2681136610 ps
CPU time 313.07 seconds
Started Jul 14 07:56:31 PM PDT 24
Finished Jul 14 08:01:45 PM PDT 24
Peak memory 609248 kb
Host smart-d98d2a4f-b8eb-4143-941e-85595d3e7cee
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754395354 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.chip_sw_rv_timer_smoketest.754395354
Directory /workspace/0.chip_sw_rv_timer_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1361419381
Short name T362
Test name
Test status
Simulation time 3364927866 ps
CPU time 227.36 seconds
Started Jul 14 07:54:50 PM PDT 24
Finished Jul 14 07:58:39 PM PDT 24
Peak memory 609988 kb
Host smart-8116a831-17d2-4681-8ac3-81d46a5582f6
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361419
381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.1361419381
Directory /workspace/0.chip_sw_sensor_ctrl_status/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pin_retention.1769569874
Short name T13
Test name
Test status
Simulation time 3155631430 ps
CPU time 256.27 seconds
Started Jul 14 07:52:00 PM PDT 24
Finished Jul 14 07:56:18 PM PDT 24
Peak memory 609456 kb
Host smart-e4be009f-57b3-4a17-8930-6f600b60f5e9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769569874 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.1769569874
Directory /workspace/0.chip_sw_sleep_pin_retention/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.4273061686
Short name T943
Test name
Test status
Simulation time 9453666328 ps
CPU time 1386.39 seconds
Started Jul 14 07:52:17 PM PDT 24
Finished Jul 14 08:15:25 PM PDT 24
Peak memory 609808 kb
Host smart-96708caf-79ae-4210-94f5-31351f64e35a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273061686 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.4273061686
Directory /workspace/0.chip_sw_sleep_pwm_pulses/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1031581305
Short name T318
Test name
Test status
Simulation time 7271442126 ps
CPU time 918.72 seconds
Started Jul 14 07:54:53 PM PDT 24
Finished Jul 14 08:10:13 PM PDT 24
Peak memory 609848 kb
Host smart-84a2bc02-5351-4326-8be5-64730f58d8d1
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031581305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl
eep_sram_ret_contents_no_scramble.1031581305
Directory /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1140544614
Short name T1137
Test name
Test status
Simulation time 8054065180 ps
CPU time 700.2 seconds
Started Jul 14 07:56:41 PM PDT 24
Finished Jul 14 08:08:22 PM PDT 24
Peak memory 610128 kb
Host smart-4789ab58-a352-4bcf-867a-6f4ba03a91ea
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140544614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep
_sram_ret_contents_scramble.1140544614
Directory /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_pass_through.1763160934
Short name T26
Test name
Test status
Simulation time 7472934961 ps
CPU time 897.23 seconds
Started Jul 14 07:52:02 PM PDT 24
Finished Jul 14 08:07:01 PM PDT 24
Peak memory 624284 kb
Host smart-1698e4e5-f267-49dc-9fa5-9388fba77a30
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763160934 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.1763160934
Directory /workspace/0.chip_sw_spi_device_pass_through/latest

Test location /workspace/coverage/default/0.chip_sw_spi_device_tpm.1295333769
Short name T52
Test name
Test status
Simulation time 3789260733 ps
CPU time 377.97 seconds
Started Jul 14 07:54:57 PM PDT 24
Finished Jul 14 08:01:16 PM PDT 24
Peak memory 617912 kb
Host smart-12e539fb-6652-4a80-bb74-90d5e7d72b14
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295333769 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.1295333769
Directory /workspace/0.chip_sw_spi_device_tpm/latest

Test location /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2705751450
Short name T44
Test name
Test status
Simulation time 2875465352 ps
CPU time 327.46 seconds
Started Jul 14 07:53:05 PM PDT 24
Finished Jul 14 07:58:33 PM PDT 24
Peak memory 609792 kb
Host smart-032cb43b-1861-41ed-8f84-b2036884ae6b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705751450 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.2705751450
Directory /workspace/0.chip_sw_spi_host_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1633326572
Short name T181
Test name
Test status
Simulation time 7364811993 ps
CPU time 839.43 seconds
Started Jul 14 07:54:32 PM PDT 24
Finished Jul 14 08:08:32 PM PDT 24
Peak memory 609988 kb
Host smart-33f318c7-3ba7-4b49-92d4-9333cc6e3c27
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633326572 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.1633326572
Directory /workspace/0.chip_sw_sram_ctrl_execution_main/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1964923422
Short name T286
Test name
Test status
Simulation time 4735104916 ps
CPU time 563.31 seconds
Started Jul 14 07:54:10 PM PDT 24
Finished Jul 14 08:03:34 PM PDT 24
Peak memory 610256 kb
Host smart-1299b40a-7eaa-436a-953d-ab0d5373110a
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964923422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr
l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw
_sram_ctrl_scrambled_access.1964923422
Directory /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.26946087
Short name T288
Test name
Test status
Simulation time 4870214404 ps
CPU time 502.31 seconds
Started Jul 14 07:56:24 PM PDT 24
Finished Jul 14 08:04:47 PM PDT 24
Peak memory 609760 kb
Host smart-d4afcfcd-6ecc-4480-8a9c-31e587e6e1c6
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s
w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26946087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.26946087
Directory /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3765476000
Short name T287
Test name
Test status
Simulation time 4303485406 ps
CPU time 540.75 seconds
Started Jul 14 07:54:50 PM PDT 24
Finished Jul 14 08:03:52 PM PDT 24
Peak memory 609072 kb
Host smart-40563771-b317-476a-848c-5699a8ae37a5
User root
Command /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk
_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765476000 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3765476000
Directory /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3302882757
Short name T1247
Test name
Test status
Simulation time 2609944002 ps
CPU time 218.71 seconds
Started Jul 14 07:54:47 PM PDT 24
Finished Jul 14 07:58:26 PM PDT 24
Peak memory 609132 kb
Host smart-3dff6fd7-6c7c-44e4-a6fd-437529b3b5cb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302882757 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.3302882757
Directory /workspace/0.chip_sw_sram_ctrl_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.652708969
Short name T1171
Test name
Test status
Simulation time 20849781012 ps
CPU time 3466.24 seconds
Started Jul 14 07:59:34 PM PDT 24
Finished Jul 14 08:57:22 PM PDT 24
Peak memory 610148 kb
Host smart-f12ae06e-ed59-4f84-ad33-0d86d68083ef
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652708969 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.652708969
Directory /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1920974077
Short name T204
Test name
Test status
Simulation time 4020380199 ps
CPU time 630.62 seconds
Started Jul 14 07:53:15 PM PDT 24
Finished Jul 14 08:03:48 PM PDT 24
Peak memory 612776 kb
Host smart-459d8348-abbc-442b-84a2-06f5af88a318
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920974077 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.1920974077
Directory /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2715980234
Short name T202
Test name
Test status
Simulation time 2711165266 ps
CPU time 267.27 seconds
Started Jul 14 07:54:34 PM PDT 24
Finished Jul 14 07:59:03 PM PDT 24
Peak memory 612296 kb
Host smart-f3eccb6b-4744-4404-9080-44f32b421e2e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715980234 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.2715980234
Directory /workspace/0.chip_sw_sysrst_ctrl_inputs/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.1445189606
Short name T1280
Test name
Test status
Simulation time 4097202600 ps
CPU time 321.42 seconds
Started Jul 14 07:54:56 PM PDT 24
Finished Jul 14 08:00:18 PM PDT 24
Peak memory 609496 kb
Host smart-8fea424e-bcf4-47e6-b86d-1339dbda82f7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445189606 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.1445189606
Directory /workspace/0.chip_sw_sysrst_ctrl_outputs/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1813050431
Short name T32
Test name
Test status
Simulation time 23742602844 ps
CPU time 2237.6 seconds
Started Jul 14 07:56:14 PM PDT 24
Finished Jul 14 08:33:33 PM PDT 24
Peak memory 612324 kb
Host smart-3a291562-5ccf-46db-9720-0df2952546ba
User root
Command /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18130504
31 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.1813050431
Directory /workspace/0.chip_sw_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1309669928
Short name T47
Test name
Test status
Simulation time 5500738600 ps
CPU time 435.26 seconds
Started Jul 14 07:52:58 PM PDT 24
Finished Jul 14 08:00:15 PM PDT 24
Peak memory 610028 kb
Host smart-207a530d-1049-4aa2-a405-1c2d68b696d4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309669928 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1309669928
Directory /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2082471879
Short name T1179
Test name
Test status
Simulation time 4065694040 ps
CPU time 676.26 seconds
Started Jul 14 07:54:25 PM PDT 24
Finished Jul 14 08:05:43 PM PDT 24
Peak memory 617044 kb
Host smart-e769f06a-242d-41b1-80df-e49bb99b9df4
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2082471879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.2082471879
Directory /workspace/0.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/0.chip_sw_uart_smoketest.1911379833
Short name T1099
Test name
Test status
Simulation time 2778973754 ps
CPU time 313.22 seconds
Started Jul 14 08:00:50 PM PDT 24
Finished Jul 14 08:06:03 PM PDT 24
Peak memory 615700 kb
Host smart-1d4adc0c-2138-4b11-9c60-1118cfceef0d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911379833 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.chip_sw_uart_smoketest.1911379833
Directory /workspace/0.chip_sw_uart_smoketest/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx.4265493174
Short name T1175
Test name
Test status
Simulation time 4411249220 ps
CPU time 474.54 seconds
Started Jul 14 07:51:15 PM PDT 24
Finished Jul 14 07:59:11 PM PDT 24
Peak memory 621912 kb
Host smart-326d0fab-dd43-47d2-bc34-f86634491872
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265493174 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.4265493174
Directory /workspace/0.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2337977472
Short name T928
Test name
Test status
Simulation time 12576286709 ps
CPU time 2926.32 seconds
Started Jul 14 07:51:37 PM PDT 24
Finished Jul 14 08:40:24 PM PDT 24
Peak memory 622536 kb
Host smart-f60a596e-0950-4107-86a4-6a8b02e2cc57
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337977472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx
_alt_clk_freq.2337977472
Directory /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3317631372
Short name T1005
Test name
Test status
Simulation time 4517530399 ps
CPU time 510.4 seconds
Started Jul 14 07:53:42 PM PDT 24
Finished Jul 14 08:02:14 PM PDT 24
Peak memory 624152 kb
Host smart-2e6e5548-d4ad-4018-9471-de959f4e8cd4
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317631372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.3317631372
Directory /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.4101443452
Short name T466
Test name
Test status
Simulation time 4059509460 ps
CPU time 628.72 seconds
Started Jul 14 07:53:25 PM PDT 24
Finished Jul 14 08:03:55 PM PDT 24
Peak memory 623216 kb
Host smart-a909b7b7-9345-4e59-80da-0382042c2f2c
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101443452 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.4101443452
Directory /workspace/0.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2490740745
Short name T1106
Test name
Test status
Simulation time 4416701184 ps
CPU time 673.49 seconds
Started Jul 14 07:53:27 PM PDT 24
Finished Jul 14 08:04:42 PM PDT 24
Peak memory 623212 kb
Host smart-034c4209-1604-4674-9ddc-c99a8d0260f3
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490740745 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.2490740745
Directory /workspace/0.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.3744463347
Short name T970
Test name
Test status
Simulation time 4103457742 ps
CPU time 689.72 seconds
Started Jul 14 07:53:03 PM PDT 24
Finished Jul 14 08:04:34 PM PDT 24
Peak memory 621884 kb
Host smart-1c267b50-84d8-47a7-b1f4-e39f2ee2e2a1
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744463347 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.3744463347
Directory /workspace/0.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2019036285
Short name T1242
Test name
Test status
Simulation time 2970685703 ps
CPU time 403.71 seconds
Started Jul 14 07:54:32 PM PDT 24
Finished Jul 14 08:01:17 PM PDT 24
Peak memory 609344 kb
Host smart-c75e5abd-85f2-433e-99fb-e2fd3001effa
User root
Command /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019036285
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.2019036285
Directory /workspace/0.chip_sw_usb_ast_clk_calib/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_dpi.1524819487
Short name T30
Test name
Test status
Simulation time 11696912340 ps
CPU time 2938.15 seconds
Started Jul 14 07:53:13 PM PDT 24
Finished Jul 14 08:42:13 PM PDT 24
Peak memory 609736 kb
Host smart-52803efd-2850-4675-a935-8cea27125c84
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1524819487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.1524819487
Directory /workspace/0.chip_sw_usbdev_dpi/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2040179502
Short name T83
Test name
Test status
Simulation time 31739946542 ps
CPU time 6859.22 seconds
Started Jul 14 07:54:45 PM PDT 24
Finished Jul 14 09:49:06 PM PDT 24
Peak memory 609572 kb
Host smart-0b1424eb-2f44-41ef-9cdd-574b28bfe2cc
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=2040179502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.2040179502
Directory /workspace/0.chip_sw_usbdev_pincfg/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_pullup.2702406842
Short name T82
Test name
Test status
Simulation time 3630048704 ps
CPU time 329.75 seconds
Started Jul 14 07:59:14 PM PDT 24
Finished Jul 14 08:04:44 PM PDT 24
Peak memory 608684 kb
Host smart-e37703a4-4fd7-4115-a360-523168e40dd4
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702406842
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.2702406842
Directory /workspace/0.chip_sw_usbdev_pullup/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2298846773
Short name T145
Test name
Test status
Simulation time 3952736712 ps
CPU time 593.47 seconds
Started Jul 14 07:52:58 PM PDT 24
Finished Jul 14 08:02:53 PM PDT 24
Peak memory 608656 kb
Host smart-90ad773d-31ec-4c27-9fad-f4979b2a829f
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229884677
3 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.2298846773
Directory /workspace/0.chip_sw_usbdev_setuprx/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_stream.2883374450
Short name T29
Test name
Test status
Simulation time 19214896274 ps
CPU time 3416.93 seconds
Started Jul 14 07:52:44 PM PDT 24
Finished Jul 14 08:49:43 PM PDT 24
Peak memory 609736 kb
Host smart-ee10829a-ac93-4360-a9a7-f10dac65443f
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru
les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2883374450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.2883374450
Directory /workspace/0.chip_sw_usbdev_stream/latest

Test location /workspace/coverage/default/0.chip_sw_usbdev_vbus.3585133451
Short name T987
Test name
Test status
Simulation time 2925940456 ps
CPU time 241.61 seconds
Started Jul 14 07:52:16 PM PDT 24
Finished Jul 14 07:56:18 PM PDT 24
Peak memory 608672 kb
Host smart-747a364c-8b48-4535-a49e-0168a7a5eb62
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585133451 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.3585133451
Directory /workspace/0.chip_sw_usbdev_vbus/latest

Test location /workspace/coverage/default/0.chip_tap_straps_dev.296769817
Short name T1003
Test name
Test status
Simulation time 2416493030 ps
CPU time 168.29 seconds
Started Jul 14 07:55:45 PM PDT 24
Finished Jul 14 07:58:34 PM PDT 24
Peak memory 619448 kb
Host smart-48fbfee6-3dde-40c9-a677-4c9a5ddba3f6
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=296769817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.296769817
Directory /workspace/0.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/0.chip_tap_straps_prod.3990144689
Short name T81
Test name
Test status
Simulation time 13335376131 ps
CPU time 1432.32 seconds
Started Jul 14 07:54:54 PM PDT 24
Finished Jul 14 08:18:47 PM PDT 24
Peak memory 620392 kb
Host smart-a64558f7-aa62-4c8a-abaf-c3df3ca54a43
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3990144689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.3990144689
Directory /workspace/0.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/0.chip_tap_straps_rma.1621351604
Short name T80
Test name
Test status
Simulation time 2216330208 ps
CPU time 124.23 seconds
Started Jul 14 07:55:24 PM PDT 24
Finished Jul 14 07:57:29 PM PDT 24
Peak memory 619984 kb
Host smart-10e96004-97f3-4c24-9ff7-69445683899f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621351604 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.1621351604
Directory /workspace/0.chip_tap_straps_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_dev.3675292122
Short name T1009
Test name
Test status
Simulation time 16229839414 ps
CPU time 4407.98 seconds
Started Jul 14 08:03:40 PM PDT 24
Finished Jul 14 09:17:09 PM PDT 24
Peak memory 609552 kb
Host smart-6b2e8297-dc85-4d0c-ae9f-38036a56a7df
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675292122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rom_e2e_asm_init_dev.3675292122
Directory /workspace/0.rom_e2e_asm_init_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_prod.2381926275
Short name T1145
Test name
Test status
Simulation time 15273268270 ps
CPU time 3759.3 seconds
Started Jul 14 08:07:08 PM PDT 24
Finished Jul 14 09:09:48 PM PDT 24
Peak memory 609532 kb
Host smart-9ecf841f-111a-40f5-a526-f2cec3b3cef2
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381926275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_
SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rom_e2e_asm_init_prod.2381926275
Directory /workspace/0.rom_e2e_asm_init_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3905676301
Short name T285
Test name
Test status
Simulation time 16079424903 ps
CPU time 4067.55 seconds
Started Jul 14 07:59:32 PM PDT 24
Finished Jul 14 09:07:20 PM PDT 24
Peak memory 609660 kb
Host smart-50a86b79-315a-4955-bf0e-434713066381
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905676301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_e2e_asm_init_prod_end.3905676301
Directory /workspace/0.rom_e2e_asm_init_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_rma.2750564540
Short name T952
Test name
Test status
Simulation time 14327149967 ps
CPU time 4078.99 seconds
Started Jul 14 08:01:41 PM PDT 24
Finished Jul 14 09:09:41 PM PDT 24
Peak memory 609616 kb
Host smart-92cb6280-e51d-4448-8325-4a4ce7aeea18
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750564540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rom_e2e_asm_init_rma.2750564540
Directory /workspace/0.rom_e2e_asm_init_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2335071362
Short name T904
Test name
Test status
Simulation time 11820769627 ps
CPU time 2571.27 seconds
Started Jul 14 07:58:52 PM PDT 24
Finished Jul 14 08:41:44 PM PDT 24
Peak memory 609952 kb
Host smart-dbe24ff3-2c22-482b-9839-7fc164d1deed
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335071362 -assert nopostproc +UVM_TESTNAME=chip_base_te
st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.rom_e2e_asm_init_test_unlocked0.2335071362
Directory /workspace/0.rom_e2e_asm_init_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3664996148
Short name T399
Test name
Test status
Simulation time 24217770436 ps
CPU time 5557.35 seconds
Started Jul 14 08:02:59 PM PDT 24
Finished Jul 14 09:35:37 PM PDT 24
Peak memory 608840 kb
Host smart-5008aa2f-2bf2-4122-b1b6-56775501f42e
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3664996148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3664996148
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3490634647
Short name T378
Test name
Test status
Simulation time 24854019116 ps
CPU time 6726.99 seconds
Started Jul 14 08:01:31 PM PDT 24
Finished Jul 14 09:53:39 PM PDT 24
Peak memory 609028 kb
Host smart-984ec3c9-638b-49ba-9485-099a3f8ae0cd
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3490634647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3490634647
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2303214482
Short name T56
Test name
Test status
Simulation time 23188040174 ps
CPU time 7238.41 seconds
Started Jul 14 08:04:53 PM PDT 24
Finished Jul 14 10:05:32 PM PDT 24
Peak memory 609696 kb
Host smart-5ce0718d-7d48-41b4-ada5-c5e93ba53754
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2303214482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2303214482
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3564818583
Short name T1294
Test name
Test status
Simulation time 18117425142 ps
CPU time 4627.36 seconds
Started Jul 14 08:01:05 PM PDT 24
Finished Jul 14 09:18:14 PM PDT 24
Peak memory 608920 kb
Host smart-1bbee388-0373-4752-bb69-d1eae00237f4
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,
mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3564818583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3564818583
Directory /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2858220880
Short name T976
Test name
Test status
Simulation time 15210668872 ps
CPU time 3380.52 seconds
Started Jul 14 08:02:50 PM PDT 24
Finished Jul 14 08:59:12 PM PDT 24
Peak memory 609788 kb
Host smart-f03e630b-dea3-47f6-a81b-65fc15cec641
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2858220880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2858220880
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3091738464
Short name T459
Test name
Test status
Simulation time 14686743000 ps
CPU time 4220.58 seconds
Started Jul 14 08:01:40 PM PDT 24
Finished Jul 14 09:12:02 PM PDT 24
Peak memory 609828 kb
Host smart-5dc4ea0b-ba4c-43f3-a652-171539d23f3a
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3091738464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3091738464
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2960858029
Short name T1320
Test name
Test status
Simulation time 15150179930 ps
CPU time 3432.15 seconds
Started Jul 14 08:03:39 PM PDT 24
Finished Jul 14 09:00:52 PM PDT 24
Peak memory 609760 kb
Host smart-bbfe6ad7-9590-4354-a00e-ae8683fe0638
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2960858029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2960858029
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1640391426
Short name T1273
Test name
Test status
Simulation time 14564144960 ps
CPU time 4265.44 seconds
Started Jul 14 08:01:21 PM PDT 24
Finished Jul 14 09:12:28 PM PDT 24
Peak memory 608856 kb
Host smart-f83cb44c-95e0-4572-be32-e50f976a5441
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1640391426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1640391426
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2434348395
Short name T108
Test name
Test status
Simulation time 11698375390 ps
CPU time 3071.01 seconds
Started Jul 14 07:59:10 PM PDT 24
Finished Jul 14 08:50:22 PM PDT 24
Peak memory 608852 kb
Host smart-71625069-aae7-49b8-9206-55a0980cc6ba
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4,
mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2434348395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2434348395
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.186876135
Short name T1140
Test name
Test status
Simulation time 15735684934 ps
CPU time 3821.02 seconds
Started Jul 14 08:00:47 PM PDT 24
Finished Jul 14 09:04:29 PM PDT 24
Peak memory 609816 kb
Host smart-0681c161-a17a-49c5-83cd-2ab1eb12c79f
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186876135 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.186876135
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2107143942
Short name T279
Test name
Test status
Simulation time 14812308644 ps
CPU time 4403.04 seconds
Started Jul 14 08:01:35 PM PDT 24
Finished Jul 14 09:14:59 PM PDT 24
Peak memory 608816 kb
Host smart-67e8c1b3-6820-4ada-86d9-69bdeda21985
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107143942
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2107143942
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1034378675
Short name T913
Test name
Test status
Simulation time 14998806584 ps
CPU time 4315.55 seconds
Started Jul 14 08:06:31 PM PDT 24
Finished Jul 14 09:18:28 PM PDT 24
Peak memory 608784 kb
Host smart-f5ae7534-0341-45d1-a4d3-fa488a7a8c7c
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103437
8675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1034378675
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.862719965
Short name T879
Test name
Test status
Simulation time 15235320080 ps
CPU time 3729.47 seconds
Started Jul 14 08:01:26 PM PDT 24
Finished Jul 14 09:03:36 PM PDT 24
Peak memory 608812 kb
Host smart-f165a84b-608d-4a80-9a9c-3e7cb633b15c
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862719965 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.862719965
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1330446992
Short name T887
Test name
Test status
Simulation time 11611800568 ps
CPU time 2805.21 seconds
Started Jul 14 08:02:49 PM PDT 24
Finished Jul 14 08:49:35 PM PDT 24
Peak memory 608832 kb
Host smart-4196be34-1216-40fe-89e5-3524a926b91e
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1330446992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1330446992
Directory /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.844923583
Short name T710
Test name
Test status
Simulation time 10596150112 ps
CPU time 2103.61 seconds
Started Jul 14 07:56:40 PM PDT 24
Finished Jul 14 08:31:46 PM PDT 24
Peak memory 623592 kb
Host smart-eb813c99-d55b-4498-bae1-56e25919fa99
User root
Command /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84492
3583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.844923583
Directory /workspace/0.rom_e2e_jtag_debug_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3924610630
Short name T258
Test name
Test status
Simulation time 10732576861 ps
CPU time 2269.05 seconds
Started Jul 14 07:56:38 PM PDT 24
Finished Jul 14 08:34:28 PM PDT 24
Peak memory 623608 kb
Host smart-bf9b521c-d67d-4650-a9fd-010b615e8903
User root
Command /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3924610630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.3924610630
Directory /workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.4155140952
Short name T1040
Test name
Test status
Simulation time 28806404495 ps
CPU time 2862.97 seconds
Started Jul 14 07:57:36 PM PDT 24
Finished Jul 14 08:45:20 PM PDT 24
Peak memory 622800 kb
Host smart-9a68869a-d9df-4c43-9999-e9684b292cb4
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di
sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4155140952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.4155140952
Directory /workspace/0.rom_e2e_jtag_inject_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3885513350
Short name T471
Test name
Test status
Simulation time 22125976357 ps
CPU time 3159.75 seconds
Started Jul 14 07:57:33 PM PDT 24
Finished Jul 14 08:50:14 PM PDT 24
Peak memory 619824 kb
Host smart-d8f96b2e-20ab-4914-a10f-a2147bd8a54c
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di
sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3885513350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.3885513350
Directory /workspace/0.rom_e2e_jtag_inject_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.3642413124
Short name T256
Test name
Test status
Simulation time 32052744070 ps
CPU time 3453.33 seconds
Started Jul 14 07:57:15 PM PDT 24
Finished Jul 14 08:54:50 PM PDT 24
Peak memory 620476 kb
Host smart-0e664257-8b6e-41cb-8988-d90066b80b8e
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock
ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642413124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_
inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject
_test_unlocked0.3642413124
Directory /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.966939607
Short name T1088
Test name
Test status
Simulation time 14608591608 ps
CPU time 3654.18 seconds
Started Jul 14 08:02:55 PM PDT 24
Finished Jul 14 09:03:50 PM PDT 24
Peak memory 609640 kb
Host smart-44284c03-8b52-4dd6-bf16-6ada914267e2
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid
_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966939607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_ini
t_rom_ext_invalid_meas.966939607
Directory /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2882950717
Short name T1070
Test name
Test status
Simulation time 15445833298 ps
CPU time 4374.36 seconds
Started Jul 14 08:01:40 PM PDT 24
Finished Jul 14 09:14:35 PM PDT 24
Peak memory 609900 kb
Host smart-993cb51d-7efd-429d-a8ec-50df95bcf97d
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:
new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882950717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.2882950717
Directory /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1473457321
Short name T1063
Test name
Test status
Simulation time 15480206756 ps
CPU time 4265.17 seconds
Started Jul 14 08:02:35 PM PDT 24
Finished Jul 14 09:13:41 PM PDT 24
Peak memory 609712 kb
Host smart-0a340e79-59e1-42b6-b3dd-48428c049db0
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas
:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473457321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext
_no_meas.1473457321
Directory /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.4070191696
Short name T1076
Test name
Test status
Simulation time 14514191944 ps
CPU time 3668.35 seconds
Started Jul 14 08:02:14 PM PDT 24
Finished Jul 14 09:03:23 PM PDT 24
Peak memory 610596 kb
Host smart-8aec303b-ff2a-4df0-bfb9-cfafd6288091
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne
w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070191696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu
tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_
shutdown_exception_c.4070191696
Directory /workspace/0.rom_e2e_shutdown_exception_c/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3989521437
Short name T1001
Test name
Test status
Simulation time 23942647810 ps
CPU time 4762.54 seconds
Started Jul 14 07:57:24 PM PDT 24
Finished Jul 14 09:16:48 PM PDT 24
Peak memory 609896 kb
Host smart-c9c80769-91d3-42d5-92e4-b00f9b906e2e
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev
:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3989521437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b
ad_dev.3989521437
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2241476611
Short name T54
Test name
Test status
Simulation time 24394398152 ps
CPU time 6085.37 seconds
Started Jul 14 08:05:06 PM PDT 24
Finished Jul 14 09:46:32 PM PDT 24
Peak memory 610700 kb
Host smart-ae1d8834-5429-417c-93b8-5c67414e104a
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p
rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2241476611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_
b_bad_prod.2241476611
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3399406029
Short name T272
Test name
Test status
Simulation time 24025101524 ps
CPU time 5541.33 seconds
Started Jul 14 08:00:46 PM PDT 24
Finished Jul 14 09:33:08 PM PDT 24
Peak memory 610816 kb
Host smart-6a85e3c9-d91e-4ac0-86c9-51a310512b85
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p
rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=3399406029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_
bad_b_bad_prod_end.3399406029
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3120163938
Short name T1227
Test name
Test status
Simulation time 23350725854 ps
CPU time 5223.39 seconds
Started Jul 14 08:01:47 PM PDT 24
Finished Jul 14 09:28:52 PM PDT 24
Peak memory 608924 kb
Host smart-aefd8b16-d1c0-4bf0-9335-b72814065d26
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r
ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=3120163938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b
_bad_rma.3120163938
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.834294317
Short name T956
Test name
Test status
Simulation time 18454362234 ps
CPU time 4408.85 seconds
Started Jul 14 08:01:21 PM PDT 24
Finished Jul 14 09:14:51 PM PDT 24
Peak memory 610128 kb
Host smart-dff11c43-8844-44a0-84fb-bab91fad5d36
User root
Command /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t
est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=834294317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_
bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alwa
ys_a_bad_b_bad_test_unlocked0.834294317
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.381660496
Short name T1038
Test name
Test status
Simulation time 15338637877 ps
CPU time 3983.81 seconds
Started Jul 14 08:04:28 PM PDT 24
Finished Jul 14 09:10:53 PM PDT 24
Peak memory 609924 kb
Host smart-6c349275-659f-491a-9bed-cdcdae5a3787
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381660496 -assert nopostproc +UVM_TESTNAME=chip_base_t
est +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.381660496
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2925685200
Short name T939
Test name
Test status
Simulation time 14856423000 ps
CPU time 4077.88 seconds
Started Jul 14 08:01:24 PM PDT 24
Finished Jul 14 09:09:23 PM PDT 24
Peak memory 608916 kb
Host smart-eb47d912-e5c2-4a3d-9a3a-32828fa43b22
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925685200 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2925685200
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2716954632
Short name T1019
Test name
Test status
Simulation time 14487899095 ps
CPU time 3450.47 seconds
Started Jul 14 08:00:29 PM PDT 24
Finished Jul 14 08:58:01 PM PDT 24
Peak memory 609864 kb
Host smart-afc0c8c0-5688-4d09-ba4f-a418980bbbc6
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716954632 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2716954632
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.423890106
Short name T1129
Test name
Test status
Simulation time 14338345418 ps
CPU time 3443.04 seconds
Started Jul 14 08:01:11 PM PDT 24
Finished Jul 14 08:58:35 PM PDT 24
Peak memory 608904 kb
Host smart-056ef334-9326-47bb-b644-ceb45c911d56
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423890106 -assert nopostproc +UVM_TESTNAME=chip_base_
test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.423890106
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3858984441
Short name T1186
Test name
Test status
Simulation time 11269409930 ps
CPU time 2916.69 seconds
Started Jul 14 07:58:56 PM PDT 24
Finished Jul 14 08:47:34 PM PDT 24
Peak memory 610032 kb
Host smart-eb054605-5e90-4b21-ae6e-a9f105d42102
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858984441 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3858984441
Directory /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1688065798
Short name T1000
Test name
Test status
Simulation time 13835056062 ps
CPU time 3647.94 seconds
Started Jul 14 08:02:29 PM PDT 24
Finished Jul 14 09:03:18 PM PDT 24
Peak memory 608868 kb
Host smart-063d5adf-25ec-4ab1-b3b0-c76aad0f8de0
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688065798 -assert nopostproc +UVM_TESTNAME=chip_base_
test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1688065798
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1765010818
Short name T273
Test name
Test status
Simulation time 15521282976 ps
CPU time 3355.12 seconds
Started Jul 14 08:00:19 PM PDT 24
Finished Jul 14 08:56:15 PM PDT 24
Peak memory 609900 kb
Host smart-0d801de4-0e18-4c87-ae4c-996a6850471c
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765010818 -assert nopostproc +UVM_TESTNAME=chip_bas
e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1765010818
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2393843940
Short name T1233
Test name
Test status
Simulation time 14256806500 ps
CPU time 3572.16 seconds
Started Jul 14 07:59:36 PM PDT 24
Finished Jul 14 08:59:09 PM PDT 24
Peak memory 609824 kb
Host smart-74598b9a-fab8-4d51-b8ee-dbe21602756f
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393843940 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2393843940
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.427348416
Short name T1049
Test name
Test status
Simulation time 13943754750 ps
CPU time 3228.51 seconds
Started Jul 14 07:59:34 PM PDT 24
Finished Jul 14 08:53:24 PM PDT 24
Peak memory 609848 kb
Host smart-43d735c0-8f50-4c2c-873d-890de54aa2a5
User root
Command /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427348416 -assert nopostproc +UVM_TESTNAME=chip_base_
test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.427348416
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest

Test location /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3920221838
Short name T1111
Test name
Test status
Simulation time 10572544786 ps
CPU time 2622.19 seconds
Started Jul 14 08:02:00 PM PDT 24
Finished Jul 14 08:45:43 PM PDT 24
Peak memory 609048 kb
Host smart-4cbef34e-e104-4d13-b55d-11f1adf25dbd
User root
Command /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:
ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920221838 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3920221838
Directory /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest

Test location /workspace/coverage/default/0.rom_e2e_smoke.3638756026
Short name T1222
Test name
Test status
Simulation time 14951026382 ps
CPU time 4070.75 seconds
Started Jul 14 08:02:53 PM PDT 24
Finished Jul 14 09:10:44 PM PDT 24
Peak memory 609836 kb
Host smart-3875ec4d-0b94-42f2-9fa4-6b734f22ddb6
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img
_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to
p/hw/dv/tools/sim.tcl +ntb_random_seed=3638756026 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.3638756026
Directory /workspace/0.rom_e2e_smoke/latest

Test location /workspace/coverage/default/0.rom_e2e_static_critical.3881317486
Short name T57
Test name
Test status
Simulation time 17260920552 ps
CPU time 4011.31 seconds
Started Jul 14 08:03:04 PM PDT 24
Finished Jul 14 09:09:56 PM PDT 24
Peak memory 609792 kb
Host smart-8b045efc-762a-41e4-8aa3-1024f8f72611
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul
es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881317486 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.3881317486
Directory /workspace/0.rom_e2e_static_critical/latest

Test location /workspace/coverage/default/0.rom_keymgr_functest.1158419395
Short name T982
Test name
Test status
Simulation time 4037279802 ps
CPU time 439.36 seconds
Started Jul 14 08:00:16 PM PDT 24
Finished Jul 14 08:07:36 PM PDT 24
Peak memory 609364 kb
Host smart-08d4470f-124c-48ec-9dc8-bcf5ab321a11
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158419395 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.1158419395
Directory /workspace/0.rom_keymgr_functest/latest

Test location /workspace/coverage/default/0.rom_raw_unlock.31809172
Short name T170
Test name
Test status
Simulation time 6818590599 ps
CPU time 303.78 seconds
Started Jul 14 07:58:11 PM PDT 24
Finished Jul 14 08:03:15 PM PDT 24
Peak memory 623140 kb
Host smart-897c5aef-54e3-4739-ac06-57ea1206f353
User root
Command /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE
xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=31809172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.31809172
Directory /workspace/0.rom_raw_unlock/latest

Test location /workspace/coverage/default/0.rom_volatile_raw_unlock.3032233930
Short name T1159
Test name
Test status
Simulation time 2152379833 ps
CPU time 106.08 seconds
Started Jul 14 07:55:47 PM PDT 24
Finished Jul 14 07:57:34 PM PDT 24
Peak memory 615832 kb
Host smart-a2569a1b-c3c3-460b-99be-83c01c936ed4
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1
+sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032233930 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.3032233930
Directory /workspace/0.rom_volatile_raw_unlock/latest

Test location /workspace/coverage/default/1.chip_jtag_csr_rw.4014320454
Short name T65
Test name
Test status
Simulation time 9375513880 ps
CPU time 1024.72 seconds
Started Jul 14 07:55:25 PM PDT 24
Finished Jul 14 08:12:31 PM PDT 24
Peak memory 607304 kb
Host smart-82a66636-4fa5-4e2e-bb28-432b4a025555
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014320454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c
hip_jtag_csr_rw.4014320454
Directory /workspace/1.chip_jtag_csr_rw/latest

Test location /workspace/coverage/default/1.chip_jtag_mem_access.2290497152
Short name T208
Test name
Test status
Simulation time 13863276520 ps
CPU time 1579.43 seconds
Started Jul 14 07:55:16 PM PDT 24
Finished Jul 14 08:21:37 PM PDT 24
Peak memory 607316 kb
Host smart-30932dea-2bd8-41d6-9d3a-0e84f42fcba9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290497152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_
mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.2
290497152
Directory /workspace/1.chip_jtag_mem_access/latest

Test location /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1470712494
Short name T7
Test name
Test status
Simulation time 3017060678 ps
CPU time 269.5 seconds
Started Jul 14 08:03:44 PM PDT 24
Finished Jul 14 08:08:14 PM PDT 24
Peak memory 618684 kb
Host smart-86ce5714-e511-4ee5-baf2-e4bec7fbf849
User root
Command /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1
470712494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.1470712494
Directory /workspace/1.chip_rv_dm_ndm_reset_req/latest

Test location /workspace/coverage/default/1.chip_sival_flash_info_access.2992337238
Short name T1187
Test name
Test status
Simulation time 2847142064 ps
CPU time 279.55 seconds
Started Jul 14 07:57:20 PM PDT 24
Finished Jul 14 08:02:00 PM PDT 24
Peak memory 608664 kb
Host smart-0aaa2d76-361d-4408-a6cc-66cba864fa71
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=2992337238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.2992337238
Directory /workspace/1.chip_sival_flash_info_access/latest

Test location /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.259743538
Short name T1148
Test name
Test status
Simulation time 18839060720 ps
CPU time 650.41 seconds
Started Jul 14 08:01:59 PM PDT 24
Finished Jul 14 08:12:50 PM PDT 24
Peak memory 618552 kb
Host smart-23f06ea8-855d-4c7c-a182-88db7abd7f0a
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=259743538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.259743538
Directory /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_aes_enc.2178722287
Short name T395
Test name
Test status
Simulation time 3152683112 ps
CPU time 326.92 seconds
Started Jul 14 07:58:48 PM PDT 24
Finished Jul 14 08:04:15 PM PDT 24
Peak memory 608676 kb
Host smart-23665a5e-6544-493b-b363-9b199dbad4b1
User root
Command /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178722287 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.2178722287
Directory /workspace/1.chip_sw_aes_enc/latest

Test location /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1604834462
Short name T892
Test name
Test status
Simulation time 3591996666 ps
CPU time 243.06 seconds
Started Jul 14 07:59:38 PM PDT 24
Finished Jul 14 08:03:42 PM PDT 24
Peak memory 609192 kb
Host smart-cb0c8bd9-4493-480b-8c8f-5f751f04da11
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604
834462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.1604834462
Directory /workspace/1.chip_sw_aes_enc_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.742401742
Short name T916
Test name
Test status
Simulation time 2932896720 ps
CPU time 272.19 seconds
Started Jul 14 08:07:35 PM PDT 24
Finished Jul 14 08:12:09 PM PDT 24
Peak memory 609220 kb
Host smart-dd82f417-bcab-4c9a-9825-fefe01b312a8
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=742401742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.742401742
Directory /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_aes_entropy.3353402904
Short name T701
Test name
Test status
Simulation time 2572921458 ps
CPU time 188.19 seconds
Started Jul 14 07:58:26 PM PDT 24
Finished Jul 14 08:01:35 PM PDT 24
Peak memory 608684 kb
Host smart-5c5fef7e-442c-495a-b25f-f75808a927b3
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353402904 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.3353402904
Directory /workspace/1.chip_sw_aes_entropy/latest

Test location /workspace/coverage/default/1.chip_sw_aes_idle.236098395
Short name T423
Test name
Test status
Simulation time 2996455068 ps
CPU time 282.13 seconds
Started Jul 14 08:01:05 PM PDT 24
Finished Jul 14 08:05:49 PM PDT 24
Peak memory 609396 kb
Host smart-5258ad18-b860-4c5a-bb65-488f071b8d46
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236098395 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.236098395
Directory /workspace/1.chip_sw_aes_idle/latest

Test location /workspace/coverage/default/1.chip_sw_aes_masking_off.907181092
Short name T664
Test name
Test status
Simulation time 2938101612 ps
CPU time 391.58 seconds
Started Jul 14 08:01:11 PM PDT 24
Finished Jul 14 08:07:44 PM PDT 24
Peak memory 609972 kb
Host smart-58f15fc8-eebe-4134-b2e7-6e4c9a3a8676
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907181092 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.907181092
Directory /workspace/1.chip_sw_aes_masking_off/latest

Test location /workspace/coverage/default/1.chip_sw_aes_smoketest.2825984820
Short name T1285
Test name
Test status
Simulation time 3134827904 ps
CPU time 403.32 seconds
Started Jul 14 08:04:09 PM PDT 24
Finished Jul 14 08:10:53 PM PDT 24
Peak memory 609052 kb
Host smart-62c2deb4-d793-465f-a982-5cc583df7cd6
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825984820 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_aes_smoketest.2825984820
Directory /workspace/1.chip_sw_aes_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_entropy.2523331548
Short name T93
Test name
Test status
Simulation time 3654279971 ps
CPU time 332.63 seconds
Started Jul 14 08:00:36 PM PDT 24
Finished Jul 14 08:06:09 PM PDT 24
Peak memory 609176 kb
Host smart-8f0b2e56-de82-4862-a3bf-ca0296f7125b
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2523331548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.2523331548
Directory /workspace/1.chip_sw_alert_handler_entropy/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_escalation.2523576034
Short name T431
Test name
Test status
Simulation time 4715663704 ps
CPU time 604.35 seconds
Started Jul 14 07:59:11 PM PDT 24
Finished Jul 14 08:09:16 PM PDT 24
Peak memory 618820 kb
Host smart-249ca6a4-c537-4d0a-831e-897335b9878f
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=2523576034 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.2523576034
Directory /workspace/1.chip_sw_alert_handler_escalation/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.208838395
Short name T313
Test name
Test status
Simulation time 5620514616 ps
CPU time 1044.5 seconds
Started Jul 14 08:00:32 PM PDT 24
Finished Jul 14 08:17:57 PM PDT 24
Peak memory 609840 kb
Host smart-a282769a-43bb-4534-ab96-b22e0378c2f4
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=208838395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.208838395
Directory /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.824213707
Short name T1239
Test name
Test status
Simulation time 9819997180 ps
CPU time 1921.36 seconds
Started Jul 14 08:03:24 PM PDT 24
Finished Jul 14 08:35:26 PM PDT 24
Peak memory 609444 kb
Host smart-223d5c4d-b61f-4a0a-ad03-e46f58c52603
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=824213707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_toggle.824213707
Directory /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1045812189
Short name T741
Test name
Test status
Simulation time 12690805256 ps
CPU time 1377.53 seconds
Started Jul 14 07:59:57 PM PDT 24
Finished Jul 14 08:22:55 PM PDT 24
Peak memory 610364 kb
Host smart-f7e4ade4-fd27-4d7a-afab-fecc7fdcca3b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler
_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045812189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han
dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.chip_sw_alert_handler_lpg_sleep_mode_pings.1045812189
Directory /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1856755168
Short name T1110
Test name
Test status
Simulation time 8029467190 ps
CPU time 1475.53 seconds
Started Jul 14 08:01:09 PM PDT 24
Finished Jul 14 08:25:45 PM PDT 24
Peak memory 609876 kb
Host smart-ce6944e4-6cf9-4224-8fcd-2f49e09f1fc9
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=1856755168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.1856755168
Directory /workspace/1.chip_sw_alert_handler_ping_ok/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1759342508
Short name T303
Test name
Test status
Simulation time 2955661672 ps
CPU time 265.85 seconds
Started Jul 14 07:59:43 PM PDT 24
Finished Jul 14 08:04:09 PM PDT 24
Peak memory 608644 kb
Host smart-852a49a4-cff4-4418-bacc-9a71035250f9
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1759342508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.1759342508
Directory /workspace/1.chip_sw_alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1494741290
Short name T712
Test name
Test status
Simulation time 254353657272 ps
CPU time 11829.1 seconds
Started Jul 14 07:58:27 PM PDT 24
Finished Jul 14 11:15:38 PM PDT 24
Peak memory 610196 kb
Host smart-160309a4-05ea-40b9-aa2a-0a7ab8a56b7a
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494741290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1494741290
Directory /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_irq.605915685
Short name T370
Test name
Test status
Simulation time 4173127466 ps
CPU time 347.3 seconds
Started Jul 14 07:59:52 PM PDT 24
Finished Jul 14 08:05:40 PM PDT 24
Peak memory 608212 kb
Host smart-5631cdc1-cf32-48c1-9ecf-ad26dc7ff08c
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605915685 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.605915685
Directory /workspace/1.chip_sw_aon_timer_irq/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3908282805
Short name T1312
Test name
Test status
Simulation time 7128691704 ps
CPU time 560.43 seconds
Started Jul 14 07:57:58 PM PDT 24
Finished Jul 14 08:07:19 PM PDT 24
Peak memory 608992 kb
Host smart-1767e834-938c-4eb9-b130-6a4d2d89b0cf
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3908282805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3908282805
Directory /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2561223677
Short name T1046
Test name
Test status
Simulation time 2909921384 ps
CPU time 259.28 seconds
Started Jul 14 08:05:34 PM PDT 24
Finished Jul 14 08:09:54 PM PDT 24
Peak memory 607944 kb
Host smart-42094bae-047f-4def-b5eb-d1224b09cf61
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561223677 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_aon_timer_smoketest.2561223677
Directory /workspace/1.chip_sw_aon_timer_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2147913197
Short name T298
Test name
Test status
Simulation time 9626840144 ps
CPU time 1274.54 seconds
Started Jul 14 08:00:33 PM PDT 24
Finished Jul 14 08:21:48 PM PDT 24
Peak memory 609996 kb
Host smart-76e16c11-2eda-4a38-8846-9728c337bdbf
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2147913197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.2147913197
Directory /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest

Test location /workspace/coverage/default/1.chip_sw_ast_clk_outputs.3361102813
Short name T1221
Test name
Test status
Simulation time 7051659196 ps
CPU time 1179.33 seconds
Started Jul 14 08:03:08 PM PDT 24
Finished Jul 14 08:22:48 PM PDT 24
Peak memory 615316 kb
Host smart-556d792e-f9a0-4627-8134-aad1c9c88dfc
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361102813 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.3361102813
Directory /workspace/1.chip_sw_ast_clk_outputs/latest

Test location /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.3970517248
Short name T135
Test name
Test status
Simulation time 21194626348 ps
CPU time 3007.63 seconds
Started Jul 14 08:08:25 PM PDT 24
Finished Jul 14 08:58:34 PM PDT 24
Peak memory 609948 kb
Host smart-964a347c-6b7a-4d95-a998-5441d06035fe
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970517248
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.3970517248
Directory /workspace/1.chip_sw_ast_clk_rst_inputs/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2582818250
Short name T959
Test name
Test status
Simulation time 8978010613 ps
CPU time 1009.39 seconds
Started Jul 14 08:01:14 PM PDT 24
Finished Jul 14 08:18:04 PM PDT 24
Peak memory 621440 kb
Host smart-0e229ec2-0cde-4f6b-b81d-59e064356c96
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=2582818250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.2582818250
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4028987002
Short name T898
Test name
Test status
Simulation time 4503753830 ps
CPU time 718.94 seconds
Started Jul 14 08:03:03 PM PDT 24
Finished Jul 14 08:15:04 PM PDT 24
Peak memory 612360 kb
Host smart-c403665b-c766-417f-a86c-b020ffd1b942
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028987002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_dev.4028987002
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1437280541
Short name T1125
Test name
Test status
Simulation time 4608474868 ps
CPU time 649.14 seconds
Started Jul 14 08:01:43 PM PDT 24
Finished Jul 14 08:12:32 PM PDT 24
Peak memory 612368 kb
Host smart-ef945675-e74c-49d6-89be-b2f623b213f5
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437280541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_rma.1437280541
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3079317368
Short name T1311
Test name
Test status
Simulation time 3283276392 ps
CPU time 628.82 seconds
Started Jul 14 08:02:20 PM PDT 24
Finished Jul 14 08:12:50 PM PDT 24
Peak memory 611104 kb
Host smart-a467fe2b-7508-4244-baa3-b0060fb707f5
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079317368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3079317368
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.11205424
Short name T419
Test name
Test status
Simulation time 5323064250 ps
CPU time 567.11 seconds
Started Jul 14 08:01:35 PM PDT 24
Finished Jul 14 08:11:02 PM PDT 24
Peak memory 612344 kb
Host smart-eb477cc7-fb5d-4f5c-a660-a0d472ba845a
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11205424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clk
mgr_external_clk_src_for_sw_slow_dev.11205424
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2849676978
Short name T891
Test name
Test status
Simulation time 4760708486 ps
CPU time 709.31 seconds
Started Jul 14 08:04:53 PM PDT 24
Finished Jul 14 08:16:43 PM PDT 24
Peak memory 612340 kb
Host smart-307f19dd-1631-40c9-8641-b28100c65d05
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849676978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_rma.2849676978
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2663329958
Short name T941
Test name
Test status
Simulation time 4857665614 ps
CPU time 821.67 seconds
Started Jul 14 08:02:11 PM PDT 24
Finished Jul 14 08:15:53 PM PDT 24
Peak memory 612396 kb
Host smart-048ef636-98b2-4520-8e33-889759c7fbd6
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663329958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2663329958
Directory /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3439978649
Short name T1023
Test name
Test status
Simulation time 3360333951 ps
CPU time 262.26 seconds
Started Jul 14 08:01:53 PM PDT 24
Finished Jul 14 08:06:15 PM PDT 24
Peak memory 609116 kb
Host smart-bc7b1874-8471-4bbe-b9cb-1e0697cb792f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439978649 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_clkmgr_jitter.3439978649
Directory /workspace/1.chip_sw_clkmgr_jitter/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3766329841
Short name T1289
Test name
Test status
Simulation time 3448592728 ps
CPU time 411.17 seconds
Started Jul 14 08:02:26 PM PDT 24
Finished Jul 14 08:09:18 PM PDT 24
Peak memory 609112 kb
Host smart-f7515b02-bc5a-4326-958d-14e42ce51c76
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766329841 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.3766329841
Directory /workspace/1.chip_sw_clkmgr_jitter_frequency/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.511386548
Short name T1081
Test name
Test status
Simulation time 2507617708 ps
CPU time 211 seconds
Started Jul 14 08:06:00 PM PDT 24
Finished Jul 14 08:09:31 PM PDT 24
Peak memory 608664 kb
Host smart-279ceb91-9834-4767-ac44-ad8902025837
User root
Command /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511386548 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.511386548
Directory /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3945758709
Short name T1069
Test name
Test status
Simulation time 4847622248 ps
CPU time 521.89 seconds
Started Jul 14 08:03:03 PM PDT 24
Finished Jul 14 08:11:45 PM PDT 24
Peak memory 609432 kb
Host smart-45f1f6c5-89d9-40e5-ba13-087508c6f883
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945758709 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.3945758709
Directory /workspace/1.chip_sw_clkmgr_off_aes_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1376391570
Short name T1306
Test name
Test status
Simulation time 3934792470 ps
CPU time 360.98 seconds
Started Jul 14 08:02:00 PM PDT 24
Finished Jul 14 08:08:01 PM PDT 24
Peak memory 609212 kb
Host smart-d656b9b5-9575-46b1-9a9f-21717321e0af
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376391570 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.1376391570
Directory /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3830394616
Short name T1026
Test name
Test status
Simulation time 5375867816 ps
CPU time 508.23 seconds
Started Jul 14 08:01:22 PM PDT 24
Finished Jul 14 08:09:51 PM PDT 24
Peak memory 609500 kb
Host smart-768e0cd4-4d5d-4e86-bef3-49947141017f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830394616 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.3830394616
Directory /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1761626329
Short name T193
Test name
Test status
Simulation time 4409139794 ps
CPU time 614.82 seconds
Started Jul 14 08:03:27 PM PDT 24
Finished Jul 14 08:13:42 PM PDT 24
Peak memory 609784 kb
Host smart-56c43ccf-5638-47b2-8ea5-f48d1c1038dc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761626329 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.1761626329
Directory /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1341099560
Short name T1288
Test name
Test status
Simulation time 9960460050 ps
CPU time 1489.69 seconds
Started Jul 14 08:01:49 PM PDT 24
Finished Jul 14 08:26:39 PM PDT 24
Peak memory 610100 kb
Host smart-c7775a0e-fa0c-4001-b07d-d638a3f1c139
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341099560
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.1341099560
Directory /workspace/1.chip_sw_clkmgr_off_peri/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3183204341
Short name T452
Test name
Test status
Simulation time 3536061427 ps
CPU time 412.98 seconds
Started Jul 14 08:01:33 PM PDT 24
Finished Jul 14 08:08:26 PM PDT 24
Peak memory 608724 kb
Host smart-8c96fc9b-c694-4733-b779-fab22ff609e4
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183204341 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.3183204341
Directory /workspace/1.chip_sw_clkmgr_reset_frequency/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1946960306
Short name T1322
Test name
Test status
Simulation time 4514589808 ps
CPU time 701.3 seconds
Started Jul 14 08:03:00 PM PDT 24
Finished Jul 14 08:14:41 PM PDT 24
Peak memory 609576 kb
Host smart-30ee2265-a960-4850-abf5-b63b4ce34824
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946960306 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.1946960306
Directory /workspace/1.chip_sw_clkmgr_sleep_frequency/latest

Test location /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.495786536
Short name T1283
Test name
Test status
Simulation time 2754939524 ps
CPU time 179.65 seconds
Started Jul 14 08:06:37 PM PDT 24
Finished Jul 14 08:09:37 PM PDT 24
Peak memory 609052 kb
Host smart-5aa11f13-d4d6-409b-b6af-eda8abfd94c0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495786536 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.chip_sw_clkmgr_smoketest.495786536
Directory /workspace/1.chip_sw_clkmgr_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1599333909
Short name T269
Test name
Test status
Simulation time 22104624128 ps
CPU time 4989.58 seconds
Started Jul 14 08:00:45 PM PDT 24
Finished Jul 14 09:23:56 PM PDT 24
Peak memory 609688 kb
Host smart-8848c0a0-9bd3-442c-ab15-e91a70ed86c1
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c
oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599333909 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.1599333909
Directory /workspace/1.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2119913493
Short name T666
Test name
Test status
Simulation time 149730560776 ps
CPU time 19231 seconds
Started Jul 14 08:04:12 PM PDT 24
Finished Jul 15 01:24:45 AM PDT 24
Peak memory 609960 kb
Host smart-04ab6390-6b9a-4cb4-8b53-9dd9493d8844
User root
Command /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de
vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2119913493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.2119913493
Directory /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2438395104
Short name T442
Test name
Test status
Simulation time 5209758894 ps
CPU time 596.65 seconds
Started Jul 14 08:03:06 PM PDT 24
Finished Jul 14 08:13:04 PM PDT 24
Peak memory 608788 kb
Host smart-4a4d5f55-12f3-4894-b281-928b48ef97db
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24383
95104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.2438395104
Directory /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_kat_test.2999149502
Short name T937
Test name
Test status
Simulation time 2303046928 ps
CPU time 192.91 seconds
Started Jul 14 08:00:01 PM PDT 24
Finished Jul 14 08:03:15 PM PDT 24
Peak memory 608684 kb
Host smart-0bb2a032-eb98-4154-a17c-39c924fa4466
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999149502 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.2999149502
Directory /workspace/1.chip_sw_csrng_kat_test/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3024299189
Short name T1144
Test name
Test status
Simulation time 6428677456 ps
CPU time 666.31 seconds
Started Jul 14 08:00:14 PM PDT 24
Finished Jul 14 08:11:21 PM PDT 24
Peak memory 610680 kb
Host smart-41d0cbaf-f1bf-4f19-8d7d-ebf5a8fd5fba
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima
ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024299189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_
lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr
ng_lc_hw_debug_en_test.3024299189
Directory /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location /workspace/coverage/default/1.chip_sw_csrng_smoketest.1160796548
Short name T1016
Test name
Test status
Simulation time 2312056548 ps
CPU time 276.42 seconds
Started Jul 14 08:08:23 PM PDT 24
Finished Jul 14 08:13:02 PM PDT 24
Peak memory 609032 kb
Host smart-1dd7a8f1-5fd5-45c9-91c3-7b78143b541b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160796548 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.chip_sw_csrng_smoketest.1160796548
Directory /workspace/1.chip_sw_csrng_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_data_integrity_escalation.17921366
Short name T278
Test name
Test status
Simulation time 6907555524 ps
CPU time 805.37 seconds
Started Jul 14 07:58:14 PM PDT 24
Finished Jul 14 08:11:40 PM PDT 24
Peak memory 610344 kb
Host smart-e9606bb0-8923-4979-8fe0-dd5a43cfe2e8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=17921366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.17921366
Directory /workspace/1.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/1.chip_sw_edn_auto_mode.1911698612
Short name T1055
Test name
Test status
Simulation time 5652047628 ps
CPU time 1429.17 seconds
Started Jul 14 08:00:11 PM PDT 24
Finished Jul 14 08:24:01 PM PDT 24
Peak memory 609880 kb
Host smart-04ab29cf-f666-446c-9ead-b9abbbdd226b
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc
elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911698612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_
auto_mode.1911698612
Directory /workspace/1.chip_sw_edn_auto_mode/latest

Test location /workspace/coverage/default/1.chip_sw_edn_boot_mode.1276243832
Short name T663
Test name
Test status
Simulation time 3458817472 ps
CPU time 651.04 seconds
Started Jul 14 07:59:41 PM PDT 24
Finished Jul 14 08:10:33 PM PDT 24
Peak memory 608368 kb
Host smart-499de79e-eaa9-4f19-b8ad-37d14158ed98
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc
elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276243832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_
boot_mode.1276243832
Directory /workspace/1.chip_sw_edn_boot_mode/latest

Test location /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2346825342
Short name T481
Test name
Test status
Simulation time 6642632056 ps
CPU time 1070.86 seconds
Started Jul 14 08:03:33 PM PDT 24
Finished Jul 14 08:21:24 PM PDT 24
Peak memory 610368 kb
Host smart-87cc2a08-6c0c-41f1-8d92-6df2d7195d08
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed
n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2346825342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.2346825342
Directory /workspace/1.chip_sw_edn_entropy_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.373031450
Short name T151
Test name
Test status
Simulation time 6951658641 ps
CPU time 1330.44 seconds
Started Jul 14 08:00:47 PM PDT 24
Finished Jul 14 08:22:58 PM PDT 24
Peak memory 610396 kb
Host smart-9348d4fe-5322-4c26-a827-8c9021b2e7a4
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e
ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373031450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.373031450
Directory /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest

Test location /workspace/coverage/default/1.chip_sw_edn_kat.260014959
Short name T926
Test name
Test status
Simulation time 3100978874 ps
CPU time 645.62 seconds
Started Jul 14 07:59:14 PM PDT 24
Finished Jul 14 08:10:01 PM PDT 24
Peak memory 615948 kb
Host smart-0d3aa6a8-b654-4c73-a704-8ddf59e889df
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag
es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260014959 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_edn_kat.260014959
Directory /workspace/1.chip_sw_edn_kat/latest

Test location /workspace/coverage/default/1.chip_sw_edn_sw_mode.270936674
Short name T465
Test name
Test status
Simulation time 9263095680 ps
CPU time 2192.93 seconds
Started Jul 14 08:00:55 PM PDT 24
Finished Jul 14 08:37:29 PM PDT 24
Peak memory 608684 kb
Host smart-94d6fc2f-f02c-43ff-ab86-be7b3bedb303
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270936674 -assert n
opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.270936674
Directory /workspace/1.chip_sw_edn_sw_mode/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1454330360
Short name T1093
Test name
Test status
Simulation time 2432639480 ps
CPU time 209.31 seconds
Started Jul 14 08:00:08 PM PDT 24
Finished Jul 14 08:03:38 PM PDT 24
Peak memory 609304 kb
Host smart-abb34f23-35fe-48f8-b033-73846e705c42
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14
54330360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.1454330360
Directory /workspace/1.chip_sw_entropy_src_ast_rng_req/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_csrng.1169633870
Short name T332
Test name
Test status
Simulation time 7378632440 ps
CPU time 1628.34 seconds
Started Jul 14 08:01:32 PM PDT 24
Finished Jul 14 08:28:42 PM PDT 24
Peak memory 609920 kb
Host smart-e1b8b48f-cb84-4295-baa6-01e9ae3fa395
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_
csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1169633870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.1169633870
Directory /workspace/1.chip_sw_entropy_src_csrng/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.392042240
Short name T1307
Test name
Test status
Simulation time 2615803816 ps
CPU time 191.69 seconds
Started Jul 14 07:58:41 PM PDT 24
Finished Jul 14 08:01:53 PM PDT 24
Peak memory 608656 kb
Host smart-a8a7a15e-338d-4e2c-99aa-5f761fb934b7
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392042240
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.392042240
Directory /workspace/1.chip_sw_entropy_src_kat_test/latest

Test location /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3602950315
Short name T947
Test name
Test status
Simulation time 3149252296 ps
CPU time 487.51 seconds
Started Jul 14 08:05:11 PM PDT 24
Finished Jul 14 08:13:19 PM PDT 24
Peak memory 608652 kb
Host smart-6360cd0b-cabc-4857-bddf-8d2e80f78b04
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3602950315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.3602950315
Directory /workspace/1.chip_sw_entropy_src_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_example_concurrency.766257199
Short name T1119
Test name
Test status
Simulation time 2421284860 ps
CPU time 271.85 seconds
Started Jul 14 07:57:36 PM PDT 24
Finished Jul 14 08:02:08 PM PDT 24
Peak memory 609228 kb
Host smart-a9bf2625-6b71-4611-8e5b-80b861606731
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766257199 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_example_concurrency.766257199
Directory /workspace/1.chip_sw_example_concurrency/latest

Test location /workspace/coverage/default/1.chip_sw_example_flash.1075161354
Short name T932
Test name
Test status
Simulation time 2294497564 ps
CPU time 183.71 seconds
Started Jul 14 08:00:54 PM PDT 24
Finished Jul 14 08:03:58 PM PDT 24
Peak memory 609112 kb
Host smart-c29da2fd-272c-4170-b12f-54d0c704e825
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075161354 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_example_flash.1075161354
Directory /workspace/1.chip_sw_example_flash/latest

Test location /workspace/coverage/default/1.chip_sw_example_manufacturer.671859899
Short name T425
Test name
Test status
Simulation time 3234111360 ps
CPU time 274.14 seconds
Started Jul 14 07:56:08 PM PDT 24
Finished Jul 14 08:00:43 PM PDT 24
Peak memory 608812 kb
Host smart-26b8f091-dc25-444d-b5e2-6a74182b3793
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671859899 -assert nopostproc +UVM_TESTNAME=chip_b
ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.chip_sw_example_manufacturer.671859899
Directory /workspace/1.chip_sw_example_manufacturer/latest

Test location /workspace/coverage/default/1.chip_sw_example_rom.1412370992
Short name T96
Test name
Test status
Simulation time 2630526994 ps
CPU time 107.79 seconds
Started Jul 14 07:55:07 PM PDT 24
Finished Jul 14 07:56:56 PM PDT 24
Peak memory 609324 kb
Host smart-2be9722d-3aa5-44a0-b059-130d91a9b475
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412370992 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_example_rom.1412370992
Directory /workspace/1.chip_sw_example_rom/latest

Test location /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.962993843
Short name T1223
Test name
Test status
Simulation time 59098075272 ps
CPU time 10172.9 seconds
Started Jul 14 07:56:54 PM PDT 24
Finished Jul 14 10:46:28 PM PDT 24
Peak memory 624160 kb
Host smart-6ce95321-c7de-433d-b0f2-bd921f79b16c
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=962993843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.962993843
Directory /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest

Test location /workspace/coverage/default/1.chip_sw_flash_crash_alert.1708203678
Short name T359
Test name
Test status
Simulation time 4229834320 ps
CPU time 728.45 seconds
Started Jul 14 08:03:17 PM PDT 24
Finished Jul 14 08:15:26 PM PDT 24
Peak memory 610364 kb
Host smart-09611b5f-1b23-4329-a57c-d9489046262a
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:
new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=1708203678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.1708203678
Directory /workspace/1.chip_sw_flash_crash_alert/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_access.235784715
Short name T478
Test name
Test status
Simulation time 5392707080 ps
CPU time 1148.54 seconds
Started Jul 14 08:00:48 PM PDT 24
Finished Jul 14 08:19:58 PM PDT 24
Peak memory 609336 kb
Host smart-8d75242d-9324-48e9-9c0b-f816fe1cb2cc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235784715 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_flash_ctrl_access.235784715
Directory /workspace/1.chip_sw_flash_ctrl_access/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1759666730
Short name T1132
Test name
Test status
Simulation time 5770095617 ps
CPU time 1274.29 seconds
Started Jul 14 07:57:06 PM PDT 24
Finished Jul 14 08:18:20 PM PDT 24
Peak memory 609540 kb
Host smart-58ace2ec-8bc6-4640-9df8-3a5f49513551
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759666730 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.1759666730
Directory /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2634727392
Short name T935
Test name
Test status
Simulation time 7327474414 ps
CPU time 1200.76 seconds
Started Jul 14 08:05:48 PM PDT 24
Finished Jul 14 08:25:49 PM PDT 24
Peak memory 608700 kb
Host smart-c9b22efe-59fc-4395-a8c5-a7a80768cb07
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634727392 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2634727392
Directory /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3346540725
Short name T955
Test name
Test status
Simulation time 5660206859 ps
CPU time 1221.18 seconds
Started Jul 14 07:58:35 PM PDT 24
Finished Jul 14 08:18:57 PM PDT 24
Peak memory 608668 kb
Host smart-1ee2905a-38dd-4a49-9dcd-4df7b5447d26
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346540725 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.3346540725
Directory /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1946814382
Short name T345
Test name
Test status
Simulation time 3457864296 ps
CPU time 461.77 seconds
Started Jul 14 08:01:05 PM PDT 24
Finished Jul 14 08:08:49 PM PDT 24
Peak memory 609156 kb
Host smart-623cca2f-b4d8-45aa-832c-7ae5c955f454
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946814382 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.1946814382
Directory /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3075130177
Short name T1241
Test name
Test status
Simulation time 5380325216 ps
CPU time 1366.11 seconds
Started Jul 14 08:06:09 PM PDT 24
Finished Jul 14 08:28:56 PM PDT 24
Peak memory 609408 kb
Host smart-217859bd-4978-4675-8acd-7ec4ec0abfdf
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075130177 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.3075130177
Directory /workspace/1.chip_sw_flash_ctrl_mem_protection/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.287844705
Short name T372
Test name
Test status
Simulation time 3679486938 ps
CPU time 749.84 seconds
Started Jul 14 07:58:19 PM PDT 24
Finished Jul 14 08:10:49 PM PDT 24
Peak memory 609492 kb
Host smart-abfd3fd9-dab0-4b0f-8863-c26bfddce088
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=287844705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.287844705
Directory /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1091810712
Short name T346
Test name
Test status
Simulation time 4524187411 ps
CPU time 699.37 seconds
Started Jul 14 08:07:13 PM PDT 24
Finished Jul 14 08:18:53 PM PDT 24
Peak memory 608688 kb
Host smart-ecef4532-77ec-4f93-bf82-7531058fb2f3
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_
rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1091810712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1091810712
Directory /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2166298889
Short name T917
Test name
Test status
Simulation time 3619657200 ps
CPU time 476.52 seconds
Started Jul 14 08:04:19 PM PDT 24
Finished Jul 14 08:12:16 PM PDT 24
Peak memory 608648 kb
Host smart-38dad570-bbcd-43bb-b5d4-534c836e8855
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166298
889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.2166298889
Directory /workspace/1.chip_sw_flash_ctrl_write_clear/latest

Test location /workspace/coverage/default/1.chip_sw_flash_init.2202701366
Short name T234
Test name
Test status
Simulation time 23119837335 ps
CPU time 2572.17 seconds
Started Jul 14 07:57:02 PM PDT 24
Finished Jul 14 08:39:56 PM PDT 24
Peak memory 610752 kb
Host smart-5b729b48-89ae-4b84-ac33-7ee70c66e0bd
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202701366 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.2202701366
Directory /workspace/1.chip_sw_flash_init/latest

Test location /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2029489787
Short name T233
Test name
Test status
Simulation time 25156789439 ps
CPU time 1871.15 seconds
Started Jul 14 08:03:51 PM PDT 24
Finished Jul 14 08:35:03 PM PDT 24
Peak memory 612768 kb
Host smart-c7ffb1dd-60a6-4c90-b9f5-5215192f6f9d
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2029489787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.2029489787
Directory /workspace/1.chip_sw_flash_init_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3235964899
Short name T1254
Test name
Test status
Simulation time 3055892970 ps
CPU time 263.02 seconds
Started Jul 14 08:12:09 PM PDT 24
Finished Jul 14 08:16:32 PM PDT 24
Peak memory 609036 kb
Host smart-4c644405-7070-4467-90ed-a47dd5487f57
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket
est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3235964899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.3235964899
Directory /workspace/1.chip_sw_flash_scrambling_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_gpio_smoketest.932518178
Short name T35
Test name
Test status
Simulation time 3341247305 ps
CPU time 314.46 seconds
Started Jul 14 08:05:31 PM PDT 24
Finished Jul 14 08:10:46 PM PDT 24
Peak memory 609656 kb
Host smart-2560f0c3-52fc-431b-a9ff-07e5ae7cde79
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932518178 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_gpio_smoketest.932518178
Directory /workspace/1.chip_sw_gpio_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc.2552410338
Short name T1235
Test name
Test status
Simulation time 3089585918 ps
CPU time 208.5 seconds
Started Jul 14 08:01:08 PM PDT 24
Finished Jul 14 08:04:37 PM PDT 24
Peak memory 608684 kb
Host smart-d2469305-aa3c-497c-bd86-0e09603c8db1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552410338 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_hmac_enc.2552410338
Directory /workspace/1.chip_sw_hmac_enc/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc_idle.140290708
Short name T97
Test name
Test status
Simulation time 3024010430 ps
CPU time 283.46 seconds
Started Jul 14 07:59:11 PM PDT 24
Finished Jul 14 08:03:55 PM PDT 24
Peak memory 609220 kb
Host smart-96f1287e-9b47-4c29-b4f4-bd9254a04131
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140290708 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_hmac_enc_idle.140290708
Directory /workspace/1.chip_sw_hmac_enc_idle/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1194851934
Short name T1166
Test name
Test status
Simulation time 3057869581 ps
CPU time 234.02 seconds
Started Jul 14 08:00:31 PM PDT 24
Finished Jul 14 08:04:25 PM PDT 24
Peak memory 608672 kb
Host smart-0e678c30-8a3c-4965-9a5b-bf2114b6f6bd
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194851934 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.1194851934
Directory /workspace/1.chip_sw_hmac_enc_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.945570239
Short name T297
Test name
Test status
Simulation time 2633111226 ps
CPU time 216.37 seconds
Started Jul 14 08:05:04 PM PDT 24
Finished Jul 14 08:08:40 PM PDT 24
Peak memory 608704 kb
Host smart-30f6c0e5-d298-41c8-a1e3-fb57d5c3955c
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945570239 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.945570239
Directory /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_multistream.1529494253
Short name T886
Test name
Test status
Simulation time 7808300840 ps
CPU time 2034.85 seconds
Started Jul 14 08:00:15 PM PDT 24
Finished Jul 14 08:34:11 PM PDT 24
Peak memory 608280 kb
Host smart-d36c830a-5e59-4608-b4eb-8276ebf3f236
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529494253 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.chip_sw_hmac_multistream.1529494253
Directory /workspace/1.chip_sw_hmac_multistream/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_oneshot.1370681690
Short name T890
Test name
Test status
Simulation time 2962125400 ps
CPU time 267.22 seconds
Started Jul 14 08:01:49 PM PDT 24
Finished Jul 14 08:06:17 PM PDT 24
Peak memory 609120 kb
Host smart-8d5db116-81b9-421a-9ebb-1fd83ea8717d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370681690 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.chip_sw_hmac_oneshot.1370681690
Directory /workspace/1.chip_sw_hmac_oneshot/latest

Test location /workspace/coverage/default/1.chip_sw_hmac_smoketest.2576112307
Short name T1027
Test name
Test status
Simulation time 3381814912 ps
CPU time 494.18 seconds
Started Jul 14 08:06:18 PM PDT 24
Finished Jul 14 08:14:33 PM PDT 24
Peak memory 609120 kb
Host smart-24d18a2c-1acf-48df-9dc2-4c74aeb911b2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576112307 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_hmac_smoketest.2576112307
Directory /workspace/1.chip_sw_hmac_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.513687475
Short name T338
Test name
Test status
Simulation time 3913420908 ps
CPU time 511.27 seconds
Started Jul 14 07:58:11 PM PDT 24
Finished Jul 14 08:06:43 PM PDT 24
Peak memory 609120 kb
Host smart-d2832f57-34bf-4e66-96c1-37aa6bf6a47d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513687475 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.513687475
Directory /workspace/1.chip_sw_i2c_device_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.990540555
Short name T354
Test name
Test status
Simulation time 5202542350 ps
CPU time 800.03 seconds
Started Jul 14 07:59:37 PM PDT 24
Finished Jul 14 08:12:58 PM PDT 24
Peak memory 608700 kb
Host smart-ed2f9d1b-9ff1-4dfb-aab9-87ddec2aba1c
User root
Command /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990540555 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.990540555
Directory /workspace/1.chip_sw_i2c_host_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.4235444827
Short name T337
Test name
Test status
Simulation time 5053833440 ps
CPU time 997.05 seconds
Started Jul 14 07:57:37 PM PDT 24
Finished Jul 14 08:14:15 PM PDT 24
Peak memory 608612 kb
Host smart-c66fb49e-1e60-484e-ab9f-36e5731f1eb9
User root
Command /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235444827 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.4235444827
Directory /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest

Test location /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2065079118
Short name T339
Test name
Test status
Simulation time 5286523024 ps
CPU time 798.37 seconds
Started Jul 14 07:58:49 PM PDT 24
Finished Jul 14 08:12:08 PM PDT 24
Peak memory 608700 kb
Host smart-e78aaaf0-e16e-467e-94e1-2b7bfd7d7eed
User root
Command /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065079118 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.2065079118
Directory /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest

Test location /workspace/coverage/default/1.chip_sw_inject_scramble_seed.3209098598
Short name T200
Test name
Test status
Simulation time 65368499808 ps
CPU time 11558.6 seconds
Started Jul 14 08:00:11 PM PDT 24
Finished Jul 14 11:12:52 PM PDT 24
Peak memory 624176 kb
Host smart-f810b301-35cc-466c-b26d-6aee7f8b1691
User root
Command /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3209098598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.3209098598
Directory /workspace/1.chip_sw_inject_scramble_seed/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2433248886
Short name T220
Test name
Test status
Simulation time 11304627290 ps
CPU time 2276.34 seconds
Started Jul 14 08:00:51 PM PDT 24
Finished Jul 14 08:38:48 PM PDT 24
Peak memory 617188 kb
Host smart-4b782b95-01ee-4e83-b144-1bee39fa3936
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433
248886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.2433248886
Directory /workspace/1.chip_sw_keymgr_key_derivation/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2080572764
Short name T221
Test name
Test status
Simulation time 12208050043 ps
CPU time 2327.17 seconds
Started Jul 14 08:01:15 PM PDT 24
Finished Jul 14 08:40:03 PM PDT 24
Peak memory 617288 kb
Host smart-919cb339-aa9c-41eb-ad77-894da987d70d
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2080572764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.2080572764
Directory /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2592105219
Short name T1232
Test name
Test status
Simulation time 9730106247 ps
CPU time 1409.22 seconds
Started Jul 14 08:05:21 PM PDT 24
Finished Jul 14 08:28:51 PM PDT 24
Peak memory 616960 kb
Host smart-97b32c71-d51e-4724-a9eb-52e026cc15c8
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2592105219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en
_reduced_freq.2592105219
Directory /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1219275188
Short name T1087
Test name
Test status
Simulation time 11701073300 ps
CPU time 2350.67 seconds
Started Jul 14 08:00:08 PM PDT 24
Finished Jul 14 08:39:19 PM PDT 24
Peak memory 615968 kb
Host smart-d8112d42-bd27-4f2e-9a1a-37d04e83ba80
User root
Command /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1219275188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.1219275188
Directory /workspace/1.chip_sw_keymgr_key_derivation_prod/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1279189611
Short name T227
Test name
Test status
Simulation time 6056397004 ps
CPU time 1329.87 seconds
Started Jul 14 08:02:05 PM PDT 24
Finished Jul 14 08:24:16 PM PDT 24
Peak memory 610832 kb
Host smart-a2b7455f-e9cb-4f4a-a981-23fbd4df4397
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127918
9611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.1279189611
Directory /workspace/1.chip_sw_keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2360872004
Short name T957
Test name
Test status
Simulation time 11176814580 ps
CPU time 2492.01 seconds
Started Jul 14 08:01:56 PM PDT 24
Finished Jul 14 08:43:28 PM PDT 24
Peak memory 610476 kb
Host smart-ca1d85ed-b76b-4d24-af10-9059f29ae81a
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23608
72004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.2360872004
Directory /workspace/1.chip_sw_keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.146444593
Short name T222
Test name
Test status
Simulation time 16826258204 ps
CPU time 5595.86 seconds
Started Jul 14 08:02:22 PM PDT 24
Finished Jul 14 09:35:39 PM PDT 24
Peak memory 610272 kb
Host smart-52106004-c1ab-40e2-ba52-f86e34be76f0
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14644
4593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.146444593
Directory /workspace/1.chip_sw_keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_app_rom.2963144416
Short name T409
Test name
Test status
Simulation time 3102221464 ps
CPU time 179.71 seconds
Started Jul 14 08:01:51 PM PDT 24
Finished Jul 14 08:04:51 PM PDT 24
Peak memory 609136 kb
Host smart-0a46b572-1f3b-4a9c-ab04-d9fab6de556c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963144416 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_kmac_app_rom.2963144416
Directory /workspace/1.chip_sw_kmac_app_rom/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_entropy.2635347548
Short name T98
Test name
Test status
Simulation time 2280990358 ps
CPU time 259.81 seconds
Started Jul 14 07:58:19 PM PDT 24
Finished Jul 14 08:02:39 PM PDT 24
Peak memory 609048 kb
Host smart-d986a1b3-172f-422d-8b4e-daa1868bef20
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635347548 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_kmac_entropy.2635347548
Directory /workspace/1.chip_sw_kmac_entropy/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_idle.1301304721
Short name T435
Test name
Test status
Simulation time 2995614364 ps
CPU time 234.5 seconds
Started Jul 14 08:02:48 PM PDT 24
Finished Jul 14 08:06:42 PM PDT 24
Peak memory 609076 kb
Host smart-b3848f77-acb3-4f25-bd1b-58cf02c1c69e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301304721 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_kmac_idle.1301304721
Directory /workspace/1.chip_sw_kmac_idle/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2137354495
Short name T968
Test name
Test status
Simulation time 3177503710 ps
CPU time 312.66 seconds
Started Jul 14 08:02:01 PM PDT 24
Finished Jul 14 08:07:14 PM PDT 24
Peak memory 609200 kb
Host smart-53f7bf8c-4c9f-4a46-acb9-60318c89f170
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137354495 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.chip_sw_kmac_mode_cshake.2137354495
Directory /workspace/1.chip_sw_kmac_mode_cshake/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.3445911800
Short name T1045
Test name
Test status
Simulation time 2596375776 ps
CPU time 474.04 seconds
Started Jul 14 08:01:28 PM PDT 24
Finished Jul 14 08:09:23 PM PDT 24
Peak memory 609272 kb
Host smart-94aa47ba-cde9-4e08-ba4d-c8568442c065
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445911800 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.chip_sw_kmac_mode_kmac.3445911800
Directory /workspace/1.chip_sw_kmac_mode_kmac/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3207178550
Short name T1018
Test name
Test status
Simulation time 2992906337 ps
CPU time 290.44 seconds
Started Jul 14 08:00:43 PM PDT 24
Finished Jul 14 08:05:34 PM PDT 24
Peak memory 608672 kb
Host smart-adb218ac-93e0-44b0-8aa7-6e63c41240ec
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207178550 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.3207178550
Directory /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1159616515
Short name T1149
Test name
Test status
Simulation time 3276462972 ps
CPU time 349.55 seconds
Started Jul 14 08:05:07 PM PDT 24
Finished Jul 14 08:10:57 PM PDT 24
Peak memory 608692 kb
Host smart-137fd6d6-be56-441f-a83b-967153182386
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11596165
15 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1159616515
Directory /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_kmac_smoketest.2732801275
Short name T1130
Test name
Test status
Simulation time 3234135848 ps
CPU time 263.46 seconds
Started Jul 14 08:04:43 PM PDT 24
Finished Jul 14 08:09:07 PM PDT 24
Peak memory 609052 kb
Host smart-87f96ad7-4a0e-4e87-93ad-af87620c9d84
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732801275 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_kmac_smoketest.2732801275
Directory /workspace/1.chip_sw_kmac_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2271885874
Short name T1177
Test name
Test status
Simulation time 3049203228 ps
CPU time 279.09 seconds
Started Jul 14 07:57:32 PM PDT 24
Finished Jul 14 08:02:11 PM PDT 24
Peak memory 609004 kb
Host smart-4f907e3d-ce9f-44d0-b177-6371edccfc5b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271885874 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.2271885874
Directory /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.427170363
Short name T73
Test name
Test status
Simulation time 4329157318 ps
CPU time 469.63 seconds
Started Jul 14 08:02:50 PM PDT 24
Finished Jul 14 08:10:41 PM PDT 24
Peak memory 610264 kb
Host smart-a81cf005-4c3a-4a76-8937-8a2aeff87758
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=427170363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.427170363
Directory /workspace/1.chip_sw_lc_ctrl_program_error/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2127670253
Short name T175
Test name
Test status
Simulation time 3850266860 ps
CPU time 175.69 seconds
Started Jul 14 07:59:02 PM PDT 24
Finished Jul 14 08:01:58 PM PDT 24
Peak memory 620000 kb
Host smart-e54b601f-dade-4253-8162-307433023309
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21276702
53 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.2127670253
Directory /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3134933005
Short name T1225
Test name
Test status
Simulation time 9264292137 ps
CPU time 1145.3 seconds
Started Jul 14 07:59:21 PM PDT 24
Finished Jul 14 08:18:27 PM PDT 24
Peak memory 622584 kb
Host smart-feb7c64d-87c9-4672-aed5-45a61ef4f3d2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134933005 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.3134933005
Directory /workspace/1.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.2406855748
Short name T678
Test name
Test status
Simulation time 2258682205 ps
CPU time 120.46 seconds
Started Jul 14 07:57:00 PM PDT 24
Finished Jul 14 07:59:01 PM PDT 24
Peak memory 614380 kb
Host smart-18ff21ce-5057-4dfb-aa45-c40e4da11f41
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes
t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2406855748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.2406855748
Directory /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.879798992
Short name T63
Test name
Test status
Simulation time 2450442479 ps
CPU time 106.53 seconds
Started Jul 14 08:00:11 PM PDT 24
Finished Jul 14 08:01:58 PM PDT 24
Peak memory 616420 kb
Host smart-520d3ad5-b0a5-43ff-9ca8-d68675aaddc4
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s
im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879798992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST
_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.879798992
Directory /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2071646083
Short name T230
Test name
Test status
Simulation time 45881679120 ps
CPU time 5443.67 seconds
Started Jul 14 08:00:51 PM PDT 24
Finished Jul 14 09:31:36 PM PDT 24
Peak memory 618576 kb
Host smart-389561eb-7f9b-4c7d-811c-33623acba1e1
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071646083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip
_sw_lc_walkthrough_dev.2071646083
Directory /workspace/1.chip_sw_lc_walkthrough_dev/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.289337768
Short name T998
Test name
Test status
Simulation time 8707667236 ps
CPU time 811.4 seconds
Started Jul 14 07:58:55 PM PDT 24
Finished Jul 14 08:12:27 PM PDT 24
Peak memory 619380 kb
Host smart-3ee5dd2d-4427-4ec1-be02-15a9663c297c
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa
lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=289337768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.289337768
Directory /workspace/1.chip_sw_lc_walkthrough_prodend/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.773757919
Short name T236
Test name
Test status
Simulation time 47016254020 ps
CPU time 5874.7 seconds
Started Jul 14 07:59:31 PM PDT 24
Finished Jul 14 09:37:27 PM PDT 24
Peak memory 619688 kb
Host smart-056a76e0-8f51-48df-9067-e97ed5fc89da
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773757919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch
ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_
sw_lc_walkthrough_rma.773757919
Directory /workspace/1.chip_sw_lc_walkthrough_rma/latest

Test location /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3056250788
Short name T316
Test name
Test status
Simulation time 32856298125 ps
CPU time 2333.28 seconds
Started Jul 14 08:00:42 PM PDT 24
Finished Jul 14 08:39:36 PM PDT 24
Peak memory 618800 kb
Host smart-193ae581-88ea-4976-9341-56330065a84d
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks
_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3056250788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun
locks.3056250788
Directory /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.179269885
Short name T482
Test name
Test status
Simulation time 16804658096 ps
CPU time 4528.32 seconds
Started Jul 14 08:02:47 PM PDT 24
Finished Jul 14 09:18:16 PM PDT 24
Peak memory 609636 kb
Host smart-1da12834-8356-439a-847e-4ae4d3d95a16
User root
Command /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_
rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=179269885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.179269885
Directory /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1895275721
Short name T1077
Test name
Test status
Simulation time 18042426969 ps
CPU time 3507.77 seconds
Started Jul 14 07:59:09 PM PDT 24
Finished Jul 14 08:57:38 PM PDT 24
Peak memory 610000 kb
Host smart-d0067abf-db15-4601-a8ad-00eb306b33fd
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne
w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1895275721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1895275721
Directory /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4024606018
Short name T1062
Test name
Test status
Simulation time 24527729748 ps
CPU time 4587.94 seconds
Started Jul 14 08:04:32 PM PDT 24
Finished Jul 14 09:21:01 PM PDT 24
Peak memory 609976 kb
Host smart-0211084d-f2df-4caf-bd0e-08a7d1bf212c
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e
cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024606018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu
ced_freq.4024606018
Directory /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1912889705
Short name T239
Test name
Test status
Simulation time 3222919940 ps
CPU time 536.75 seconds
Started Jul 14 07:59:13 PM PDT 24
Finished Jul 14 08:08:11 PM PDT 24
Peak memory 609404 kb
Host smart-0bb5f1c5-428b-4f76-8937-bcb5b4fe22ad
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn
_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912889705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.1912889705
Directory /workspace/1.chip_sw_otbn_mem_scramble/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_randomness.266491322
Short name T101
Test name
Test status
Simulation time 6144237104 ps
CPU time 1000.54 seconds
Started Jul 14 08:00:37 PM PDT 24
Finished Jul 14 08:17:18 PM PDT 24
Peak memory 609884 kb
Host smart-8c54030e-25e6-4c98-b034-18944f0e8c08
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=266491322 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.266491322
Directory /workspace/1.chip_sw_otbn_randomness/latest

Test location /workspace/coverage/default/1.chip_sw_otbn_smoketest.1377722372
Short name T150
Test name
Test status
Simulation time 8540061786 ps
CPU time 1668.78 seconds
Started Jul 14 08:06:12 PM PDT 24
Finished Jul 14 08:34:02 PM PDT 24
Peak memory 609540 kb
Host smart-04fb479b-fab6-465d-855e-8f9bd14f2421
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377722372 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.chip_sw_otbn_smoketest.1377722372
Directory /workspace/1.chip_sw_otbn_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.3029412503
Short name T921
Test name
Test status
Simulation time 3193977046 ps
CPU time 339.82 seconds
Started Jul 14 07:58:18 PM PDT 24
Finished Jul 14 08:03:58 PM PDT 24
Peak memory 609600 kb
Host smart-5b789cc4-f482-4cd0-a374-9c8b67ba5c2d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029412503 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.3029412503
Directory /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3087611535
Short name T224
Test name
Test status
Simulation time 7358899100 ps
CPU time 1369.84 seconds
Started Jul 14 07:58:24 PM PDT 24
Finished Jul 14 08:21:14 PM PDT 24
Peak memory 609936 kb
Host smart-58b9b1b7-4529-405e-af07-afe8f46e1f87
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3087611535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.3087611535
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2972805837
Short name T1071
Test name
Test status
Simulation time 9851006966 ps
CPU time 1394.37 seconds
Started Jul 14 07:59:12 PM PDT 24
Finished Jul 14 08:22:27 PM PDT 24
Peak memory 609672 kb
Host smart-d1be9b13-b5a0-4275-8350-84ae30cd9589
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2972805837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.2972805837
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.99326513
Short name T1058
Test name
Test status
Simulation time 7147318348 ps
CPU time 1184.36 seconds
Started Jul 14 07:58:29 PM PDT 24
Finished Jul 14 08:18:14 PM PDT 24
Peak memory 609880 kb
Host smart-19fda881-ff4a-4817-abad-7243271a250d
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=99326513 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.99326513
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.689227051
Short name T1325
Test name
Test status
Simulation time 4171283082 ps
CPU time 788.18 seconds
Started Jul 14 07:57:00 PM PDT 24
Finished Jul 14 08:10:09 PM PDT 24
Peak memory 608668 kb
Host smart-1703298f-45f3-4fdb-982c-17353e202d26
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=689227051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.689227051
Directory /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1474500968
Short name T1138
Test name
Test status
Simulation time 2404113096 ps
CPU time 217.73 seconds
Started Jul 14 08:08:48 PM PDT 24
Finished Jul 14 08:12:26 PM PDT 24
Peak memory 609196 kb
Host smart-833c0ade-e3c7-4c0c-985d-a326f838a05a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474500968 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_otp_ctrl_smoketest.1474500968
Directory /workspace/1.chip_sw_otp_ctrl_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_pattgen_ios.3325041981
Short name T355
Test name
Test status
Simulation time 2617020196 ps
CPU time 275.15 seconds
Started Jul 14 08:00:09 PM PDT 24
Finished Jul 14 08:04:47 PM PDT 24
Peak memory 609668 kb
Host smart-c13f27da-468d-4649-ac24-d2782c7b672b
User root
Command /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325041981 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.3325041981
Directory /workspace/1.chip_sw_pattgen_ios/latest

Test location /workspace/coverage/default/1.chip_sw_plic_sw_irq.2520739064
Short name T693
Test name
Test status
Simulation time 2594775990 ps
CPU time 222.34 seconds
Started Jul 14 08:01:32 PM PDT 24
Finished Jul 14 08:05:15 PM PDT 24
Peak memory 609112 kb
Host smart-ae50b4cc-3f6c-4169-a657-9b8167121587
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520739064 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.chip_sw_plic_sw_irq.2520739064
Directory /workspace/1.chip_sw_plic_sw_irq/latest

Test location /workspace/coverage/default/1.chip_sw_power_idle_load.1195201866
Short name T986
Test name
Test status
Simulation time 4930386940 ps
CPU time 672.52 seconds
Started Jul 14 08:05:33 PM PDT 24
Finished Jul 14 08:16:46 PM PDT 24
Peak memory 608656 kb
Host smart-90365e6e-4615-4e7c-84d9-fdfb7a936865
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195201866 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.1195201866
Directory /workspace/1.chip_sw_power_idle_load/latest

Test location /workspace/coverage/default/1.chip_sw_power_sleep_load.1603185264
Short name T700
Test name
Test status
Simulation time 4959186440 ps
CPU time 450.88 seconds
Started Jul 14 08:05:45 PM PDT 24
Finished Jul 14 08:13:18 PM PDT 24
Peak memory 608740 kb
Host smart-2abcdd53-484b-4f2a-bb7f-ba78475ef786
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603185264 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.1603185264
Directory /workspace/1.chip_sw_power_sleep_load/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2364512290
Short name T1305
Test name
Test status
Simulation time 12224416383 ps
CPU time 1714.71 seconds
Started Jul 14 08:04:48 PM PDT 24
Finished Jul 14 08:33:23 PM PDT 24
Peak memory 610632 kb
Host smart-9821a713-f7f9-4663-9441-b5131e7f27b5
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364
512290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.2364512290
Directory /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.672331786
Short name T936
Test name
Test status
Simulation time 28269101168 ps
CPU time 2371.68 seconds
Started Jul 14 08:01:06 PM PDT 24
Finished Jul 14 08:40:38 PM PDT 24
Peak memory 609084 kb
Host smart-62455f80-edfe-471a-8cb0-eac4610550fc
User root
Command /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672
331786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.672331786
Directory /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3511098306
Short name T455
Test name
Test status
Simulation time 14684112808 ps
CPU time 1445.44 seconds
Started Jul 14 08:03:28 PM PDT 24
Finished Jul 14 08:27:34 PM PDT 24
Peak memory 610620 kb
Host smart-e066e052-2263-492e-97b8-1bf18318eb22
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3511098306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3511098306
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3254329122
Short name T104
Test name
Test status
Simulation time 25886793584 ps
CPU time 1402.18 seconds
Started Jul 14 08:03:22 PM PDT 24
Finished Jul 14 08:26:45 PM PDT 24
Peak memory 610256 kb
Host smart-ced54a7a-85a9-4e49-b1f9-e6b74e649be7
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3254329122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3254329122
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1330410625
Short name T1107
Test name
Test status
Simulation time 9238895916 ps
CPU time 803 seconds
Started Jul 14 07:58:56 PM PDT 24
Finished Jul 14 08:12:20 PM PDT 24
Peak memory 609088 kb
Host smart-b4337857-77e8-4234-9c31-725f1d3f93f1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330410625 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.1330410625
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3415700464
Short name T966
Test name
Test status
Simulation time 6150373510 ps
CPU time 544.58 seconds
Started Jul 14 07:57:07 PM PDT 24
Finished Jul 14 08:06:13 PM PDT 24
Peak memory 616512 kb
Host smart-fde5488d-7e22-4576-a928-102658003a63
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3415700464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3415700464
Directory /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.796178974
Short name T1295
Test name
Test status
Simulation time 9303439250 ps
CPU time 403.78 seconds
Started Jul 14 07:59:02 PM PDT 24
Finished Jul 14 08:05:46 PM PDT 24
Peak memory 609072 kb
Host smart-647362b9-9a97-42b4-82c2-395bd0c9964a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796178974 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.796178974
Directory /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2600896547
Short name T342
Test name
Test status
Simulation time 4149298024 ps
CPU time 521.09 seconds
Started Jul 14 08:03:33 PM PDT 24
Finished Jul 14 08:12:14 PM PDT 24
Peak memory 608956 kb
Host smart-446f15d0-e8d8-42c5-a318-b937af97dfe0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600896547 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.2600896547
Directory /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1302260612
Short name T945
Test name
Test status
Simulation time 4203229560 ps
CPU time 485.03 seconds
Started Jul 14 07:57:09 PM PDT 24
Finished Jul 14 08:05:15 PM PDT 24
Peak memory 615428 kb
Host smart-db3b612e-ad02-43df-b6f8-1d0d94638da7
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1302260612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.1302260612
Directory /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3417903691
Short name T1249
Test name
Test status
Simulation time 11599372433 ps
CPU time 1457.53 seconds
Started Jul 14 07:59:00 PM PDT 24
Finished Jul 14 08:23:18 PM PDT 24
Peak memory 610600 kb
Host smart-e541e78b-1d73-4c8b-9662-4e3cbf640176
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417903691 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3417903691
Directory /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3196072558
Short name T1165
Test name
Test status
Simulation time 7680086200 ps
CPU time 687.58 seconds
Started Jul 14 07:58:22 PM PDT 24
Finished Jul 14 08:09:51 PM PDT 24
Peak memory 609852 kb
Host smart-ce8b1c1c-5912-4746-8963-f86a01ded781
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196072558 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.3196072558
Directory /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.934246646
Short name T1264
Test name
Test status
Simulation time 22864430693 ps
CPU time 3674.11 seconds
Started Jul 14 08:04:33 PM PDT 24
Finished Jul 14 09:05:48 PM PDT 24
Peak memory 610372 kb
Host smart-51d3d568-cd06-4178-8ece-a36510e7d7d0
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=934246646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.934246646
Directory /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2559323524
Short name T16
Test name
Test status
Simulation time 24161677006 ps
CPU time 1676.1 seconds
Started Jul 14 08:03:43 PM PDT 24
Finished Jul 14 08:31:40 PM PDT 24
Peak memory 610236 kb
Host smart-34cc1ea1-0958-4a52-947d-406d8dc7cf16
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2559323524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2559323524
Directory /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2550599213
Short name T1060
Test name
Test status
Simulation time 33582262345 ps
CPU time 2993.1 seconds
Started Jul 14 07:59:15 PM PDT 24
Finished Jul 14 08:49:09 PM PDT 24
Peak memory 610560 kb
Host smart-d95e1b24-c972-463a-9896-e5431bdfd341
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power
_glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550599213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit
ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s
leep_power_glitch_reset.2550599213
Directory /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1643372167
Short name T390
Test name
Test status
Simulation time 5902699100 ps
CPU time 422.16 seconds
Started Jul 14 08:03:07 PM PDT 24
Finished Jul 14 08:10:10 PM PDT 24
Peak memory 610336 kb
Host smart-e981974e-1d83-42aa-a936-370c22cfb25c
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul
es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1643372167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s
leep_wake_up.1643372167
Directory /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.4195026695
Short name T691
Test name
Test status
Simulation time 2860646300 ps
CPU time 276.89 seconds
Started Jul 14 07:58:34 PM PDT 24
Finished Jul 14 08:03:11 PM PDT 24
Peak memory 609120 kb
Host smart-a3c18552-0d50-443c-b8e5-709d1144ebd0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195026695 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.4195026695
Directory /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.218209108
Short name T1210
Test name
Test status
Simulation time 5877057477 ps
CPU time 531.08 seconds
Started Jul 14 07:58:35 PM PDT 24
Finished Jul 14 08:07:26 PM PDT 24
Peak memory 615904 kb
Host smart-c6890971-81b4-455f-ba74-a6cedf1eacff
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=218209108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.218209108
Directory /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3106530874
Short name T133
Test name
Test status
Simulation time 5235146904 ps
CPU time 567.93 seconds
Started Jul 14 08:01:09 PM PDT 24
Finished Jul 14 08:10:37 PM PDT 24
Peak memory 608664 kb
Host smart-f5ea358b-7aa5-4c6a-904d-7a0f543239bd
User root
Command /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31065308
74 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3106530874
Directory /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2088110693
Short name T1065
Test name
Test status
Simulation time 6739677354 ps
CPU time 608.79 seconds
Started Jul 14 08:04:16 PM PDT 24
Finished Jul 14 08:14:25 PM PDT 24
Peak memory 610144 kb
Host smart-bae318f2-cce7-44d5-a583-49218a4bf890
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2088110693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.2088110693
Directory /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2775518944
Short name T905
Test name
Test status
Simulation time 5183841000 ps
CPU time 392.6 seconds
Started Jul 14 08:08:46 PM PDT 24
Finished Jul 14 08:15:18 PM PDT 24
Peak memory 608744 kb
Host smart-24f0a1a3-9143-4030-85ca-6db63f2de144
User root
Command /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775518944 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.2775518944
Directory /workspace/1.chip_sw_pwrmgr_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2535775706
Short name T433
Test name
Test status
Simulation time 7386362600 ps
CPU time 1125.85 seconds
Started Jul 14 07:59:42 PM PDT 24
Finished Jul 14 08:18:28 PM PDT 24
Peak memory 608880 kb
Host smart-fbe0bf3e-ac98-4c94-984d-e86179a34bab
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535775706 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.2535775706
Directory /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.534296445
Short name T1208
Test name
Test status
Simulation time 5469406360 ps
CPU time 650.9 seconds
Started Jul 14 07:58:11 PM PDT 24
Finished Jul 14 08:09:03 PM PDT 24
Peak memory 609508 kb
Host smart-3235d8c1-9be2-44ed-9edf-6d4f705a709d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534296445 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.534296445
Directory /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1698616541
Short name T984
Test name
Test status
Simulation time 6692704380 ps
CPU time 338 seconds
Started Jul 14 08:05:55 PM PDT 24
Finished Jul 14 08:11:33 PM PDT 24
Peak memory 609600 kb
Host smart-4328c028-84ba-400f-a701-2df333486b87
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698616541 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.1698616541
Directory /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2396265371
Short name T1236
Test name
Test status
Simulation time 4278460402 ps
CPU time 529.29 seconds
Started Jul 14 07:59:05 PM PDT 24
Finished Jul 14 08:07:55 PM PDT 24
Peak memory 608712 kb
Host smart-bdcc6c6e-77ce-4247-907a-aabab48f2fae
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239
6265371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.2396265371
Directory /workspace/1.chip_sw_pwrmgr_wdog_reset/latest

Test location /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.4187985276
Short name T410
Test name
Test status
Simulation time 9777693573 ps
CPU time 531.47 seconds
Started Jul 14 08:04:09 PM PDT 24
Finished Jul 14 08:13:01 PM PDT 24
Peak memory 624168 kb
Host smart-69de295e-193d-4212-ab56-222aad7303f1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187985276 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.4187985276
Directory /workspace/1.chip_sw_rom_ctrl_integrity_check/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2092774390
Short name T330
Test name
Test status
Simulation time 9962707300 ps
CPU time 1794.84 seconds
Started Jul 14 07:57:01 PM PDT 24
Finished Jul 14 08:26:56 PM PDT 24
Peak memory 610396 kb
Host smart-4e0cbeb5-452a-4912-af9f-038d6beb306c
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=2092774390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.2092774390
Directory /workspace/1.chip_sw_rstmgr_alert_info/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.4054254637
Short name T265
Test name
Test status
Simulation time 6939266290 ps
CPU time 836.27 seconds
Started Jul 14 07:59:46 PM PDT 24
Finished Jul 14 08:13:43 PM PDT 24
Peak memory 609660 kb
Host smart-140d18ec-7e51-4255-87a3-1e4b8eb47883
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054254637 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.4054254637
Directory /workspace/1.chip_sw_rstmgr_cpu_info/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3476182927
Short name T1274
Test name
Test status
Simulation time 5580459668 ps
CPU time 789.34 seconds
Started Jul 14 07:58:03 PM PDT 24
Finished Jul 14 08:11:14 PM PDT 24
Peak memory 640872 kb
Host smart-ee6cccfb-f3ae-492c-b4cc-5d08e5c6ca03
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3476182927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.3476182927
Directory /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.659622400
Short name T1291
Test name
Test status
Simulation time 2893682600 ps
CPU time 307.08 seconds
Started Jul 14 08:07:14 PM PDT 24
Finished Jul 14 08:12:22 PM PDT 24
Peak memory 609096 kb
Host smart-134cf65c-972e-46b8-9783-7566d469f088
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659622400 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.chip_sw_rstmgr_smoketest.659622400
Directory /workspace/1.chip_sw_rstmgr_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1449207173
Short name T1102
Test name
Test status
Simulation time 3691711768 ps
CPU time 385.12 seconds
Started Jul 14 07:57:54 PM PDT 24
Finished Jul 14 08:04:20 PM PDT 24
Peak memory 609436 kb
Host smart-765a29c5-b39e-487d-b908-e719dd68e62b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449207173 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_rstmgr_sw_req.1449207173
Directory /workspace/1.chip_sw_rstmgr_sw_req/latest

Test location /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.48641291
Short name T209
Test name
Test status
Simulation time 2501617760 ps
CPU time 223.06 seconds
Started Jul 14 07:57:12 PM PDT 24
Finished Jul 14 08:00:55 PM PDT 24
Peak memory 609120 kb
Host smart-189f3154-8999-49b0-b957-b371ff4637e8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48641291 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.48641291
Directory /workspace/1.chip_sw_rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.615868097
Short name T182
Test name
Test status
Simulation time 2867122696 ps
CPU time 300.76 seconds
Started Jul 14 08:03:01 PM PDT 24
Finished Jul 14 08:08:03 PM PDT 24
Peak memory 608208 kb
Host smart-759718fe-8ad8-4e61-9ba3-7e3f287804d8
User root
Command /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=615868097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.615868097
Directory /workspace/1.chip_sw_rv_core_ibex_address_translation/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.776593615
Short name T180
Test name
Test status
Simulation time 2093296778 ps
CPU time 213.23 seconds
Started Jul 14 08:03:55 PM PDT 24
Finished Jul 14 08:07:29 PM PDT 24
Peak memory 608612 kb
Host smart-05aee467-32b5-49ed-9497-f8ad978bd3ee
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776593615 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.776593615
Directory /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2435120664
Short name T99
Test name
Test status
Simulation time 4542283374 ps
CPU time 797.45 seconds
Started Jul 14 07:57:48 PM PDT 24
Finished Jul 14 08:11:06 PM PDT 24
Peak memory 608668 kb
Host smart-a680cf70-3c55-49d9-957a-b8a8a053d34a
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24351
20664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.2435120664
Directory /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest

Test location /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.895046365
Short name T1091
Test name
Test status
Simulation time 5205517132 ps
CPU time 1149.71 seconds
Started Jul 14 08:01:31 PM PDT 24
Finished Jul 14 08:20:41 PM PDT 24
Peak memory 608652 kb
Host smart-cab47b6a-2eef-451d-a0f0-19a9a54edc6b
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=895046365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.895046365
Directory /workspace/1.chip_sw_rv_core_ibex_rnd/latest

Test location /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2371541969
Short name T244
Test name
Test status
Simulation time 4647498531 ps
CPU time 526.83 seconds
Started Jul 14 08:03:40 PM PDT 24
Finished Jul 14 08:12:28 PM PDT 24
Peak memory 623496 kb
Host smart-f9d250ff-514c-4123-a91c-9cd191d2022c
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371541969 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.2371541969
Directory /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.773213290
Short name T1163
Test name
Test status
Simulation time 5679664698 ps
CPU time 644.01 seconds
Started Jul 14 08:05:47 PM PDT 24
Finished Jul 14 08:16:32 PM PDT 24
Peak memory 619520 kb
Host smart-dd43751c-ddb1-4bcf-acb5-3406a4a935ee
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773213290 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.773213290
Directory /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3663777144
Short name T1256
Test name
Test status
Simulation time 4706515096 ps
CPU time 443.5 seconds
Started Jul 14 08:03:16 PM PDT 24
Finished Jul 14 08:10:40 PM PDT 24
Peak memory 618452 kb
Host smart-77330c75-0e99-468f-89ba-bd92d5377d27
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366377
7144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3663777144
Directory /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.403662443
Short name T336
Test name
Test status
Simulation time 2177756318 ps
CPU time 268.94 seconds
Started Jul 14 08:05:53 PM PDT 24
Finished Jul 14 08:10:22 PM PDT 24
Peak memory 607968 kb
Host smart-24f47811-8694-41be-8da6-12c6947b5659
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403662443 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.chip_sw_rv_plic_smoketest.403662443
Directory /workspace/1.chip_sw_rv_plic_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_rv_timer_irq.139575712
Short name T458
Test name
Test status
Simulation time 2897843910 ps
CPU time 210.69 seconds
Started Jul 14 07:58:16 PM PDT 24
Finished Jul 14 08:01:48 PM PDT 24
Peak memory 609288 kb
Host smart-ea7f37a7-7792-4204-8c0e-c13281d38321
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139575712 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_rv_timer_irq.139575712
Directory /workspace/1.chip_sw_rv_timer_irq/latest

Test location /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.125877029
Short name T254
Test name
Test status
Simulation time 2734127748 ps
CPU time 182 seconds
Started Jul 14 08:06:18 PM PDT 24
Finished Jul 14 08:09:20 PM PDT 24
Peak memory 608632 kb
Host smart-058a9b1f-d909-4d2b-9f65-a0f5b6375fd5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125877029 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.chip_sw_rv_timer_smoketest.125877029
Directory /workspace/1.chip_sw_rv_timer_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3731748929
Short name T140
Test name
Test status
Simulation time 2949564819 ps
CPU time 241.03 seconds
Started Jul 14 08:01:27 PM PDT 24
Finished Jul 14 08:05:29 PM PDT 24
Peak memory 609992 kb
Host smart-a8acc93e-7140-471f-b4aa-2c95bbfec146
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731748
929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.3731748929
Directory /workspace/1.chip_sw_sensor_ctrl_status/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.3420824716
Short name T109
Test name
Test status
Simulation time 10399252136 ps
CPU time 1336.6 seconds
Started Jul 14 07:57:35 PM PDT 24
Finished Jul 14 08:19:52 PM PDT 24
Peak memory 610092 kb
Host smart-d214871c-0d56-421b-94bb-667b432b175c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420824716 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.3420824716
Directory /workspace/1.chip_sw_sleep_pwm_pulses/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.477138326
Short name T456
Test name
Test status
Simulation time 7476440744 ps
CPU time 823.14 seconds
Started Jul 14 08:03:10 PM PDT 24
Finished Jul 14 08:16:54 PM PDT 24
Peak memory 609880 kb
Host smart-322c6d64-14df-4998-ab11-bdb127cbb11d
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477138326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sle
ep_sram_ret_contents_no_scramble.477138326
Directory /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3772311675
Short name T1188
Test name
Test status
Simulation time 8759683340 ps
CPU time 714.78 seconds
Started Jul 14 08:06:59 PM PDT 24
Finished Jul 14 08:18:54 PM PDT 24
Peak memory 609848 kb
Host smart-fbdcba0e-4213-4d20-95a7-89bd14d7de78
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772311675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep
_sram_ret_contents_scramble.3772311675
Directory /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3329349467
Short name T196
Test name
Test status
Simulation time 5268374951 ps
CPU time 550.55 seconds
Started Jul 14 07:58:48 PM PDT 24
Finished Jul 14 08:07:59 PM PDT 24
Peak memory 624292 kb
Host smart-f38026ab-7c39-4422-b032-2299e830b680
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329349467 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.3329349467
Directory /workspace/1.chip_sw_spi_device_pass_through/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1384672872
Short name T198
Test name
Test status
Simulation time 4805371699 ps
CPU time 652.66 seconds
Started Jul 14 07:58:14 PM PDT 24
Finished Jul 14 08:09:07 PM PDT 24
Peak memory 624256 kb
Host smart-819282fd-248e-4164-8cb7-bb550d5c08d1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384672872 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.1384672872
Directory /workspace/1.chip_sw_spi_device_pass_through_collision/latest

Test location /workspace/coverage/default/1.chip_sw_spi_device_tpm.443868097
Short name T50
Test name
Test status
Simulation time 3508258413 ps
CPU time 489.94 seconds
Started Jul 14 08:01:23 PM PDT 24
Finished Jul 14 08:09:33 PM PDT 24
Peak memory 617904 kb
Host smart-5f83d92b-8805-48f4-9881-39462fec56b8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443868097 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.443868097
Directory /workspace/1.chip_sw_spi_device_tpm/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.236585758
Short name T305
Test name
Test status
Simulation time 8761157385 ps
CPU time 788.86 seconds
Started Jul 14 08:01:02 PM PDT 24
Finished Jul 14 08:14:12 PM PDT 24
Peak memory 608776 kb
Host smart-a07a0052-a63a-4703-8180-5ca51f3228ef
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236585758 -assert nopostproc +UV
M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.236585758
Directory /workspace/1.chip_sw_sram_ctrl_execution_main/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3292005424
Short name T179
Test name
Test status
Simulation time 4097130240 ps
CPU time 622.25 seconds
Started Jul 14 08:02:39 PM PDT 24
Finished Jul 14 08:13:03 PM PDT 24
Peak memory 609992 kb
Host smart-ee1371da-9c82-414a-875f-24ac57b0459d
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292005424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr
l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw
_sram_ctrl_scrambled_access.3292005424
Directory /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1606133986
Short name T648
Test name
Test status
Simulation time 4335068127 ps
CPU time 569.85 seconds
Started Jul 14 08:02:56 PM PDT 24
Finished Jul 14 08:12:26 PM PDT 24
Peak memory 610284 kb
Host smart-25f58504-e35d-4e0e-94bf-3849e88d82a0
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s
w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606133986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1606133986
Directory /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3191174104
Short name T1153
Test name
Test status
Simulation time 5152102215 ps
CPU time 609.58 seconds
Started Jul 14 08:04:55 PM PDT 24
Finished Jul 14 08:15:05 PM PDT 24
Peak memory 610348 kb
Host smart-5533e737-8fe4-4309-9e71-8b9c77cdfbc8
User root
Command /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk
_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191174104 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3191174104
Directory /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.262934316
Short name T1068
Test name
Test status
Simulation time 3183577864 ps
CPU time 261.5 seconds
Started Jul 14 08:06:26 PM PDT 24
Finished Jul 14 08:10:49 PM PDT 24
Peak memory 609260 kb
Host smart-0a52bbfa-58d1-46b7-8cbd-13210850f97e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262934316 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.chip_sw_sram_ctrl_smoketest.262934316
Directory /workspace/1.chip_sw_sram_ctrl_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1583516513
Short name T1157
Test name
Test status
Simulation time 20876888581 ps
CPU time 3333.39 seconds
Started Jul 14 08:00:41 PM PDT 24
Finished Jul 14 08:56:15 PM PDT 24
Peak memory 610032 kb
Host smart-e12c7d07-4df1-4bb1-b574-eee3d52f01fb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583516513 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.1583516513
Directory /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1838578435
Short name T1262
Test name
Test status
Simulation time 4580603627 ps
CPU time 602.36 seconds
Started Jul 14 07:59:41 PM PDT 24
Finished Jul 14 08:09:46 PM PDT 24
Peak memory 612732 kb
Host smart-efe3fc2a-7f42-49f7-b421-a33877894470
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838578435 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.1838578435
Directory /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.804298639
Short name T203
Test name
Test status
Simulation time 3059205479 ps
CPU time 321.77 seconds
Started Jul 14 07:58:33 PM PDT 24
Finished Jul 14 08:03:56 PM PDT 24
Peak memory 612764 kb
Host smart-96cac329-2be1-4f5b-86ce-ae5b63aa6f99
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804298639 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.804298639
Directory /workspace/1.chip_sw_sysrst_ctrl_inputs/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.290429732
Short name T207
Test name
Test status
Simulation time 3877232300 ps
CPU time 448.65 seconds
Started Jul 14 07:57:00 PM PDT 24
Finished Jul 14 08:04:30 PM PDT 24
Peak memory 608696 kb
Host smart-4cca4da5-c500-469f-88d4-8ddf048799e0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290429732 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.290429732
Directory /workspace/1.chip_sw_sysrst_ctrl_outputs/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2695183258
Short name T33
Test name
Test status
Simulation time 22824033352 ps
CPU time 1870.07 seconds
Started Jul 14 07:58:01 PM PDT 24
Finished Jul 14 08:29:12 PM PDT 24
Peak memory 614048 kb
Host smart-355f4788-8a08-458f-a236-a2a5c5d68146
User root
Command /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26951832
58 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.2695183258
Directory /workspace/1.chip_sw_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2554756858
Short name T48
Test name
Test status
Simulation time 6373539884 ps
CPU time 473.33 seconds
Started Jul 14 07:59:04 PM PDT 24
Finished Jul 14 08:06:58 PM PDT 24
Peak memory 610036 kb
Host smart-624164b7-4530-4035-8d1d-1cd9d7e6ec8a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554756858 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2554756858
Directory /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1811534253
Short name T444
Test name
Test status
Simulation time 4031000140 ps
CPU time 747.5 seconds
Started Jul 14 07:59:06 PM PDT 24
Finished Jul 14 08:11:34 PM PDT 24
Peak memory 618296 kb
Host smart-65a11926-e9d1-408f-809e-3b3464967742
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1811534253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.1811534253
Directory /workspace/1.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/1.chip_sw_uart_smoketest.1150047093
Short name T1265
Test name
Test status
Simulation time 3561645576 ps
CPU time 323.79 seconds
Started Jul 14 08:09:25 PM PDT 24
Finished Jul 14 08:14:49 PM PDT 24
Peak memory 615864 kb
Host smart-ff6a304e-891f-4152-b0d9-4ae7b857431b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150047093 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.chip_sw_uart_smoketest.1150047093
Directory /workspace/1.chip_sw_uart_smoketest/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx.2009155898
Short name T333
Test name
Test status
Simulation time 4495378704 ps
CPU time 619.58 seconds
Started Jul 14 07:57:14 PM PDT 24
Finished Jul 14 08:07:34 PM PDT 24
Peak memory 622200 kb
Host smart-e855765f-b72d-41b1-b6a0-275071dcf968
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009155898 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.2009155898
Directory /workspace/1.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3993637581
Short name T1013
Test name
Test status
Simulation time 7758384812 ps
CPU time 1702.52 seconds
Started Jul 14 07:58:43 PM PDT 24
Finished Jul 14 08:27:07 PM PDT 24
Peak memory 624100 kb
Host smart-f9907cd1-d481-4dfa-a3cb-631b1000d1c6
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993637581 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx
_alt_clk_freq.3993637581
Directory /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.4180822947
Short name T1128
Test name
Test status
Simulation time 77721156218 ps
CPU time 13127.4 seconds
Started Jul 14 07:57:57 PM PDT 24
Finished Jul 14 11:36:46 PM PDT 24
Peak memory 634500 kb
Host smart-721ab79f-21dc-4806-9c65-441bc4f28c90
User root
Command /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4180822947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.4180822947
Directory /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1956631505
Short name T1215
Test name
Test status
Simulation time 4782689248 ps
CPU time 714.46 seconds
Started Jul 14 07:59:45 PM PDT 24
Finished Jul 14 08:11:40 PM PDT 24
Peak memory 623460 kb
Host smart-fcca0a8f-e787-4526-a8b3-0dc630a87273
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956631505 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.1956631505
Directory /workspace/1.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3487836869
Short name T1059
Test name
Test status
Simulation time 3923590140 ps
CPU time 704 seconds
Started Jul 14 07:58:42 PM PDT 24
Finished Jul 14 08:10:27 PM PDT 24
Peak memory 623208 kb
Host smart-c283dea1-78db-4707-9b85-affd066d37b0
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487836869 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.3487836869
Directory /workspace/1.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1453316239
Short name T900
Test name
Test status
Simulation time 4609443328 ps
CPU time 696.6 seconds
Started Jul 14 07:59:05 PM PDT 24
Finished Jul 14 08:10:43 PM PDT 24
Peak memory 622152 kb
Host smart-f23dc488-130f-4428-b09f-86fb61b5e189
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453316239 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.1453316239
Directory /workspace/1.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/1.chip_tap_straps_prod.160928055
Short name T62
Test name
Test status
Simulation time 2624331683 ps
CPU time 126.4 seconds
Started Jul 14 08:01:53 PM PDT 24
Finished Jul 14 08:04:00 PM PDT 24
Peak memory 620256 kb
Host smart-16342e01-14e3-4fe6-8a6b-2f09748ff6c4
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=160928055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.160928055
Directory /workspace/1.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/1.chip_tap_straps_rma.141491482
Short name T76
Test name
Test status
Simulation time 7068609350 ps
CPU time 885.69 seconds
Started Jul 14 08:03:33 PM PDT 24
Finished Jul 14 08:18:19 PM PDT 24
Peak memory 620316 kb
Host smart-820e9a6a-9a9f-46a6-8094-841b33673069
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141491482 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.141491482
Directory /workspace/1.chip_tap_straps_rma/latest

Test location /workspace/coverage/default/1.chip_tap_straps_testunlock0.3987856878
Short name T967
Test name
Test status
Simulation time 2443135319 ps
CPU time 152.69 seconds
Started Jul 14 08:02:21 PM PDT 24
Finished Jul 14 08:04:54 PM PDT 24
Peak memory 619836 kb
Host smart-bb2c9841-f52b-4b51-ac35-c1cd5994c74d
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te
st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987856878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.3987856878
Directory /workspace/1.chip_tap_straps_testunlock0/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_dev.1641031116
Short name T940
Test name
Test status
Simulation time 15268369474 ps
CPU time 3415.8 seconds
Started Jul 14 08:10:00 PM PDT 24
Finished Jul 14 09:06:57 PM PDT 24
Peak memory 610500 kb
Host smart-5d1c90cb-19d4-4951-89c4-07b5bf275ad7
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641031116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rom_e2e_asm_init_dev.1641031116
Directory /workspace/1.rom_e2e_asm_init_dev/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_prod.900705889
Short name T379
Test name
Test status
Simulation time 15386210989 ps
CPU time 3164.48 seconds
Started Jul 14 08:10:15 PM PDT 24
Finished Jul 14 09:03:01 PM PDT 24
Peak memory 609368 kb
Host smart-2f610c43-608e-449b-97c5-cdd0c7031d40
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900705889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rom_e2e_asm_init_prod.900705889
Directory /workspace/1.rom_e2e_asm_init_prod/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.39612273
Short name T1083
Test name
Test status
Simulation time 15081369760 ps
CPU time 3385.56 seconds
Started Jul 14 08:09:27 PM PDT 24
Finished Jul 14 09:05:54 PM PDT 24
Peak memory 609444 kb
Host smart-acc04d95-323a-4760-8b4b-56e53d43b7d2
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39612273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.rom_e2e_asm_init_prod_end.39612273
Directory /workspace/1.rom_e2e_asm_init_prod_end/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_rma.965201322
Short name T884
Test name
Test status
Simulation time 14197732500 ps
CPU time 4203.73 seconds
Started Jul 14 08:08:33 PM PDT 24
Finished Jul 14 09:18:37 PM PDT 24
Peak memory 610856 kb
Host smart-3c997031-df5f-4b12-af29-38affc892a7f
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965201322 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rom_e2e_asm_init_rma.965201322
Directory /workspace/1.rom_e2e_asm_init_rma/latest

Test location /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2985834331
Short name T1228
Test name
Test status
Simulation time 11444802330 ps
CPU time 2543.8 seconds
Started Jul 14 08:13:47 PM PDT 24
Finished Jul 14 08:56:11 PM PDT 24
Peak memory 610044 kb
Host smart-3d78771b-54ab-4778-b32d-7525d0565b1f
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p
rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985834331 -assert nopostproc +UVM_TESTNAME=chip_base_te
st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.rom_e2e_asm_init_test_unlocked0.2985834331
Directory /workspace/1.rom_e2e_asm_init_test_unlocked0/latest

Test location /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2407294630
Short name T418
Test name
Test status
Simulation time 15293082024 ps
CPU time 3695.39 seconds
Started Jul 14 08:10:10 PM PDT 24
Finished Jul 14 09:11:46 PM PDT 24
Peak memory 609812 kb
Host smart-cf08c1ca-3c1d-45df-9c6a-a50c52d40636
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid
_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407294630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip
_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in
it_rom_ext_invalid_meas.2407294630
Directory /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1618816408
Short name T1002
Test name
Test status
Simulation time 15116952440 ps
CPU time 3780.59 seconds
Started Jul 14 08:09:47 PM PDT 24
Finished Jul 14 09:12:49 PM PDT 24
Peak memory 609896 kb
Host smart-f89177f9-9b4c-4692-bf47-b5a64094ef07
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:
new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618816408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.1618816408
Directory /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.4267362356
Short name T1073
Test name
Test status
Simulation time 14518029212 ps
CPU time 3472.94 seconds
Started Jul 14 08:08:17 PM PDT 24
Finished Jul 14 09:06:13 PM PDT 24
Peak memory 609760 kb
Host smart-8e973e5c-075a-433c-bf24-bebefa4de718
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas
:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267362356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext
_no_meas.4267362356
Directory /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.224611372
Short name T1024
Test name
Test status
Simulation time 15306218572 ps
CPU time 3675.27 seconds
Started Jul 14 08:09:12 PM PDT 24
Finished Jul 14 09:10:28 PM PDT 24
Peak memory 610684 kb
Host smart-5c81bb0f-f16a-428f-b3dd-eaea179f7dd2
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne
w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224611372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shut
down_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_s
hutdown_exception_c.224611372
Directory /workspace/1.rom_e2e_shutdown_exception_c/latest

Test location /workspace/coverage/default/1.rom_e2e_shutdown_output.910368185
Short name T1156
Test name
Test status
Simulation time 22738127130 ps
CPU time 3315.76 seconds
Started Jul 14 08:09:18 PM PDT 24
Finished Jul 14 09:04:35 PM PDT 24
Peak memory 611036 kb
Host smart-84080edc-b1a1-400e-b71b-daedbc934761
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f
lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910368185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip
_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rom_e2e_shutdown_output.910368185
Directory /workspace/1.rom_e2e_shutdown_output/latest

Test location /workspace/coverage/default/1.rom_e2e_smoke.2716077324
Short name T949
Test name
Test status
Simulation time 14338106980 ps
CPU time 3908.72 seconds
Started Jul 14 08:10:05 PM PDT 24
Finished Jul 14 09:15:14 PM PDT 24
Peak memory 609732 kb
Host smart-a4c180ec-a1a6-4486-8de5-eacf04d58366
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img
_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to
p/hw/dv/tools/sim.tcl +ntb_random_seed=2716077324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.2716077324
Directory /workspace/1.rom_e2e_smoke/latest

Test location /workspace/coverage/default/1.rom_e2e_static_critical.345455531
Short name T408
Test name
Test status
Simulation time 17449268660 ps
CPU time 4737.47 seconds
Started Jul 14 08:08:40 PM PDT 24
Finished Jul 14 09:27:39 PM PDT 24
Peak memory 609768 kb
Host smart-15dfd2a8-9a49-4c76-b526-370cce5f36e5
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul
es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345455531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.345455531
Directory /workspace/1.rom_e2e_static_critical/latest

Test location /workspace/coverage/default/1.rom_keymgr_functest.1505683194
Short name T1031
Test name
Test status
Simulation time 4026327368 ps
CPU time 630.8 seconds
Started Jul 14 08:05:19 PM PDT 24
Finished Jul 14 08:15:50 PM PDT 24
Peak memory 609328 kb
Host smart-0956f931-aea7-473b-b35a-bb3ab9b519b9
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505683194 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.1505683194
Directory /workspace/1.rom_keymgr_functest/latest

Test location /workspace/coverage/default/1.rom_raw_unlock.2544000507
Short name T708
Test name
Test status
Simulation time 6273570278 ps
CPU time 303 seconds
Started Jul 14 08:09:36 PM PDT 24
Finished Jul 14 08:14:40 PM PDT 24
Peak memory 618692 kb
Host smart-9396bfaf-c5bd-4102-b16a-10206e8350b8
User root
Command /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE
xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2544000507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.2544000507
Directory /workspace/1.rom_raw_unlock/latest

Test location /workspace/coverage/default/1.rom_volatile_raw_unlock.1069607842
Short name T1300
Test name
Test status
Simulation time 2812039972 ps
CPU time 105.92 seconds
Started Jul 14 08:05:05 PM PDT 24
Finished Jul 14 08:06:51 PM PDT 24
Peak memory 617116 kb
Host smart-3238b7d7-f960-46ae-97e3-c940e41d4e37
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1
+sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069607842 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.1069607842
Directory /workspace/1.rom_volatile_raw_unlock/latest

Test location /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1386583003
Short name T756
Test name
Test status
Simulation time 3486629240 ps
CPU time 348.37 seconds
Started Jul 14 08:18:32 PM PDT 24
Finished Jul 14 08:24:21 PM PDT 24
Peak memory 648248 kb
Host smart-d384bb9f-4a49-4e11-84cd-36ef7f9c5db8
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386583003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1386583003
Directory /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.544681798
Short name T1053
Test name
Test status
Simulation time 13686498720 ps
CPU time 2845.15 seconds
Started Jul 14 08:18:30 PM PDT 24
Finished Jul 14 09:05:56 PM PDT 24
Peak memory 618512 kb
Host smart-4d227e5a-ca08-4b5f-a643-7bbb491a3b46
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=544681798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.544681798
Directory /workspace/10.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2394244367
Short name T1298
Test name
Test status
Simulation time 7632292735 ps
CPU time 713.45 seconds
Started Jul 14 08:21:15 PM PDT 24
Finished Jul 14 08:33:09 PM PDT 24
Peak memory 620696 kb
Host smart-27c22b46-1686-417b-b6e0-a308e2939b1e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394244367 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.2394244367
Directory /workspace/11.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.461880220
Short name T1281
Test name
Test status
Simulation time 8254239488 ps
CPU time 1441.99 seconds
Started Jul 14 08:18:26 PM PDT 24
Finished Jul 14 08:42:29 PM PDT 24
Peak memory 618280 kb
Host smart-166d02a6-1b5e-452b-b2cd-23e2dd2d4485
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=461880220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.461880220
Directory /workspace/11.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.199135732
Short name T796
Test name
Test status
Simulation time 3704804700 ps
CPU time 470.33 seconds
Started Jul 14 08:20:17 PM PDT 24
Finished Jul 14 08:28:08 PM PDT 24
Peak memory 648240 kb
Host smart-bbdaf638-3ae5-4384-8432-13c204fade9d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199135732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_s
w_alert_handler_lpg_sleep_mode_alerts.199135732
Directory /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2079636989
Short name T895
Test name
Test status
Simulation time 7201017634 ps
CPU time 504.8 seconds
Started Jul 14 08:18:21 PM PDT 24
Finished Jul 14 08:26:47 PM PDT 24
Peak memory 620700 kb
Host smart-cb73f5ee-77a8-4ff4-99cd-a8fcc51a4445
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079636989 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.2079636989
Directory /workspace/12.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1217947205
Short name T1104
Test name
Test status
Simulation time 8055585332 ps
CPU time 1417.78 seconds
Started Jul 14 08:18:39 PM PDT 24
Finished Jul 14 08:42:17 PM PDT 24
Peak memory 618248 kb
Host smart-b962e44c-33f5-4280-b525-f5c151725dc3
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1217947205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.1217947205
Directory /workspace/12.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.56669996
Short name T1114
Test name
Test status
Simulation time 12600342343 ps
CPU time 918.72 seconds
Started Jul 14 08:21:20 PM PDT 24
Finished Jul 14 08:36:40 PM PDT 24
Peak memory 622876 kb
Host smart-6ced7055-646c-40a7-933f-2e8709af0c2d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56669996 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.56669996
Directory /workspace/13.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3999354365
Short name T146
Test name
Test status
Simulation time 13051731992 ps
CPU time 2257.14 seconds
Started Jul 14 08:18:13 PM PDT 24
Finished Jul 14 08:55:51 PM PDT 24
Peak memory 618316 kb
Host smart-55a0c5e6-1ea2-404b-a90c-4020be6796dc
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3999354365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.3999354365
Directory /workspace/13.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3649900617
Short name T1101
Test name
Test status
Simulation time 5891368557 ps
CPU time 489.09 seconds
Started Jul 14 08:18:28 PM PDT 24
Finished Jul 14 08:26:38 PM PDT 24
Peak memory 620708 kb
Host smart-18e120e8-dd48-45c3-a38f-9a862d8bd53f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649900617 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.3649900617
Directory /workspace/14.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2047772583
Short name T739
Test name
Test status
Simulation time 3729581636 ps
CPU time 369.93 seconds
Started Jul 14 08:20:25 PM PDT 24
Finished Jul 14 08:26:35 PM PDT 24
Peak memory 648100 kb
Host smart-e066ffb4-3847-4bbc-bf7e-397ca8b59321
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047772583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2047772583
Directory /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3049196208
Short name T304
Test name
Test status
Simulation time 4389969000 ps
CPU time 362.8 seconds
Started Jul 14 08:20:16 PM PDT 24
Finished Jul 14 08:26:19 PM PDT 24
Peak memory 648456 kb
Host smart-d1c86b2b-2e91-447b-852a-80e8aa488727
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049196208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3049196208
Directory /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3061265583
Short name T446
Test name
Test status
Simulation time 4218604596 ps
CPU time 755.18 seconds
Started Jul 14 08:21:11 PM PDT 24
Finished Jul 14 08:33:47 PM PDT 24
Peak memory 618220 kb
Host smart-4791bbb0-bf92-4eb0-a577-072dbd882bdb
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3061265583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.3061265583
Directory /workspace/16.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1973193588
Short name T787
Test name
Test status
Simulation time 3579329592 ps
CPU time 563.62 seconds
Started Jul 14 08:20:14 PM PDT 24
Finished Jul 14 08:29:38 PM PDT 24
Peak memory 648012 kb
Host smart-274be591-e1b2-41f9-b668-e8deb7d2e2f3
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973193588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1973193588
Directory /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/17.chip_sw_all_escalation_resets.2906522398
Short name T1316
Test name
Test status
Simulation time 4756020862 ps
CPU time 620.8 seconds
Started Jul 14 08:21:56 PM PDT 24
Finished Jul 14 08:32:17 PM PDT 24
Peak memory 649736 kb
Host smart-6ab5f6c5-42d1-46ec-80a3-ac7b197a1c64
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2906522398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.2906522398
Directory /workspace/17.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1858417540
Short name T461
Test name
Test status
Simulation time 4689488800 ps
CPU time 611.9 seconds
Started Jul 14 08:18:45 PM PDT 24
Finished Jul 14 08:28:57 PM PDT 24
Peak memory 618492 kb
Host smart-6f1a99c5-14c3-4a17-81ae-ce9e542c180d
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1858417540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.1858417540
Directory /workspace/17.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2489570868
Short name T1022
Test name
Test status
Simulation time 12940651086 ps
CPU time 2232.77 seconds
Started Jul 14 08:20:22 PM PDT 24
Finished Jul 14 08:57:36 PM PDT 24
Peak memory 618260 kb
Host smart-1a6c3e54-a04a-40a9-bd52-09882d76aef4
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2489570868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.2489570868
Directory /workspace/18.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2064457301
Short name T964
Test name
Test status
Simulation time 13841584630 ps
CPU time 2585.24 seconds
Started Jul 14 08:19:36 PM PDT 24
Finished Jul 14 09:02:42 PM PDT 24
Peak memory 618516 kb
Host smart-5aa33ed2-8000-4313-b61e-cad95277fe2e
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2064457301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.2064457301
Directory /workspace/19.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/2.chip_jtag_mem_access.4273901599
Short name T199
Test name
Test status
Simulation time 13444614220 ps
CPU time 1621.34 seconds
Started Jul 14 08:05:13 PM PDT 24
Finished Jul 14 08:32:15 PM PDT 24
Peak memory 607300 kb
Host smart-8b39b864-1ef0-4991-b1c0-2217ae2fda76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273901599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_
mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.4
273901599
Directory /workspace/2.chip_jtag_mem_access/latest

Test location /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3185429917
Short name T412
Test name
Test status
Simulation time 3581589800 ps
CPU time 330.62 seconds
Started Jul 14 08:13:53 PM PDT 24
Finished Jul 14 08:19:24 PM PDT 24
Peak memory 618868 kb
Host smart-471a2e50-5b53-4cb4-90fc-4ac375d163c2
User root
Command /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3
185429917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.3185429917
Directory /workspace/2.chip_rv_dm_ndm_reset_req/latest

Test location /workspace/coverage/default/2.chip_sival_flash_info_access.1423040996
Short name T353
Test name
Test status
Simulation time 3645584980 ps
CPU time 285.32 seconds
Started Jul 14 08:07:32 PM PDT 24
Finished Jul 14 08:12:18 PM PDT 24
Peak memory 608656 kb
Host smart-872f63a4-359f-4301-be29-d1286dadb0d2
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=1423040996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.1423040996
Directory /workspace/2.chip_sival_flash_info_access/latest

Test location /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.578331066
Short name T1299
Test name
Test status
Simulation time 18648259876 ps
CPU time 512.64 seconds
Started Jul 14 08:09:32 PM PDT 24
Finished Jul 14 08:18:06 PM PDT 24
Peak memory 618520 kb
Host smart-b749ebdb-4929-4a4d-9337-3afe524c75c3
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=578331066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.578331066
Directory /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_aes_enc.1732855270
Short name T962
Test name
Test status
Simulation time 2884308880 ps
CPU time 295.4 seconds
Started Jul 14 08:16:59 PM PDT 24
Finished Jul 14 08:21:55 PM PDT 24
Peak memory 609432 kb
Host smart-d0b91fcd-bd2f-458b-acdb-1cabba9fb3ea
User root
Command /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732855270 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.1732855270
Directory /workspace/2.chip_sw_aes_enc/latest

Test location /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.28497586
Short name T440
Test name
Test status
Simulation time 3246378985 ps
CPU time 310.75 seconds
Started Jul 14 08:10:13 PM PDT 24
Finished Jul 14 08:15:24 PM PDT 24
Peak memory 608680 kb
Host smart-d34dcf32-f08e-4f1e-a052-fcf746663023
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849
7586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.28497586
Directory /workspace/2.chip_sw_aes_enc_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1376923082
Short name T116
Test name
Test status
Simulation time 2470816944 ps
CPU time 242.92 seconds
Started Jul 14 08:13:43 PM PDT 24
Finished Jul 14 08:17:47 PM PDT 24
Peak memory 608692 kb
Host smart-8ae271d1-3986-452a-8b76-89f64abbc93e
User root
Command /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1376923082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.1376923082
Directory /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_aes_entropy.2428109418
Short name T1252
Test name
Test status
Simulation time 3514361080 ps
CPU time 350.1 seconds
Started Jul 14 08:12:58 PM PDT 24
Finished Jul 14 08:18:49 PM PDT 24
Peak memory 608684 kb
Host smart-8a62f663-dc7c-4c25-b995-0c2924015e7b
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428109418 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.2428109418
Directory /workspace/2.chip_sw_aes_entropy/latest

Test location /workspace/coverage/default/2.chip_sw_aes_idle.3416649291
Short name T1209
Test name
Test status
Simulation time 3164798218 ps
CPU time 303.24 seconds
Started Jul 14 08:09:48 PM PDT 24
Finished Jul 14 08:14:52 PM PDT 24
Peak memory 608676 kb
Host smart-4d872be0-25a2-4afe-b115-c639c394ea2b
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416649291 -asser
t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.3416649291
Directory /workspace/2.chip_sw_aes_idle/latest

Test location /workspace/coverage/default/2.chip_sw_aes_masking_off.1589355317
Short name T1191
Test name
Test status
Simulation time 2423118517 ps
CPU time 246.85 seconds
Started Jul 14 08:10:15 PM PDT 24
Finished Jul 14 08:14:22 PM PDT 24
Peak memory 609380 kb
Host smart-d266253a-e355-4101-93de-39ed8aa35657
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589355317 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.1589355317
Directory /workspace/2.chip_sw_aes_masking_off/latest

Test location /workspace/coverage/default/2.chip_sw_aes_smoketest.1617270691
Short name T1238
Test name
Test status
Simulation time 3169742236 ps
CPU time 298.25 seconds
Started Jul 14 08:15:16 PM PDT 24
Finished Jul 14 08:20:14 PM PDT 24
Peak memory 609152 kb
Host smart-ba6c72ce-86a0-4c70-a724-0b1f6321848b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617270691 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_aes_smoketest.1617270691
Directory /workspace/2.chip_sw_aes_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_entropy.831044611
Short name T157
Test name
Test status
Simulation time 3132746925 ps
CPU time 359.55 seconds
Started Jul 14 08:10:48 PM PDT 24
Finished Jul 14 08:16:49 PM PDT 24
Peak memory 608980 kb
Host smart-c5d1079c-1bec-4748-84a7-bc44b0cb7de4
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=831044611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.831044611
Directory /workspace/2.chip_sw_alert_handler_entropy/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_escalation.1077899500
Short name T1105
Test name
Test status
Simulation time 4793101180 ps
CPU time 489.04 seconds
Started Jul 14 08:11:01 PM PDT 24
Finished Jul 14 08:19:11 PM PDT 24
Peak memory 618572 kb
Host smart-ad4ff6d2-4dc8-4e32-ab74-7d3aa8db7984
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test
_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb
_random_seed=1077899500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.1077899500
Directory /workspace/2.chip_sw_alert_handler_escalation/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2815253484
Short name T1112
Test name
Test status
Simulation time 6788870920 ps
CPU time 1310.98 seconds
Started Jul 14 08:10:36 PM PDT 24
Finished Jul 14 08:32:28 PM PDT 24
Peak memory 609612 kb
Host smart-1471a4af-1d9f-4081-9379-fa91064650bb
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2815253484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.2815253484
Directory /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.907938845
Short name T1086
Test name
Test status
Simulation time 8766703270 ps
CPU time 1720.77 seconds
Started Jul 14 08:13:02 PM PDT 24
Finished Jul 14 08:41:43 PM PDT 24
Peak memory 609472 kb
Host smart-776f4a6a-ff55-49c1-bfa3-ad59fc49dc6f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,
test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=907938845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_toggle.907938845
Directory /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3586921334
Short name T742
Test name
Test status
Simulation time 12948635320 ps
CPU time 1315.86 seconds
Started Jul 14 08:12:13 PM PDT 24
Finished Jul 14 08:34:10 PM PDT 24
Peak memory 610348 kb
Host smart-7a281f6e-924b-41f4-8d1b-39585ec68c2f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler
_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586921334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han
dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.chip_sw_alert_handler_lpg_sleep_mode_pings.3586921334
Directory /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3518933581
Short name T315
Test name
Test status
Simulation time 8603098416 ps
CPU time 1365.03 seconds
Started Jul 14 08:10:43 PM PDT 24
Finished Jul 14 08:33:29 PM PDT 24
Peak memory 608704 kb
Host smart-60754681-4c12-4a44-b2f2-5501150ab3c0
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=3518933581 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.3518933581
Directory /workspace/2.chip_sw_alert_handler_ping_ok/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1036322576
Short name T479
Test name
Test status
Simulation time 3152979416 ps
CPU time 388.92 seconds
Started Jul 14 08:11:07 PM PDT 24
Finished Jul 14 08:17:37 PM PDT 24
Peak memory 609456 kb
Host smart-46c1b188-3341-47d0-a7db-adecb327a0a5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1036322576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.1036322576
Directory /workspace/2.chip_sw_alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1952548588
Short name T91
Test name
Test status
Simulation time 256323774954 ps
CPU time 11109.5 seconds
Started Jul 14 08:12:16 PM PDT 24
Finished Jul 14 11:17:27 PM PDT 24
Peak memory 609896 kb
Host smart-a7cd2d7c-bae8-4e75-a00e-19d5033cdee0
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n
ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952548588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1952548588
Directory /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location /workspace/coverage/default/2.chip_sw_alert_test.4153229104
Short name T68
Test name
Test status
Simulation time 3729758000 ps
CPU time 386.15 seconds
Started Jul 14 08:11:08 PM PDT 24
Finished Jul 14 08:17:35 PM PDT 24
Peak memory 609216 kb
Host smart-f3b8d97d-0cfd-400a-b6f9-185a9a6a5e0b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153229104 -assert nopostproc +UVM_TESTNAME=chip_ba
se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.chip_sw_alert_test.4153229104
Directory /workspace/2.chip_sw_alert_test/latest

Test location /workspace/coverage/default/2.chip_sw_all_escalation_resets.3645454527
Short name T1275
Test name
Test status
Simulation time 5213396032 ps
CPU time 850.33 seconds
Started Jul 14 08:10:07 PM PDT 24
Finished Jul 14 08:24:18 PM PDT 24
Peak memory 649544 kb
Host smart-f1fe94da-7c91-49c4-8ba4-ab42abc39f57
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3645454527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.3645454527
Directory /workspace/2.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_irq.1663918829
Short name T1317
Test name
Test status
Simulation time 3410039580 ps
CPU time 393.77 seconds
Started Jul 14 08:12:31 PM PDT 24
Finished Jul 14 08:19:06 PM PDT 24
Peak memory 609380 kb
Host smart-cdae902f-14cb-4f3f-b8bf-82fcb2fc241b
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663918829 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.1663918829
Directory /workspace/2.chip_sw_aon_timer_irq/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2765878060
Short name T902
Test name
Test status
Simulation time 8102276164 ps
CPU time 542.52 seconds
Started Jul 14 08:09:48 PM PDT 24
Finished Jul 14 08:18:52 PM PDT 24
Peak memory 608936 kb
Host smart-fd41b0ee-4512-46dd-aaaf-7a5d0210ba30
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2765878060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2765878060
Directory /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2066046529
Short name T944
Test name
Test status
Simulation time 2964995290 ps
CPU time 292.95 seconds
Started Jul 14 08:15:48 PM PDT 24
Finished Jul 14 08:20:41 PM PDT 24
Peak memory 609016 kb
Host smart-03fcf74c-1534-49af-b2a4-3c4f22493961
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066046529 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_sw_aon_timer_smoketest.2066046529
Directory /workspace/2.chip_sw_aon_timer_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2759286469
Short name T996
Test name
Test status
Simulation time 10549841650 ps
CPU time 1291 seconds
Started Jul 14 08:11:47 PM PDT 24
Finished Jul 14 08:33:19 PM PDT 24
Peak memory 609968 kb
Host smart-a4a185f2-e57b-4ad1-a5d2-47d10e656d4c
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2759286469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.2759286469
Directory /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest

Test location /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2001052645
Short name T1146
Test name
Test status
Simulation time 4587976520 ps
CPU time 560.31 seconds
Started Jul 14 08:09:36 PM PDT 24
Finished Jul 14 08:18:57 PM PDT 24
Peak memory 609928 kb
Host smart-b54dc7ee-bc3d-452f-84f9-9a3335a0ea6a
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2001052645 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.2001052645
Directory /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location /workspace/coverage/default/2.chip_sw_ast_clk_outputs.2662773254
Short name T1036
Test name
Test status
Simulation time 6792715200 ps
CPU time 971.25 seconds
Started Jul 14 08:13:09 PM PDT 24
Finished Jul 14 08:29:21 PM PDT 24
Peak memory 615332 kb
Host smart-0d95b95b-dd46-4b76-bae9-e4faebf4821f
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662773254 -assert nopo
stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.2662773254
Directory /workspace/2.chip_sw_ast_clk_outputs/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2474352375
Short name T172
Test name
Test status
Simulation time 11778943890 ps
CPU time 752.63 seconds
Started Jul 14 08:12:31 PM PDT 24
Finished Jul 14 08:25:04 PM PDT 24
Peak memory 622924 kb
Host smart-367fc576-fe99-4ef0-8485-899b51c270f4
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r
ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim
.tcl +ntb_random_seed=2474352375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.2474352375
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2937341189
Short name T192
Test name
Test status
Simulation time 4698391160 ps
CPU time 598.65 seconds
Started Jul 14 08:13:01 PM PDT 24
Finished Jul 14 08:23:00 PM PDT 24
Peak memory 611128 kb
Host smart-ae388b74-5281-4058-9fb6-7dfafa32f0e9
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937341189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_dev.2937341189
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3604342708
Short name T117
Test name
Test status
Simulation time 3249445144 ps
CPU time 733.34 seconds
Started Jul 14 08:13:47 PM PDT 24
Finished Jul 14 08:26:01 PM PDT 24
Peak memory 612364 kb
Host smart-0a83c543-7070-4ab4-9255-3b8ebd032fd5
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604342708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c
lkmgr_external_clk_src_for_sw_fast_rma.3604342708
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2773605380
Short name T881
Test name
Test status
Simulation time 3961444978 ps
CPU time 706.72 seconds
Started Jul 14 08:11:37 PM PDT 24
Finished Jul 14 08:23:24 PM PDT 24
Peak memory 612356 kb
Host smart-d2452325-9a9a-48c3-8f78-474fbd4e97d4
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773605380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2773605380
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3966354207
Short name T988
Test name
Test status
Simulation time 4401330024 ps
CPU time 730.2 seconds
Started Jul 14 08:15:17 PM PDT 24
Finished Jul 14 08:27:27 PM PDT 24
Peak memory 612548 kb
Host smart-902debe7-b032-41a1-b866-93826ce87043
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966354207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_dev.3966354207
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3803627718
Short name T1033
Test name
Test status
Simulation time 4999006536 ps
CPU time 764.53 seconds
Started Jul 14 08:13:48 PM PDT 24
Finished Jul 14 08:26:33 PM PDT 24
Peak memory 612056 kb
Host smart-ae29a420-c32f-4762-a4d3-015e6bfe6a0d
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima
ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803627718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c
lkmgr_external_clk_src_for_sw_slow_rma.3803627718
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3960644211
Short name T1034
Test name
Test status
Simulation time 5433317186 ps
CPU time 647.41 seconds
Started Jul 14 08:12:52 PM PDT 24
Finished Jul 14 08:23:40 PM PDT 24
Peak memory 612364 kb
Host smart-be69018c-b1ae-4c38-afdf-80e05c715897
User root
Command /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_
dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960644211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV
M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3960644211
Directory /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2708201766
Short name T1189
Test name
Test status
Simulation time 2707315952 ps
CPU time 276.26 seconds
Started Jul 14 08:12:51 PM PDT 24
Finished Jul 14 08:17:28 PM PDT 24
Peak memory 609284 kb
Host smart-f7fa6a16-3f89-46e5-9c4d-1a50d90b3eca
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708201766 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_clkmgr_jitter.2708201766
Directory /workspace/2.chip_sw_clkmgr_jitter/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.798349549
Short name T948
Test name
Test status
Simulation time 3447255624 ps
CPU time 397.44 seconds
Started Jul 14 08:13:09 PM PDT 24
Finished Jul 14 08:19:48 PM PDT 24
Peak memory 609112 kb
Host smart-04e71f91-fdad-4e1f-9eb6-89cdb4a5d5fb
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798349549 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.798349549
Directory /workspace/2.chip_sw_clkmgr_jitter_frequency/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.1042728219
Short name T912
Test name
Test status
Simulation time 3195171168 ps
CPU time 198.7 seconds
Started Jul 14 08:12:40 PM PDT 24
Finished Jul 14 08:15:59 PM PDT 24
Peak memory 608664 kb
Host smart-0fdccb4e-6473-4891-9259-8d76377b1f52
User root
Command /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042728219 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.1042728219
Directory /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1902722397
Short name T1134
Test name
Test status
Simulation time 4228497168 ps
CPU time 682.41 seconds
Started Jul 14 08:12:03 PM PDT 24
Finished Jul 14 08:23:26 PM PDT 24
Peak memory 609228 kb
Host smart-10a2f1a8-cd5e-4f88-817b-60e3969afca0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902722397 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.1902722397
Directory /workspace/2.chip_sw_clkmgr_off_aes_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3962501039
Short name T1029
Test name
Test status
Simulation time 4515353392 ps
CPU time 653.91 seconds
Started Jul 14 08:12:41 PM PDT 24
Finished Jul 14 08:23:36 PM PDT 24
Peak memory 609628 kb
Host smart-e7ebed38-f7de-44da-8386-46f321fa1f60
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962501039 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.3962501039
Directory /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.488167043
Short name T990
Test name
Test status
Simulation time 4741361260 ps
CPU time 722.3 seconds
Started Jul 14 08:11:38 PM PDT 24
Finished Jul 14 08:23:40 PM PDT 24
Peak memory 609724 kb
Host smart-c39e2312-a344-4238-8a47-bdf699802673
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488167043 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.488167043
Directory /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.823714321
Short name T969
Test name
Test status
Simulation time 4717412140 ps
CPU time 535.22 seconds
Started Jul 14 08:13:41 PM PDT 24
Finished Jul 14 08:22:37 PM PDT 24
Peak memory 609764 kb
Host smart-2c14310d-7b0e-48d2-bd71-12dec3e12f14
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823714321 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.823714321
Directory /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3362625131
Short name T1090
Test name
Test status
Simulation time 9235037480 ps
CPU time 1056.58 seconds
Started Jul 14 08:12:31 PM PDT 24
Finished Jul 14 08:30:08 PM PDT 24
Peak memory 609840 kb
Host smart-a3afdd44-70f2-4c4e-a1b1-52016845be7c
User root
Command /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362625131
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.3362625131
Directory /workspace/2.chip_sw_clkmgr_off_peri/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3044910449
Short name T1245
Test name
Test status
Simulation time 3379438632 ps
CPU time 538.04 seconds
Started Jul 14 08:13:18 PM PDT 24
Finished Jul 14 08:22:16 PM PDT 24
Peak memory 608976 kb
Host smart-a49cfa99-ca4e-4bff-a7d5-f9d938eb4b3e
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044910449 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.3044910449
Directory /workspace/2.chip_sw_clkmgr_reset_frequency/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3119600141
Short name T882
Test name
Test status
Simulation time 4240303272 ps
CPU time 640.6 seconds
Started Jul 14 08:14:17 PM PDT 24
Finished Jul 14 08:24:58 PM PDT 24
Peak memory 609072 kb
Host smart-66acb3c4-fae5-4d1f-8aa3-ac362aaf281d
User root
Command /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119600141 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.3119600141
Directory /workspace/2.chip_sw_clkmgr_sleep_frequency/latest

Test location /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1404919856
Short name T271
Test name
Test status
Simulation time 2936388200 ps
CPU time 215.88 seconds
Started Jul 14 08:14:16 PM PDT 24
Finished Jul 14 08:17:52 PM PDT 24
Peak memory 608688 kb
Host smart-10c9526f-9f76-4490-acaf-96b9aff12eb1
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404919856 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.chip_sw_clkmgr_smoketest.1404919856
Directory /workspace/2.chip_sw_clkmgr_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1306739964
Short name T665
Test name
Test status
Simulation time 36656353238 ps
CPU time 7538.44 seconds
Started Jul 14 08:13:01 PM PDT 24
Finished Jul 14 10:18:41 PM PDT 24
Peak memory 610004 kb
Host smart-a3a2d6d4-3687-4e41-94d9-7f0bf290a010
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c
oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306739964 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.1306739964
Directory /workspace/2.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1468189856
Short name T111
Test name
Test status
Simulation time 23545586559 ps
CPU time 4472.55 seconds
Started Jul 14 08:16:04 PM PDT 24
Finished Jul 14 09:30:37 PM PDT 24
Peak memory 610016 kb
Host smart-feb47073-f281-44a1-b52a-5936ca2a7965
User root
Command /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de
vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1468189856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.1468189856
Directory /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2139589440
Short name T908
Test name
Test status
Simulation time 4997323884 ps
CPU time 370.32 seconds
Started Jul 14 08:10:39 PM PDT 24
Finished Jul 14 08:16:49 PM PDT 24
Peak memory 608792 kb
Host smart-a4cfb2e7-0a08-4146-a357-ba90dca9a9f7
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21395
89440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.2139589440
Directory /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_kat_test.3700645756
Short name T295
Test name
Test status
Simulation time 2822717130 ps
CPU time 347.92 seconds
Started Jul 14 08:11:04 PM PDT 24
Finished Jul 14 08:16:52 PM PDT 24
Peak memory 608700 kb
Host smart-80999745-96b8-4c8d-83e7-4c946e6b74b3
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700645756 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.3700645756
Directory /workspace/2.chip_sw_csrng_kat_test/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3610080045
Short name T397
Test name
Test status
Simulation time 7222478112 ps
CPU time 689.25 seconds
Started Jul 14 08:10:49 PM PDT 24
Finished Jul 14 08:22:19 PM PDT 24
Peak memory 610736 kb
Host smart-d2937eb5-38bc-415e-8383-06cc054da802
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima
ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610080045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_
lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr
ng_lc_hw_debug_en_test.3610080045
Directory /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location /workspace/coverage/default/2.chip_sw_csrng_smoketest.2266250129
Short name T1321
Test name
Test status
Simulation time 3439580132 ps
CPU time 299.49 seconds
Started Jul 14 08:13:51 PM PDT 24
Finished Jul 14 08:18:51 PM PDT 24
Peak memory 609244 kb
Host smart-83cc3421-96ac-47c8-866c-3a85dc8bbd69
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266250129 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.chip_sw_csrng_smoketest.2266250129
Directory /workspace/2.chip_sw_csrng_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_data_integrity_escalation.5551683
Short name T1184
Test name
Test status
Simulation time 5065200200 ps
CPU time 568.29 seconds
Started Jul 14 08:06:47 PM PDT 24
Finished Jul 14 08:16:16 PM PDT 24
Peak memory 610108 kb
Host smart-a1f2390b-3550-496c-b07b-f0163729ed46
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=5551683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.5551683
Directory /workspace/2.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/2.chip_sw_edn_auto_mode.182518199
Short name T1244
Test name
Test status
Simulation time 4516313952 ps
CPU time 1042.48 seconds
Started Jul 14 08:11:25 PM PDT 24
Finished Jul 14 08:28:48 PM PDT 24
Peak memory 608612 kb
Host smart-f8d8720f-c031-4bc4-8de5-c745c40a4e93
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc
elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182518199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_a
uto_mode.182518199
Directory /workspace/2.chip_sw_edn_auto_mode/latest

Test location /workspace/coverage/default/2.chip_sw_edn_boot_mode.3480649836
Short name T283
Test name
Test status
Simulation time 3644180876 ps
CPU time 543.75 seconds
Started Jul 14 08:11:16 PM PDT 24
Finished Jul 14 08:20:20 PM PDT 24
Peak memory 609736 kb
Host smart-81d07c01-90e2-40a6-9b2a-1fa7cf8def85
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc
elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480649836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_
boot_mode.3480649836
Directory /workspace/2.chip_sw_edn_boot_mode/latest

Test location /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3342373812
Short name T1261
Test name
Test status
Simulation time 6120312848 ps
CPU time 1195.41 seconds
Started Jul 14 08:10:55 PM PDT 24
Finished Jul 14 08:30:51 PM PDT 24
Peak memory 610352 kb
Host smart-5c45625c-cfa0-475f-995a-79af7d2d269a
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed
n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3342373812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.3342373812
Directory /workspace/2.chip_sw_edn_entropy_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1384189876
Short name T1192
Test name
Test status
Simulation time 5977888903 ps
CPU time 1009.07 seconds
Started Jul 14 08:10:51 PM PDT 24
Finished Jul 14 08:27:42 PM PDT 24
Peak memory 610424 kb
Host smart-89b45d02-a833-4f2c-8365-50a2b755c92a
User root
Command /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e
ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384189876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.1384189876
Directory /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest

Test location /workspace/coverage/default/2.chip_sw_edn_kat.1820957789
Short name T923
Test name
Test status
Simulation time 3572602424 ps
CPU time 665.98 seconds
Started Jul 14 08:13:00 PM PDT 24
Finished Jul 14 08:24:06 PM PDT 24
Peak memory 615032 kb
Host smart-4ff59ad1-6926-4dfe-8072-a27d09556a75
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag
es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820957789 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.chip_sw_edn_kat.1820957789
Directory /workspace/2.chip_sw_edn_kat/latest

Test location /workspace/coverage/default/2.chip_sw_edn_sw_mode.1004543510
Short name T1035
Test name
Test status
Simulation time 5672684808 ps
CPU time 1188.3 seconds
Started Jul 14 08:10:50 PM PDT 24
Finished Jul 14 08:30:40 PM PDT 24
Peak memory 608656 kb
Host smart-6018562d-bebe-4a7e-82d7-449109e4c245
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004543510 -assert
nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.1004543510
Directory /workspace/2.chip_sw_edn_sw_mode/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2783289907
Short name T914
Test name
Test status
Simulation time 2895397744 ps
CPU time 189.28 seconds
Started Jul 14 08:11:37 PM PDT 24
Finished Jul 14 08:14:46 PM PDT 24
Peak memory 608668 kb
Host smart-ddbd6772-2a95-4e81-b682-08ba2deae816
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27
83289907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.2783289907
Directory /workspace/2.chip_sw_entropy_src_ast_rng_req/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.4119192185
Short name T299
Test name
Test status
Simulation time 2598264810 ps
CPU time 234.77 seconds
Started Jul 14 08:10:11 PM PDT 24
Finished Jul 14 08:14:06 PM PDT 24
Peak memory 608660 kb
Host smart-7d6f7d35-3919-494d-8bb5-f74d5e505984
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119192185
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.4119192185
Directory /workspace/2.chip_sw_entropy_src_kat_test/latest

Test location /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.892849919
Short name T1041
Test name
Test status
Simulation time 3937350286 ps
CPU time 488.36 seconds
Started Jul 14 08:15:29 PM PDT 24
Finished Jul 14 08:23:38 PM PDT 24
Peak memory 608696 kb
Host smart-9b491c62-ac7c-4b21-94c0-52b1f1e4b303
User root
Command /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=892849919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.892849919
Directory /workspace/2.chip_sw_entropy_src_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_example_concurrency.243820245
Short name T885
Test name
Test status
Simulation time 2629007268 ps
CPU time 253.02 seconds
Started Jul 14 08:10:02 PM PDT 24
Finished Jul 14 08:14:16 PM PDT 24
Peak memory 609268 kb
Host smart-ea656c6a-62ad-4816-9c84-533951c05c7d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243820245 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_example_concurrency.243820245
Directory /workspace/2.chip_sw_example_concurrency/latest

Test location /workspace/coverage/default/2.chip_sw_example_flash.862421485
Short name T432
Test name
Test status
Simulation time 2632772278 ps
CPU time 197.47 seconds
Started Jul 14 08:06:44 PM PDT 24
Finished Jul 14 08:10:02 PM PDT 24
Peak memory 607912 kb
Host smart-41c8a07e-e858-4f17-9626-cadebaaf3774
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862421485 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_example_flash.862421485
Directory /workspace/2.chip_sw_example_flash/latest

Test location /workspace/coverage/default/2.chip_sw_example_manufacturer.3949018740
Short name T1096
Test name
Test status
Simulation time 3231987934 ps
CPU time 251.07 seconds
Started Jul 14 08:10:06 PM PDT 24
Finished Jul 14 08:14:17 PM PDT 24
Peak memory 609036 kb
Host smart-30afe636-e414-4d1c-9f29-b50c66f2869d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949018740 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_example_manufacturer.3949018740
Directory /workspace/2.chip_sw_example_manufacturer/latest

Test location /workspace/coverage/default/2.chip_sw_example_rom.2912869426
Short name T927
Test name
Test status
Simulation time 2434964960 ps
CPU time 143.4 seconds
Started Jul 14 08:05:46 PM PDT 24
Finished Jul 14 08:08:10 PM PDT 24
Peak memory 608876 kb
Host smart-67c0ac9d-b393-4164-8745-a11a9d835bff
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912869426 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_example_rom.2912869426
Directory /workspace/2.chip_sw_example_rom/latest

Test location /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2065651480
Short name T1190
Test name
Test status
Simulation time 59256827242 ps
CPU time 10973.2 seconds
Started Jul 14 08:07:04 PM PDT 24
Finished Jul 14 11:09:59 PM PDT 24
Peak memory 623208 kb
Host smart-3a54f377-23d4-46cc-bd3a-4d837d82a952
User root
Command /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=2065651480 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.2065651480
Directory /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest

Test location /workspace/coverage/default/2.chip_sw_flash_crash_alert.3405903565
Short name T1234
Test name
Test status
Simulation time 4820413936 ps
CPU time 540.26 seconds
Started Jul 14 08:15:27 PM PDT 24
Finished Jul 14 08:24:27 PM PDT 24
Peak memory 610440 kb
Host smart-f753412e-12be-47a9-816b-35d7e6a77645
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:
new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool
s/sim.tcl +ntb_random_seed=3405903565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.3405903565
Directory /workspace/2.chip_sw_flash_crash_alert/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_access.133944407
Short name T938
Test name
Test status
Simulation time 5741015528 ps
CPU time 1334.88 seconds
Started Jul 14 08:09:25 PM PDT 24
Finished Jul 14 08:31:41 PM PDT 24
Peak memory 608656 kb
Host smart-7f66764b-674c-4422-b9c9-0023fc4fee48
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133944407 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_flash_ctrl_access.133944407
Directory /workspace/2.chip_sw_flash_ctrl_access/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.415433200
Short name T1206
Test name
Test status
Simulation time 5991050584 ps
CPU time 1165.28 seconds
Started Jul 14 08:08:07 PM PDT 24
Finished Jul 14 08:27:33 PM PDT 24
Peak memory 609596 kb
Host smart-8c8c6ea7-0bd5-4adb-b6b5-7db943d66137
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415433200 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.415433200
Directory /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2013859084
Short name T1313
Test name
Test status
Simulation time 7522769136 ps
CPU time 1202.82 seconds
Started Jul 14 08:13:59 PM PDT 24
Finished Jul 14 08:34:02 PM PDT 24
Peak memory 608672 kb
Host smart-fca92a41-afc3-4e92-b848-749fc5882fe7
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013859084 -
assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2013859084
Directory /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2956734205
Short name T934
Test name
Test status
Simulation time 5779356735 ps
CPU time 1293.9 seconds
Started Jul 14 08:07:28 PM PDT 24
Finished Jul 14 08:29:03 PM PDT 24
Peak memory 608644 kb
Host smart-a4f4f548-1547-4353-aa89-fb4a66f09e38
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956734205 -assert nopostproc +UVM
_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.2956734205
Directory /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3427555134
Short name T368
Test name
Test status
Simulation time 3379499960 ps
CPU time 372.07 seconds
Started Jul 14 08:11:56 PM PDT 24
Finished Jul 14 08:18:08 PM PDT 24
Peak memory 608648 kb
Host smart-b7d1d3e7-c942-4b91-9187-e8b6b372b91a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427555134 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.3427555134
Directory /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1573310039
Short name T237
Test name
Test status
Simulation time 4223409783 ps
CPU time 472.45 seconds
Started Jul 14 08:06:49 PM PDT 24
Finished Jul 14 08:14:42 PM PDT 24
Peak memory 608668 kb
Host smart-20336bbe-ac8c-4b61-95e3-81dd5b5ea6ca
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15
73310039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.1573310039
Directory /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3442935863
Short name T978
Test name
Test status
Simulation time 5222573430 ps
CPU time 1022.67 seconds
Started Jul 14 08:13:41 PM PDT 24
Finished Jul 14 08:30:45 PM PDT 24
Peak memory 608676 kb
Host smart-f6f33a62-3b70-4e77-8c8a-64958f9e9efd
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442935863 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.3442935863
Directory /workspace/2.chip_sw_flash_ctrl_mem_protection/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1460357748
Short name T1199
Test name
Test status
Simulation time 3612923550 ps
CPU time 705.84 seconds
Started Jul 14 08:08:01 PM PDT 24
Finished Jul 14 08:19:48 PM PDT 24
Peak memory 609576 kb
Host smart-dec03719-105a-4fd2-9a1f-925a3c938b04
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460357748
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.1460357748
Directory /workspace/2.chip_sw_flash_ctrl_ops/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.4136153777
Short name T351
Test name
Test status
Simulation time 4468862253 ps
CPU time 854.62 seconds
Started Jul 14 08:08:32 PM PDT 24
Finished Jul 14 08:22:47 PM PDT 24
Peak memory 609684 kb
Host smart-144fe088-bbcd-4232-844a-4851822d4c53
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4136153777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.4136153777
Directory /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2831259452
Short name T352
Test name
Test status
Simulation time 4782819844 ps
CPU time 764.72 seconds
Started Jul 14 08:14:05 PM PDT 24
Finished Jul 14 08:26:51 PM PDT 24
Peak memory 609824 kb
Host smart-f4461c53-77da-4168-b12b-2c2226e5d29e
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_
rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2831259452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2831259452
Directory /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.3346018055
Short name T878
Test name
Test status
Simulation time 3099128332 ps
CPU time 442.5 seconds
Started Jul 14 08:14:01 PM PDT 24
Finished Jul 14 08:21:24 PM PDT 24
Peak memory 608680 kb
Host smart-b8185e4c-0810-4fdf-91f2-a82c48d6d49e
User root
Command /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346018
055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.3346018055
Directory /workspace/2.chip_sw_flash_ctrl_write_clear/latest

Test location /workspace/coverage/default/2.chip_sw_flash_init.4006600123
Short name T232
Test name
Test status
Simulation time 24024710305 ps
CPU time 2166.1 seconds
Started Jul 14 08:08:41 PM PDT 24
Finished Jul 14 08:44:49 PM PDT 24
Peak memory 611344 kb
Host smart-1530fbe5-a742-41fa-b206-6e38a3224a5c
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006600123 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.4006600123
Directory /workspace/2.chip_sw_flash_init/latest

Test location /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.4149578928
Short name T1207
Test name
Test status
Simulation time 19895706322 ps
CPU time 1954 seconds
Started Jul 14 08:12:27 PM PDT 24
Finished Jul 14 08:45:01 PM PDT 24
Peak memory 614012 kb
Host smart-9a807f63-af29-43c6-9080-2db604633e8c
User root
Command /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4149578928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.4149578928
Directory /workspace/2.chip_sw_flash_init_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2562700278
Short name T1010
Test name
Test status
Simulation time 2150969612 ps
CPU time 198.85 seconds
Started Jul 14 08:17:05 PM PDT 24
Finished Jul 14 08:20:24 PM PDT 24
Peak memory 609108 kb
Host smart-a1e3eb4b-8e1e-4a71-b7df-9bdb546f52da
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket
est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2562700278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.2562700278
Directory /workspace/2.chip_sw_flash_scrambling_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_gpio_smoketest.1845599738
Short name T1117
Test name
Test status
Simulation time 3527893297 ps
CPU time 265.39 seconds
Started Jul 14 08:14:02 PM PDT 24
Finished Jul 14 08:18:27 PM PDT 24
Peak memory 609644 kb
Host smart-d5be738b-9b2e-4e35-864f-40495baabdb0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845599738 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_sw_gpio_smoketest.1845599738
Directory /workspace/2.chip_sw_gpio_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc.3450105826
Short name T349
Test name
Test status
Simulation time 2560007688 ps
CPU time 323.24 seconds
Started Jul 14 08:11:39 PM PDT 24
Finished Jul 14 08:17:03 PM PDT 24
Peak memory 609080 kb
Host smart-a0176061-66c8-441c-b0a8-856e9151f9fc
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450105826 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_hmac_enc.3450105826
Directory /workspace/2.chip_sw_hmac_enc/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc_idle.19141947
Short name T1193
Test name
Test status
Simulation time 2654229136 ps
CPU time 309.23 seconds
Started Jul 14 08:12:31 PM PDT 24
Finished Jul 14 08:17:41 PM PDT 24
Peak memory 609152 kb
Host smart-7901fe69-65d3-4d94-98ce-b4e1c041edb8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19141947 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.chip_sw_hmac_enc_idle.19141947
Directory /workspace/2.chip_sw_hmac_enc_idle/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.2866484583
Short name T1122
Test name
Test status
Simulation time 3148456673 ps
CPU time 240.17 seconds
Started Jul 14 08:10:16 PM PDT 24
Finished Jul 14 08:14:16 PM PDT 24
Peak memory 609124 kb
Host smart-5555be7d-a2a2-47ad-9ec0-01fc7bd0f85c
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866484583 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.2866484583
Directory /workspace/2.chip_sw_hmac_enc_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1270735760
Short name T1277
Test name
Test status
Simulation time 3904128551 ps
CPU time 352.47 seconds
Started Jul 14 08:14:06 PM PDT 24
Finished Jul 14 08:19:59 PM PDT 24
Peak memory 608700 kb
Host smart-c406ef36-8f7e-44d3-a34a-7a3b05b0707e
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270735760 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.1270735760
Directory /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_multistream.1718231316
Short name T1072
Test name
Test status
Simulation time 8235524664 ps
CPU time 1722.79 seconds
Started Jul 14 08:12:11 PM PDT 24
Finished Jul 14 08:40:54 PM PDT 24
Peak memory 609540 kb
Host smart-e10fbd35-2b93-4029-b6fa-ceb20dacf207
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718231316 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.chip_sw_hmac_multistream.1718231316
Directory /workspace/2.chip_sw_hmac_multistream/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_oneshot.3675920322
Short name T1180
Test name
Test status
Simulation time 3482628900 ps
CPU time 438.3 seconds
Started Jul 14 08:11:19 PM PDT 24
Finished Jul 14 08:18:38 PM PDT 24
Peak memory 608992 kb
Host smart-38f60fba-e980-4f8a-a59e-adb3c29980c2
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675920322 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_hmac_oneshot.3675920322
Directory /workspace/2.chip_sw_hmac_oneshot/latest

Test location /workspace/coverage/default/2.chip_sw_hmac_smoketest.4279928173
Short name T1007
Test name
Test status
Simulation time 2953622920 ps
CPU time 477.81 seconds
Started Jul 14 08:14:26 PM PDT 24
Finished Jul 14 08:22:24 PM PDT 24
Peak memory 609096 kb
Host smart-8ceff3e8-a6a8-49d0-84de-62a818896339
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279928173 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_hmac_smoketest.4279928173
Directory /workspace/2.chip_sw_hmac_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2992058213
Short name T1253
Test name
Test status
Simulation time 4418783240 ps
CPU time 678.18 seconds
Started Jul 14 08:08:18 PM PDT 24
Finished Jul 14 08:19:38 PM PDT 24
Peak memory 609000 kb
Host smart-d37bb869-4b0e-41a9-a209-161222d7947b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992058213 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.2992058213
Directory /workspace/2.chip_sw_i2c_device_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.312220096
Short name T328
Test name
Test status
Simulation time 5043240448 ps
CPU time 903.2 seconds
Started Jul 14 08:07:53 PM PDT 24
Finished Jul 14 08:22:56 PM PDT 24
Peak memory 608580 kb
Host smart-187b98be-356a-4023-ba60-d42d2fd5655a
User root
Command /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312220096 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.312220096
Directory /workspace/2.chip_sw_i2c_host_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3137968005
Short name T327
Test name
Test status
Simulation time 4526603072 ps
CPU time 732.48 seconds
Started Jul 14 08:07:28 PM PDT 24
Finished Jul 14 08:19:42 PM PDT 24
Peak memory 608608 kb
Host smart-55cd88d1-c255-47b9-816e-04805dea7477
User root
Command /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137968005 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.3137968005
Directory /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest

Test location /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3366668319
Short name T103
Test name
Test status
Simulation time 5176905592 ps
CPU time 788.9 seconds
Started Jul 14 08:06:52 PM PDT 24
Finished Jul 14 08:20:01 PM PDT 24
Peak memory 608700 kb
Host smart-46505465-5d1a-4050-85d4-81e832eb530a
User root
Command /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366668319 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.3366668319
Directory /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest

Test location /workspace/coverage/default/2.chip_sw_inject_scramble_seed.56682246
Short name T1109
Test name
Test status
Simulation time 64802070345 ps
CPU time 12309.9 seconds
Started Jul 14 08:10:53 PM PDT 24
Finished Jul 14 11:36:06 PM PDT 24
Peak memory 623812 kb
Host smart-4fc0b01c-21a9-471f-9553-1c6e0a4bea53
User root
Command /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=56682246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.56682246
Directory /workspace/2.chip_sw_inject_scramble_seed/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.382353664
Short name T997
Test name
Test status
Simulation time 10608339300 ps
CPU time 1863.02 seconds
Started Jul 14 08:11:24 PM PDT 24
Finished Jul 14 08:42:28 PM PDT 24
Peak memory 616224 kb
Host smart-b6eda38f-ed21-4dad-aa8d-8c3c852183e0
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823
53664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.382353664
Directory /workspace/2.chip_sw_keymgr_key_derivation/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3718134794
Short name T1008
Test name
Test status
Simulation time 8172503158 ps
CPU time 1778.14 seconds
Started Jul 14 08:12:58 PM PDT 24
Finished Jul 14 08:42:38 PM PDT 24
Peak memory 617004 kb
Host smart-7a0cf553-255b-43e3-b330-75552942a829
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3718134794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.3718134794
Directory /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1891712433
Short name T1067
Test name
Test status
Simulation time 8727236785 ps
CPU time 1328.88 seconds
Started Jul 14 08:13:57 PM PDT 24
Finished Jul 14 08:36:06 PM PDT 24
Peak memory 616284 kb
Host smart-1132db70-d739-474e-9554-dd74fe101f6f
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1891712433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en
_reduced_freq.1891712433
Directory /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3042748209
Short name T1200
Test name
Test status
Simulation time 7134585176 ps
CPU time 1288.38 seconds
Started Jul 14 08:12:18 PM PDT 24
Finished Jul 14 08:33:47 PM PDT 24
Peak memory 616524 kb
Host smart-28c92b86-6815-4962-9602-44ab9a82e377
User root
Command /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3042748209 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.3042748209
Directory /workspace/2.chip_sw_keymgr_key_derivation_prod/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.939326741
Short name T225
Test name
Test status
Simulation time 6344848712 ps
CPU time 1176.61 seconds
Started Jul 14 08:12:09 PM PDT 24
Finished Jul 14 08:31:47 PM PDT 24
Peak memory 610776 kb
Host smart-d19b6ad7-eabe-47fe-b360-e51fad8ea15a
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939326
741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.939326741
Directory /workspace/2.chip_sw_keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.4099887894
Short name T152
Test name
Test status
Simulation time 12329658270 ps
CPU time 2561.18 seconds
Started Jul 14 08:12:30 PM PDT 24
Finished Jul 14 08:55:12 PM PDT 24
Peak memory 610428 kb
Host smart-6dcfe6a1-6ea7-46ac-a176-672098da0bf1
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40998
87894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.4099887894
Directory /workspace/2.chip_sw_keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3859986771
Short name T228
Test name
Test status
Simulation time 16924909144 ps
CPU time 4669.91 seconds
Started Jul 14 08:11:02 PM PDT 24
Finished Jul 14 09:28:53 PM PDT 24
Peak memory 610336 kb
Host smart-6b95add6-52c1-4bac-91bc-7a60eea3222a
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38599
86771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.3859986771
Directory /workspace/2.chip_sw_keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_app_rom.1562212473
Short name T1084
Test name
Test status
Simulation time 2722382028 ps
CPU time 222.25 seconds
Started Jul 14 08:12:07 PM PDT 24
Finished Jul 14 08:15:50 PM PDT 24
Peak memory 609220 kb
Host smart-bf3973d6-7c39-4229-a5e2-dee5a4d3ae40
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562212473 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_kmac_app_rom.1562212473
Directory /workspace/2.chip_sw_kmac_app_rom/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_entropy.2406493859
Short name T1226
Test name
Test status
Simulation time 2844903720 ps
CPU time 291.34 seconds
Started Jul 14 08:07:19 PM PDT 24
Finished Jul 14 08:12:11 PM PDT 24
Peak memory 609288 kb
Host smart-3495cb7d-4495-4ccd-b61b-13b6e70ba95e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406493859 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_kmac_entropy.2406493859
Directory /workspace/2.chip_sw_kmac_entropy/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_idle.2571272028
Short name T1056
Test name
Test status
Simulation time 2905141836 ps
CPU time 345.72 seconds
Started Jul 14 08:12:28 PM PDT 24
Finished Jul 14 08:18:14 PM PDT 24
Peak memory 608628 kb
Host smart-1a027ab5-de44-4d59-8718-198dac6b1843
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571272028 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_kmac_idle.2571272028
Directory /workspace/2.chip_sw_kmac_idle/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2336198274
Short name T953
Test name
Test status
Simulation time 3008463230 ps
CPU time 288.64 seconds
Started Jul 14 08:11:41 PM PDT 24
Finished Jul 14 08:16:29 PM PDT 24
Peak memory 607992 kb
Host smart-4fcb603b-0426-4c1c-86af-0f336a44af7a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336198274 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.chip_sw_kmac_mode_cshake.2336198274
Directory /workspace/2.chip_sw_kmac_mode_cshake/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1974786601
Short name T480
Test name
Test status
Simulation time 3102799508 ps
CPU time 463.95 seconds
Started Jul 14 08:12:04 PM PDT 24
Finished Jul 14 08:19:49 PM PDT 24
Peak memory 609284 kb
Host smart-24d0b963-d8e4-42e1-b3d0-b64a68b8f9d4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974786601 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_sw_kmac_mode_kmac.1974786601
Directory /workspace/2.chip_sw_kmac_mode_kmac/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3280661297
Short name T1066
Test name
Test status
Simulation time 2900688456 ps
CPU time 268.8 seconds
Started Jul 14 08:11:45 PM PDT 24
Finished Jul 14 08:16:15 PM PDT 24
Peak memory 608684 kb
Host smart-b4275955-4d8f-4eff-ab73-9dcb77a12c62
User root
Command /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280661297 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.3280661297
Directory /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.4136537958
Short name T1160
Test name
Test status
Simulation time 3945492939 ps
CPU time 315.39 seconds
Started Jul 14 08:14:11 PM PDT 24
Finished Jul 14 08:19:27 PM PDT 24
Peak memory 608912 kb
Host smart-f2a8a888-0732-49ef-be35-54e57458cc8e
User root
Command /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41365379
58 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.4136537958
Directory /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_kmac_smoketest.3136818936
Short name T1098
Test name
Test status
Simulation time 2703675196 ps
CPU time 320.09 seconds
Started Jul 14 08:15:48 PM PDT 24
Finished Jul 14 08:21:09 PM PDT 24
Peak memory 608652 kb
Host smart-c9af5371-398c-4534-a091-7483b5325b5c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136818936 -assert nopostproc +UVM_TESTNAME=chi
p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.chip_sw_kmac_smoketest.3136818936
Directory /workspace/2.chip_sw_kmac_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2706477762
Short name T1259
Test name
Test status
Simulation time 2511865390 ps
CPU time 320.8 seconds
Started Jul 14 08:10:54 PM PDT 24
Finished Jul 14 08:16:15 PM PDT 24
Peak memory 607916 kb
Host smart-97f38649-51d9-4f9e-880b-5cda474a4683
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706477762 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.2706477762
Directory /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.3789322273
Short name T72
Test name
Test status
Simulation time 4896200728 ps
CPU time 413.35 seconds
Started Jul 14 08:12:01 PM PDT 24
Finished Jul 14 08:18:54 PM PDT 24
Peak memory 610076 kb
Host smart-e41966fd-5a41-41c8-a416-c570219200eb
User root
Command /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3789322273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.3789322273
Directory /workspace/2.chip_sw_lc_ctrl_program_error/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2320805036
Short name T1211
Test name
Test status
Simulation time 2510251683 ps
CPU time 149.02 seconds
Started Jul 14 08:13:10 PM PDT 24
Finished Jul 14 08:15:40 PM PDT 24
Peak memory 619620 kb
Host smart-9508491f-c163-4014-86d8-af057587710e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23208050
36 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.2320805036
Directory /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.705575628
Short name T1015
Test name
Test status
Simulation time 8749471562 ps
CPU time 659.54 seconds
Started Jul 14 08:09:48 PM PDT 24
Finished Jul 14 08:20:49 PM PDT 24
Peak memory 622180 kb
Host smart-437992a4-251d-4a84-96e4-366946339e20
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705575628 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.705575628
Directory /workspace/2.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1110679367
Short name T1089
Test name
Test status
Simulation time 2998323716 ps
CPU time 114.72 seconds
Started Jul 14 08:07:50 PM PDT 24
Finished Jul 14 08:09:45 PM PDT 24
Peak memory 614404 kb
Host smart-24fe063b-3163-41e2-b508-d76fdc80650d
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes
t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1110679367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.1110679367
Directory /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1100471025
Short name T680
Test name
Test status
Simulation time 2737620864 ps
CPU time 130.87 seconds
Started Jul 14 08:08:20 PM PDT 24
Finished Jul 14 08:10:34 PM PDT 24
Peak memory 617280 kb
Host smart-0131fbdd-ea3c-40c5-8030-bcfabb2631b5
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s
im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100471025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1100471025
Directory /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.532079608
Short name T1196
Test name
Test status
Simulation time 50720728408 ps
CPU time 5480 seconds
Started Jul 14 08:07:54 PM PDT 24
Finished Jul 14 09:39:16 PM PDT 24
Peak memory 614992 kb
Host smart-c85f29e0-dcee-44b6-9f9e-11fdb4ae7dc8
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532079608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch
ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_
sw_lc_walkthrough_dev.532079608
Directory /workspace/2.chip_sw_lc_walkthrough_dev/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1385367478
Short name T1054
Test name
Test status
Simulation time 9956671070 ps
CPU time 1056.56 seconds
Started Jul 14 08:09:12 PM PDT 24
Finished Jul 14 08:26:50 PM PDT 24
Peak memory 619140 kb
Host smart-afb21b74-3dea-4cc9-98bf-ca229c848a9d
User root
Command /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa
lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385367478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.1385367478
Directory /workspace/2.chip_sw_lc_walkthrough_prodend/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2860965175
Short name T167
Test name
Test status
Simulation time 47798954148 ps
CPU time 5165.48 seconds
Started Jul 14 08:09:07 PM PDT 24
Finished Jul 14 09:35:13 PM PDT 24
Peak memory 616100 kb
Host smart-47a70049-df34-4e86-a56b-ff38e434a661
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de
vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860965175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c
hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip
_sw_lc_walkthrough_rma.2860965175
Directory /workspace/2.chip_sw_lc_walkthrough_rma/latest

Test location /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.4227032732
Short name T1051
Test name
Test status
Simulation time 30256358665 ps
CPU time 2228.34 seconds
Started Jul 14 08:08:29 PM PDT 24
Finished Jul 14 08:45:38 PM PDT 24
Peak memory 619544 kb
Host smart-cd5b258b-e068-4382-8b9e-b398506a20c2
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks
_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4227032732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun
locks.4227032732
Directory /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2812424546
Short name T1162
Test name
Test status
Simulation time 16846617048 ps
CPU time 3590.95 seconds
Started Jul 14 08:10:21 PM PDT 24
Finished Jul 14 09:10:13 PM PDT 24
Peak memory 608816 kb
Host smart-7be4ea30-10cc-4745-98d4-146ce11185d0
User root
Command /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_
rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2812424546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.2812424546
Directory /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1758854714
Short name T1150
Test name
Test status
Simulation time 18319227354 ps
CPU time 3466.26 seconds
Started Jul 14 08:09:40 PM PDT 24
Finished Jul 14 09:07:27 PM PDT 24
Peak memory 609928 kb
Host smart-d9f5d795-ed17-4563-99ae-7f2faa75b486
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne
w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1758854714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1758854714
Directory /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3838824451
Short name T1246
Test name
Test status
Simulation time 24495418274 ps
CPU time 3743.6 seconds
Started Jul 14 08:14:49 PM PDT 24
Finished Jul 14 09:17:14 PM PDT 24
Peak memory 609612 kb
Host smart-13fcbb7d-ad7a-4437-8f29-b57e150b2d03
User root
Command /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e
cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838824451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu
ced_freq.3838824451
Directory /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1460551334
Short name T43
Test name
Test status
Simulation time 3348706690 ps
CPU time 449.94 seconds
Started Jul 14 08:16:53 PM PDT 24
Finished Jul 14 08:24:24 PM PDT 24
Peak memory 608696 kb
Host smart-1d7bab6c-82fc-4c04-bff9-1cd9ab43ad5b
User root
Command /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn
_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460551334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.1460551334
Directory /workspace/2.chip_sw_otbn_mem_scramble/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_randomness.1731325464
Short name T1178
Test name
Test status
Simulation time 6057321652 ps
CPU time 1074.55 seconds
Started Jul 14 08:10:28 PM PDT 24
Finished Jul 14 08:28:23 PM PDT 24
Peak memory 609864 kb
Host smart-6541604c-dab8-423e-b0a5-28793e2da4fe
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1731325464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.1731325464
Directory /workspace/2.chip_sw_otbn_randomness/latest

Test location /workspace/coverage/default/2.chip_sw_otbn_smoketest.468163981
Short name T1004
Test name
Test status
Simulation time 6202040048 ps
CPU time 1141.31 seconds
Started Jul 14 08:15:36 PM PDT 24
Finished Jul 14 08:34:38 PM PDT 24
Peak memory 609480 kb
Host smart-06ebe3b7-1a74-4f30-8a05-a8e5f2566de5
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468163981 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.chip_sw_otbn_smoketest.468163981
Directory /workspace/2.chip_sw_otbn_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.4135758035
Short name T910
Test name
Test status
Simulation time 3601846735 ps
CPU time 246.63 seconds
Started Jul 14 08:10:06 PM PDT 24
Finished Jul 14 08:14:13 PM PDT 24
Peak memory 609644 kb
Host smart-d1b4ff32-0b24-4a4f-8017-cace079c95d0
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135758035 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.4135758035
Directory /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1353458007
Short name T989
Test name
Test status
Simulation time 7389167930 ps
CPU time 1099.45 seconds
Started Jul 14 08:07:33 PM PDT 24
Finished Jul 14 08:25:53 PM PDT 24
Peak memory 609940 kb
Host smart-bb93d361-487d-4b85-bf7a-42240fe68de6
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1353458007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.1353458007
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2075649295
Short name T457
Test name
Test status
Simulation time 7371135340 ps
CPU time 1139.83 seconds
Started Jul 14 08:12:35 PM PDT 24
Finished Jul 14 08:31:35 PM PDT 24
Peak memory 609980 kb
Host smart-d559321f-4d51-4c21-bf08-646422e6a5cd
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2075649295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.2075649295
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1348409940
Short name T950
Test name
Test status
Simulation time 8540059896 ps
CPU time 1155.41 seconds
Started Jul 14 08:13:25 PM PDT 24
Finished Jul 14 08:32:41 PM PDT 24
Peak memory 609972 kb
Host smart-9a001260-c91e-4f2b-94f8-9a9c882ca605
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes
t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1348409940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.1348409940
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3339506171
Short name T1224
Test name
Test status
Simulation time 4335915080 ps
CPU time 772.68 seconds
Started Jul 14 08:07:41 PM PDT 24
Finished Jul 14 08:20:34 PM PDT 24
Peak memory 609364 kb
Host smart-61ca8d0f-efaa-4b96-9ab0-3173e0a44012
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new
_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s
im.tcl +ntb_random_seed=3339506171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3339506171
Directory /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.4205482244
Short name T1017
Test name
Test status
Simulation time 3022799480 ps
CPU time 261.66 seconds
Started Jul 14 08:15:55 PM PDT 24
Finished Jul 14 08:20:17 PM PDT 24
Peak memory 607996 kb
Host smart-6af7732a-d93f-42da-8417-d6ccb7ac6971
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205482244 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_otp_ctrl_smoketest.4205482244
Directory /workspace/2.chip_sw_otp_ctrl_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_pattgen_ios.407794410
Short name T5
Test name
Test status
Simulation time 2768358948 ps
CPU time 203.3 seconds
Started Jul 14 08:07:35 PM PDT 24
Finished Jul 14 08:10:59 PM PDT 24
Peak memory 609716 kb
Host smart-6a709fd2-d363-4135-848a-d879f0f8667c
User root
Command /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407794410 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.407794410
Directory /workspace/2.chip_sw_pattgen_ios/latest

Test location /workspace/coverage/default/2.chip_sw_plic_sw_irq.3114639039
Short name T252
Test name
Test status
Simulation time 3258563982 ps
CPU time 286.16 seconds
Started Jul 14 08:14:12 PM PDT 24
Finished Jul 14 08:18:59 PM PDT 24
Peak memory 609188 kb
Host smart-5631b8e3-ef3c-4f08-8725-55bed303c34f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114639039 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.chip_sw_plic_sw_irq.3114639039
Directory /workspace/2.chip_sw_plic_sw_irq/latest

Test location /workspace/coverage/default/2.chip_sw_power_idle_load.2461515166
Short name T702
Test name
Test status
Simulation time 4643126444 ps
CPU time 635.53 seconds
Started Jul 14 08:16:28 PM PDT 24
Finished Jul 14 08:27:04 PM PDT 24
Peak memory 608740 kb
Host smart-9c96afc5-41f4-455e-ae63-f52ac58d25a7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461515166 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.2461515166
Directory /workspace/2.chip_sw_power_idle_load/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.369352945
Short name T1297
Test name
Test status
Simulation time 9196410796 ps
CPU time 1336.97 seconds
Started Jul 14 08:08:33 PM PDT 24
Finished Jul 14 08:30:50 PM PDT 24
Peak memory 610412 kb
Host smart-7bd60f0e-b746-4814-9dd4-6c82b09bf46d
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693
52945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.369352945
Directory /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1579186381
Short name T894
Test name
Test status
Simulation time 33126251460 ps
CPU time 2582.02 seconds
Started Jul 14 08:11:28 PM PDT 24
Finished Jul 14 08:54:30 PM PDT 24
Peak memory 609868 kb
Host smart-de487ca5-48b1-4719-b1d6-a8dbd4bb6ad1
User root
Command /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157
9186381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.1579186381
Directory /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2794532477
Short name T675
Test name
Test status
Simulation time 17633580236 ps
CPU time 1799.77 seconds
Started Jul 14 08:10:16 PM PDT 24
Finished Jul 14 08:40:18 PM PDT 24
Peak memory 610672 kb
Host smart-8912409f-fbb7-4722-8224-a20809764e4e
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2794532477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2794532477
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2826310024
Short name T414
Test name
Test status
Simulation time 25435520292 ps
CPU time 1691.86 seconds
Started Jul 14 08:18:34 PM PDT 24
Finished Jul 14 08:46:46 PM PDT 24
Peak memory 610016 kb
Host smart-b13b6f5f-c21a-4900-8835-44969017dfb1
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2826310024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2826310024
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1565671669
Short name T1315
Test name
Test status
Simulation time 7507128460 ps
CPU time 958.4 seconds
Started Jul 14 08:08:49 PM PDT 24
Finished Jul 14 08:24:48 PM PDT 24
Peak memory 610108 kb
Host smart-eeab22fa-8bf6-45af-b8de-22ecd6621ebf
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565671669 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.1565671669
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.964994571
Short name T1147
Test name
Test status
Simulation time 8233368582 ps
CPU time 558.73 seconds
Started Jul 14 08:10:26 PM PDT 24
Finished Jul 14 08:19:46 PM PDT 24
Peak memory 615808 kb
Host smart-e9a5a05b-6a2a-4eca-b7dd-34a9603ef1ee
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=964994571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.964994571
Directory /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1053499814
Short name T141
Test name
Test status
Simulation time 7689491416 ps
CPU time 549.49 seconds
Started Jul 14 08:08:48 PM PDT 24
Finished Jul 14 08:17:59 PM PDT 24
Peak memory 609928 kb
Host smart-90113bc2-7275-40d2-acce-f692fe500f3f
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053499814 -assert nopostproc +UVM_TESTNAME=c
hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.1053499814
Directory /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3546606228
Short name T925
Test name
Test status
Simulation time 4980664618 ps
CPU time 409.67 seconds
Started Jul 14 08:11:15 PM PDT 24
Finished Jul 14 08:18:06 PM PDT 24
Peak memory 615792 kb
Host smart-a58ff5a3-0cdd-43a5-b8ae-a86ce52d6f9a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3546606228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.3546606228
Directory /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3713927709
Short name T1198
Test name
Test status
Simulation time 11435680487 ps
CPU time 1343.87 seconds
Started Jul 14 08:09:39 PM PDT 24
Finished Jul 14 08:32:04 PM PDT 24
Peak memory 610648 kb
Host smart-213506e3-1a30-4217-b8e1-2383f8d02fba
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713927709 -assert nop
ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3713927709
Directory /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2543165446
Short name T413
Test name
Test status
Simulation time 7510336500 ps
CPU time 405 seconds
Started Jul 14 08:13:51 PM PDT 24
Finished Jul 14 08:20:37 PM PDT 24
Peak memory 609872 kb
Host smart-9dfb3d91-2ab3-48d3-8014-9a82f01d61f8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543165446 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2543165446
Directory /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1229307146
Short name T1057
Test name
Test status
Simulation time 7491448930 ps
CPU time 715.13 seconds
Started Jul 14 08:09:59 PM PDT 24
Finished Jul 14 08:21:56 PM PDT 24
Peak memory 610092 kb
Host smart-f13cc8ee-404a-4ed0-8618-e84f2405a363
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229307146 -assert nopostpr
oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.1229307146
Directory /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.128034933
Short name T1061
Test name
Test status
Simulation time 18275168312 ps
CPU time 1829.87 seconds
Started Jul 14 08:09:52 PM PDT 24
Finished Jul 14 08:40:23 PM PDT 24
Peak memory 610656 kb
Host smart-1612563c-8805-41d7-ab6e-2b7475f4c9c2
User root
Command /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom
:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=128034933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.128034933
Directory /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.815006269
Short name T2
Test name
Test status
Simulation time 24890615696 ps
CPU time 1956.13 seconds
Started Jul 14 08:15:15 PM PDT 24
Finished Jul 14 08:47:52 PM PDT 24
Peak memory 610244 kb
Host smart-d9ff8afd-31ca-49f3-ab42-47c422236a97
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=815006269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.815006269
Directory /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2070561009
Short name T1170
Test name
Test status
Simulation time 40682397870 ps
CPU time 3817.43 seconds
Started Jul 14 08:10:09 PM PDT 24
Finished Jul 14 09:13:48 PM PDT 24
Peak memory 611220 kb
Host smart-e1024c62-f7f0-44ec-9148-94d91cdbc9bb
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power
_glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070561009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit
ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s
leep_power_glitch_reset.2070561009
Directory /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3000135068
Short name T391
Test name
Test status
Simulation time 5732071908 ps
CPU time 573.18 seconds
Started Jul 14 08:13:29 PM PDT 24
Finished Jul 14 08:23:03 PM PDT 24
Peak memory 610160 kb
Host smart-4acd3e34-44e6-4aa1-b4f3-91add9a1cc67
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul
es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3000135068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s
leep_wake_up.3000135068
Directory /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.374744957
Short name T692
Test name
Test status
Simulation time 3250131598 ps
CPU time 361.32 seconds
Started Jul 14 08:13:16 PM PDT 24
Finished Jul 14 08:19:18 PM PDT 24
Peak memory 608012 kb
Host smart-c74491bf-a098-4000-afd3-005d13a0254a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374744957 -assert nopostproc +UVM_T
ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.374744957
Directory /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.4249876712
Short name T960
Test name
Test status
Simulation time 4928422478 ps
CPU time 408.54 seconds
Started Jul 14 08:09:47 PM PDT 24
Finished Jul 14 08:16:36 PM PDT 24
Peak memory 616668 kb
Host smart-074a26f1-77ff-4b6a-89eb-a4222f7b0583
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s
eed=4249876712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.4249876712
Directory /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2175279678
Short name T128
Test name
Test status
Simulation time 5051796492 ps
CPU time 481.35 seconds
Started Jul 14 08:12:12 PM PDT 24
Finished Jul 14 08:20:13 PM PDT 24
Peak memory 608684 kb
Host smart-29d382fb-4aa1-42c2-a401-58a37f270cb2
User root
Command /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21752796
78 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2175279678
Directory /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.15827167
Short name T924
Test name
Test status
Simulation time 6912432708 ps
CPU time 600.41 seconds
Started Jul 14 08:12:55 PM PDT 24
Finished Jul 14 08:22:57 PM PDT 24
Peak memory 610168 kb
Host smart-7f2b9bc7-ab66-4d3c-9f79-1746bfe2114b
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r
om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=15827167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.15827167
Directory /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1950332738
Short name T1075
Test name
Test status
Simulation time 5213173210 ps
CPU time 473.81 seconds
Started Jul 14 08:14:21 PM PDT 24
Finished Jul 14 08:22:15 PM PDT 24
Peak memory 609500 kb
Host smart-409e0225-aca6-4854-bc87-7382c3d02cdb
User root
Command /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950332738 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.1950332738
Directory /workspace/2.chip_sw_pwrmgr_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1380887089
Short name T1043
Test name
Test status
Simulation time 8566729504 ps
CPU time 1374.79 seconds
Started Jul 14 08:08:20 PM PDT 24
Finished Jul 14 08:31:18 PM PDT 24
Peak memory 610144 kb
Host smart-e3ac2b7f-bcde-4fd0-a0b8-115688a6a679
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380887089 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.1380887089
Directory /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.4037811444
Short name T975
Test name
Test status
Simulation time 5096590774 ps
CPU time 464.09 seconds
Started Jul 14 08:08:58 PM PDT 24
Finished Jul 14 08:16:43 PM PDT 24
Peak memory 609704 kb
Host smart-669e1e64-a26b-44cf-8920-8e2e8809633a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037811444 -assert no
postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.4037811444
Directory /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1331128508
Short name T980
Test name
Test status
Simulation time 5751030696 ps
CPU time 331.57 seconds
Started Jul 14 08:17:20 PM PDT 24
Finished Jul 14 08:22:52 PM PDT 24
Peak memory 609728 kb
Host smart-4f7ffdac-99a3-4ec3-9601-297e3ce0dfc4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331128508 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.1331128508
Directory /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1184065326
Short name T436
Test name
Test status
Simulation time 5100664744 ps
CPU time 672.21 seconds
Started Jul 14 08:10:10 PM PDT 24
Finished Jul 14 08:21:22 PM PDT 24
Peak memory 609940 kb
Host smart-9fd09169-28bd-42c3-9275-2788744f3fb1
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118
4065326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.1184065326
Directory /workspace/2.chip_sw_pwrmgr_wdog_reset/latest

Test location /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2562065216
Short name T1115
Test name
Test status
Simulation time 9060567772 ps
CPU time 664.27 seconds
Started Jul 14 08:11:45 PM PDT 24
Finished Jul 14 08:22:50 PM PDT 24
Peak memory 624204 kb
Host smart-795d4f9b-05c0-4b2f-9817-c58701f9f56c
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562065216 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.2562065216
Directory /workspace/2.chip_sw_rom_ctrl_integrity_check/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1246224092
Short name T240
Test name
Test status
Simulation time 5046302290 ps
CPU time 842.46 seconds
Started Jul 14 08:09:09 PM PDT 24
Finished Jul 14 08:23:13 PM PDT 24
Peak memory 609864 kb
Host smart-8cc6f65d-0a52-4f95-b354-2a53e6c24dc8
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246224092 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.1246224092
Directory /workspace/2.chip_sw_rstmgr_cpu_info/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1799826088
Short name T734
Test name
Test status
Simulation time 5464991000 ps
CPU time 568.67 seconds
Started Jul 14 08:06:29 PM PDT 24
Finished Jul 14 08:16:00 PM PDT 24
Peak memory 640632 kb
Host smart-7a73bdef-b44f-41de-b6e2-c19af6db8b44
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1799826088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.1799826088
Directory /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.236577396
Short name T1155
Test name
Test status
Simulation time 3556160548 ps
CPU time 314.79 seconds
Started Jul 14 08:14:13 PM PDT 24
Finished Jul 14 08:19:28 PM PDT 24
Peak memory 609040 kb
Host smart-d8879313-50f8-4abb-8c6f-13053ff94a53
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236577396 -assert nopostproc +UVM_TESTNAME=ch
ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.chip_sw_rstmgr_smoketest.236577396
Directory /workspace/2.chip_sw_rstmgr_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.875776971
Short name T1278
Test name
Test status
Simulation time 3102138540 ps
CPU time 368.44 seconds
Started Jul 14 08:09:04 PM PDT 24
Finished Jul 14 08:15:13 PM PDT 24
Peak memory 608120 kb
Host smart-89df4ab5-d9fd-4349-89f1-1a60cc40bcf4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875776971 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_rstmgr_sw_req.875776971
Directory /workspace/2.chip_sw_rstmgr_sw_req/latest

Test location /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.4021983485
Short name T1154
Test name
Test status
Simulation time 3185676536 ps
CPU time 312.77 seconds
Started Jul 14 08:08:08 PM PDT 24
Finished Jul 14 08:13:22 PM PDT 24
Peak memory 609300 kb
Host smart-f9f8b15d-4621-4f4d-8c9d-4b9e675ce291
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021983485 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.4021983485
Directory /workspace/2.chip_sw_rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2959650804
Short name T300
Test name
Test status
Simulation time 2692410296 ps
CPU time 250.96 seconds
Started Jul 14 08:13:05 PM PDT 24
Finished Jul 14 08:17:16 PM PDT 24
Peak memory 608680 kb
Host smart-ce50fe71-ec46-44e2-a914-2b23b7438d55
User root
Command /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2959650804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.2959650804
Directory /workspace/2.chip_sw_rv_core_ibex_address_translation/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3543783002
Short name T301
Test name
Test status
Simulation time 2867949557 ps
CPU time 299.4 seconds
Started Jul 14 08:15:11 PM PDT 24
Finished Jul 14 08:20:11 PM PDT 24
Peak memory 609264 kb
Host smart-b8e9d628-55bf-4a87-a3a5-a3ab4ff12667
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543783002 -assert nopostp
roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.3543783002
Directory /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2361486430
Short name T107
Test name
Test status
Simulation time 5133565560 ps
CPU time 860.28 seconds
Started Jul 14 08:12:03 PM PDT 24
Finished Jul 14 08:26:25 PM PDT 24
Peak memory 608684 kb
Host smart-5f7a3a33-ad97-4587-b716-62599963c069
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23614
86430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.2361486430
Directory /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest

Test location /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1896313002
Short name T1270
Test name
Test status
Simulation time 5503709410 ps
CPU time 811.04 seconds
Started Jul 14 08:15:51 PM PDT 24
Finished Jul 14 08:29:23 PM PDT 24
Peak memory 608696 kb
Host smart-d911fb68-4e7c-490a-88b5-bda2d14d5b1d
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te
st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1896313002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.1896313002
Directory /workspace/2.chip_sw_rv_core_ibex_rnd/latest

Test location /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2523072885
Short name T186
Test name
Test status
Simulation time 5294180832 ps
CPU time 460 seconds
Started Jul 14 08:12:21 PM PDT 24
Finished Jul 14 08:20:01 PM PDT 24
Peak memory 618624 kb
Host smart-f85c0e77-d011-47bd-93c9-e6b2ec0e42db
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523072885 -asse
rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.2523072885
Directory /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2626433427
Short name T1194
Test name
Test status
Simulation time 3804842368 ps
CPU time 532.1 seconds
Started Jul 14 08:11:59 PM PDT 24
Finished Jul 14 08:20:52 PM PDT 24
Peak memory 619368 kb
Host smart-3b4581e1-359e-4010-b897-4ec50877d1b3
User root
Command /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262643
3427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2626433427
Directory /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1474085523
Short name T919
Test name
Test status
Simulation time 3213656896 ps
CPU time 211.82 seconds
Started Jul 14 08:18:11 PM PDT 24
Finished Jul 14 08:21:43 PM PDT 24
Peak memory 609240 kb
Host smart-ccd9a4c6-cd4e-4842-b855-47587ba7af9a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474085523 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_rv_plic_smoketest.1474085523
Directory /workspace/2.chip_sw_rv_plic_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_rv_timer_irq.678479900
Short name T460
Test name
Test status
Simulation time 2477523320 ps
CPU time 211.39 seconds
Started Jul 14 08:10:21 PM PDT 24
Finished Jul 14 08:13:53 PM PDT 24
Peak memory 607988 kb
Host smart-f144a659-65d0-4295-95c1-d95044f420ed
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678479900 -assert nopostproc +UVM_TESTNAME=
chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.chip_sw_rv_timer_irq.678479900
Directory /workspace/2.chip_sw_rv_timer_irq/latest

Test location /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.2296006967
Short name T977
Test name
Test status
Simulation time 3773991752 ps
CPU time 349.04 seconds
Started Jul 14 08:14:45 PM PDT 24
Finished Jul 14 08:20:35 PM PDT 24
Peak memory 609288 kb
Host smart-3098a915-b9ea-4c7b-bd1a-5d35871f6194
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296006967 -assert nopostproc +UVM_TESTNAME
=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.chip_sw_rv_timer_smoketest.2296006967
Directory /workspace/2.chip_sw_rv_timer_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2075323844
Short name T1092
Test name
Test status
Simulation time 2903974565 ps
CPU time 182.94 seconds
Started Jul 14 08:11:45 PM PDT 24
Finished Jul 14 08:14:49 PM PDT 24
Peak memory 609636 kb
Host smart-f0a6aced-37b7-4be5-a4f4-a03110f73dea
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075323
844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.2075323844
Directory /workspace/2.chip_sw_sensor_ctrl_status/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1079346837
Short name T14
Test name
Test status
Simulation time 4697799220 ps
CPU time 449.29 seconds
Started Jul 14 08:06:21 PM PDT 24
Finished Jul 14 08:13:51 PM PDT 24
Peak memory 608664 kb
Host smart-bfe66a95-e94e-48f6-9d74-4787f8643f0b
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079346837 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.1079346837
Directory /workspace/2.chip_sw_sleep_pin_retention/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3149281143
Short name T11
Test name
Test status
Simulation time 3290756372 ps
CPU time 270.67 seconds
Started Jul 14 08:06:49 PM PDT 24
Finished Jul 14 08:11:20 PM PDT 24
Peak memory 608632 kb
Host smart-53064375-9e16-4bad-aa05-40d6b6b07a76
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149281143
-assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.3149281143
Directory /workspace/2.chip_sw_sleep_pin_wake/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2138337227
Short name T992
Test name
Test status
Simulation time 9090973442 ps
CPU time 1389.14 seconds
Started Jul 14 08:07:49 PM PDT 24
Finished Jul 14 08:30:59 PM PDT 24
Peak memory 610068 kb
Host smart-51dff506-8d77-4be6-b70d-d7fd9908f61d
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138337227 -assert nopostproc +UVM_TESTN
AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.2138337227
Directory /workspace/2.chip_sw_sleep_pwm_pulses/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2057565767
Short name T393
Test name
Test status
Simulation time 8840735756 ps
CPU time 767.1 seconds
Started Jul 14 08:14:50 PM PDT 24
Finished Jul 14 08:27:38 PM PDT 24
Peak memory 610240 kb
Host smart-3b0354da-95ce-47ac-bb8f-6c93379a5020
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057565767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl
eep_sram_ret_contents_no_scramble.2057565767
Directory /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2495702129
Short name T889
Test name
Test status
Simulation time 8565809344 ps
CPU time 1002.83 seconds
Started Jul 14 08:14:03 PM PDT 24
Finished Jul 14 08:30:47 PM PDT 24
Peak memory 610140 kb
Host smart-e85b920e-328b-4635-bbd0-3b1dd27c6640
User root
Command /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495702129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=
chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep
_sram_ret_contents_scramble.2495702129
Directory /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_pass_through.1693675222
Short name T24
Test name
Test status
Simulation time 6965724828 ps
CPU time 840.27 seconds
Started Jul 14 08:10:51 PM PDT 24
Finished Jul 14 08:24:52 PM PDT 24
Peak memory 624280 kb
Host smart-dbd98ac2-7c79-42d8-8a29-7f1ae5e06a15
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693675222 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.1693675222
Directory /workspace/2.chip_sw_spi_device_pass_through/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2672620448
Short name T197
Test name
Test status
Simulation time 4414820395 ps
CPU time 587.85 seconds
Started Jul 14 08:07:05 PM PDT 24
Finished Jul 14 08:16:54 PM PDT 24
Peak memory 624328 kb
Host smart-31a932ca-8deb-46b0-91e2-756cb52551d4
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672620448 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.2672620448
Directory /workspace/2.chip_sw_spi_device_pass_through_collision/latest

Test location /workspace/coverage/default/2.chip_sw_spi_device_tpm.763510239
Short name T51
Test name
Test status
Simulation time 3283661373 ps
CPU time 342.56 seconds
Started Jul 14 08:07:33 PM PDT 24
Finished Jul 14 08:13:16 PM PDT 24
Peak memory 618608 kb
Host smart-a2b925f9-1742-4521-84ec-7b1c0e4f8d29
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763510239 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.763510239
Directory /workspace/2.chip_sw_spi_device_tpm/latest

Test location /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3538881527
Short name T46
Test name
Test status
Simulation time 3206842396 ps
CPU time 325.57 seconds
Started Jul 14 08:07:48 PM PDT 24
Finished Jul 14 08:13:15 PM PDT 24
Peak memory 609760 kb
Host smart-938dbc7c-77dd-4a59-95ab-e0ee00b7982e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538881527 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.3538881527
Directory /workspace/2.chip_sw_spi_host_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1361188411
Short name T178
Test name
Test status
Simulation time 5823246942 ps
CPU time 660.22 seconds
Started Jul 14 08:13:20 PM PDT 24
Finished Jul 14 08:24:21 PM PDT 24
Peak memory 610332 kb
Host smart-06fe6b29-2f96-4cc3-a412-245fbcb11933
User root
Command /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram
_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361188411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr
l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw
_sram_ctrl_scrambled_access.1361188411
Directory /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3480980388
Short name T289
Test name
Test status
Simulation time 4948875869 ps
CPU time 636.89 seconds
Started Jul 14 08:14:59 PM PDT 24
Finished Jul 14 08:25:37 PM PDT 24
Peak memory 609988 kb
Host smart-2c55135e-8dd6-461c-a103-9ae3dbec1bbc
User root
Command /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk
_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480980388 -assert nopostproc +UVM_TESTNA
ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3480980388
Directory /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1442430785
Short name T1030
Test name
Test status
Simulation time 3161100002 ps
CPU time 232.75 seconds
Started Jul 14 08:16:29 PM PDT 24
Finished Jul 14 08:20:22 PM PDT 24
Peak memory 609052 kb
Host smart-a59dc456-fbc5-4b3e-a14c-91ad2b18d222
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442430785 -assert nopostproc +UVM_TESTNAM
E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.1442430785
Directory /workspace/2.chip_sw_sram_ctrl_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.472586700
Short name T1319
Test name
Test status
Simulation time 4793162403 ps
CPU time 695.57 seconds
Started Jul 14 08:09:21 PM PDT 24
Finished Jul 14 08:20:59 PM PDT 24
Peak memory 613052 kb
Host smart-9d4a3a14-81f5-4d67-9ea1-0549b3dba8f9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472586700 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.472586700
Directory /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.4219998196
Short name T206
Test name
Test status
Simulation time 3575825219 ps
CPU time 428.5 seconds
Started Jul 14 08:10:48 PM PDT 24
Finished Jul 14 08:17:58 PM PDT 24
Peak memory 608704 kb
Host smart-a51bc2e6-b023-440f-802c-2a59d83fa6d3
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219998196 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.4219998196
Directory /workspace/2.chip_sw_sysrst_ctrl_outputs/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.557538648
Short name T205
Test name
Test status
Simulation time 22978731296 ps
CPU time 1965.01 seconds
Started Jul 14 08:11:03 PM PDT 24
Finished Jul 14 08:43:49 PM PDT 24
Peak memory 613968 kb
Host smart-afbbccbd-5636-4dcb-a55c-8bde5c577fd8
User root
Command /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55753864
8 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.557538648
Directory /workspace/2.chip_sw_sysrst_ctrl_reset/latest

Test location /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2181936206
Short name T49
Test name
Test status
Simulation time 6134835394 ps
CPU time 549.74 seconds
Started Jul 14 08:16:53 PM PDT 24
Finished Jul 14 08:26:04 PM PDT 24
Peak memory 608824 kb
Host smart-6ccbbfad-d14c-4327-8d5f-0a19a13f4836
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181936206 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2181936206
Directory /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1466573035
Short name T421
Test name
Test status
Simulation time 9302857512 ps
CPU time 1255.56 seconds
Started Jul 14 08:07:25 PM PDT 24
Finished Jul 14 08:28:21 PM PDT 24
Peak memory 618560 kb
Host smart-b853a3e9-ce9b-40a4-b43e-fc7fb7d82a9a
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=1466573035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.1466573035
Directory /workspace/2.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/2.chip_sw_uart_smoketest.519064263
Short name T915
Test name
Test status
Simulation time 3298324620 ps
CPU time 274.52 seconds
Started Jul 14 08:16:29 PM PDT 24
Finished Jul 14 08:21:04 PM PDT 24
Peak memory 615692 kb
Host smart-e5a3fe3d-f14f-4dc5-b52d-9652ba35370e
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519064263 -assert nopostproc +UVM_TESTNAME=chip
_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.chip_sw_uart_smoketest.519064263
Directory /workspace/2.chip_sw_uart_smoketest/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx.1359439132
Short name T1183
Test name
Test status
Simulation time 4124575926 ps
CPU time 659.71 seconds
Started Jul 14 08:06:54 PM PDT 24
Finished Jul 14 08:17:55 PM PDT 24
Peak memory 623156 kb
Host smart-876db495-79bf-42eb-8259-4f51dc857e9a
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359439132 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.1359439132
Directory /workspace/2.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3392016068
Short name T961
Test name
Test status
Simulation time 9172729110 ps
CPU time 1564.04 seconds
Started Jul 14 08:07:29 PM PDT 24
Finished Jul 14 08:33:34 PM PDT 24
Peak memory 622568 kb
Host smart-5e4fb210-8388-4a1f-80cf-2f6998a001f9
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392016068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx
_alt_clk_freq.3392016068
Directory /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3942876863
Short name T443
Test name
Test status
Simulation time 4917151571 ps
CPU time 567.84 seconds
Started Jul 14 08:08:43 PM PDT 24
Finished Jul 14 08:18:12 PM PDT 24
Peak memory 624164 kb
Host smart-4bfb98d0-8fc6-43f7-a33d-e670aa4b487b
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942876863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.3942876863
Directory /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2051955332
Short name T1158
Test name
Test status
Simulation time 77801117604 ps
CPU time 14148.3 seconds
Started Jul 14 08:07:08 PM PDT 24
Finished Jul 15 12:02:59 AM PDT 24
Peak memory 634500 kb
Host smart-8e5cfb53-09dd-40f5-946e-86ce4b147b7d
User root
Command /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test
:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2051955332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.2051955332
Directory /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.126665238
Short name T1052
Test name
Test status
Simulation time 4235170808 ps
CPU time 750.63 seconds
Started Jul 14 08:06:48 PM PDT 24
Finished Jul 14 08:19:19 PM PDT 24
Peak memory 623188 kb
Host smart-f20b1c9d-d4ca-420e-87f5-97e017330064
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126665238 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.126665238
Directory /workspace/2.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3461808238
Short name T1290
Test name
Test status
Simulation time 4195670978 ps
CPU time 725.05 seconds
Started Jul 14 08:07:44 PM PDT 24
Finished Jul 14 08:19:50 PM PDT 24
Peak memory 623224 kb
Host smart-d23a42b9-33d7-4fc4-b98a-bacaa5aae745
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461808238 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.3461808238
Directory /workspace/2.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1577407844
Short name T888
Test name
Test status
Simulation time 4300042116 ps
CPU time 896.76 seconds
Started Jul 14 08:11:05 PM PDT 24
Finished Jul 14 08:26:03 PM PDT 24
Peak memory 622232 kb
Host smart-ca2acc57-7049-414c-9bb8-ed4dae9b8989
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577407844 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.1577407844
Directory /workspace/2.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/2.chip_tap_straps_dev.2954464273
Short name T1123
Test name
Test status
Simulation time 3163524624 ps
CPU time 174.16 seconds
Started Jul 14 08:14:06 PM PDT 24
Finished Jul 14 08:17:00 PM PDT 24
Peak memory 620280 kb
Host smart-4ca74f30-2cb7-42ee-83f7-9c37c26f4b41
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2954464273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.2954464273
Directory /workspace/2.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/2.chip_tap_straps_prod.3480562536
Short name T1251
Test name
Test status
Simulation time 2935772971 ps
CPU time 144.71 seconds
Started Jul 14 08:11:59 PM PDT 24
Finished Jul 14 08:14:24 PM PDT 24
Peak memory 619812 kb
Host smart-4f0ea825-d8af-4ee2-aabf-d1664b85a850
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3480562536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.3480562536
Directory /workspace/2.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_dev.1442961927
Short name T918
Test name
Test status
Simulation time 15394529676 ps
CPU time 3100.97 seconds
Started Jul 14 08:19:11 PM PDT 24
Finished Jul 14 09:10:53 PM PDT 24
Peak memory 609368 kb
Host smart-49c28b48-f25b-48ff-a54f-5cd37160e14c
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442961927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rom_e2e_asm_init_dev.1442961927
Directory /workspace/2.rom_e2e_asm_init_dev/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_prod.1579831148
Short name T1168
Test name
Test status
Simulation time 15466178520 ps
CPU time 3812.27 seconds
Started Jul 14 08:19:31 PM PDT 24
Finished Jul 14 09:23:04 PM PDT 24
Peak memory 609524 kb
Host smart-5c23a8f5-b08e-4224-86ed-f58f848aaced
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579831148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_
SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rom_e2e_asm_init_prod.1579831148
Directory /workspace/2.rom_e2e_asm_init_prod/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3108069593
Short name T963
Test name
Test status
Simulation time 15427828132 ps
CPU time 3595.91 seconds
Started Jul 14 08:18:21 PM PDT 24
Finished Jul 14 09:18:17 PM PDT 24
Peak memory 609544 kb
Host smart-b9fc2bd3-619c-4e4b-96d7-70c4f649b07b
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108069593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_e2e_asm_init_prod_end.3108069593
Directory /workspace/2.rom_e2e_asm_init_prod_end/latest

Test location /workspace/coverage/default/2.rom_e2e_asm_init_rma.3842156743
Short name T909
Test name
Test status
Simulation time 14342980040 ps
CPU time 3634.25 seconds
Started Jul 14 08:17:57 PM PDT 24
Finished Jul 14 09:18:32 PM PDT 24
Peak memory 610868 kb
Host smart-cbe19a22-abd8-4abd-9f45-ebb0d23aca79
User root
Command /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod
_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842156743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S
EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rom_e2e_asm_init_rma.3842156743
Directory /workspace/2.rom_e2e_asm_init_rma/latest

Test location /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1964967778
Short name T1204
Test name
Test status
Simulation time 15013245512 ps
CPU time 3582.35 seconds
Started Jul 14 08:20:31 PM PDT 24
Finished Jul 14 09:20:14 PM PDT 24
Peak memory 609664 kb
Host smart-cdceddc4-4fd6-41f7-9016-16ce75f97da5
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid
_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964967778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip
_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in
it_rom_ext_invalid_meas.1964967778
Directory /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3629903178
Short name T1032
Test name
Test status
Simulation time 14506745966 ps
CPU time 3519.98 seconds
Started Jul 14 08:18:50 PM PDT 24
Finished Jul 14 09:17:31 PM PDT 24
Peak memory 609884 kb
Host smart-299652e8-328f-4345-827f-602f6a20b6d4
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:
new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629903178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.3629903178
Directory /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.922939986
Short name T983
Test name
Test status
Simulation time 14942415840 ps
CPU time 3422.91 seconds
Started Jul 14 08:18:55 PM PDT 24
Finished Jul 14 09:15:59 PM PDT 24
Peak memory 609896 kb
Host smart-90229cd1-2e96-410f-8e8d-aa8ac6d38f85
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas
:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922939986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_
no_meas.922939986
Directory /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3746102224
Short name T53
Test name
Test status
Simulation time 14885591689 ps
CPU time 3172.76 seconds
Started Jul 14 08:18:25 PM PDT 24
Finished Jul 14 09:11:18 PM PDT 24
Peak memory 610448 kb
Host smart-1ec4d73e-0ef4-40a7-b7f8-a1577eed723b
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne
w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746102224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu
tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_
shutdown_exception_c.3746102224
Directory /workspace/2.rom_e2e_shutdown_exception_c/latest

Test location /workspace/coverage/default/2.rom_e2e_shutdown_output.2589299884
Short name T1185
Test name
Test status
Simulation time 28970211953 ps
CPU time 3170.43 seconds
Started Jul 14 08:17:54 PM PDT 24
Finished Jul 14 09:10:46 PM PDT 24
Peak memory 611040 kb
Host smart-d4fb90a6-7f48-45e2-ac83-c42aee489f4a
User root
Command /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f
lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589299884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi
p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rom_e2e_shutdown_output.2589299884
Directory /workspace/2.rom_e2e_shutdown_output/latest

Test location /workspace/coverage/default/2.rom_e2e_smoke.1080290928
Short name T942
Test name
Test status
Simulation time 14821881578 ps
CPU time 3156.78 seconds
Started Jul 14 08:19:46 PM PDT 24
Finished Jul 14 09:12:24 PM PDT 24
Peak memory 609696 kb
Host smart-f6e9020f-c1dd-4fad-8266-c1756ed4da38
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img
_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to
p/hw/dv/tools/sim.tcl +ntb_random_seed=1080290928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.1080290928
Directory /workspace/2.rom_e2e_smoke/latest

Test location /workspace/coverage/default/2.rom_e2e_static_critical.3148160756
Short name T951
Test name
Test status
Simulation time 17612431332 ps
CPU time 3993.02 seconds
Started Jul 14 08:20:45 PM PDT 24
Finished Jul 14 09:27:19 PM PDT 24
Peak memory 609672 kb
Host smart-a7b7883a-ab11-42db-8127-08603e42b09f
User root
Command /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul
es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148160756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.3148160756
Directory /workspace/2.rom_e2e_static_critical/latest

Test location /workspace/coverage/default/2.rom_keymgr_functest.1694840081
Short name T396
Test name
Test status
Simulation time 4429144770 ps
CPU time 388.59 seconds
Started Jul 14 08:16:50 PM PDT 24
Finished Jul 14 08:23:20 PM PDT 24
Peak memory 608880 kb
Host smart-13d282cb-cd67-485a-b690-05d668bb3ad1
User root
Command /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694840081 -ass
ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.1694840081
Directory /workspace/2.rom_keymgr_functest/latest

Test location /workspace/coverage/default/2.rom_raw_unlock.3287241103
Short name T1124
Test name
Test status
Simulation time 6784048296 ps
CPU time 287.81 seconds
Started Jul 14 08:15:04 PM PDT 24
Finished Jul 14 08:19:52 PM PDT 24
Peak memory 623184 kb
Host smart-a8ffd1bd-8468-4179-a38b-b87761ff476d
User root
Command /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE
xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3287241103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.3287241103
Directory /workspace/2.rom_raw_unlock/latest

Test location /workspace/coverage/default/2.rom_volatile_raw_unlock.2316269965
Short name T163
Test name
Test status
Simulation time 2928267051 ps
CPU time 122.96 seconds
Started Jul 14 08:13:52 PM PDT 24
Finished Jul 14 08:15:55 PM PDT 24
Peak memory 615848 kb
Host smart-be69c954-dc57-4e8b-b6f2-1538bd4d1d8a
User root
Command /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1
+sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316269965 -assert nopostproc +UVM_
TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.2316269965
Directory /workspace/2.rom_volatile_raw_unlock/latest

Test location /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3548140036
Short name T766
Test name
Test status
Simulation time 3820995150 ps
CPU time 313.67 seconds
Started Jul 14 08:19:57 PM PDT 24
Finished Jul 14 08:25:11 PM PDT 24
Peak memory 647964 kb
Host smart-8e9bf455-745f-42ca-a3e7-1095d23e719a
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548140036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3548140036
Directory /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/22.chip_sw_all_escalation_resets.1439877195
Short name T801
Test name
Test status
Simulation time 5097291320 ps
CPU time 623.08 seconds
Started Jul 14 08:22:15 PM PDT 24
Finished Jul 14 08:32:39 PM PDT 24
Peak memory 649808 kb
Host smart-ea0354cb-bfb8-4903-b01d-73dee253d2cd
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1439877195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.1439877195
Directory /workspace/22.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1479668051
Short name T752
Test name
Test status
Simulation time 4064095416 ps
CPU time 438.7 seconds
Started Jul 14 08:21:02 PM PDT 24
Finished Jul 14 08:28:21 PM PDT 24
Peak memory 648464 kb
Host smart-84acc17c-32d1-41f3-abd4-b78ea2e823cc
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479668051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1479668051
Directory /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/24.chip_sw_all_escalation_resets.1811687141
Short name T374
Test name
Test status
Simulation time 5745140048 ps
CPU time 690.95 seconds
Started Jul 14 08:20:22 PM PDT 24
Finished Jul 14 08:31:54 PM PDT 24
Peak memory 649644 kb
Host smart-b1e39c73-c596-42fc-961b-e83c1bd77982
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1811687141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.1811687141
Directory /workspace/24.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.688086684
Short name T814
Test name
Test status
Simulation time 4300875364 ps
CPU time 453.17 seconds
Started Jul 14 08:20:10 PM PDT 24
Finished Jul 14 08:27:44 PM PDT 24
Peak memory 648464 kb
Host smart-feee6f3b-3d9a-44cd-90c8-94a35693e778
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688086684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_s
w_alert_handler_lpg_sleep_mode_alerts.688086684
Directory /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.4125844642
Short name T1012
Test name
Test status
Simulation time 3625174968 ps
CPU time 437.22 seconds
Started Jul 14 08:19:51 PM PDT 24
Finished Jul 14 08:27:09 PM PDT 24
Peak memory 648468 kb
Host smart-cfad4203-40a3-4460-a5eb-7c6b403790c8
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125844642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4125844642
Directory /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/28.chip_sw_all_escalation_resets.2589835639
Short name T356
Test name
Test status
Simulation time 4634841460 ps
CPU time 568.17 seconds
Started Jul 14 08:21:22 PM PDT 24
Finished Jul 14 08:30:51 PM PDT 24
Peak memory 649560 kb
Host smart-48da02b5-e008-4b6d-9aa2-d1a76bcd5130
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2589835639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.2589835639
Directory /workspace/28.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1278788096
Short name T958
Test name
Test status
Simulation time 8235962626 ps
CPU time 685.64 seconds
Started Jul 14 08:15:09 PM PDT 24
Finished Jul 14 08:26:36 PM PDT 24
Peak memory 608904 kb
Host smart-9907f4d4-ec26-4104-b179-45065d7d66a7
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1278788096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1278788096
Directory /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.3564447162
Short name T667
Test name
Test status
Simulation time 26281578440 ps
CPU time 5134.99 seconds
Started Jul 14 08:19:54 PM PDT 24
Finished Jul 14 09:45:30 PM PDT 24
Peak memory 609972 kb
Host smart-f2d0fab6-8fed-4068-b563-9170389757c5
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c
oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564447162 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.3564447162
Directory /workspace/3.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/3.chip_sw_data_integrity_escalation.61606963
Short name T276
Test name
Test status
Simulation time 5767276184 ps
CPU time 908.79 seconds
Started Jul 14 08:14:49 PM PDT 24
Finished Jul 14 08:29:58 PM PDT 24
Peak memory 610392 kb
Host smart-75ba994c-d0ee-45d2-833e-2c184053fa31
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=61606963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.61606963
Directory /workspace/3.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.809938044
Short name T78
Test name
Test status
Simulation time 4913157394 ps
CPU time 487.41 seconds
Started Jul 14 08:15:41 PM PDT 24
Finished Jul 14 08:23:49 PM PDT 24
Peak memory 619372 kb
Host smart-77d1c565-e863-4155-81c2-ef799d957e79
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809938044 -assert nopostproc +UVM_TEST
NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.809938044
Directory /workspace/3.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3089931504
Short name T212
Test name
Test status
Simulation time 8563585710 ps
CPU time 1425.25 seconds
Started Jul 14 08:18:53 PM PDT 24
Finished Jul 14 08:42:40 PM PDT 24
Peak memory 618532 kb
Host smart-b492be25-6603-44e9-bfa4-17bfd7f4777e
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3089931504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.3089931504
Directory /workspace/3.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx.3641030935
Short name T1248
Test name
Test status
Simulation time 3717394760 ps
CPU time 589.92 seconds
Started Jul 14 08:15:30 PM PDT 24
Finished Jul 14 08:25:21 PM PDT 24
Peak memory 623140 kb
Host smart-cb5f2de3-eee9-4318-ab81-0db932943938
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641030935 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.3641030935
Directory /workspace/3.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.944118656
Short name T1118
Test name
Test status
Simulation time 4262401065 ps
CPU time 633.6 seconds
Started Jul 14 08:15:21 PM PDT 24
Finished Jul 14 08:25:55 PM PDT 24
Peak memory 622612 kb
Host smart-51ba4d38-b596-4d64-acd8-8dec8309da86
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944118656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba
udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_
alt_clk_freq.944118656
Directory /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2105346691
Short name T213
Test name
Test status
Simulation time 8646060040 ps
CPU time 1404.54 seconds
Started Jul 14 08:15:27 PM PDT 24
Finished Jul 14 08:38:52 PM PDT 24
Peak memory 624132 kb
Host smart-beda8c48-fef6-48ae-b538-918c78704305
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105346691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.2105346691
Directory /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1658679011
Short name T991
Test name
Test status
Simulation time 4464576510 ps
CPU time 669.01 seconds
Started Jul 14 08:16:54 PM PDT 24
Finished Jul 14 08:28:05 PM PDT 24
Peak memory 622188 kb
Host smart-e9cc3cf4-87fa-43aa-8b20-faa117224324
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658679011 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.1658679011
Directory /workspace/3.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.288201424
Short name T1272
Test name
Test status
Simulation time 4491949178 ps
CPU time 553.67 seconds
Started Jul 14 08:16:37 PM PDT 24
Finished Jul 14 08:25:51 PM PDT 24
Peak memory 623496 kb
Host smart-f072bdc9-5c2a-4d4a-b560-01c2e44ba9cd
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288201424 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.288201424
Directory /workspace/3.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3352374154
Short name T1100
Test name
Test status
Simulation time 4230753664 ps
CPU time 567.4 seconds
Started Jul 14 08:15:07 PM PDT 24
Finished Jul 14 08:24:35 PM PDT 24
Peak memory 623196 kb
Host smart-b10f2403-8220-4539-aabd-e8550b726bf8
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352374154 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.3352374154
Directory /workspace/3.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/3.chip_tap_straps_dev.1132884802
Short name T375
Test name
Test status
Simulation time 4175875478 ps
CPU time 368.27 seconds
Started Jul 14 08:18:43 PM PDT 24
Finished Jul 14 08:24:52 PM PDT 24
Peak memory 620388 kb
Host smart-2f4c8407-ad44-4640-ada0-9612d9a66573
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1132884802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.1132884802
Directory /workspace/3.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/3.chip_tap_straps_prod.1689582555
Short name T217
Test name
Test status
Simulation time 3165917113 ps
CPU time 166.47 seconds
Started Jul 14 08:14:53 PM PDT 24
Finished Jul 14 08:17:40 PM PDT 24
Peak memory 620612 kb
Host smart-95b8c420-4977-41d1-8afe-07cac4cbbd92
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1689582555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.1689582555
Directory /workspace/3.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2310079745
Short name T747
Test name
Test status
Simulation time 3359758240 ps
CPU time 440.5 seconds
Started Jul 14 08:20:30 PM PDT 24
Finished Jul 14 08:27:52 PM PDT 24
Peak memory 648132 kb
Host smart-3a0ca777-f83b-4bd3-914c-56513d6a8251
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310079745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2310079745
Directory /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/33.chip_sw_all_escalation_resets.2988984990
Short name T282
Test name
Test status
Simulation time 6278788220 ps
CPU time 649.37 seconds
Started Jul 14 08:20:13 PM PDT 24
Finished Jul 14 08:31:03 PM PDT 24
Peak memory 649672 kb
Host smart-d3bc1332-ccd8-44b9-be64-13774c4e7082
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2988984990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.2988984990
Directory /workspace/33.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3677987633
Short name T807
Test name
Test status
Simulation time 3803258824 ps
CPU time 376.19 seconds
Started Jul 14 08:22:35 PM PDT 24
Finished Jul 14 08:28:52 PM PDT 24
Peak memory 648208 kb
Host smart-f35df8e2-ff6b-42f7-8371-7e0830539ecf
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677987633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3677987633
Directory /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/34.chip_sw_all_escalation_resets.2742475771
Short name T771
Test name
Test status
Simulation time 5679985576 ps
CPU time 820.27 seconds
Started Jul 14 08:21:30 PM PDT 24
Finished Jul 14 08:35:10 PM PDT 24
Peak memory 649604 kb
Host smart-07c5852c-d314-422c-bf60-204cfb2f569b
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2742475771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.2742475771
Directory /workspace/34.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3798805273
Short name T17
Test name
Test status
Simulation time 4144656438 ps
CPU time 416.88 seconds
Started Jul 14 08:22:40 PM PDT 24
Finished Jul 14 08:29:37 PM PDT 24
Peak memory 648496 kb
Host smart-a4c11be9-05d2-40e9-8d6a-73aa6650622e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798805273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3798805273
Directory /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/35.chip_sw_all_escalation_resets.4144835586
Short name T281
Test name
Test status
Simulation time 4722131228 ps
CPU time 623.44 seconds
Started Jul 14 08:22:37 PM PDT 24
Finished Jul 14 08:33:01 PM PDT 24
Peak memory 649608 kb
Host smart-2309c5a6-dc05-43e9-a55c-ebbd1c793141
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4144835586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.4144835586
Directory /workspace/35.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.37735793
Short name T800
Test name
Test status
Simulation time 3834087180 ps
CPU time 372.88 seconds
Started Jul 14 08:20:53 PM PDT 24
Finished Jul 14 08:27:09 PM PDT 24
Peak memory 648468 kb
Host smart-3632a09d-8ac8-44f5-93e0-5c3438090a16
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37735793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_
escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw
_alert_handler_lpg_sleep_mode_alerts.37735793
Directory /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/36.chip_sw_all_escalation_resets.3468747397
Short name T760
Test name
Test status
Simulation time 6342119418 ps
CPU time 778.5 seconds
Started Jul 14 08:21:07 PM PDT 24
Finished Jul 14 08:34:06 PM PDT 24
Peak memory 649308 kb
Host smart-87a5758f-17ad-4785-95eb-3e8726e1319a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3468747397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.3468747397
Directory /workspace/36.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3474616594
Short name T805
Test name
Test status
Simulation time 4086248630 ps
CPU time 487 seconds
Started Jul 14 08:21:36 PM PDT 24
Finished Jul 14 08:29:44 PM PDT 24
Peak memory 648160 kb
Host smart-818e27c7-7c61-4d03-9081-197faf303605
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474616594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3474616594
Directory /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/37.chip_sw_all_escalation_resets.1594844657
Short name T411
Test name
Test status
Simulation time 5293707016 ps
CPU time 721.05 seconds
Started Jul 14 08:20:52 PM PDT 24
Finished Jul 14 08:32:56 PM PDT 24
Peak memory 649668 kb
Host smart-a1a24c89-05f5-444a-97ec-2f97182f543f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1594844657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.1594844657
Directory /workspace/37.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1614131730
Short name T1303
Test name
Test status
Simulation time 4237722564 ps
CPU time 335.32 seconds
Started Jul 14 08:21:45 PM PDT 24
Finished Jul 14 08:27:21 PM PDT 24
Peak memory 648256 kb
Host smart-b6f5057f-2307-4ee6-91db-317c7a7a1222
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614131730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1614131730
Directory /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/39.chip_sw_all_escalation_resets.261354949
Short name T400
Test name
Test status
Simulation time 5614880990 ps
CPU time 639.24 seconds
Started Jul 14 08:22:53 PM PDT 24
Finished Jul 14 08:33:33 PM PDT 24
Peak memory 649572 kb
Host smart-d007eed8-5a3b-413f-a9d1-a79658eb4a4e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
261354949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.261354949
Directory /workspace/39.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1079944910
Short name T730
Test name
Test status
Simulation time 3246730866 ps
CPU time 457.08 seconds
Started Jul 14 08:15:50 PM PDT 24
Finished Jul 14 08:23:28 PM PDT 24
Peak memory 648144 kb
Host smart-ee5f4b4e-bb2c-48cb-afec-3c9d19043af6
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079944910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s
w_alert_handler_lpg_sleep_mode_alerts.1079944910
Directory /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/4.chip_sw_all_escalation_resets.4069097105
Short name T420
Test name
Test status
Simulation time 6257143730 ps
CPU time 801.28 seconds
Started Jul 14 08:16:06 PM PDT 24
Finished Jul 14 08:29:27 PM PDT 24
Peak memory 649568 kb
Host smart-16182b9b-824e-4d7b-b167-3b7c47a5c7c8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4069097105 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.4069097105
Directory /workspace/4.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.157378567
Short name T995
Test name
Test status
Simulation time 6797140980 ps
CPU time 481.08 seconds
Started Jul 14 08:16:17 PM PDT 24
Finished Jul 14 08:24:19 PM PDT 24
Peak memory 608936 kb
Host smart-41bc8a9b-e488-4988-b00b-ade0c6cca342
User root
Command /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=157378567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.157378567
Directory /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2530838630
Short name T1304
Test name
Test status
Simulation time 14597218740 ps
CPU time 3684.43 seconds
Started Jul 14 08:15:43 PM PDT 24
Finished Jul 14 09:17:09 PM PDT 24
Peak memory 610040 kb
Host smart-cc4b98ac-7b66-4906-8084-569f6b245f2a
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c
oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530838630 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.2530838630
Directory /workspace/4.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/4.chip_sw_data_integrity_escalation.1403966753
Short name T290
Test name
Test status
Simulation time 5376964360 ps
CPU time 673.9 seconds
Started Jul 14 08:16:26 PM PDT 24
Finished Jul 14 08:27:40 PM PDT 24
Peak memory 610236 kb
Host smart-3b62642b-e1bc-4be3-b096-f9db265ba322
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro
m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1403966753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.1403966753
Directory /workspace/4.chip_sw_data_integrity_escalation/latest

Test location /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2226977018
Short name T1218
Test name
Test status
Simulation time 8919399939 ps
CPU time 744.31 seconds
Started Jul 14 08:16:17 PM PDT 24
Finished Jul 14 08:28:42 PM PDT 24
Peak memory 622312 kb
Host smart-59e04a13-d871-44c3-a8c8-3e9ee7ff01c9
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226977018 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.2226977018
Directory /workspace/4.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4159406358
Short name T125
Test name
Test status
Simulation time 8268980722 ps
CPU time 817.19 seconds
Started Jul 14 08:17:47 PM PDT 24
Finished Jul 14 08:31:25 PM PDT 24
Peak memory 609188 kb
Host smart-e485788a-d8ed-427b-9f4d-73b2658e4a88
User root
Command /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41594063
58 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.4159406358
Directory /workspace/4.chip_sw_sensor_ctrl_alert/latest

Test location /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.174418201
Short name T1048
Test name
Test status
Simulation time 8283948220 ps
CPU time 1512.77 seconds
Started Jul 14 08:16:33 PM PDT 24
Finished Jul 14 08:41:47 PM PDT 24
Peak memory 618256 kb
Host smart-bbfbff80-f5a7-451b-a725-9c093fc69e7c
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=174418201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.174418201
Directory /workspace/4.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx.1231297086
Short name T216
Test name
Test status
Simulation time 4628385896 ps
CPU time 677.81 seconds
Started Jul 14 08:15:47 PM PDT 24
Finished Jul 14 08:27:05 PM PDT 24
Peak memory 623448 kb
Host smart-d56c2b05-726a-422a-8bcd-607f9c1ddf88
User root
Command /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231297086 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.1231297086
Directory /workspace/4.chip_sw_uart_tx_rx/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3454017398
Short name T1230
Test name
Test status
Simulation time 3951358784 ps
CPU time 492.59 seconds
Started Jul 14 08:17:06 PM PDT 24
Finished Jul 14 08:25:19 PM PDT 24
Peak memory 624144 kb
Host smart-01d8eba3-99cc-45fb-9d69-8001727578d6
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454017398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx
_alt_clk_freq.3454017398
Directory /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1863664854
Short name T930
Test name
Test status
Simulation time 4891637667 ps
CPU time 444.51 seconds
Started Jul 14 08:16:26 PM PDT 24
Finished Jul 14 08:23:51 PM PDT 24
Peak memory 624160 kb
Host smart-c2868131-8dcc-41a0-9fbd-b91c4e810908
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s
w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863664854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b
audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx
_alt_clk_freq_low_speed.1863664854
Directory /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2031734986
Short name T1314
Test name
Test status
Simulation time 3914350880 ps
CPU time 797.45 seconds
Started Jul 14 08:15:59 PM PDT 24
Finished Jul 14 08:29:17 PM PDT 24
Peak memory 621944 kb
Host smart-f4a08d58-7624-4df8-b266-c039c08753d9
User root
Command /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031734986 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.2031734986
Directory /workspace/4.chip_sw_uart_tx_rx_idx1/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1550468502
Short name T1212
Test name
Test status
Simulation time 3855107150 ps
CPU time 738.69 seconds
Started Jul 14 08:16:12 PM PDT 24
Finished Jul 14 08:28:32 PM PDT 24
Peak memory 621908 kb
Host smart-5fbc852c-c676-41a4-8af2-b6730384ae7f
User root
Command /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550468502 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.1550468502
Directory /workspace/4.chip_sw_uart_tx_rx_idx2/latest

Test location /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1510157113
Short name T28
Test name
Test status
Simulation time 3875003904 ps
CPU time 658.56 seconds
Started Jul 14 08:17:10 PM PDT 24
Finished Jul 14 08:28:09 PM PDT 24
Peak memory 623228 kb
Host smart-74d0f243-5ad1-4295-9f85-3e2b13376521
User root
Command /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510157113 -a
ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.1510157113
Directory /workspace/4.chip_sw_uart_tx_rx_idx3/latest

Test location /workspace/coverage/default/4.chip_tap_straps_dev.1786363399
Short name T971
Test name
Test status
Simulation time 4195198095 ps
CPU time 283.71 seconds
Started Jul 14 08:16:24 PM PDT 24
Finished Jul 14 08:21:08 PM PDT 24
Peak memory 621184 kb
Host smart-a8f58ebf-4485-4d30-bebc-d219e4e60377
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:
new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1786363399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.1786363399
Directory /workspace/4.chip_tap_straps_dev/latest

Test location /workspace/coverage/default/4.chip_tap_straps_prod.1139110661
Short name T1042
Test name
Test status
Simulation time 2811880529 ps
CPU time 163.47 seconds
Started Jul 14 08:16:16 PM PDT 24
Finished Jul 14 08:18:59 PM PDT 24
Peak memory 619832 kb
Host smart-342cfca7-be1d-4786-92e5-12dd75c9b989
User root
Command /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom
:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1139110661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.1139110661
Directory /workspace/4.chip_tap_straps_prod/latest

Test location /workspace/coverage/default/4.chip_tap_straps_rma.2365516051
Short name T77
Test name
Test status
Simulation time 6365659390 ps
CPU time 627.91 seconds
Started Jul 14 08:15:41 PM PDT 24
Finished Jul 14 08:26:10 PM PDT 24
Peak memory 620320 kb
Host smart-336c91af-bf12-49a4-ba0e-c0dba07227b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365516051 -as
sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.2365516051
Directory /workspace/4.chip_tap_straps_rma/latest

Test location /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1654397744
Short name T753
Test name
Test status
Simulation time 3310956976 ps
CPU time 312.61 seconds
Started Jul 14 08:20:38 PM PDT 24
Finished Jul 14 08:25:51 PM PDT 24
Peak memory 648512 kb
Host smart-dc0f91d4-6482-4cd6-869f-708a27613ed7
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654397744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1654397744
Directory /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2383305223
Short name T799
Test name
Test status
Simulation time 4315546192 ps
CPU time 338.7 seconds
Started Jul 14 08:21:39 PM PDT 24
Finished Jul 14 08:27:18 PM PDT 24
Peak memory 648768 kb
Host smart-0c64ea3c-16e0-4649-b471-afe335ec18ad
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383305223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2383305223
Directory /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3926677364
Short name T402
Test name
Test status
Simulation time 3679331746 ps
CPU time 366.73 seconds
Started Jul 14 08:24:18 PM PDT 24
Finished Jul 14 08:30:25 PM PDT 24
Peak memory 648260 kb
Host smart-b2f7dbfb-4570-4c8c-938d-2d71da9ff8d6
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926677364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3926677364
Directory /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/42.chip_sw_all_escalation_resets.265232610
Short name T1229
Test name
Test status
Simulation time 5687947366 ps
CPU time 600.07 seconds
Started Jul 14 08:21:37 PM PDT 24
Finished Jul 14 08:31:38 PM PDT 24
Peak memory 649628 kb
Host smart-373e1704-05d9-4c47-8e81-4f08277e4b70
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
265232610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.265232610
Directory /workspace/42.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/43.chip_sw_all_escalation_resets.3477474020
Short name T1014
Test name
Test status
Simulation time 5913366408 ps
CPU time 725.57 seconds
Started Jul 14 08:22:45 PM PDT 24
Finished Jul 14 08:34:51 PM PDT 24
Peak memory 649612 kb
Host smart-dbe37af2-181b-40e4-bb1b-1805bbc3cb46
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3477474020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.3477474020
Directory /workspace/43.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1212316002
Short name T670
Test name
Test status
Simulation time 4318111536 ps
CPU time 316.19 seconds
Started Jul 14 08:21:43 PM PDT 24
Finished Jul 14 08:27:00 PM PDT 24
Peak memory 648544 kb
Host smart-cb8fe5a2-cece-4c3f-8f09-dbfd11744958
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212316002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1212316002
Directory /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/45.chip_sw_all_escalation_resets.3538668523
Short name T795
Test name
Test status
Simulation time 5638312628 ps
CPU time 748.33 seconds
Started Jul 14 08:22:13 PM PDT 24
Finished Jul 14 08:34:42 PM PDT 24
Peak memory 649536 kb
Host smart-07a26140-6682-4bbd-acec-142bbf470aa5
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3538668523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.3538668523
Directory /workspace/45.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2557568317
Short name T245
Test name
Test status
Simulation time 4595375968 ps
CPU time 519.95 seconds
Started Jul 14 08:21:50 PM PDT 24
Finished Jul 14 08:30:30 PM PDT 24
Peak memory 648176 kb
Host smart-c2cee75e-bada-4538-a1d6-5689d43829fd
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557568317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2557568317
Directory /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/47.chip_sw_all_escalation_resets.2430774220
Short name T361
Test name
Test status
Simulation time 5550829716 ps
CPU time 545.22 seconds
Started Jul 14 08:21:41 PM PDT 24
Finished Jul 14 08:30:47 PM PDT 24
Peak memory 649292 kb
Host smart-63c933e3-7bf4-4138-9540-b92e0f12ea9e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2430774220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.2430774220
Directory /workspace/47.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.4055080737
Short name T738
Test name
Test status
Simulation time 4324746598 ps
CPU time 411.25 seconds
Started Jul 14 08:22:19 PM PDT 24
Finished Jul 14 08:29:11 PM PDT 24
Peak memory 648260 kb
Host smart-38d7103a-ba04-491f-b338-acf564e6b60f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055080737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4055080737
Directory /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/49.chip_sw_all_escalation_resets.580368100
Short name T775
Test name
Test status
Simulation time 5575117044 ps
CPU time 654.73 seconds
Started Jul 14 08:25:07 PM PDT 24
Finished Jul 14 08:36:02 PM PDT 24
Peak memory 649864 kb
Host smart-7ea764f2-d5c6-4045-b5fb-a949ceb6418f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
580368100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.580368100
Directory /workspace/49.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3177664125
Short name T110
Test name
Test status
Simulation time 4663809688 ps
CPU time 591.95 seconds
Started Jul 14 08:18:06 PM PDT 24
Finished Jul 14 08:27:58 PM PDT 24
Peak memory 648268 kb
Host smart-75196e80-4dd2-4f83-84df-d41d3e01f42e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177664125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s
w_alert_handler_lpg_sleep_mode_alerts.3177664125
Directory /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/5.chip_sw_all_escalation_resets.579603034
Short name T376
Test name
Test status
Simulation time 6295183880 ps
CPU time 866.18 seconds
Started Jul 14 08:17:03 PM PDT 24
Finished Jul 14 08:31:30 PM PDT 24
Peak memory 649264 kb
Host smart-2513b65a-4f60-4993-b006-f6486ba28564
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
579603034 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.579603034
Directory /workspace/5.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.448876714
Short name T1282
Test name
Test status
Simulation time 25434353648 ps
CPU time 5421.04 seconds
Started Jul 14 08:16:43 PM PDT 24
Finished Jul 14 09:47:05 PM PDT 24
Peak memory 609980 kb
Host smart-326819ff-469c-4450-a6f3-66d0f07805cf
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c
oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448876714 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.448876714
Directory /workspace/5.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1948355083
Short name T965
Test name
Test status
Simulation time 13015009063 ps
CPU time 927.75 seconds
Started Jul 14 08:18:35 PM PDT 24
Finished Jul 14 08:34:03 PM PDT 24
Peak memory 623964 kb
Host smart-eb6100c9-b687-4f9b-bf8b-447b64eee1e7
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948355083 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.1948355083
Directory /workspace/5.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.4059861151
Short name T147
Test name
Test status
Simulation time 12565904460 ps
CPU time 2715.96 seconds
Started Jul 14 08:17:06 PM PDT 24
Finished Jul 14 09:02:22 PM PDT 24
Peak memory 618276 kb
Host smart-4f8e6842-1b71-4471-b7b7-38cdd58d3137
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=4059861151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.4059861151
Directory /workspace/5.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/50.chip_sw_all_escalation_resets.1974308574
Short name T263
Test name
Test status
Simulation time 4408295996 ps
CPU time 646.28 seconds
Started Jul 14 08:22:34 PM PDT 24
Finished Jul 14 08:33:21 PM PDT 24
Peak memory 649576 kb
Host smart-3b8eef93-4f25-4443-9de1-ed75cd47f694
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1974308574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.1974308574
Directory /workspace/50.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.569222867
Short name T816
Test name
Test status
Simulation time 4434679128 ps
CPU time 368.29 seconds
Started Jul 14 08:23:53 PM PDT 24
Finished Jul 14 08:30:02 PM PDT 24
Peak memory 648152 kb
Host smart-33b12af5-ecef-448d-8adf-711c2df4d0d8
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569222867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_s
w_alert_handler_lpg_sleep_mode_alerts.569222867
Directory /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/52.chip_sw_all_escalation_resets.460555894
Short name T786
Test name
Test status
Simulation time 5353423160 ps
CPU time 535.12 seconds
Started Jul 14 08:24:45 PM PDT 24
Finished Jul 14 08:33:40 PM PDT 24
Peak memory 649660 kb
Host smart-02f6d771-567c-44b2-a4b4-c75953599532
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
460555894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.460555894
Directory /workspace/52.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/53.chip_sw_all_escalation_resets.1291066821
Short name T768
Test name
Test status
Simulation time 5271223800 ps
CPU time 545.19 seconds
Started Jul 14 08:23:10 PM PDT 24
Finished Jul 14 08:32:15 PM PDT 24
Peak memory 649848 kb
Host smart-b1eacb89-56b1-4a9f-8eb6-524b483a58cc
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1291066821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.1291066821
Directory /workspace/53.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/54.chip_sw_all_escalation_resets.46886898
Short name T357
Test name
Test status
Simulation time 4865246080 ps
CPU time 654.33 seconds
Started Jul 14 08:22:51 PM PDT 24
Finished Jul 14 08:33:46 PM PDT 24
Peak memory 616260 kb
Host smart-be812599-726c-4909-b2a4-7528d3bb0d9a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
46886898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.46886898
Directory /workspace/54.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1862843195
Short name T792
Test name
Test status
Simulation time 4059531084 ps
CPU time 315.25 seconds
Started Jul 14 08:24:51 PM PDT 24
Finished Jul 14 08:30:07 PM PDT 24
Peak memory 648228 kb
Host smart-67785a2e-b965-4122-9bc8-b86eb4001801
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862843195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1862843195
Directory /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/55.chip_sw_all_escalation_resets.1179832074
Short name T785
Test name
Test status
Simulation time 5346544350 ps
CPU time 642.94 seconds
Started Jul 14 08:26:08 PM PDT 24
Finished Jul 14 08:36:52 PM PDT 24
Peak memory 649560 kb
Host smart-15b848e2-4c3d-40ed-8b6f-fff23847a1f2
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1179832074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.1179832074
Directory /workspace/55.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1491091601
Short name T1276
Test name
Test status
Simulation time 3537272778 ps
CPU time 380.99 seconds
Started Jul 14 08:25:21 PM PDT 24
Finished Jul 14 08:31:42 PM PDT 24
Peak memory 648248 kb
Host smart-8935de93-1944-4206-956d-8aed83811f8c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491091601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1491091601
Directory /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.933392519
Short name T783
Test name
Test status
Simulation time 3798998182 ps
CPU time 441.5 seconds
Started Jul 14 08:25:01 PM PDT 24
Finished Jul 14 08:32:23 PM PDT 24
Peak memory 648024 kb
Host smart-33113e45-b74d-44e9-bd69-4d7ce749f16f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933392519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_s
w_alert_handler_lpg_sleep_mode_alerts.933392519
Directory /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/57.chip_sw_all_escalation_resets.1807917554
Short name T727
Test name
Test status
Simulation time 6654332648 ps
CPU time 679.27 seconds
Started Jul 14 08:23:42 PM PDT 24
Finished Jul 14 08:35:02 PM PDT 24
Peak memory 649512 kb
Host smart-e50bcd92-2e9d-45f2-9761-c0501ea395ab
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1807917554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.1807917554
Directory /workspace/57.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/58.chip_sw_all_escalation_resets.2428356495
Short name T165
Test name
Test status
Simulation time 5609438716 ps
CPU time 514.96 seconds
Started Jul 14 08:25:05 PM PDT 24
Finished Jul 14 08:33:41 PM PDT 24
Peak memory 616204 kb
Host smart-379b4426-a0f4-4d9e-a64f-78a230228938
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2428356495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.2428356495
Directory /workspace/58.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2864198052
Short name T310
Test name
Test status
Simulation time 4182627588 ps
CPU time 501.98 seconds
Started Jul 14 08:18:42 PM PDT 24
Finished Jul 14 08:27:04 PM PDT 24
Peak memory 648396 kb
Host smart-ac93b57b-78f1-4f94-bbf0-7911bc5c002b
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864198052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s
w_alert_handler_lpg_sleep_mode_alerts.2864198052
Directory /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.513943717
Short name T1284
Test name
Test status
Simulation time 20592424548 ps
CPU time 5174.34 seconds
Started Jul 14 08:17:52 PM PDT 24
Finished Jul 14 09:44:07 PM PDT 24
Peak memory 609928 kb
Host smart-2341fac8-50d5-470e-b799-7cab951983ae
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c
oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513943717 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.513943717
Directory /workspace/6.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3530900481
Short name T437
Test name
Test status
Simulation time 6664262907 ps
CPU time 616.91 seconds
Started Jul 14 08:17:23 PM PDT 24
Finished Jul 14 08:27:40 PM PDT 24
Peak memory 619384 kb
Host smart-accbe8b1-955a-4168-bd90-34fe177b64ee
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530900481 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.3530900481
Directory /workspace/6.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3191352274
Short name T901
Test name
Test status
Simulation time 12453314410 ps
CPU time 2486.01 seconds
Started Jul 14 08:17:40 PM PDT 24
Finished Jul 14 08:59:07 PM PDT 24
Peak memory 618240 kb
Host smart-e769e1a0-94cd-4e58-87c7-fe2be9c97b50
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3191352274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.3191352274
Directory /workspace/6.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3031817248
Short name T1267
Test name
Test status
Simulation time 3700446590 ps
CPU time 368.82 seconds
Started Jul 14 08:23:52 PM PDT 24
Finished Jul 14 08:30:02 PM PDT 24
Peak memory 648208 kb
Host smart-dce77745-a435-4b6f-a994-98a4395ac4e6
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031817248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3031817248
Directory /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1109698544
Short name T774
Test name
Test status
Simulation time 4219667000 ps
CPU time 448.55 seconds
Started Jul 14 08:23:17 PM PDT 24
Finished Jul 14 08:30:46 PM PDT 24
Peak memory 648492 kb
Host smart-617002de-f3e5-4f16-a4b1-e0d62b2b3fd5
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109698544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1109698544
Directory /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/61.chip_sw_all_escalation_resets.2697228797
Short name T445
Test name
Test status
Simulation time 5748358650 ps
CPU time 582.91 seconds
Started Jul 14 08:25:14 PM PDT 24
Finished Jul 14 08:34:57 PM PDT 24
Peak memory 649476 kb
Host smart-9999577e-b3e3-4e4d-8f14-12c49d01ce74
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2697228797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.2697228797
Directory /workspace/61.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3085190720
Short name T291
Test name
Test status
Simulation time 3848588910 ps
CPU time 440.33 seconds
Started Jul 14 08:23:12 PM PDT 24
Finished Jul 14 08:30:33 PM PDT 24
Peak memory 648352 kb
Host smart-f6310fd8-78de-49d5-8678-47a22caa3cf9
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085190720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3085190720
Directory /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/63.chip_sw_all_escalation_resets.596355291
Short name T794
Test name
Test status
Simulation time 6372521840 ps
CPU time 705.88 seconds
Started Jul 14 08:25:24 PM PDT 24
Finished Jul 14 08:37:11 PM PDT 24
Peak memory 649544 kb
Host smart-a1d91e00-d891-48bf-a674-bb7c09e8c10a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
596355291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.596355291
Directory /workspace/63.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.4163211263
Short name T802
Test name
Test status
Simulation time 3604365980 ps
CPU time 386.87 seconds
Started Jul 14 08:23:50 PM PDT 24
Finished Jul 14 08:30:18 PM PDT 24
Peak memory 648208 kb
Host smart-71086298-2671-4298-8c0c-fa6cc9e71b27
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163211263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_
sw_alert_handler_lpg_sleep_mode_alerts.4163211263
Directory /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/64.chip_sw_all_escalation_resets.123894123
Short name T392
Test name
Test status
Simulation time 4962294930 ps
CPU time 538.25 seconds
Started Jul 14 08:23:03 PM PDT 24
Finished Jul 14 08:32:03 PM PDT 24
Peak memory 649304 kb
Host smart-d0163ffc-8498-453d-8db1-c1d1e99b44f0
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
123894123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.123894123
Directory /workspace/64.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/65.chip_sw_all_escalation_resets.3507657769
Short name T280
Test name
Test status
Simulation time 4715195640 ps
CPU time 492.19 seconds
Started Jul 14 08:23:04 PM PDT 24
Finished Jul 14 08:31:17 PM PDT 24
Peak memory 616308 kb
Host smart-24f24a34-619c-470a-a4c2-b703cf57d79a
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3507657769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.3507657769
Directory /workspace/65.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3172745969
Short name T764
Test name
Test status
Simulation time 3901194636 ps
CPU time 366.66 seconds
Started Jul 14 08:25:00 PM PDT 24
Finished Jul 14 08:31:07 PM PDT 24
Peak memory 648184 kb
Host smart-3825dc83-403c-4487-a0df-e59ab1356b90
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172745969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3172745969
Directory /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/66.chip_sw_all_escalation_resets.3019372440
Short name T292
Test name
Test status
Simulation time 5018738816 ps
CPU time 626.03 seconds
Started Jul 14 08:24:25 PM PDT 24
Finished Jul 14 08:34:51 PM PDT 24
Peak memory 649524 kb
Host smart-92f43bc4-2513-4dd5-b1e4-933d78e69fc5
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3019372440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.3019372440
Directory /workspace/66.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2398984664
Short name T158
Test name
Test status
Simulation time 3325181344 ps
CPU time 351.4 seconds
Started Jul 14 08:24:48 PM PDT 24
Finished Jul 14 08:30:40 PM PDT 24
Peak memory 648364 kb
Host smart-3b0ed293-1ff2-4bf1-af45-6e3e9d21768f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398984664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2398984664
Directory /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/67.chip_sw_all_escalation_resets.2076508990
Short name T972
Test name
Test status
Simulation time 4267139320 ps
CPU time 703.03 seconds
Started Jul 14 08:23:41 PM PDT 24
Finished Jul 14 08:35:24 PM PDT 24
Peak memory 649376 kb
Host smart-bd91f177-8da9-43fb-b146-89ebb196a6b8
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2076508990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.2076508990
Directory /workspace/67.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.726671868
Short name T711
Test name
Test status
Simulation time 3410857660 ps
CPU time 421.07 seconds
Started Jul 14 08:24:33 PM PDT 24
Finished Jul 14 08:31:35 PM PDT 24
Peak memory 648132 kb
Host smart-7449cd14-a641-4deb-b935-fa7750e7ff30
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726671868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_s
w_alert_handler_lpg_sleep_mode_alerts.726671868
Directory /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.316108117
Short name T70
Test name
Test status
Simulation time 4333638932 ps
CPU time 358.82 seconds
Started Jul 14 08:23:35 PM PDT 24
Finished Jul 14 08:29:34 PM PDT 24
Peak memory 648388 kb
Host smart-a97437cb-f436-4fbf-af30-7d884d32da27
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316108117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_s
w_alert_handler_lpg_sleep_mode_alerts.316108117
Directory /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/69.chip_sw_all_escalation_resets.3562587058
Short name T293
Test name
Test status
Simulation time 4521032084 ps
CPU time 613.36 seconds
Started Jul 14 08:23:24 PM PDT 24
Finished Jul 14 08:33:38 PM PDT 24
Peak memory 649516 kb
Host smart-260dd55c-3c59-4f7d-bbba-302e5f211a63
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3562587058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.3562587058
Directory /workspace/69.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3293346026
Short name T1172
Test name
Test status
Simulation time 3915567430 ps
CPU time 430.52 seconds
Started Jul 14 08:19:03 PM PDT 24
Finished Jul 14 08:26:14 PM PDT 24
Peak memory 648204 kb
Host smart-120e456e-a028-4e5c-8f40-b78bc74d0cac
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293346026 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s
w_alert_handler_lpg_sleep_mode_alerts.3293346026
Directory /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.662045409
Short name T1161
Test name
Test status
Simulation time 9125459280 ps
CPU time 2003.98 seconds
Started Jul 14 08:18:22 PM PDT 24
Finished Jul 14 08:51:46 PM PDT 24
Peak memory 608632 kb
Host smart-612207b3-52b4-4f8a-b007-d23f201dae75
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c
oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662045409 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.662045409
Directory /workspace/7.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2087038375
Short name T1064
Test name
Test status
Simulation time 7135245961 ps
CPU time 724.27 seconds
Started Jul 14 08:19:04 PM PDT 24
Finished Jul 14 08:31:09 PM PDT 24
Peak memory 620684 kb
Host smart-43d82361-75d7-4884-b85e-7adfbb762551
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087038375 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.2087038375
Directory /workspace/7.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3147209759
Short name T1250
Test name
Test status
Simulation time 3459385224 ps
CPU time 516.36 seconds
Started Jul 14 08:17:50 PM PDT 24
Finished Jul 14 08:26:27 PM PDT 24
Peak memory 618048 kb
Host smart-a1b16669-67ae-42cb-9817-79354227ed01
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3147209759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.3147209759
Directory /workspace/7.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3906410883
Short name T1094
Test name
Test status
Simulation time 3576811960 ps
CPU time 444.16 seconds
Started Jul 14 08:26:27 PM PDT 24
Finished Jul 14 08:33:52 PM PDT 24
Peak memory 647972 kb
Host smart-a5273805-784c-49b4-b762-cd5afd9e793d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906410883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3906410883
Directory /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2121662288
Short name T758
Test name
Test status
Simulation time 3556963444 ps
CPU time 308.16 seconds
Started Jul 14 08:24:46 PM PDT 24
Finished Jul 14 08:29:54 PM PDT 24
Peak memory 648088 kb
Host smart-f5a8c6fb-2707-4d45-a0b6-5c69bf49bce4
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121662288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2121662288
Directory /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/71.chip_sw_all_escalation_resets.1550667267
Short name T1255
Test name
Test status
Simulation time 5241659176 ps
CPU time 592.24 seconds
Started Jul 14 08:25:15 PM PDT 24
Finished Jul 14 08:35:08 PM PDT 24
Peak memory 649612 kb
Host smart-ebe76337-5906-410c-b02a-f293ff94eeef
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1550667267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.1550667267
Directory /workspace/71.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3444555698
Short name T722
Test name
Test status
Simulation time 3875300540 ps
CPU time 372.11 seconds
Started Jul 14 08:25:24 PM PDT 24
Finished Jul 14 08:31:37 PM PDT 24
Peak memory 647936 kb
Host smart-d9f9a440-1b61-4acf-89c3-a637387e8ab2
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444555698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3444555698
Directory /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/72.chip_sw_all_escalation_resets.3104058584
Short name T736
Test name
Test status
Simulation time 5847018060 ps
CPU time 612.19 seconds
Started Jul 14 08:24:50 PM PDT 24
Finished Jul 14 08:35:03 PM PDT 24
Peak memory 649536 kb
Host smart-994f92b3-3cd6-4cca-a3a1-a20ecbc1bc84
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3104058584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.3104058584
Directory /workspace/72.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/73.chip_sw_all_escalation_resets.605315899
Short name T1176
Test name
Test status
Simulation time 5544999204 ps
CPU time 630.85 seconds
Started Jul 14 08:25:31 PM PDT 24
Finished Jul 14 08:36:03 PM PDT 24
Peak memory 649600 kb
Host smart-f948efd4-f650-414e-9f2b-ffccceb5d2d4
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
605315899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.605315899
Directory /workspace/73.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2824547357
Short name T1323
Test name
Test status
Simulation time 4332565840 ps
CPU time 414.72 seconds
Started Jul 14 08:25:56 PM PDT 24
Finished Jul 14 08:32:52 PM PDT 24
Peak memory 648288 kb
Host smart-76c8e8e5-f72a-4709-8b64-8b35b103d223
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824547357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2824547357
Directory /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/74.chip_sw_all_escalation_resets.2100313241
Short name T719
Test name
Test status
Simulation time 5670261872 ps
CPU time 537.57 seconds
Started Jul 14 08:25:29 PM PDT 24
Finished Jul 14 08:34:28 PM PDT 24
Peak memory 649516 kb
Host smart-d737d52b-79ff-4ca7-aab9-1ab3ddbc18f6
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2100313241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.2100313241
Directory /workspace/74.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2829032541
Short name T749
Test name
Test status
Simulation time 4079388440 ps
CPU time 291.96 seconds
Started Jul 14 08:25:08 PM PDT 24
Finished Jul 14 08:30:00 PM PDT 24
Peak memory 648124 kb
Host smart-69eaf94d-479a-4b9f-9b2a-1e3fb4669f7d
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829032541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2829032541
Directory /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2184701294
Short name T780
Test name
Test status
Simulation time 3816245604 ps
CPU time 390.97 seconds
Started Jul 14 08:25:23 PM PDT 24
Finished Jul 14 08:31:54 PM PDT 24
Peak memory 647980 kb
Host smart-1a896204-5913-4b1e-9811-05f4552aa05f
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184701294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2184701294
Directory /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.665782036
Short name T763
Test name
Test status
Simulation time 3632502454 ps
CPU time 362.88 seconds
Started Jul 14 08:25:47 PM PDT 24
Finished Jul 14 08:31:51 PM PDT 24
Peak memory 648228 kb
Host smart-e1a34ff7-b042-4994-a20e-433750aa984e
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665782036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_s
w_alert_handler_lpg_sleep_mode_alerts.665782036
Directory /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/78.chip_sw_all_escalation_resets.3374619367
Short name T262
Test name
Test status
Simulation time 4871141630 ps
CPU time 619.42 seconds
Started Jul 14 08:24:59 PM PDT 24
Finished Jul 14 08:35:19 PM PDT 24
Peak memory 650104 kb
Host smart-581d05fc-6021-4045-9333-84dd945c8f1f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3374619367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.3374619367
Directory /workspace/78.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2047687896
Short name T728
Test name
Test status
Simulation time 4474162162 ps
CPU time 325.32 seconds
Started Jul 14 08:27:48 PM PDT 24
Finished Jul 14 08:33:14 PM PDT 24
Peak memory 648496 kb
Host smart-da7529ee-335f-4324-978d-1717b4b32d23
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047687896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2047687896
Directory /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/8.chip_sw_all_escalation_resets.140826652
Short name T762
Test name
Test status
Simulation time 4807505072 ps
CPU time 581.08 seconds
Started Jul 14 08:18:50 PM PDT 24
Finished Jul 14 08:28:32 PM PDT 24
Peak memory 649608 kb
Host smart-e936b971-5dc6-46e2-bbb6-d7c34d18c1c3
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
140826652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.140826652
Directory /workspace/8.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1716550994
Short name T259
Test name
Test status
Simulation time 12819128696 ps
CPU time 2816.11 seconds
Started Jul 14 08:18:53 PM PDT 24
Finished Jul 14 09:05:49 PM PDT 24
Peak memory 609992 kb
Host smart-023d2047-9e76-4627-84b1-f30d3095d84a
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c
oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716550994 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.1716550994
Directory /workspace/8.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2263567447
Short name T171
Test name
Test status
Simulation time 11331059437 ps
CPU time 1094.7 seconds
Started Jul 14 08:17:48 PM PDT 24
Finished Jul 14 08:36:03 PM PDT 24
Peak memory 623132 kb
Host smart-1ebeb77c-c116-4482-a6ce-fe55fef4ae59
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263567447 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.2263567447
Directory /workspace/8.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3262443993
Short name T1078
Test name
Test status
Simulation time 13331813976 ps
CPU time 3028.47 seconds
Started Jul 14 08:17:30 PM PDT 24
Finished Jul 14 09:07:59 PM PDT 24
Peak memory 618516 kb
Host smart-e47781eb-04d5-4ff8-9e2e-86355d469a71
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=3262443993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.3262443993
Directory /workspace/8.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.460438520
Short name T1308
Test name
Test status
Simulation time 3518043680 ps
CPU time 312.43 seconds
Started Jul 14 08:24:36 PM PDT 24
Finished Jul 14 08:29:49 PM PDT 24
Peak memory 648204 kb
Host smart-a2aaa93f-c7d3-4c2e-8a8e-7b981199e579
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460438520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all
_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_s
w_alert_handler_lpg_sleep_mode_alerts.460438520
Directory /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/80.chip_sw_all_escalation_resets.622142631
Short name T1214
Test name
Test status
Simulation time 5798614120 ps
CPU time 626.11 seconds
Started Jul 14 08:24:25 PM PDT 24
Finished Jul 14 08:34:52 PM PDT 24
Peak memory 649548 kb
Host smart-2dc238e0-efd7-433a-a93b-d53a6aa65f49
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
622142631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.622142631
Directory /workspace/80.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/81.chip_sw_all_escalation_resets.53749843
Short name T42
Test name
Test status
Simulation time 5558892712 ps
CPU time 457.67 seconds
Started Jul 14 08:27:11 PM PDT 24
Finished Jul 14 08:34:49 PM PDT 24
Peak memory 649488 kb
Host smart-d5e7854b-42eb-4496-99de-55527c872a77
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
53749843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.53749843
Directory /workspace/81.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1083409890
Short name T981
Test name
Test status
Simulation time 3815622048 ps
CPU time 315.43 seconds
Started Jul 14 08:25:45 PM PDT 24
Finished Jul 14 08:31:01 PM PDT 24
Peak memory 648300 kb
Host smart-cf1c3078-59a0-4ca0-b6c1-a48475f6c146
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083409890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1083409890
Directory /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/82.chip_sw_all_escalation_resets.3730882722
Short name T464
Test name
Test status
Simulation time 4383731632 ps
CPU time 537.38 seconds
Started Jul 14 08:25:42 PM PDT 24
Finished Jul 14 08:34:40 PM PDT 24
Peak memory 649728 kb
Host smart-7182d316-d5b8-4657-91ad-f9c5ebddb58e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3730882722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.3730882722
Directory /workspace/82.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3382178526
Short name T779
Test name
Test status
Simulation time 3461741780 ps
CPU time 350.54 seconds
Started Jul 14 08:25:08 PM PDT 24
Finished Jul 14 08:30:59 PM PDT 24
Peak memory 648336 kb
Host smart-c652ff58-db67-4b49-aa3e-d6e1b29d5d77
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382178526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3382178526
Directory /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/83.chip_sw_all_escalation_resets.3426612925
Short name T394
Test name
Test status
Simulation time 5565177428 ps
CPU time 550.81 seconds
Started Jul 14 08:27:43 PM PDT 24
Finished Jul 14 08:36:54 PM PDT 24
Peak memory 649692 kb
Host smart-5747802f-7f55-4207-a9f5-1562f31e448f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3426612925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.3426612925
Directory /workspace/83.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3500665178
Short name T740
Test name
Test status
Simulation time 3934499824 ps
CPU time 309.45 seconds
Started Jul 14 08:28:09 PM PDT 24
Finished Jul 14 08:33:19 PM PDT 24
Peak memory 647972 kb
Host smart-f83e40e6-e96e-4934-9f65-26a548859482
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500665178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_
sw_alert_handler_lpg_sleep_mode_alerts.3500665178
Directory /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/84.chip_sw_all_escalation_resets.2585848625
Short name T1318
Test name
Test status
Simulation time 6213295130 ps
CPU time 643.3 seconds
Started Jul 14 08:25:31 PM PDT 24
Finished Jul 14 08:36:16 PM PDT 24
Peak memory 649284 kb
Host smart-5980e2c8-4410-4066-b353-a39b22373f8e
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2585848625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.2585848625
Directory /workspace/84.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/85.chip_sw_all_escalation_resets.2533115707
Short name T267
Test name
Test status
Simulation time 4788695648 ps
CPU time 527.43 seconds
Started Jul 14 08:26:40 PM PDT 24
Finished Jul 14 08:35:28 PM PDT 24
Peak memory 649592 kb
Host smart-bff659c2-bd67-4872-a1b1-31571aafd60f
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2533115707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.2533115707
Directory /workspace/85.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/86.chip_sw_all_escalation_resets.2028420052
Short name T769
Test name
Test status
Simulation time 5296836392 ps
CPU time 482.59 seconds
Started Jul 14 08:25:48 PM PDT 24
Finished Jul 14 08:33:51 PM PDT 24
Peak memory 649560 kb
Host smart-522a4e88-0484-41ed-9f91-95987eb366b1
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2028420052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.2028420052
Directory /workspace/86.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1310071824
Short name T434
Test name
Test status
Simulation time 3039159064 ps
CPU time 374.9 seconds
Started Jul 14 08:25:36 PM PDT 24
Finished Jul 14 08:31:52 PM PDT 24
Peak memory 648204 kb
Host smart-0ffa6906-33b1-4575-8619-efc682fb4378
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310071824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1310071824
Directory /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/87.chip_sw_all_escalation_resets.696545129
Short name T360
Test name
Test status
Simulation time 4927999248 ps
CPU time 527.65 seconds
Started Jul 14 08:25:17 PM PDT 24
Finished Jul 14 08:34:05 PM PDT 24
Peak memory 649596 kb
Host smart-d0fe68e6-3010-49e9-bc9d-b83ac6d91798
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
696545129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.696545129
Directory /workspace/87.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1978729097
Short name T811
Test name
Test status
Simulation time 4188321064 ps
CPU time 333.83 seconds
Started Jul 14 08:26:47 PM PDT 24
Finished Jul 14 08:32:22 PM PDT 24
Peak memory 648280 kb
Host smart-f6d61ddd-74b5-4108-85be-e31f8d2e5c9c
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978729097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_
sw_alert_handler_lpg_sleep_mode_alerts.1978729097
Directory /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/88.chip_sw_all_escalation_resets.4200858726
Short name T294
Test name
Test status
Simulation time 5713938824 ps
CPU time 516.28 seconds
Started Jul 14 08:26:27 PM PDT 24
Finished Jul 14 08:35:04 PM PDT 24
Peak memory 649584 kb
Host smart-a1d7335c-04f1-4cc6-884a-dc44f1754c36
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4200858726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.4200858726
Directory /workspace/88.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2261849729
Short name T319
Test name
Test status
Simulation time 3728917288 ps
CPU time 345.89 seconds
Started Jul 14 08:25:51 PM PDT 24
Finished Jul 14 08:31:38 PM PDT 24
Peak memory 648316 kb
Host smart-ed568821-b654-43a6-937d-ed8e415dfdb7
User root
Command /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main
,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h
andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261849729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al
l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_
sw_alert_handler_lpg_sleep_mode_alerts.2261849729
Directory /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location /workspace/coverage/default/89.chip_sw_all_escalation_resets.2361038341
Short name T723
Test name
Test status
Simulation time 4899271464 ps
CPU time 441.53 seconds
Started Jul 14 08:26:48 PM PDT 24
Finished Jul 14 08:34:10 PM PDT 24
Peak memory 649452 kb
Host smart-17933d22-054f-4d60-91cb-e02c4474b7c1
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2361038341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.2361038341
Directory /workspace/89.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/9.chip_sw_all_escalation_resets.3424955760
Short name T817
Test name
Test status
Simulation time 5359136328 ps
CPU time 568.69 seconds
Started Jul 14 08:17:54 PM PDT 24
Finished Jul 14 08:27:23 PM PDT 24
Peak memory 649488 kb
Host smart-5cb1fd4d-4ebb-4876-ba6a-c61cc0e66bfc
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3424955760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.3424955760
Directory /workspace/9.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3886912043
Short name T1324
Test name
Test status
Simulation time 27870791000 ps
CPU time 6098.83 seconds
Started Jul 14 08:20:02 PM PDT 24
Finished Jul 14 10:01:43 PM PDT 24
Peak memory 609984 kb
Host smart-338329c6-e0ad-428a-84d8-d2f6c7c2ea91
User root
Command /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c
oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886912043 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.3886912043
Directory /workspace/9.chip_sw_csrng_edn_concurrency/latest

Test location /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.4223434682
Short name T1220
Test name
Test status
Simulation time 11461451054 ps
CPU time 1044.16 seconds
Started Jul 14 08:20:19 PM PDT 24
Finished Jul 14 08:37:44 PM PDT 24
Peak memory 624148 kb
Host smart-64b5c239-0c9d-4fed-b51a-211aa6b8bd0a
User root
Command /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223434682 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.4223434682
Directory /workspace/9.chip_sw_lc_ctrl_transition/latest

Test location /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2684228142
Short name T27
Test name
Test status
Simulation time 8706544296 ps
CPU time 1281.94 seconds
Started Jul 14 08:17:51 PM PDT 24
Finished Jul 14 08:39:13 PM PDT 24
Peak memory 618192 kb
Host smart-efa9909d-88a7-4ea7-96d4-7518670dce41
User root
Command /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random
_seed=2684228142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.2684228142
Directory /workspace/9.chip_sw_uart_rand_baudrate/latest

Test location /workspace/coverage/default/90.chip_sw_all_escalation_resets.170952242
Short name T735
Test name
Test status
Simulation time 4579651670 ps
CPU time 614.85 seconds
Started Jul 14 08:26:19 PM PDT 24
Finished Jul 14 08:36:34 PM PDT 24
Peak memory 649504 kb
Host smart-0372c63c-a068-48ef-b5b1-f9ebe3a69e51
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
170952242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.170952242
Directory /workspace/90.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/91.chip_sw_all_escalation_resets.1834825562
Short name T365
Test name
Test status
Simulation time 5601907510 ps
CPU time 584.84 seconds
Started Jul 14 08:25:47 PM PDT 24
Finished Jul 14 08:35:33 PM PDT 24
Peak memory 649188 kb
Host smart-1afd8d19-ac1a-42db-804c-9d0d19336eb1
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1834825562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.1834825562
Directory /workspace/91.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/92.chip_sw_all_escalation_resets.609543636
Short name T804
Test name
Test status
Simulation time 5082074376 ps
CPU time 651.73 seconds
Started Jul 14 08:25:41 PM PDT 24
Finished Jul 14 08:36:33 PM PDT 24
Peak memory 649600 kb
Host smart-9306d979-0e08-4f76-b9e7-b39d526113c9
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
609543636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.609543636
Directory /workspace/92.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/93.chip_sw_all_escalation_resets.567037560
Short name T803
Test name
Test status
Simulation time 4583976280 ps
CPU time 430.73 seconds
Started Jul 14 08:25:53 PM PDT 24
Finished Jul 14 08:33:04 PM PDT 24
Peak memory 649628 kb
Host smart-961566d1-00e2-4e46-b5d5-8ca387f7f7f1
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
567037560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.567037560
Directory /workspace/93.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/94.chip_sw_all_escalation_resets.678174286
Short name T776
Test name
Test status
Simulation time 4823933632 ps
CPU time 564.36 seconds
Started Jul 14 08:25:54 PM PDT 24
Finished Jul 14 08:35:19 PM PDT 24
Peak memory 649904 kb
Host smart-78fcb7d3-d137-4dc5-a179-4f102b7cc9b5
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
678174286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.678174286
Directory /workspace/94.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/96.chip_sw_all_escalation_resets.4074112216
Short name T778
Test name
Test status
Simulation time 5460399904 ps
CPU time 848.23 seconds
Started Jul 14 08:26:59 PM PDT 24
Finished Jul 14 08:41:08 PM PDT 24
Peak memory 649320 kb
Host smart-8b739baf-322d-4f9c-8f70-771d0c1a6fcd
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4074112216 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.4074112216
Directory /workspace/96.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/97.chip_sw_all_escalation_resets.1510982782
Short name T341
Test name
Test status
Simulation time 5372645544 ps
CPU time 766.97 seconds
Started Jul 14 08:25:46 PM PDT 24
Finished Jul 14 08:38:34 PM PDT 24
Peak memory 649688 kb
Host smart-226dba44-e0bf-4384-9207-b1e250e10534
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1510982782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.1510982782
Directory /workspace/97.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/default/98.chip_sw_all_escalation_resets.1047477220
Short name T791
Test name
Test status
Simulation time 4500014140 ps
CPU time 515.3 seconds
Started Jul 14 08:26:18 PM PDT 24
Finished Jul 14 08:34:53 PM PDT 24
Peak memory 649532 kb
Host smart-c7068647-d6a4-4a69-b28a-bf10acb64a42
User root
Command /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1047477220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.1047477220
Directory /workspace/98.chip_sw_all_escalation_resets/latest

Test location /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.217865062
Short name T41
Test name
Test status
Simulation time 3845012625 ps
CPU time 204.95 seconds
Started Jul 14 08:19:23 PM PDT 24
Finished Jul 14 08:22:48 PM PDT 24
Peak memory 640284 kb
Host smart-592a8ef6-fb6a-416e-bd51-249c652aaffc
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217865062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n
ull -cm_name 1.chip_padctrl_attributes.217865062
Directory /workspace/1.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1692315846
Short name T190
Test name
Test status
Simulation time 4340450778 ps
CPU time 251.9 seconds
Started Jul 14 08:19:24 PM PDT 24
Finished Jul 14 08:23:36 PM PDT 24
Peak memory 642140 kb
Host smart-ff788ad9-07cd-4ab1-8043-76d010de451c
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692315846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 2.chip_padctrl_attributes.1692315846
Directory /workspace/2.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1164335796
Short name T194
Test name
Test status
Simulation time 4758585585 ps
CPU time 338.36 seconds
Started Jul 14 08:19:24 PM PDT 24
Finished Jul 14 08:25:03 PM PDT 24
Peak memory 648520 kb
Host smart-cdca7ade-9588-408f-9263-97a967c5476e
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164335796 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 3.chip_padctrl_attributes.1164335796
Directory /workspace/3.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1814822430
Short name T191
Test name
Test status
Simulation time 4433036970 ps
CPU time 255.26 seconds
Started Jul 14 08:19:27 PM PDT 24
Finished Jul 14 08:23:43 PM PDT 24
Peak memory 640268 kb
Host smart-c3159e72-e6e4-4920-9965-838d27c91155
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814822430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 4.chip_padctrl_attributes.1814822430
Directory /workspace/4.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.562520973
Short name T195
Test name
Test status
Simulation time 4617881576 ps
CPU time 210.28 seconds
Started Jul 14 08:19:29 PM PDT 24
Finished Jul 14 08:22:59 PM PDT 24
Peak memory 640300 kb
Host smart-a799eec1-6889-4496-9786-679d4cdaad2e
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562520973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n
ull -cm_name 5.chip_padctrl_attributes.562520973
Directory /workspace/5.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.320414827
Short name T188
Test name
Test status
Simulation time 4433394030 ps
CPU time 321.49 seconds
Started Jul 14 08:19:35 PM PDT 24
Finished Jul 14 08:24:57 PM PDT 24
Peak memory 642572 kb
Host smart-9657fa8a-e940-4f87-ad76-27cb42e372f9
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320414827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n
ull -cm_name 6.chip_padctrl_attributes.320414827
Directory /workspace/6.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2556779911
Short name T189
Test name
Test status
Simulation time 3738328250 ps
CPU time 253.94 seconds
Started Jul 14 08:19:50 PM PDT 24
Finished Jul 14 08:24:05 PM PDT 24
Peak memory 640276 kb
Host smart-9d421a8e-0fe9-4cf5-9e6c-1009403204e6
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556779911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 7.chip_padctrl_attributes.2556779911
Directory /workspace/7.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.856632003
Short name T187
Test name
Test status
Simulation time 5169645608 ps
CPU time 250.92 seconds
Started Jul 14 08:19:43 PM PDT 24
Finished Jul 14 08:23:54 PM PDT 24
Peak memory 656716 kb
Host smart-d681ea4d-7238-437b-94ba-e182e4f56879
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856632003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n
ull -cm_name 9.chip_padctrl_attributes.856632003
Directory /workspace/9.chip_padctrl_attributes/latest
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