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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.01 95.41 93.61 95.49 94.41 97.53 99.60


Total test records in report: 2907
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T1017 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.4205482244 Jul 14 08:15:55 PM PDT 24 Jul 14 08:20:17 PM PDT 24 3022799480 ps
T1018 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3207178550 Jul 14 08:00:43 PM PDT 24 Jul 14 08:05:34 PM PDT 24 2992906337 ps
T750 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.4291795167 Jul 14 07:54:21 PM PDT 24 Jul 14 08:03:14 PM PDT 24 5098937182 ps
T757 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3555959040 Jul 14 08:24:51 PM PDT 24 Jul 14 08:31:16 PM PDT 24 3508398792 ps
T1019 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2716954632 Jul 14 08:00:29 PM PDT 24 Jul 14 08:58:01 PM PDT 24 14487899095 ps
T736 /workspace/coverage/default/72.chip_sw_all_escalation_resets.3104058584 Jul 14 08:24:50 PM PDT 24 Jul 14 08:35:03 PM PDT 24 5847018060 ps
T94 /workspace/coverage/default/0.chip_sw_gpio_smoketest.4147074122 Jul 14 07:57:45 PM PDT 24 Jul 14 08:01:44 PM PDT 24 3193396651 ps
T1020 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2082590274 Jul 14 07:56:05 PM PDT 24 Jul 14 08:13:13 PM PDT 24 7229714340 ps
T1021 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2332258032 Jul 14 08:19:48 PM PDT 24 Jul 14 08:28:15 PM PDT 24 4371254902 ps
T129 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1731500071 Jul 14 08:12:35 PM PDT 24 Jul 14 08:23:29 PM PDT 24 6080127620 ps
T50 /workspace/coverage/default/1.chip_sw_spi_device_tpm.443868097 Jul 14 08:01:23 PM PDT 24 Jul 14 08:09:33 PM PDT 24 3508258413 ps
T482 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.179269885 Jul 14 08:02:47 PM PDT 24 Jul 14 09:18:16 PM PDT 24 16804658096 ps
T680 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1100471025 Jul 14 08:08:20 PM PDT 24 Jul 14 08:10:34 PM PDT 24 2737620864 ps
T1022 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2489570868 Jul 14 08:20:22 PM PDT 24 Jul 14 08:57:36 PM PDT 24 12940651086 ps
T370 /workspace/coverage/default/1.chip_sw_aon_timer_irq.605915685 Jul 14 07:59:52 PM PDT 24 Jul 14 08:05:40 PM PDT 24 4173127466 ps
T681 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3302634905 Jul 14 07:54:26 PM PDT 24 Jul 14 07:56:38 PM PDT 24 3442933458 ps
T741 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1045812189 Jul 14 07:59:57 PM PDT 24 Jul 14 08:22:55 PM PDT 24 12690805256 ps
T355 /workspace/coverage/default/1.chip_sw_pattgen_ios.3325041981 Jul 14 08:00:09 PM PDT 24 Jul 14 08:04:47 PM PDT 24 2617020196 ps
T15 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1794718006 Jul 14 07:54:36 PM PDT 24 Jul 14 08:20:13 PM PDT 24 20385929312 ps
T373 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2417455462 Jul 14 07:53:21 PM PDT 24 Jul 14 08:02:24 PM PDT 24 5453987896 ps
T305 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.236585758 Jul 14 08:01:02 PM PDT 24 Jul 14 08:14:12 PM PDT 24 8761157385 ps
T1023 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3439978649 Jul 14 08:01:53 PM PDT 24 Jul 14 08:06:15 PM PDT 24 3360333951 ps
T1024 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.224611372 Jul 14 08:09:12 PM PDT 24 Jul 14 09:10:28 PM PDT 24 15306218572 ps
T815 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3945498949 Jul 14 08:21:29 PM PDT 24 Jul 14 08:25:55 PM PDT 24 4058310400 ps
T1025 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2006111479 Jul 14 07:54:33 PM PDT 24 Jul 14 08:09:14 PM PDT 24 8165805770 ps
T1026 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3830394616 Jul 14 08:01:22 PM PDT 24 Jul 14 08:09:51 PM PDT 24 5375867816 ps
T1027 /workspace/coverage/default/1.chip_sw_hmac_smoketest.2576112307 Jul 14 08:06:18 PM PDT 24 Jul 14 08:14:33 PM PDT 24 3381814912 ps
T1028 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.499852496 Jul 14 08:00:58 PM PDT 24 Jul 14 08:06:28 PM PDT 24 3689536439 ps
T1029 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3962501039 Jul 14 08:12:41 PM PDT 24 Jul 14 08:23:36 PM PDT 24 4515353392 ps
T813 /workspace/coverage/default/21.chip_sw_all_escalation_resets.2250452532 Jul 14 08:19:33 PM PDT 24 Jul 14 08:29:33 PM PDT 24 5946229844 ps
T795 /workspace/coverage/default/45.chip_sw_all_escalation_resets.3538668523 Jul 14 08:22:13 PM PDT 24 Jul 14 08:34:42 PM PDT 24 5638312628 ps
T1030 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1442430785 Jul 14 08:16:29 PM PDT 24 Jul 14 08:20:22 PM PDT 24 3161100002 ps
T800 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.37735793 Jul 14 08:20:53 PM PDT 24 Jul 14 08:27:09 PM PDT 24 3834087180 ps
T742 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3586921334 Jul 14 08:12:13 PM PDT 24 Jul 14 08:34:10 PM PDT 24 12948635320 ps
T1031 /workspace/coverage/default/1.rom_keymgr_functest.1505683194 Jul 14 08:05:19 PM PDT 24 Jul 14 08:15:50 PM PDT 24 4026327368 ps
T76 /workspace/coverage/default/1.chip_tap_straps_rma.141491482 Jul 14 08:03:33 PM PDT 24 Jul 14 08:18:19 PM PDT 24 7068609350 ps
T51 /workspace/coverage/default/2.chip_sw_spi_device_tpm.763510239 Jul 14 08:07:33 PM PDT 24 Jul 14 08:13:16 PM PDT 24 3283661373 ps
T791 /workspace/coverage/default/98.chip_sw_all_escalation_resets.1047477220 Jul 14 08:26:18 PM PDT 24 Jul 14 08:34:53 PM PDT 24 4500014140 ps
T1032 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3629903178 Jul 14 08:18:50 PM PDT 24 Jul 14 09:17:31 PM PDT 24 14506745966 ps
T251 /workspace/coverage/default/0.chip_sw_plic_sw_irq.3517615456 Jul 14 07:55:53 PM PDT 24 Jul 14 08:00:31 PM PDT 24 2952872680 ps
T1033 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3803627718 Jul 14 08:13:48 PM PDT 24 Jul 14 08:26:33 PM PDT 24 4999006536 ps
T1034 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3960644211 Jul 14 08:12:52 PM PDT 24 Jul 14 08:23:40 PM PDT 24 5433317186 ps
T1035 /workspace/coverage/default/2.chip_sw_edn_sw_mode.1004543510 Jul 14 08:10:50 PM PDT 24 Jul 14 08:30:40 PM PDT 24 5672684808 ps
T776 /workspace/coverage/default/94.chip_sw_all_escalation_resets.678174286 Jul 14 08:25:54 PM PDT 24 Jul 14 08:35:19 PM PDT 24 4823933632 ps
T668 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4096624876 Jul 14 07:58:00 PM PDT 24 Jul 14 09:11:22 PM PDT 24 24930841338 ps
T1036 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.2662773254 Jul 14 08:13:09 PM PDT 24 Jul 14 08:29:21 PM PDT 24 6792715200 ps
T1037 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.91959857 Jul 14 07:58:12 PM PDT 24 Jul 14 08:04:43 PM PDT 24 5857198428 ps
T793 /workspace/coverage/default/29.chip_sw_all_escalation_resets.777383361 Jul 14 08:21:28 PM PDT 24 Jul 14 08:29:42 PM PDT 24 5767273308 ps
T205 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.557538648 Jul 14 08:11:03 PM PDT 24 Jul 14 08:43:49 PM PDT 24 22978731296 ps
T1038 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.381660496 Jul 14 08:04:28 PM PDT 24 Jul 14 09:10:53 PM PDT 24 15338637877 ps
T1039 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3982205657 Jul 14 07:51:41 PM PDT 24 Jul 14 08:10:59 PM PDT 24 6437277304 ps
T1040 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.4155140952 Jul 14 07:57:36 PM PDT 24 Jul 14 08:45:20 PM PDT 24 28806404495 ps
T749 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2829032541 Jul 14 08:25:08 PM PDT 24 Jul 14 08:30:00 PM PDT 24 4079388440 ps
T1041 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.892849919 Jul 14 08:15:29 PM PDT 24 Jul 14 08:23:38 PM PDT 24 3937350286 ps
T11 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3149281143 Jul 14 08:06:49 PM PDT 24 Jul 14 08:11:20 PM PDT 24 3290756372 ps
T440 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.28497586 Jul 14 08:10:13 PM PDT 24 Jul 14 08:15:24 PM PDT 24 3246378985 ps
T441 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.4102762882 Jul 14 07:57:57 PM PDT 24 Jul 14 08:02:11 PM PDT 24 2271959440 ps
T442 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2438395104 Jul 14 08:03:06 PM PDT 24 Jul 14 08:13:04 PM PDT 24 5209758894 ps
T443 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3942876863 Jul 14 08:08:43 PM PDT 24 Jul 14 08:18:12 PM PDT 24 4917151571 ps
T444 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1811534253 Jul 14 07:59:06 PM PDT 24 Jul 14 08:11:34 PM PDT 24 4031000140 ps
T445 /workspace/coverage/default/61.chip_sw_all_escalation_resets.2697228797 Jul 14 08:25:14 PM PDT 24 Jul 14 08:34:57 PM PDT 24 5748358650 ps
T104 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3254329122 Jul 14 08:03:22 PM PDT 24 Jul 14 08:26:45 PM PDT 24 25886793584 ps
T52 /workspace/coverage/default/0.chip_sw_spi_device_tpm.1295333769 Jul 14 07:54:57 PM PDT 24 Jul 14 08:01:16 PM PDT 24 3789260733 ps
T446 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3061265583 Jul 14 08:21:11 PM PDT 24 Jul 14 08:33:47 PM PDT 24 4218604596 ps
T1042 /workspace/coverage/default/4.chip_tap_straps_prod.1139110661 Jul 14 08:16:16 PM PDT 24 Jul 14 08:18:59 PM PDT 24 2811880529 ps
T342 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2600896547 Jul 14 08:03:33 PM PDT 24 Jul 14 08:12:14 PM PDT 24 4149298024 ps
T1043 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1380887089 Jul 14 08:08:20 PM PDT 24 Jul 14 08:31:18 PM PDT 24 8566729504 ps
T1044 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1718356197 Jul 14 08:01:07 PM PDT 24 Jul 14 08:10:05 PM PDT 24 4659729168 ps
T1045 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.3445911800 Jul 14 08:01:28 PM PDT 24 Jul 14 08:09:23 PM PDT 24 2596375776 ps
T348 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1984696709 Jul 14 07:55:37 PM PDT 24 Jul 14 08:08:54 PM PDT 24 5266067708 ps
T1046 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2561223677 Jul 14 08:05:34 PM PDT 24 Jul 14 08:09:54 PM PDT 24 2909921384 ps
T691 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.4195026695 Jul 14 07:58:34 PM PDT 24 Jul 14 08:03:11 PM PDT 24 2860646300 ps
T44 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2705751450 Jul 14 07:53:05 PM PDT 24 Jul 14 07:58:33 PM PDT 24 2875465352 ps
T770 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2099219055 Jul 14 08:22:25 PM PDT 24 Jul 14 08:28:31 PM PDT 24 3752351560 ps
T1047 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1715479308 Jul 14 07:54:17 PM PDT 24 Jul 14 08:30:50 PM PDT 24 10676578084 ps
T817 /workspace/coverage/default/9.chip_sw_all_escalation_resets.3424955760 Jul 14 08:17:54 PM PDT 24 Jul 14 08:27:23 PM PDT 24 5359136328 ps
T1048 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.174418201 Jul 14 08:16:33 PM PDT 24 Jul 14 08:41:47 PM PDT 24 8283948220 ps
T1049 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.427348416 Jul 14 07:59:34 PM PDT 24 Jul 14 08:53:24 PM PDT 24 13943754750 ps
T1050 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.264683394 Jul 14 07:58:09 PM PDT 24 Jul 14 08:07:32 PM PDT 24 5682162718 ps
T343 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2125690600 Jul 14 07:55:02 PM PDT 24 Jul 14 08:01:33 PM PDT 24 4191874712 ps
T1051 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.4227032732 Jul 14 08:08:29 PM PDT 24 Jul 14 08:45:38 PM PDT 24 30256358665 ps
T155 /workspace/coverage/default/2.chip_plic_all_irqs_10.3056672218 Jul 14 08:12:39 PM PDT 24 Jul 14 08:21:25 PM PDT 24 3690614556 ps
T1052 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.126665238 Jul 14 08:06:48 PM PDT 24 Jul 14 08:19:19 PM PDT 24 4235170808 ps
T1053 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.544681798 Jul 14 08:18:30 PM PDT 24 Jul 14 09:05:56 PM PDT 24 13686498720 ps
T1054 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1385367478 Jul 14 08:09:12 PM PDT 24 Jul 14 08:26:50 PM PDT 24 9956671070 ps
T1055 /workspace/coverage/default/1.chip_sw_edn_auto_mode.1911698612 Jul 14 08:00:11 PM PDT 24 Jul 14 08:24:01 PM PDT 24 5652047628 ps
T809 /workspace/coverage/default/44.chip_sw_all_escalation_resets.2574849987 Jul 14 08:22:25 PM PDT 24 Jul 14 08:33:00 PM PDT 24 4931195952 ps
T1056 /workspace/coverage/default/2.chip_sw_kmac_idle.2571272028 Jul 14 08:12:28 PM PDT 24 Jul 14 08:18:14 PM PDT 24 2905141836 ps
T1057 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1229307146 Jul 14 08:09:59 PM PDT 24 Jul 14 08:21:56 PM PDT 24 7491448930 ps
T725 /workspace/coverage/default/1.chip_sw_all_escalation_resets.3691220369 Jul 14 07:56:29 PM PDT 24 Jul 14 08:07:02 PM PDT 24 5874393960 ps
T1058 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.99326513 Jul 14 07:58:29 PM PDT 24 Jul 14 08:18:14 PM PDT 24 7147318348 ps
T1059 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3487836869 Jul 14 07:58:42 PM PDT 24 Jul 14 08:10:27 PM PDT 24 3923590140 ps
T156 /workspace/coverage/default/1.chip_plic_all_irqs_10.1992474738 Jul 14 08:01:13 PM PDT 24 Jul 14 08:09:12 PM PDT 24 3507052342 ps
T244 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2371541969 Jul 14 08:03:40 PM PDT 24 Jul 14 08:12:28 PM PDT 24 4647498531 ps
T792 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1862843195 Jul 14 08:24:51 PM PDT 24 Jul 14 08:30:07 PM PDT 24 4059531084 ps
T1060 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2550599213 Jul 14 07:59:15 PM PDT 24 Jul 14 08:49:09 PM PDT 24 33582262345 ps
T665 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1306739964 Jul 14 08:13:01 PM PDT 24 Jul 14 10:18:41 PM PDT 24 36656353238 ps
T1061 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.128034933 Jul 14 08:09:52 PM PDT 24 Jul 14 08:40:23 PM PDT 24 18275168312 ps
T1062 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4024606018 Jul 14 08:04:32 PM PDT 24 Jul 14 09:21:01 PM PDT 24 24527729748 ps
T300 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2959650804 Jul 14 08:13:05 PM PDT 24 Jul 14 08:17:16 PM PDT 24 2692410296 ps
T1063 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1473457321 Jul 14 08:02:35 PM PDT 24 Jul 14 09:13:41 PM PDT 24 15480206756 ps
T806 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2514315172 Jul 14 08:19:48 PM PDT 24 Jul 14 08:26:14 PM PDT 24 3326304090 ps
T201 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.641527929 Jul 14 07:53:45 PM PDT 24 Jul 14 11:13:50 PM PDT 24 64545381774 ps
T1064 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2087038375 Jul 14 08:19:04 PM PDT 24 Jul 14 08:31:09 PM PDT 24 7135245961 ps
T1065 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2088110693 Jul 14 08:04:16 PM PDT 24 Jul 14 08:14:25 PM PDT 24 6739677354 ps
T1066 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3280661297 Jul 14 08:11:45 PM PDT 24 Jul 14 08:16:15 PM PDT 24 2900688456 ps
T9 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.853646589 Jul 14 07:53:09 PM PDT 24 Jul 14 07:58:12 PM PDT 24 3780472058 ps
T430 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1322014183 Jul 14 07:57:50 PM PDT 24 Jul 14 08:03:49 PM PDT 24 2956526040 ps
T431 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.2523576034 Jul 14 07:59:11 PM PDT 24 Jul 14 08:09:16 PM PDT 24 4715663704 ps
T290 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.1403966753 Jul 14 08:16:26 PM PDT 24 Jul 14 08:27:40 PM PDT 24 5376964360 ps
T432 /workspace/coverage/default/2.chip_sw_example_flash.862421485 Jul 14 08:06:44 PM PDT 24 Jul 14 08:10:02 PM PDT 24 2632772278 ps
T433 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2535775706 Jul 14 07:59:42 PM PDT 24 Jul 14 08:18:28 PM PDT 24 7386362600 ps
T434 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1310071824 Jul 14 08:25:36 PM PDT 24 Jul 14 08:31:52 PM PDT 24 3039159064 ps
T435 /workspace/coverage/default/1.chip_sw_kmac_idle.1301304721 Jul 14 08:02:48 PM PDT 24 Jul 14 08:06:42 PM PDT 24 2995614364 ps
T436 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1184065326 Jul 14 08:10:10 PM PDT 24 Jul 14 08:21:22 PM PDT 24 5100664744 ps
T437 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3530900481 Jul 14 08:17:23 PM PDT 24 Jul 14 08:27:40 PM PDT 24 6664262907 ps
T10 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1265734526 Jul 14 07:55:28 PM PDT 24 Jul 14 08:19:50 PM PDT 24 22695612892 ps
T1067 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1891712433 Jul 14 08:13:57 PM PDT 24 Jul 14 08:36:06 PM PDT 24 8727236785 ps
T1068 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.262934316 Jul 14 08:06:26 PM PDT 24 Jul 14 08:10:49 PM PDT 24 3183577864 ps
T411 /workspace/coverage/default/37.chip_sw_all_escalation_resets.1594844657 Jul 14 08:20:52 PM PDT 24 Jul 14 08:32:56 PM PDT 24 5293707016 ps
T708 /workspace/coverage/default/1.rom_raw_unlock.2544000507 Jul 14 08:09:36 PM PDT 24 Jul 14 08:14:40 PM PDT 24 6273570278 ps
T1069 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3945758709 Jul 14 08:03:03 PM PDT 24 Jul 14 08:11:45 PM PDT 24 4847622248 ps
T682 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.358027364 Jul 14 07:53:44 PM PDT 24 Jul 14 07:56:22 PM PDT 24 3387927101 ps
T1070 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2882950717 Jul 14 08:01:40 PM PDT 24 Jul 14 09:14:35 PM PDT 24 15445833298 ps
T354 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.990540555 Jul 14 07:59:37 PM PDT 24 Jul 14 08:12:58 PM PDT 24 5202542350 ps
T1071 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2972805837 Jul 14 07:59:12 PM PDT 24 Jul 14 08:22:27 PM PDT 24 9851006966 ps
T1072 /workspace/coverage/default/2.chip_sw_hmac_multistream.1718231316 Jul 14 08:12:11 PM PDT 24 Jul 14 08:40:54 PM PDT 24 8235524664 ps
T340 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3209680145 Jul 14 07:52:45 PM PDT 24 Jul 14 08:02:07 PM PDT 24 3693380520 ps
T226 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.154747566 Jul 14 07:54:58 PM PDT 24 Jul 14 08:15:12 PM PDT 24 6240225700 ps
T1073 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.4267362356 Jul 14 08:08:17 PM PDT 24 Jul 14 09:06:13 PM PDT 24 14518029212 ps
T1074 /workspace/coverage/default/0.chip_sw_example_flash.1459109118 Jul 14 07:54:24 PM PDT 24 Jul 14 07:59:03 PM PDT 24 3159332116 ps
T734 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1799826088 Jul 14 08:06:29 PM PDT 24 Jul 14 08:16:00 PM PDT 24 5464991000 ps
T1075 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1950332738 Jul 14 08:14:21 PM PDT 24 Jul 14 08:22:15 PM PDT 24 5213173210 ps
T1076 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.4070191696 Jul 14 08:02:14 PM PDT 24 Jul 14 09:03:23 PM PDT 24 14514191944 ps
T1077 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1895275721 Jul 14 07:59:09 PM PDT 24 Jul 14 08:57:38 PM PDT 24 18042426969 ps
T1078 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3262443993 Jul 14 08:17:30 PM PDT 24 Jul 14 09:07:59 PM PDT 24 13331813976 ps
T803 /workspace/coverage/default/93.chip_sw_all_escalation_resets.567037560 Jul 14 08:25:53 PM PDT 24 Jul 14 08:33:04 PM PDT 24 4583976280 ps
T237 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1573310039 Jul 14 08:06:49 PM PDT 24 Jul 14 08:14:42 PM PDT 24 4223409783 ps
T1079 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3771170901 Jul 14 07:57:00 PM PDT 24 Jul 14 09:22:18 PM PDT 24 23284688160 ps
T376 /workspace/coverage/default/5.chip_sw_all_escalation_resets.579603034 Jul 14 08:17:03 PM PDT 24 Jul 14 08:31:30 PM PDT 24 6295183880 ps
T12 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.2823628024 Jul 14 07:55:09 PM PDT 24 Jul 14 07:58:59 PM PDT 24 3365270732 ps
T1080 /workspace/coverage/default/0.chip_sw_kmac_entropy.1357504961 Jul 14 07:55:34 PM PDT 24 Jul 14 07:59:32 PM PDT 24 2897418224 ps
T1081 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.511386548 Jul 14 08:06:00 PM PDT 24 Jul 14 08:09:31 PM PDT 24 2507617708 ps
T66 /workspace/coverage/default/1.chip_sw_alert_test.1683264292 Jul 14 08:00:10 PM PDT 24 Jul 14 08:06:12 PM PDT 24 3572200120 ps
T1082 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3264870180 Jul 14 07:56:36 PM PDT 24 Jul 14 08:03:22 PM PDT 24 3348192776 ps
T1083 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.39612273 Jul 14 08:09:27 PM PDT 24 Jul 14 09:05:54 PM PDT 24 15081369760 ps
T767 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1915861019 Jul 14 08:19:24 PM PDT 24 Jul 14 08:26:28 PM PDT 24 3680261394 ps
T1084 /workspace/coverage/default/2.chip_sw_kmac_app_rom.1562212473 Jul 14 08:12:07 PM PDT 24 Jul 14 08:15:50 PM PDT 24 2722382028 ps
T326 /workspace/coverage/default/0.chip_plic_all_irqs_0.3941327911 Jul 14 07:54:27 PM PDT 24 Jul 14 08:15:33 PM PDT 24 5710116680 ps
T1085 /workspace/coverage/default/0.chip_sw_kmac_app_rom.1180777132 Jul 14 07:55:00 PM PDT 24 Jul 14 07:58:51 PM PDT 24 2479535960 ps
T1086 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.907938845 Jul 14 08:13:02 PM PDT 24 Jul 14 08:41:43 PM PDT 24 8766703270 ps
T802 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.4163211263 Jul 14 08:23:50 PM PDT 24 Jul 14 08:30:18 PM PDT 24 3604365980 ps
T1087 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1219275188 Jul 14 08:00:08 PM PDT 24 Jul 14 08:39:19 PM PDT 24 11701073300 ps
T1088 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.966939607 Jul 14 08:02:55 PM PDT 24 Jul 14 09:03:50 PM PDT 24 14608591608 ps
T1089 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1110679367 Jul 14 08:07:50 PM PDT 24 Jul 14 08:09:45 PM PDT 24 2998323716 ps
T684 /workspace/coverage/default/7.chip_sw_all_escalation_resets.3444119209 Jul 14 08:17:35 PM PDT 24 Jul 14 08:27:18 PM PDT 24 5057170952 ps
T764 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3172745969 Jul 14 08:25:00 PM PDT 24 Jul 14 08:31:07 PM PDT 24 3901194636 ps
T761 /workspace/coverage/default/20.chip_sw_all_escalation_resets.1045683705 Jul 14 08:19:37 PM PDT 24 Jul 14 08:29:11 PM PDT 24 5858342930 ps
T1090 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3362625131 Jul 14 08:12:31 PM PDT 24 Jul 14 08:30:08 PM PDT 24 9235037480 ps
T1091 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.895046365 Jul 14 08:01:31 PM PDT 24 Jul 14 08:20:41 PM PDT 24 5205517132 ps
T1092 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2075323844 Jul 14 08:11:45 PM PDT 24 Jul 14 08:14:49 PM PDT 24 2903974565 ps
T399 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3664996148 Jul 14 08:02:59 PM PDT 24 Jul 14 09:35:37 PM PDT 24 24217770436 ps
T339 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2065079118 Jul 14 07:58:49 PM PDT 24 Jul 14 08:12:08 PM PDT 24 5286523024 ps
T1093 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1454330360 Jul 14 08:00:08 PM PDT 24 Jul 14 08:03:38 PM PDT 24 2432639480 ps
T1094 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3906410883 Jul 14 08:26:27 PM PDT 24 Jul 14 08:33:52 PM PDT 24 3576811960 ps
T732 /workspace/coverage/default/77.chip_sw_all_escalation_resets.1484149302 Jul 14 08:24:48 PM PDT 24 Jul 14 08:35:27 PM PDT 24 5572966280 ps
T238 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3102925166 Jul 14 07:57:54 PM PDT 24 Jul 14 08:04:51 PM PDT 24 4233921512 ps
T1095 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3126834464 Jul 14 07:53:01 PM PDT 24 Jul 14 08:37:53 PM PDT 24 31411226540 ps
T1096 /workspace/coverage/default/2.chip_sw_example_manufacturer.3949018740 Jul 14 08:10:06 PM PDT 24 Jul 14 08:14:17 PM PDT 24 3231987934 ps
T1097 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.103701715 Jul 14 07:52:29 PM PDT 24 Jul 14 08:25:20 PM PDT 24 31194399190 ps
T1098 /workspace/coverage/default/2.chip_sw_kmac_smoketest.3136818936 Jul 14 08:15:48 PM PDT 24 Jul 14 08:21:09 PM PDT 24 2703675196 ps
T1099 /workspace/coverage/default/0.chip_sw_uart_smoketest.1911379833 Jul 14 08:00:50 PM PDT 24 Jul 14 08:06:03 PM PDT 24 2778973754 ps
T82 /workspace/coverage/default/0.chip_sw_usbdev_pullup.2702406842 Jul 14 07:59:14 PM PDT 24 Jul 14 08:04:44 PM PDT 24 3630048704 ps
T1100 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3352374154 Jul 14 08:15:07 PM PDT 24 Jul 14 08:24:35 PM PDT 24 4230753664 ps
T1101 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3649900617 Jul 14 08:18:28 PM PDT 24 Jul 14 08:26:38 PM PDT 24 5891368557 ps
T227 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1279189611 Jul 14 08:02:05 PM PDT 24 Jul 14 08:24:16 PM PDT 24 6056397004 ps
T1102 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1449207173 Jul 14 07:57:54 PM PDT 24 Jul 14 08:04:20 PM PDT 24 3691711768 ps
T1103 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2821950791 Jul 14 07:54:17 PM PDT 24 Jul 14 08:05:40 PM PDT 24 3716527430 ps
T262 /workspace/coverage/default/78.chip_sw_all_escalation_resets.3374619367 Jul 14 08:24:59 PM PDT 24 Jul 14 08:35:19 PM PDT 24 4871141630 ps
T1104 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1217947205 Jul 14 08:18:39 PM PDT 24 Jul 14 08:42:17 PM PDT 24 8055585332 ps
T1105 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.1077899500 Jul 14 08:11:01 PM PDT 24 Jul 14 08:19:11 PM PDT 24 4793101180 ps
T1106 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2490740745 Jul 14 07:53:27 PM PDT 24 Jul 14 08:04:42 PM PDT 24 4416701184 ps
T1107 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1330410625 Jul 14 07:58:56 PM PDT 24 Jul 14 08:12:20 PM PDT 24 9238895916 ps
T1108 /workspace/coverage/default/0.chip_sw_hmac_oneshot.1758099890 Jul 14 07:57:19 PM PDT 24 Jul 14 08:03:08 PM PDT 24 2810613788 ps
T1109 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.56682246 Jul 14 08:10:53 PM PDT 24 Jul 14 11:36:06 PM PDT 24 64802070345 ps
T1110 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1856755168 Jul 14 08:01:09 PM PDT 24 Jul 14 08:25:45 PM PDT 24 8029467190 ps
T1111 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3920221838 Jul 14 08:02:00 PM PDT 24 Jul 14 08:45:43 PM PDT 24 10572544786 ps
T1112 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2815253484 Jul 14 08:10:36 PM PDT 24 Jul 14 08:32:28 PM PDT 24 6788870920 ps
T1113 /workspace/coverage/default/16.chip_sw_all_escalation_resets.1861483224 Jul 14 08:20:10 PM PDT 24 Jul 14 08:31:38 PM PDT 24 5891048504 ps
T1114 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.56669996 Jul 14 08:21:20 PM PDT 24 Jul 14 08:36:40 PM PDT 24 12600342343 ps
T377 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3079171563 Jul 14 08:21:22 PM PDT 24 Jul 14 08:28:22 PM PDT 24 3925561796 ps
T1115 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2562065216 Jul 14 08:11:45 PM PDT 24 Jul 14 08:22:50 PM PDT 24 9060567772 ps
T1116 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2008170447 Jul 14 07:54:45 PM PDT 24 Jul 14 08:14:06 PM PDT 24 5881934132 ps
T1117 /workspace/coverage/default/2.chip_sw_gpio_smoketest.1845599738 Jul 14 08:14:02 PM PDT 24 Jul 14 08:18:27 PM PDT 24 3527893297 ps
T1118 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.944118656 Jul 14 08:15:21 PM PDT 24 Jul 14 08:25:55 PM PDT 24 4262401065 ps
T1119 /workspace/coverage/default/1.chip_sw_example_concurrency.766257199 Jul 14 07:57:36 PM PDT 24 Jul 14 08:02:08 PM PDT 24 2421284860 ps
T1120 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2226550891 Jul 14 07:53:47 PM PDT 24 Jul 14 09:31:05 PM PDT 24 27922710080 ps
T1121 /workspace/coverage/default/0.chip_sw_example_manufacturer.1661289191 Jul 14 07:53:02 PM PDT 24 Jul 14 07:57:02 PM PDT 24 2748717888 ps
T1122 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.2866484583 Jul 14 08:10:16 PM PDT 24 Jul 14 08:14:16 PM PDT 24 3148456673 ps
T1123 /workspace/coverage/default/2.chip_tap_straps_dev.2954464273 Jul 14 08:14:06 PM PDT 24 Jul 14 08:17:00 PM PDT 24 3163524624 ps
T277 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.193514425 Jul 14 07:54:47 PM PDT 24 Jul 14 08:09:43 PM PDT 24 5834821842 ps
T1124 /workspace/coverage/default/2.rom_raw_unlock.3287241103 Jul 14 08:15:04 PM PDT 24 Jul 14 08:19:52 PM PDT 24 6784048296 ps
T1125 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1437280541 Jul 14 08:01:43 PM PDT 24 Jul 14 08:12:32 PM PDT 24 4608474868 ps
T1126 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.402717455 Jul 14 07:59:15 PM PDT 24 Jul 14 08:35:37 PM PDT 24 12705363922 ps
T1127 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2405539746 Jul 14 07:56:00 PM PDT 24 Jul 14 08:01:55 PM PDT 24 4837315208 ps
T692 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.374744957 Jul 14 08:13:16 PM PDT 24 Jul 14 08:19:18 PM PDT 24 3250131598 ps
T83 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2040179502 Jul 14 07:54:45 PM PDT 24 Jul 14 09:49:06 PM PDT 24 31739946542 ps
T1128 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.4180822947 Jul 14 07:57:57 PM PDT 24 Jul 14 11:36:46 PM PDT 24 77721156218 ps
T1129 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.423890106 Jul 14 08:01:11 PM PDT 24 Jul 14 08:58:35 PM PDT 24 14338345418 ps
T252 /workspace/coverage/default/2.chip_sw_plic_sw_irq.3114639039 Jul 14 08:14:12 PM PDT 24 Jul 14 08:18:59 PM PDT 24 3258563982 ps
T1130 /workspace/coverage/default/1.chip_sw_kmac_smoketest.2732801275 Jul 14 08:04:43 PM PDT 24 Jul 14 08:09:07 PM PDT 24 3234135848 ps
T1131 /workspace/coverage/default/0.chip_sw_aes_smoketest.3953429010 Jul 14 07:57:32 PM PDT 24 Jul 14 08:02:19 PM PDT 24 3127370400 ps
T1132 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1759666730 Jul 14 07:57:06 PM PDT 24 Jul 14 08:18:20 PM PDT 24 5770095617 ps
T278 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.17921366 Jul 14 07:58:14 PM PDT 24 Jul 14 08:11:40 PM PDT 24 6907555524 ps
T1133 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.442799867 Jul 14 08:09:24 PM PDT 24 Jul 14 09:25:59 PM PDT 24 42668123800 ps
T812 /workspace/coverage/default/19.chip_sw_all_escalation_resets.3302614772 Jul 14 08:20:11 PM PDT 24 Jul 14 08:30:53 PM PDT 24 4909065596 ps
T37 /workspace/coverage/default/1.chip_sw_gpio.2752542309 Jul 14 07:57:56 PM PDT 24 Jul 14 08:04:28 PM PDT 24 3674575664 ps
T367 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.6936985 Jul 14 07:52:38 PM PDT 24 Jul 14 07:58:58 PM PDT 24 18514510486 ps
T1134 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1902722397 Jul 14 08:12:03 PM PDT 24 Jul 14 08:23:26 PM PDT 24 4228497168 ps
T49 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2181936206 Jul 14 08:16:53 PM PDT 24 Jul 14 08:26:04 PM PDT 24 6134835394 ps
T1135 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2183081999 Jul 14 08:02:39 PM PDT 24 Jul 14 09:32:33 PM PDT 24 24454826600 ps
T337 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.4235444827 Jul 14 07:57:37 PM PDT 24 Jul 14 08:14:15 PM PDT 24 5053833440 ps
T23 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.35825406 Jul 14 08:06:50 PM PDT 24 Jul 14 08:11:25 PM PDT 24 3313024380 ps
T112 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1309294199 Jul 14 07:54:40 PM PDT 24 Jul 15 02:06:09 AM PDT 24 156005696188 ps
T1136 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3030043548 Jul 14 07:55:58 PM PDT 24 Jul 14 08:06:27 PM PDT 24 4444244656 ps
T762 /workspace/coverage/default/8.chip_sw_all_escalation_resets.140826652 Jul 14 08:18:50 PM PDT 24 Jul 14 08:28:32 PM PDT 24 4807505072 ps
T1137 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1140544614 Jul 14 07:56:41 PM PDT 24 Jul 14 08:08:22 PM PDT 24 8054065180 ps
T1138 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1474500968 Jul 14 08:08:48 PM PDT 24 Jul 14 08:12:26 PM PDT 24 2404113096 ps
T1139 /workspace/coverage/default/14.chip_sw_all_escalation_resets.3349150957 Jul 14 08:18:40 PM PDT 24 Jul 14 08:29:35 PM PDT 24 4734926866 ps
T775 /workspace/coverage/default/49.chip_sw_all_escalation_resets.580368100 Jul 14 08:25:07 PM PDT 24 Jul 14 08:36:02 PM PDT 24 5575117044 ps
T1140 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.186876135 Jul 14 08:00:47 PM PDT 24 Jul 14 09:04:29 PM PDT 24 15735684934 ps
T1141 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.545931589 Jul 14 07:53:16 PM PDT 24 Jul 14 08:04:49 PM PDT 24 4078329580 ps
T387 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3312573993 Jul 14 07:52:56 PM PDT 24 Jul 14 08:04:28 PM PDT 24 3953260520 ps
T1142 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3538291272 Jul 14 07:55:38 PM PDT 24 Jul 14 08:04:12 PM PDT 24 7083455480 ps
T1143 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.601399571 Jul 14 07:53:46 PM PDT 24 Jul 14 07:58:13 PM PDT 24 3415647635 ps
T389 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2368781428 Jul 14 07:53:16 PM PDT 24 Jul 14 07:59:14 PM PDT 24 6136727288 ps
T1144 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3024299189 Jul 14 08:00:14 PM PDT 24 Jul 14 08:11:21 PM PDT 24 6428677456 ps
T1145 /workspace/coverage/default/0.rom_e2e_asm_init_prod.2381926275 Jul 14 08:07:08 PM PDT 24 Jul 14 09:09:48 PM PDT 24 15273268270 ps
T1146 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2001052645 Jul 14 08:09:36 PM PDT 24 Jul 14 08:18:57 PM PDT 24 4587976520 ps
T676 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.990270956 Jul 14 07:54:10 PM PDT 24 Jul 14 08:06:28 PM PDT 24 5075780572 ps
T1147 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.964994571 Jul 14 08:10:26 PM PDT 24 Jul 14 08:19:46 PM PDT 24 8233368582 ps
T1148 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.259743538 Jul 14 08:01:59 PM PDT 24 Jul 14 08:12:50 PM PDT 24 18839060720 ps
T1149 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1159616515 Jul 14 08:05:07 PM PDT 24 Jul 14 08:10:57 PM PDT 24 3276462972 ps
T1150 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1758854714 Jul 14 08:09:40 PM PDT 24 Jul 14 09:07:27 PM PDT 24 18319227354 ps
T1151 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2927886721 Jul 14 07:54:08 PM PDT 24 Jul 14 07:59:12 PM PDT 24 2715803000 ps
T804 /workspace/coverage/default/92.chip_sw_all_escalation_resets.609543636 Jul 14 08:25:41 PM PDT 24 Jul 14 08:36:33 PM PDT 24 5082074376 ps
T324 /workspace/coverage/default/1.chip_plic_all_irqs_20.2273431764 Jul 14 08:01:30 PM PDT 24 Jul 14 08:16:58 PM PDT 24 4844302886 ps
T1152 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1877243400 Jul 14 07:53:20 PM PDT 24 Jul 14 08:03:37 PM PDT 24 7533619568 ps
T1153 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3191174104 Jul 14 08:04:55 PM PDT 24 Jul 14 08:15:05 PM PDT 24 5152102215 ps
T720 /workspace/coverage/default/41.chip_sw_all_escalation_resets.3266704104 Jul 14 08:22:00 PM PDT 24 Jul 14 08:34:05 PM PDT 24 5491754632 ps
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