| T16 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2559323524 |
|
|
Jul 14 08:03:43 PM PDT 24 |
Jul 14 08:31:40 PM PDT 24 |
24161677006 ps |
| T1154 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.4021983485 |
|
|
Jul 14 08:08:08 PM PDT 24 |
Jul 14 08:13:22 PM PDT 24 |
3185676536 ps |
| T1155 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.236577396 |
|
|
Jul 14 08:14:13 PM PDT 24 |
Jul 14 08:19:28 PM PDT 24 |
3556160548 ps |
| T1156 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.910368185 |
|
|
Jul 14 08:09:18 PM PDT 24 |
Jul 14 09:04:35 PM PDT 24 |
22738127130 ps |
| T390 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1643372167 |
|
|
Jul 14 08:03:07 PM PDT 24 |
Jul 14 08:10:10 PM PDT 24 |
5902699100 ps |
| T1157 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1583516513 |
|
|
Jul 14 08:00:41 PM PDT 24 |
Jul 14 08:56:15 PM PDT 24 |
20876888581 ps |
| T1158 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2051955332 |
|
|
Jul 14 08:07:08 PM PDT 24 |
Jul 15 12:02:59 AM PDT 24 |
77801117604 ps |
| T199 |
/workspace/coverage/default/2.chip_jtag_mem_access.4273901599 |
|
|
Jul 14 08:05:13 PM PDT 24 |
Jul 14 08:32:15 PM PDT 24 |
13444614220 ps |
| T263 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1974308574 |
|
|
Jul 14 08:22:34 PM PDT 24 |
Jul 14 08:33:21 PM PDT 24 |
4408295996 ps |
| T1159 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.3032233930 |
|
|
Jul 14 07:55:47 PM PDT 24 |
Jul 14 07:57:34 PM PDT 24 |
2152379833 ps |
| T1160 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.4136537958 |
|
|
Jul 14 08:14:11 PM PDT 24 |
Jul 14 08:19:27 PM PDT 24 |
3945492939 ps |
| T1161 |
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.662045409 |
|
|
Jul 14 08:18:22 PM PDT 24 |
Jul 14 08:51:46 PM PDT 24 |
9125459280 ps |
| T1162 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2812424546 |
|
|
Jul 14 08:10:21 PM PDT 24 |
Jul 14 09:10:13 PM PDT 24 |
16846617048 ps |
| T798 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1977990067 |
|
|
Jul 14 08:00:17 PM PDT 24 |
Jul 14 08:06:36 PM PDT 24 |
3888143234 ps |
| T329 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1764133915 |
|
|
Jul 14 07:51:57 PM PDT 24 |
Jul 14 08:21:53 PM PDT 24 |
14104654476 ps |
| T1163 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.773213290 |
|
|
Jul 14 08:05:47 PM PDT 24 |
Jul 14 08:16:32 PM PDT 24 |
5679664698 ps |
| T1164 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.670105915 |
|
|
Jul 14 07:52:38 PM PDT 24 |
Jul 14 08:00:58 PM PDT 24 |
4796821104 ps |
| T1165 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3196072558 |
|
|
Jul 14 07:58:22 PM PDT 24 |
Jul 14 08:09:51 PM PDT 24 |
7680086200 ps |
| T816 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.569222867 |
|
|
Jul 14 08:23:53 PM PDT 24 |
Jul 14 08:30:02 PM PDT 24 |
4434679128 ps |
| T1166 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1194851934 |
|
|
Jul 14 08:00:31 PM PDT 24 |
Jul 14 08:04:25 PM PDT 24 |
3057869581 ps |
| T1167 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1977329000 |
|
|
Jul 14 07:57:13 PM PDT 24 |
Jul 14 08:04:37 PM PDT 24 |
3282138492 ps |
| T206 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.4219998196 |
|
|
Jul 14 08:10:48 PM PDT 24 |
Jul 14 08:17:58 PM PDT 24 |
3575825219 ps |
| T1168 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.1579831148 |
|
|
Jul 14 08:19:31 PM PDT 24 |
Jul 14 09:23:04 PM PDT 24 |
15466178520 ps |
| T723 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.2361038341 |
|
|
Jul 14 08:26:48 PM PDT 24 |
Jul 14 08:34:10 PM PDT 24 |
4899271464 ps |
| T1169 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.591790272 |
|
|
Jul 14 07:53:33 PM PDT 24 |
Jul 14 08:08:25 PM PDT 24 |
6710438316 ps |
| T196 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.3329349467 |
|
|
Jul 14 07:58:48 PM PDT 24 |
Jul 14 08:07:59 PM PDT 24 |
5268374951 ps |
| T1170 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2070561009 |
|
|
Jul 14 08:10:09 PM PDT 24 |
Jul 14 09:13:48 PM PDT 24 |
40682397870 ps |
| T1171 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.652708969 |
|
|
Jul 14 07:59:34 PM PDT 24 |
Jul 14 08:57:22 PM PDT 24 |
20849781012 ps |
| T1172 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3293346026 |
|
|
Jul 14 08:19:03 PM PDT 24 |
Jul 14 08:26:14 PM PDT 24 |
3915567430 ps |
| T45 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.871021089 |
|
|
Jul 14 07:58:06 PM PDT 24 |
Jul 14 08:02:47 PM PDT 24 |
3090505840 ps |
| T1173 |
/workspace/coverage/default/0.chip_sw_aes_idle.1398827465 |
|
|
Jul 14 07:52:05 PM PDT 24 |
Jul 14 07:55:16 PM PDT 24 |
2063057948 ps |
| T1174 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3261346357 |
|
|
Jul 14 07:53:20 PM PDT 24 |
Jul 14 08:04:35 PM PDT 24 |
5394545768 ps |
| T794 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.596355291 |
|
|
Jul 14 08:25:24 PM PDT 24 |
Jul 14 08:37:11 PM PDT 24 |
6372521840 ps |
| T722 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3444555698 |
|
|
Jul 14 08:25:24 PM PDT 24 |
Jul 14 08:31:37 PM PDT 24 |
3875300540 ps |
| T1175 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.4265493174 |
|
|
Jul 14 07:51:15 PM PDT 24 |
Jul 14 07:59:11 PM PDT 24 |
4411249220 ps |
| T1176 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.605315899 |
|
|
Jul 14 08:25:31 PM PDT 24 |
Jul 14 08:36:03 PM PDT 24 |
5544999204 ps |
| T1177 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2271885874 |
|
|
Jul 14 07:57:32 PM PDT 24 |
Jul 14 08:02:11 PM PDT 24 |
3049203228 ps |
| T1178 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.1731325464 |
|
|
Jul 14 08:10:28 PM PDT 24 |
Jul 14 08:28:23 PM PDT 24 |
6057321652 ps |
| T165 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.2428356495 |
|
|
Jul 14 08:25:05 PM PDT 24 |
Jul 14 08:33:41 PM PDT 24 |
5609438716 ps |
| T372 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.287844705 |
|
|
Jul 14 07:58:19 PM PDT 24 |
Jul 14 08:10:49 PM PDT 24 |
3679486938 ps |
| T1179 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2082471879 |
|
|
Jul 14 07:54:25 PM PDT 24 |
Jul 14 08:05:43 PM PDT 24 |
4065694040 ps |
| T1180 |
/workspace/coverage/default/2.chip_sw_hmac_oneshot.3675920322 |
|
|
Jul 14 08:11:19 PM PDT 24 |
Jul 14 08:18:38 PM PDT 24 |
3482628900 ps |
| T1181 |
/workspace/coverage/default/0.chip_sw_power_idle_load.1542887827 |
|
|
Jul 14 07:58:44 PM PDT 24 |
Jul 14 08:11:07 PM PDT 24 |
3829065738 ps |
| T648 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1606133986 |
|
|
Jul 14 08:02:56 PM PDT 24 |
Jul 14 08:12:26 PM PDT 24 |
4335068127 ps |
| T700 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.1603185264 |
|
|
Jul 14 08:05:45 PM PDT 24 |
Jul 14 08:13:18 PM PDT 24 |
4959186440 ps |
| T1182 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1040005876 |
|
|
Jul 14 07:54:30 PM PDT 24 |
Jul 14 07:58:50 PM PDT 24 |
3399516840 ps |
| T801 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.1439877195 |
|
|
Jul 14 08:22:15 PM PDT 24 |
Jul 14 08:32:39 PM PDT 24 |
5097291320 ps |
| T810 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2462726829 |
|
|
Jul 14 08:25:04 PM PDT 24 |
Jul 14 08:31:22 PM PDT 24 |
3855019144 ps |
| T1183 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.1359439132 |
|
|
Jul 14 08:06:54 PM PDT 24 |
Jul 14 08:17:55 PM PDT 24 |
4124575926 ps |
| T1184 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.5551683 |
|
|
Jul 14 08:06:47 PM PDT 24 |
Jul 14 08:16:16 PM PDT 24 |
5065200200 ps |
| T1185 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.2589299884 |
|
|
Jul 14 08:17:54 PM PDT 24 |
Jul 14 09:10:46 PM PDT 24 |
28970211953 ps |
| T1186 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3858984441 |
|
|
Jul 14 07:58:56 PM PDT 24 |
Jul 14 08:47:34 PM PDT 24 |
11269409930 ps |
| T799 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2383305223 |
|
|
Jul 14 08:21:39 PM PDT 24 |
Jul 14 08:27:18 PM PDT 24 |
4315546192 ps |
| T1187 |
/workspace/coverage/default/1.chip_sival_flash_info_access.2992337238 |
|
|
Jul 14 07:57:20 PM PDT 24 |
Jul 14 08:02:00 PM PDT 24 |
2847142064 ps |
| T371 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.993870906 |
|
|
Jul 14 07:52:45 PM PDT 24 |
Jul 14 08:04:02 PM PDT 24 |
4318367196 ps |
| T1188 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3772311675 |
|
|
Jul 14 08:06:59 PM PDT 24 |
Jul 14 08:18:54 PM PDT 24 |
8759683340 ps |
| T7 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1470712494 |
|
|
Jul 14 08:03:44 PM PDT 24 |
Jul 14 08:08:14 PM PDT 24 |
3017060678 ps |
| T460 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.678479900 |
|
|
Jul 14 08:10:21 PM PDT 24 |
Jul 14 08:13:53 PM PDT 24 |
2477523320 ps |
| T461 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1858417540 |
|
|
Jul 14 08:18:45 PM PDT 24 |
Jul 14 08:28:57 PM PDT 24 |
4689488800 ps |
| T462 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.3315002366 |
|
|
Jul 14 07:54:04 PM PDT 24 |
Jul 14 08:04:20 PM PDT 24 |
2866746194 ps |
| T463 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.4120558300 |
|
|
Jul 14 07:51:58 PM PDT 24 |
Jul 14 08:01:42 PM PDT 24 |
5683507560 ps |
| T391 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3000135068 |
|
|
Jul 14 08:13:29 PM PDT 24 |
Jul 14 08:23:03 PM PDT 24 |
5732071908 ps |
| T464 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3730882722 |
|
|
Jul 14 08:25:42 PM PDT 24 |
Jul 14 08:34:40 PM PDT 24 |
4383731632 ps |
| T465 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.270936674 |
|
|
Jul 14 08:00:55 PM PDT 24 |
Jul 14 08:37:29 PM PDT 24 |
9263095680 ps |
| T466 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.4101443452 |
|
|
Jul 14 07:53:25 PM PDT 24 |
Jul 14 08:03:55 PM PDT 24 |
4059509460 ps |
| T467 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3566144721 |
|
|
Jul 14 08:21:27 PM PDT 24 |
Jul 14 08:27:30 PM PDT 24 |
3584512600 ps |
| T1189 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.2708201766 |
|
|
Jul 14 08:12:51 PM PDT 24 |
Jul 14 08:17:28 PM PDT 24 |
2707315952 ps |
| T1190 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2065651480 |
|
|
Jul 14 08:07:04 PM PDT 24 |
Jul 14 11:09:59 PM PDT 24 |
59256827242 ps |
| T197 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2672620448 |
|
|
Jul 14 08:07:05 PM PDT 24 |
Jul 14 08:16:54 PM PDT 24 |
4414820395 ps |
| T1191 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.1589355317 |
|
|
Jul 14 08:10:15 PM PDT 24 |
Jul 14 08:14:22 PM PDT 24 |
2423118517 ps |
| T1192 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1384189876 |
|
|
Jul 14 08:10:51 PM PDT 24 |
Jul 14 08:27:42 PM PDT 24 |
5977888903 ps |
| T1193 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.19141947 |
|
|
Jul 14 08:12:31 PM PDT 24 |
Jul 14 08:17:41 PM PDT 24 |
2654229136 ps |
| T1194 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2626433427 |
|
|
Jul 14 08:11:59 PM PDT 24 |
Jul 14 08:20:52 PM PDT 24 |
3804842368 ps |
| T323 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.3017350543 |
|
|
Jul 14 08:11:38 PM PDT 24 |
Jul 14 08:30:51 PM PDT 24 |
6217001576 ps |
| T264 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.960567894 |
|
|
Jul 14 08:20:57 PM PDT 24 |
Jul 14 08:29:31 PM PDT 24 |
4294099930 ps |
| T1195 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2943040950 |
|
|
Jul 14 07:54:12 PM PDT 24 |
Jul 14 08:07:03 PM PDT 24 |
4838685640 ps |
| T265 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.4054254637 |
|
|
Jul 14 07:59:46 PM PDT 24 |
Jul 14 08:13:43 PM PDT 24 |
6939266290 ps |
| T1196 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.532079608 |
|
|
Jul 14 08:07:54 PM PDT 24 |
Jul 14 09:39:16 PM PDT 24 |
50720728408 ps |
| T1197 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.339716836 |
|
|
Jul 14 07:52:00 PM PDT 24 |
Jul 14 07:56:10 PM PDT 24 |
3617631800 ps |
| T771 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.2742475771 |
|
|
Jul 14 08:21:30 PM PDT 24 |
Jul 14 08:35:10 PM PDT 24 |
5679985576 ps |
| T1198 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3713927709 |
|
|
Jul 14 08:09:39 PM PDT 24 |
Jul 14 08:32:04 PM PDT 24 |
11435680487 ps |
| T1199 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1460357748 |
|
|
Jul 14 08:08:01 PM PDT 24 |
Jul 14 08:19:48 PM PDT 24 |
3612923550 ps |
| T1200 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3042748209 |
|
|
Jul 14 08:12:18 PM PDT 24 |
Jul 14 08:33:47 PM PDT 24 |
7134585176 ps |
| T1201 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.936214433 |
|
|
Jul 14 07:57:22 PM PDT 24 |
Jul 14 08:03:15 PM PDT 24 |
3402553136 ps |
| T1202 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2017336895 |
|
|
Jul 14 07:53:05 PM PDT 24 |
Jul 14 08:01:39 PM PDT 24 |
6117600820 ps |
| T796 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.199135732 |
|
|
Jul 14 08:20:17 PM PDT 24 |
Jul 14 08:28:08 PM PDT 24 |
3704804700 ps |
| T1203 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.4058318627 |
|
|
Jul 14 07:55:38 PM PDT 24 |
Jul 14 08:01:32 PM PDT 24 |
3033936710 ps |
| T325 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.698780404 |
|
|
Jul 14 08:12:16 PM PDT 24 |
Jul 14 08:27:48 PM PDT 24 |
4529788080 ps |
| T1204 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1964967778 |
|
|
Jul 14 08:20:31 PM PDT 24 |
Jul 14 09:20:14 PM PDT 24 |
15013245512 ps |
| T1205 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3710021931 |
|
|
Jul 14 07:53:01 PM PDT 24 |
Jul 14 09:24:43 PM PDT 24 |
46007189836 ps |
| T1206 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.415433200 |
|
|
Jul 14 08:08:07 PM PDT 24 |
Jul 14 08:27:33 PM PDT 24 |
5991050584 ps |
| T1207 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.4149578928 |
|
|
Jul 14 08:12:27 PM PDT 24 |
Jul 14 08:45:01 PM PDT 24 |
19895706322 ps |
| T1208 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.534296445 |
|
|
Jul 14 07:58:11 PM PDT 24 |
Jul 14 08:09:03 PM PDT 24 |
5469406360 ps |
| T1209 |
/workspace/coverage/default/2.chip_sw_aes_idle.3416649291 |
|
|
Jul 14 08:09:48 PM PDT 24 |
Jul 14 08:14:52 PM PDT 24 |
3164798218 ps |
| T160 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3765462881 |
|
|
Jul 14 08:10:19 PM PDT 24 |
Jul 14 08:11:48 PM PDT 24 |
1945429547 ps |
| T1210 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.218209108 |
|
|
Jul 14 07:58:35 PM PDT 24 |
Jul 14 08:07:26 PM PDT 24 |
5877057477 ps |
| T773 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.2320151016 |
|
|
Jul 14 08:22:55 PM PDT 24 |
Jul 14 08:35:49 PM PDT 24 |
4493580990 ps |
| T1211 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2320805036 |
|
|
Jul 14 08:13:10 PM PDT 24 |
Jul 14 08:15:40 PM PDT 24 |
2510251683 ps |
| T1212 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1550468502 |
|
|
Jul 14 08:16:12 PM PDT 24 |
Jul 14 08:28:32 PM PDT 24 |
3855107150 ps |
| T1213 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2477965277 |
|
|
Jul 14 07:54:08 PM PDT 24 |
Jul 14 08:55:52 PM PDT 24 |
18206692038 ps |
| T765 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.1490066588 |
|
|
Jul 14 08:20:38 PM PDT 24 |
Jul 14 08:34:49 PM PDT 24 |
5580764044 ps |
| T1214 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.622142631 |
|
|
Jul 14 08:24:25 PM PDT 24 |
Jul 14 08:34:52 PM PDT 24 |
5798614120 ps |
| T1215 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1956631505 |
|
|
Jul 14 07:59:45 PM PDT 24 |
Jul 14 08:11:40 PM PDT 24 |
4782689248 ps |
| T1216 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1803706555 |
|
|
Jul 14 07:53:48 PM PDT 24 |
Jul 14 08:05:27 PM PDT 24 |
3947633415 ps |
| T135 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.3970517248 |
|
|
Jul 14 08:08:25 PM PDT 24 |
Jul 14 08:58:34 PM PDT 24 |
21194626348 ps |
| T1217 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2022056937 |
|
|
Jul 14 07:54:06 PM PDT 24 |
Jul 14 07:56:07 PM PDT 24 |
2450530175 ps |
| T778 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.4074112216 |
|
|
Jul 14 08:26:59 PM PDT 24 |
Jul 14 08:41:08 PM PDT 24 |
5460399904 ps |
| T785 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.1179832074 |
|
|
Jul 14 08:26:08 PM PDT 24 |
Jul 14 08:36:52 PM PDT 24 |
5346544350 ps |
| T1218 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2226977018 |
|
|
Jul 14 08:16:17 PM PDT 24 |
Jul 14 08:28:42 PM PDT 24 |
8919399939 ps |
| T1219 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.3331459745 |
|
|
Jul 14 07:52:19 PM PDT 24 |
Jul 14 07:56:27 PM PDT 24 |
2547559288 ps |
| T1220 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.4223434682 |
|
|
Jul 14 08:20:19 PM PDT 24 |
Jul 14 08:37:44 PM PDT 24 |
11461451054 ps |
| T266 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1847823100 |
|
|
Jul 14 08:27:51 PM PDT 24 |
Jul 14 08:36:23 PM PDT 24 |
4874468800 ps |
| T1221 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.3361102813 |
|
|
Jul 14 08:03:08 PM PDT 24 |
Jul 14 08:22:48 PM PDT 24 |
7051659196 ps |
| T1222 |
/workspace/coverage/default/0.rom_e2e_smoke.3638756026 |
|
|
Jul 14 08:02:53 PM PDT 24 |
Jul 14 09:10:44 PM PDT 24 |
14951026382 ps |
| T413 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2543165446 |
|
|
Jul 14 08:13:51 PM PDT 24 |
Jul 14 08:20:37 PM PDT 24 |
7510336500 ps |
| T1223 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.962993843 |
|
|
Jul 14 07:56:54 PM PDT 24 |
Jul 14 10:46:28 PM PDT 24 |
59098075272 ps |
| T1224 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3339506171 |
|
|
Jul 14 08:07:41 PM PDT 24 |
Jul 14 08:20:34 PM PDT 24 |
4335915080 ps |
| T766 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3548140036 |
|
|
Jul 14 08:19:57 PM PDT 24 |
Jul 14 08:25:11 PM PDT 24 |
3820995150 ps |
| T1225 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3134933005 |
|
|
Jul 14 07:59:21 PM PDT 24 |
Jul 14 08:18:27 PM PDT 24 |
9264292137 ps |
| T1226 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.2406493859 |
|
|
Jul 14 08:07:19 PM PDT 24 |
Jul 14 08:12:11 PM PDT 24 |
2844903720 ps |
| T666 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2119913493 |
|
|
Jul 14 08:04:12 PM PDT 24 |
Jul 15 01:24:45 AM PDT 24 |
149730560776 ps |
| T1227 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3120163938 |
|
|
Jul 14 08:01:47 PM PDT 24 |
Jul 14 09:28:52 PM PDT 24 |
23350725854 ps |
| T1228 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2985834331 |
|
|
Jul 14 08:13:47 PM PDT 24 |
Jul 14 08:56:11 PM PDT 24 |
11444802330 ps |
| T1229 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.265232610 |
|
|
Jul 14 08:21:37 PM PDT 24 |
Jul 14 08:31:38 PM PDT 24 |
5687947366 ps |
| T1230 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3454017398 |
|
|
Jul 14 08:17:06 PM PDT 24 |
Jul 14 08:25:19 PM PDT 24 |
3951358784 ps |
| T338 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.513687475 |
|
|
Jul 14 07:58:11 PM PDT 24 |
Jul 14 08:06:43 PM PDT 24 |
3913420908 ps |
| T1231 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.33767677 |
|
|
Jul 14 07:52:31 PM PDT 24 |
Jul 14 08:18:11 PM PDT 24 |
6968970696 ps |
| T788 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.3907842193 |
|
|
Jul 14 08:22:53 PM PDT 24 |
Jul 14 08:33:34 PM PDT 24 |
4509512592 ps |
| T1232 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2592105219 |
|
|
Jul 14 08:05:21 PM PDT 24 |
Jul 14 08:28:51 PM PDT 24 |
9730106247 ps |
| T1233 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2393843940 |
|
|
Jul 14 07:59:36 PM PDT 24 |
Jul 14 08:59:09 PM PDT 24 |
14256806500 ps |
| T1234 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.3405903565 |
|
|
Jul 14 08:15:27 PM PDT 24 |
Jul 14 08:24:27 PM PDT 24 |
4820413936 ps |
| T1235 |
/workspace/coverage/default/1.chip_sw_hmac_enc.2552410338 |
|
|
Jul 14 08:01:08 PM PDT 24 |
Jul 14 08:04:37 PM PDT 24 |
3089585918 ps |
| T1236 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2396265371 |
|
|
Jul 14 07:59:05 PM PDT 24 |
Jul 14 08:07:55 PM PDT 24 |
4278460402 ps |
| T781 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3962513959 |
|
|
Jul 14 08:19:24 PM PDT 24 |
Jul 14 08:27:22 PM PDT 24 |
3876975552 ps |
| T1237 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1261965239 |
|
|
Jul 14 07:54:17 PM PDT 24 |
Jul 14 08:05:50 PM PDT 24 |
8982701040 ps |
| T1238 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.1617270691 |
|
|
Jul 14 08:15:16 PM PDT 24 |
Jul 14 08:20:14 PM PDT 24 |
3169742236 ps |
| T1239 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.824213707 |
|
|
Jul 14 08:03:24 PM PDT 24 |
Jul 14 08:35:26 PM PDT 24 |
9819997180 ps |
| T1240 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2953531744 |
|
|
Jul 14 07:54:39 PM PDT 24 |
Jul 14 07:57:14 PM PDT 24 |
2378233590 ps |
| T1241 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3075130177 |
|
|
Jul 14 08:06:09 PM PDT 24 |
Jul 14 08:28:56 PM PDT 24 |
5380325216 ps |
| T1242 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2019036285 |
|
|
Jul 14 07:54:32 PM PDT 24 |
Jul 14 08:01:17 PM PDT 24 |
2970685703 ps |
| T162 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3745607424 |
|
|
Jul 14 07:58:22 PM PDT 24 |
Jul 14 08:00:05 PM PDT 24 |
2640089796 ps |
| T1243 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2734812250 |
|
|
Jul 14 07:54:22 PM PDT 24 |
Jul 14 08:00:26 PM PDT 24 |
3362926142 ps |
| T1244 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.182518199 |
|
|
Jul 14 08:11:25 PM PDT 24 |
Jul 14 08:28:48 PM PDT 24 |
4516313952 ps |
| T710 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.844923583 |
|
|
Jul 14 07:56:40 PM PDT 24 |
Jul 14 08:31:46 PM PDT 24 |
10596150112 ps |
| T1245 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3044910449 |
|
|
Jul 14 08:13:18 PM PDT 24 |
Jul 14 08:22:16 PM PDT 24 |
3379438632 ps |
| T267 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2533115707 |
|
|
Jul 14 08:26:40 PM PDT 24 |
Jul 14 08:35:28 PM PDT 24 |
4788695648 ps |
| T414 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2826310024 |
|
|
Jul 14 08:18:34 PM PDT 24 |
Jul 14 08:46:46 PM PDT 24 |
25435520292 ps |
| T1246 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3838824451 |
|
|
Jul 14 08:14:49 PM PDT 24 |
Jul 14 09:17:14 PM PDT 24 |
24495418274 ps |
| T1247 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3302882757 |
|
|
Jul 14 07:54:47 PM PDT 24 |
Jul 14 07:58:26 PM PDT 24 |
2609944002 ps |
| T67 |
/workspace/coverage/default/0.chip_sw_alert_test.4040726291 |
|
|
Jul 14 07:56:05 PM PDT 24 |
Jul 14 08:02:10 PM PDT 24 |
2831400786 ps |
| T1248 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.3641030935 |
|
|
Jul 14 08:15:30 PM PDT 24 |
Jul 14 08:25:21 PM PDT 24 |
3717394760 ps |
| T1249 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3417903691 |
|
|
Jul 14 07:59:00 PM PDT 24 |
Jul 14 08:23:18 PM PDT 24 |
11599372433 ps |
| T780 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2184701294 |
|
|
Jul 14 08:25:23 PM PDT 24 |
Jul 14 08:31:54 PM PDT 24 |
3816245604 ps |
| T1250 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3147209759 |
|
|
Jul 14 08:17:50 PM PDT 24 |
Jul 14 08:26:27 PM PDT 24 |
3459385224 ps |
| T1251 |
/workspace/coverage/default/2.chip_tap_straps_prod.3480562536 |
|
|
Jul 14 08:11:59 PM PDT 24 |
Jul 14 08:14:24 PM PDT 24 |
2935772971 ps |
| T68 |
/workspace/coverage/default/2.chip_sw_alert_test.4153229104 |
|
|
Jul 14 08:11:08 PM PDT 24 |
Jul 14 08:17:35 PM PDT 24 |
3729758000 ps |
| T1252 |
/workspace/coverage/default/2.chip_sw_aes_entropy.2428109418 |
|
|
Jul 14 08:12:58 PM PDT 24 |
Jul 14 08:18:49 PM PDT 24 |
3514361080 ps |
| T693 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.2520739064 |
|
|
Jul 14 08:01:32 PM PDT 24 |
Jul 14 08:05:15 PM PDT 24 |
2594775990 ps |
| T818 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2039635533 |
|
|
Jul 14 08:26:35 PM PDT 24 |
Jul 14 08:32:48 PM PDT 24 |
3257337494 ps |
| T1253 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2992058213 |
|
|
Jul 14 08:08:18 PM PDT 24 |
Jul 14 08:19:38 PM PDT 24 |
4418783240 ps |
| T1254 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3235964899 |
|
|
Jul 14 08:12:09 PM PDT 24 |
Jul 14 08:16:32 PM PDT 24 |
3055892970 ps |
| T392 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.123894123 |
|
|
Jul 14 08:23:03 PM PDT 24 |
Jul 14 08:32:03 PM PDT 24 |
4962294930 ps |
| T301 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3543783002 |
|
|
Jul 14 08:15:11 PM PDT 24 |
Jul 14 08:20:11 PM PDT 24 |
2867949557 ps |
| T797 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.3561393427 |
|
|
Jul 14 07:53:11 PM PDT 24 |
Jul 14 08:05:48 PM PDT 24 |
4555945300 ps |
| T1255 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.1550667267 |
|
|
Jul 14 08:25:15 PM PDT 24 |
Jul 14 08:35:08 PM PDT 24 |
5241659176 ps |
| T1256 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3663777144 |
|
|
Jul 14 08:03:16 PM PDT 24 |
Jul 14 08:10:40 PM PDT 24 |
4706515096 ps |
| T1257 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2313260834 |
|
|
Jul 14 07:53:38 PM PDT 24 |
Jul 14 08:02:08 PM PDT 24 |
3099237688 ps |
| T1258 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.2055587502 |
|
|
Jul 14 07:54:45 PM PDT 24 |
Jul 14 08:18:55 PM PDT 24 |
8015345708 ps |
| T8 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1502949836 |
|
|
Jul 14 07:55:22 PM PDT 24 |
Jul 14 08:00:24 PM PDT 24 |
3258332730 ps |
| T1259 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2706477762 |
|
|
Jul 14 08:10:54 PM PDT 24 |
Jul 14 08:16:15 PM PDT 24 |
2511865390 ps |
| T1260 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.622267553 |
|
|
Jul 14 07:56:00 PM PDT 24 |
Jul 14 08:38:53 PM PDT 24 |
10164573416 ps |
| T136 |
/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.240393083 |
|
|
Jul 14 08:02:32 PM PDT 24 |
Jul 14 08:53:36 PM PDT 24 |
19823428051 ps |
| T207 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.290429732 |
|
|
Jul 14 07:57:00 PM PDT 24 |
Jul 14 08:04:30 PM PDT 24 |
3877232300 ps |
| T1261 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3342373812 |
|
|
Jul 14 08:10:55 PM PDT 24 |
Jul 14 08:30:51 PM PDT 24 |
6120312848 ps |
| T1262 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1838578435 |
|
|
Jul 14 07:59:41 PM PDT 24 |
Jul 14 08:09:46 PM PDT 24 |
4580603627 ps |
| T292 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3019372440 |
|
|
Jul 14 08:24:25 PM PDT 24 |
Jul 14 08:34:51 PM PDT 24 |
5018738816 ps |
| T38 |
/workspace/coverage/default/0.chip_sw_gpio.976185597 |
|
|
Jul 14 07:53:38 PM PDT 24 |
Jul 14 08:01:48 PM PDT 24 |
3740161410 ps |
| T1263 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1743543382 |
|
|
Jul 14 07:53:16 PM PDT 24 |
Jul 14 09:34:07 PM PDT 24 |
50638661028 ps |
| T1264 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.934246646 |
|
|
Jul 14 08:04:33 PM PDT 24 |
Jul 14 09:05:48 PM PDT 24 |
22864430693 ps |
| T1265 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.1150047093 |
|
|
Jul 14 08:09:25 PM PDT 24 |
Jul 14 08:14:49 PM PDT 24 |
3561645576 ps |
| T1266 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2687155144 |
|
|
Jul 14 07:53:00 PM PDT 24 |
Jul 14 08:01:50 PM PDT 24 |
5361425544 ps |
| T1267 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3031817248 |
|
|
Jul 14 08:23:52 PM PDT 24 |
Jul 14 08:30:02 PM PDT 24 |
3700446590 ps |
| T1268 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.6780687 |
|
|
Jul 14 08:21:21 PM PDT 24 |
Jul 14 08:31:17 PM PDT 24 |
6403162664 ps |
| T1269 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.85796865 |
|
|
Jul 14 07:52:39 PM PDT 24 |
Jul 14 08:01:10 PM PDT 24 |
5561506534 ps |
| T1270 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1896313002 |
|
|
Jul 14 08:15:51 PM PDT 24 |
Jul 14 08:29:23 PM PDT 24 |
5503709410 ps |
| T1271 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.581087975 |
|
|
Jul 14 07:56:44 PM PDT 24 |
Jul 14 08:00:48 PM PDT 24 |
2691929200 ps |
| T1272 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.288201424 |
|
|
Jul 14 08:16:37 PM PDT 24 |
Jul 14 08:25:51 PM PDT 24 |
4491949178 ps |
| T438 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3255798772 |
|
|
Jul 14 07:55:04 PM PDT 24 |
Jul 14 08:04:02 PM PDT 24 |
7712522676 ps |
| T777 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.737273455 |
|
|
Jul 14 08:20:58 PM PDT 24 |
Jul 14 08:32:53 PM PDT 24 |
4438947666 ps |
| T1273 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1640391426 |
|
|
Jul 14 08:01:21 PM PDT 24 |
Jul 14 09:12:28 PM PDT 24 |
14564144960 ps |
| T1274 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3476182927 |
|
|
Jul 14 07:58:03 PM PDT 24 |
Jul 14 08:11:14 PM PDT 24 |
5580459668 ps |
| T1275 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.3645454527 |
|
|
Jul 14 08:10:07 PM PDT 24 |
Jul 14 08:24:18 PM PDT 24 |
5213396032 ps |
| T1276 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1491091601 |
|
|
Jul 14 08:25:21 PM PDT 24 |
Jul 14 08:31:42 PM PDT 24 |
3537272778 ps |
| T1277 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1270735760 |
|
|
Jul 14 08:14:06 PM PDT 24 |
Jul 14 08:19:59 PM PDT 24 |
3904128551 ps |
| T1278 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.875776971 |
|
|
Jul 14 08:09:04 PM PDT 24 |
Jul 14 08:15:13 PM PDT 24 |
3102138540 ps |
| T786 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.460555894 |
|
|
Jul 14 08:24:45 PM PDT 24 |
Jul 14 08:33:40 PM PDT 24 |
5353423160 ps |
| T1279 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.4063497493 |
|
|
Jul 14 07:55:03 PM PDT 24 |
Jul 14 08:02:06 PM PDT 24 |
3841007520 ps |
| T1280 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.1445189606 |
|
|
Jul 14 07:54:56 PM PDT 24 |
Jul 14 08:00:18 PM PDT 24 |
4097202600 ps |
| T1281 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.461880220 |
|
|
Jul 14 08:18:26 PM PDT 24 |
Jul 14 08:42:29 PM PDT 24 |
8254239488 ps |
| T1282 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.448876714 |
|
|
Jul 14 08:16:43 PM PDT 24 |
Jul 14 09:47:05 PM PDT 24 |
25434353648 ps |
| T1283 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.495786536 |
|
|
Jul 14 08:06:37 PM PDT 24 |
Jul 14 08:09:37 PM PDT 24 |
2754939524 ps |
| T1284 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.513943717 |
|
|
Jul 14 08:17:52 PM PDT 24 |
Jul 14 09:44:07 PM PDT 24 |
20592424548 ps |
| T14 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.1079346837 |
|
|
Jul 14 08:06:21 PM PDT 24 |
Jul 14 08:13:51 PM PDT 24 |
4697799220 ps |
| T302 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1448823686 |
|
|
Jul 14 07:53:45 PM PDT 24 |
Jul 14 07:57:49 PM PDT 24 |
3095708001 ps |
| T819 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.302541348 |
|
|
Jul 14 08:27:27 PM PDT 24 |
Jul 14 08:35:34 PM PDT 24 |
3487340128 ps |
| T332 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.1169633870 |
|
|
Jul 14 08:01:32 PM PDT 24 |
Jul 14 08:28:42 PM PDT 24 |
7378632440 ps |
| T1285 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.2825984820 |
|
|
Jul 14 08:04:09 PM PDT 24 |
Jul 14 08:10:53 PM PDT 24 |
3134827904 ps |
| T198 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1384672872 |
|
|
Jul 14 07:58:14 PM PDT 24 |
Jul 14 08:09:07 PM PDT 24 |
4805371699 ps |
| T1286 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1560930273 |
|
|
Jul 14 07:54:48 PM PDT 24 |
Jul 14 08:02:11 PM PDT 24 |
3042858028 ps |
| T330 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2092774390 |
|
|
Jul 14 07:57:01 PM PDT 24 |
Jul 14 08:26:56 PM PDT 24 |
9962707300 ps |
| T1287 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1679288799 |
|
|
Jul 14 07:54:54 PM PDT 24 |
Jul 14 08:01:23 PM PDT 24 |
3492203200 ps |
| T1288 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1341099560 |
|
|
Jul 14 08:01:49 PM PDT 24 |
Jul 14 08:26:39 PM PDT 24 |
9960460050 ps |
| T1289 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3766329841 |
|
|
Jul 14 08:02:26 PM PDT 24 |
Jul 14 08:09:18 PM PDT 24 |
3448592728 ps |
| T46 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3538881527 |
|
|
Jul 14 08:07:48 PM PDT 24 |
Jul 14 08:13:15 PM PDT 24 |
3206842396 ps |
| T1290 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3461808238 |
|
|
Jul 14 08:07:44 PM PDT 24 |
Jul 14 08:19:50 PM PDT 24 |
4195670978 ps |
| T1291 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.659622400 |
|
|
Jul 14 08:07:14 PM PDT 24 |
Jul 14 08:12:22 PM PDT 24 |
2893682600 ps |
| T1292 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2549036675 |
|
|
Jul 14 07:53:47 PM PDT 24 |
Jul 14 08:02:29 PM PDT 24 |
4444299976 ps |
| T1293 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.3592042 |
|
|
Jul 14 08:19:05 PM PDT 24 |
Jul 14 08:29:40 PM PDT 24 |
4554928704 ps |
| T760 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.3468747397 |
|
|
Jul 14 08:21:07 PM PDT 24 |
Jul 14 08:34:06 PM PDT 24 |
6342119418 ps |
| T1294 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3564818583 |
|
|
Jul 14 08:01:05 PM PDT 24 |
Jul 14 09:18:14 PM PDT 24 |
18117425142 ps |
| T1295 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.796178974 |
|
|
Jul 14 07:59:02 PM PDT 24 |
Jul 14 08:05:46 PM PDT 24 |
9303439250 ps |
| T1296 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2201165969 |
|
|
Jul 14 07:55:48 PM PDT 24 |
Jul 14 08:00:12 PM PDT 24 |
2994362008 ps |
| T1297 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.369352945 |
|
|
Jul 14 08:08:33 PM PDT 24 |
Jul 14 08:30:50 PM PDT 24 |
9196410796 ps |
| T774 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1109698544 |
|
|
Jul 14 08:23:17 PM PDT 24 |
Jul 14 08:30:46 PM PDT 24 |
4219667000 ps |
| T1298 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2394244367 |
|
|
Jul 14 08:21:15 PM PDT 24 |
Jul 14 08:33:09 PM PDT 24 |
7632292735 ps |
| T1299 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.578331066 |
|
|
Jul 14 08:09:32 PM PDT 24 |
Jul 14 08:18:06 PM PDT 24 |
18648259876 ps |
| T293 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.3562587058 |
|
|
Jul 14 08:23:24 PM PDT 24 |
Jul 14 08:33:38 PM PDT 24 |
4521032084 ps |
| T1300 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.1069607842 |
|
|
Jul 14 08:05:05 PM PDT 24 |
Jul 14 08:06:51 PM PDT 24 |
2812039972 ps |
| T1301 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2245179220 |
|
|
Jul 14 07:55:52 PM PDT 24 |
Jul 14 08:14:03 PM PDT 24 |
5331788024 ps |
| T1302 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1003870691 |
|
|
Jul 14 07:53:19 PM PDT 24 |
Jul 14 08:03:35 PM PDT 24 |
4121697760 ps |
| T1303 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1614131730 |
|
|
Jul 14 08:21:45 PM PDT 24 |
Jul 14 08:27:21 PM PDT 24 |
4237722564 ps |
| T1304 |
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2530838630 |
|
|
Jul 14 08:15:43 PM PDT 24 |
Jul 14 09:17:09 PM PDT 24 |
14597218740 ps |
| T724 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.682919807 |
|
|
Jul 14 08:26:06 PM PDT 24 |
Jul 14 08:31:38 PM PDT 24 |
3328822368 ps |
| T1305 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2364512290 |
|
|
Jul 14 08:04:48 PM PDT 24 |
Jul 14 08:33:23 PM PDT 24 |
12224416383 ps |
| T1306 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1376391570 |
|
|
Jul 14 08:02:00 PM PDT 24 |
Jul 14 08:08:01 PM PDT 24 |
3934792470 ps |
| T1307 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.392042240 |
|
|
Jul 14 07:58:41 PM PDT 24 |
Jul 14 08:01:53 PM PDT 24 |
2615803816 ps |
| T1308 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.460438520 |
|
|
Jul 14 08:24:36 PM PDT 24 |
Jul 14 08:29:49 PM PDT 24 |
3518043680 ps |
| T1309 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.4122599430 |
|
|
Jul 14 07:54:04 PM PDT 24 |
Jul 14 07:57:55 PM PDT 24 |
3172901557 ps |
| T1310 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.170807466 |
|
|
Jul 14 07:53:40 PM PDT 24 |
Jul 14 09:33:43 PM PDT 24 |
48705248184 ps |
| T1311 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3079317368 |
|
|
Jul 14 08:02:20 PM PDT 24 |
Jul 14 08:12:50 PM PDT 24 |
3283276392 ps |
| T1312 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3908282805 |
|
|
Jul 14 07:57:58 PM PDT 24 |
Jul 14 08:07:19 PM PDT 24 |
7128691704 ps |
| T1313 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2013859084 |
|
|
Jul 14 08:13:59 PM PDT 24 |
Jul 14 08:34:02 PM PDT 24 |
7522769136 ps |
| T1314 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2031734986 |
|
|
Jul 14 08:15:59 PM PDT 24 |
Jul 14 08:29:17 PM PDT 24 |
3914350880 ps |
| T1315 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1565671669 |
|
|
Jul 14 08:08:49 PM PDT 24 |
Jul 14 08:24:48 PM PDT 24 |
7507128460 ps |
| T1316 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.2906522398 |
|
|
Jul 14 08:21:56 PM PDT 24 |
Jul 14 08:32:17 PM PDT 24 |
4756020862 ps |
| T1317 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.1663918829 |
|
|
Jul 14 08:12:31 PM PDT 24 |
Jul 14 08:19:06 PM PDT 24 |
3410039580 ps |
| T294 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.4200858726 |
|
|
Jul 14 08:26:27 PM PDT 24 |
Jul 14 08:35:04 PM PDT 24 |
5713938824 ps |
| T1318 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2585848625 |
|
|
Jul 14 08:25:31 PM PDT 24 |
Jul 14 08:36:16 PM PDT 24 |
6213295130 ps |
| T1319 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.472586700 |
|
|
Jul 14 08:09:21 PM PDT 24 |
Jul 14 08:20:59 PM PDT 24 |
4793162403 ps |
| T814 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.688086684 |
|
|
Jul 14 08:20:10 PM PDT 24 |
Jul 14 08:27:44 PM PDT 24 |
4300875364 ps |