Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
10309 |
0 |
0 |
T1 |
36764 |
4 |
0 |
0 |
T2 |
0 |
2 |
0 |
0 |
T3 |
0 |
2 |
0 |
0 |
T8 |
507872 |
8 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
22455 |
1 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
7 |
0 |
0 |
T16 |
0 |
2 |
0 |
0 |
T95 |
0 |
2 |
0 |
0 |
T96 |
0 |
2 |
0 |
0 |
T97 |
69346 |
0 |
0 |
0 |
T98 |
9971 |
0 |
0 |
0 |
T99 |
407672 |
0 |
0 |
0 |
T100 |
93759 |
0 |
0 |
0 |
T101 |
26004 |
0 |
0 |
0 |
T102 |
30703 |
0 |
0 |
0 |
T103 |
16060 |
0 |
0 |
0 |
T104 |
149139 |
0 |
0 |
0 |
T105 |
76118 |
0 |
0 |
0 |
T146 |
0 |
29 |
0 |
0 |
T147 |
0 |
14 |
0 |
0 |
T220 |
0 |
2 |
0 |
0 |
T391 |
0 |
53 |
0 |
0 |
T392 |
0 |
14 |
0 |
0 |
T393 |
0 |
68 |
0 |
0 |
T413 |
0 |
43 |
0 |
0 |
T423 |
0 |
14 |
0 |
0 |
T424 |
0 |
8 |
0 |
0 |
T425 |
119846 |
0 |
0 |
0 |
T426 |
87232 |
0 |
0 |
0 |
T427 |
132008 |
0 |
0 |
0 |
T428 |
99638 |
0 |
0 |
0 |
T429 |
627802 |
0 |
0 |
0 |
T430 |
280304 |
0 |
0 |
0 |
T431 |
601876 |
0 |
0 |
0 |
T432 |
45844 |
0 |
0 |
0 |
T433 |
72836 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
10317 |
0 |
0 |
T1 |
71833 |
5 |
0 |
0 |
T2 |
0 |
2 |
0 |
0 |
T3 |
0 |
2 |
0 |
0 |
T8 |
507872 |
8 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
491 |
1 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
T16 |
0 |
2 |
0 |
0 |
T95 |
0 |
2 |
0 |
0 |
T96 |
0 |
2 |
0 |
0 |
T97 |
136259 |
0 |
0 |
0 |
T98 |
18832 |
0 |
0 |
0 |
T99 |
805108 |
0 |
0 |
0 |
T100 |
182922 |
0 |
0 |
0 |
T101 |
50694 |
0 |
0 |
0 |
T102 |
60086 |
0 |
0 |
0 |
T103 |
31178 |
0 |
0 |
0 |
T104 |
291207 |
0 |
0 |
0 |
T105 |
149704 |
0 |
0 |
0 |
T146 |
0 |
29 |
0 |
0 |
T147 |
0 |
14 |
0 |
0 |
T220 |
0 |
2 |
0 |
0 |
T391 |
0 |
53 |
0 |
0 |
T392 |
0 |
14 |
0 |
0 |
T393 |
0 |
68 |
0 |
0 |
T413 |
0 |
43 |
0 |
0 |
T423 |
0 |
14 |
0 |
0 |
T424 |
0 |
8 |
0 |
0 |
T425 |
119846 |
0 |
0 |
0 |
T426 |
87232 |
0 |
0 |
0 |
T427 |
132008 |
0 |
0 |
0 |
T428 |
99638 |
0 |
0 |
0 |
T429 |
627802 |
0 |
0 |
0 |
T430 |
280304 |
0 |
0 |
0 |
T431 |
601876 |
0 |
0 |
0 |
T432 |
45844 |
0 |
0 |
0 |
T433 |
72836 |
0 |
0 |
0 |