| T935 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3186435546 |
|
|
Jul 15 08:26:30 PM PDT 24 |
Jul 15 08:33:45 PM PDT 24 |
4414477066 ps |
| T68 |
/workspace/coverage/default/3.chip_tap_straps_rma.3158548166 |
|
|
Jul 15 08:24:26 PM PDT 24 |
Jul 15 08:38:15 PM PDT 24 |
8193059863 ps |
| T799 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3571836589 |
|
|
Jul 15 08:29:54 PM PDT 24 |
Jul 15 08:37:26 PM PDT 24 |
3963436296 ps |
| T936 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1740479575 |
|
|
Jul 15 08:25:23 PM PDT 24 |
Jul 15 08:33:46 PM PDT 24 |
5695811010 ps |
| T252 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.4284115622 |
|
|
Jul 15 08:30:53 PM PDT 24 |
Jul 15 08:40:22 PM PDT 24 |
4048665696 ps |
| T299 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.1786151232 |
|
|
Jul 15 08:34:19 PM PDT 24 |
Jul 15 08:44:49 PM PDT 24 |
5380613644 ps |
| T234 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2112090917 |
|
|
Jul 15 08:01:48 PM PDT 24 |
Jul 15 08:09:29 PM PDT 24 |
5427190300 ps |
| T300 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3093963245 |
|
|
Jul 15 08:04:09 PM PDT 24 |
Jul 15 08:15:27 PM PDT 24 |
4368225704 ps |
| T232 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2499675637 |
|
|
Jul 15 08:11:05 PM PDT 24 |
Jul 15 09:03:26 PM PDT 24 |
11749410200 ps |
| T301 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2150517292 |
|
|
Jul 15 08:03:56 PM PDT 24 |
Jul 15 08:14:45 PM PDT 24 |
4265807064 ps |
| T39 |
/workspace/coverage/default/1.chip_sw_gpio.1984203208 |
|
|
Jul 15 08:10:11 PM PDT 24 |
Jul 15 08:17:06 PM PDT 24 |
3991626980 ps |
| T35 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1950987983 |
|
|
Jul 15 08:04:16 PM PDT 24 |
Jul 15 08:58:08 PM PDT 24 |
20725459100 ps |
| T302 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1155996312 |
|
|
Jul 15 08:04:27 PM PDT 24 |
Jul 15 08:25:57 PM PDT 24 |
7249795816 ps |
| T303 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3852836973 |
|
|
Jul 15 08:33:09 PM PDT 24 |
Jul 15 08:40:05 PM PDT 24 |
3773553544 ps |
| T397 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.381874830 |
|
|
Jul 15 08:18:33 PM PDT 24 |
Jul 15 08:23:51 PM PDT 24 |
2727793080 ps |
| T937 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.33971781 |
|
|
Jul 15 08:25:48 PM PDT 24 |
Jul 15 08:44:29 PM PDT 24 |
5866099672 ps |
| T938 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2371391180 |
|
|
Jul 15 08:09:41 PM PDT 24 |
Jul 15 08:15:14 PM PDT 24 |
2649765676 ps |
| T396 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2933253911 |
|
|
Jul 15 08:30:06 PM PDT 24 |
Jul 15 08:36:33 PM PDT 24 |
3355878520 ps |
| T939 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.761321817 |
|
|
Jul 15 08:05:00 PM PDT 24 |
Jul 15 08:08:51 PM PDT 24 |
2957259568 ps |
| T404 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2644066752 |
|
|
Jul 15 08:14:55 PM PDT 24 |
Jul 15 08:17:29 PM PDT 24 |
2736467248 ps |
| T746 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.2864423447 |
|
|
Jul 15 08:26:05 PM PDT 24 |
Jul 15 08:40:03 PM PDT 24 |
5833601016 ps |
| T940 |
/workspace/coverage/default/2.chip_sw_example_concurrency.3128509273 |
|
|
Jul 15 08:16:43 PM PDT 24 |
Jul 15 08:21:23 PM PDT 24 |
2952128624 ps |
| T941 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.2178384114 |
|
|
Jul 15 08:05:20 PM PDT 24 |
Jul 15 08:10:19 PM PDT 24 |
2835170224 ps |
| T803 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2761738465 |
|
|
Jul 15 08:30:34 PM PDT 24 |
Jul 15 08:38:12 PM PDT 24 |
3956117432 ps |
| T942 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.1081505621 |
|
|
Jul 15 08:09:51 PM PDT 24 |
Jul 15 08:25:37 PM PDT 24 |
6240722484 ps |
| T283 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3197227150 |
|
|
Jul 15 08:09:30 PM PDT 24 |
Jul 15 08:16:13 PM PDT 24 |
3375699844 ps |
| T730 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2068657061 |
|
|
Jul 15 08:32:08 PM PDT 24 |
Jul 15 08:38:32 PM PDT 24 |
4045838588 ps |
| T798 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1217738677 |
|
|
Jul 15 08:28:08 PM PDT 24 |
Jul 15 08:34:48 PM PDT 24 |
3986434426 ps |
| T257 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.3570399835 |
|
|
Jul 15 08:13:08 PM PDT 24 |
Jul 15 08:20:08 PM PDT 24 |
4052037252 ps |
| T943 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2913517893 |
|
|
Jul 15 08:03:29 PM PDT 24 |
Jul 15 08:20:00 PM PDT 24 |
10707278481 ps |
| T22 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.447259412 |
|
|
Jul 15 08:07:34 PM PDT 24 |
Jul 15 08:12:06 PM PDT 24 |
3309923608 ps |
| T402 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2941086343 |
|
|
Jul 15 08:33:58 PM PDT 24 |
Jul 15 08:46:31 PM PDT 24 |
5467547880 ps |
| T944 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1179241735 |
|
|
Jul 15 08:19:02 PM PDT 24 |
Jul 15 08:22:00 PM PDT 24 |
2862790544 ps |
| T945 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.339878966 |
|
|
Jul 15 08:04:05 PM PDT 24 |
Jul 15 08:21:35 PM PDT 24 |
7766074266 ps |
| T946 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1662406163 |
|
|
Jul 15 08:12:09 PM PDT 24 |
Jul 15 09:19:26 PM PDT 24 |
14685396934 ps |
| T408 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3133823229 |
|
|
Jul 15 08:32:40 PM PDT 24 |
Jul 15 08:40:47 PM PDT 24 |
4312534680 ps |
| T750 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3984158495 |
|
|
Jul 15 08:29:20 PM PDT 24 |
Jul 15 08:37:39 PM PDT 24 |
4119150280 ps |
| T732 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3547572327 |
|
|
Jul 15 08:16:50 PM PDT 24 |
Jul 15 08:40:41 PM PDT 24 |
9444773392 ps |
| T262 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.4191499053 |
|
|
Jul 15 08:06:31 PM PDT 24 |
Jul 15 08:38:55 PM PDT 24 |
11384008898 ps |
| T947 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.833669604 |
|
|
Jul 15 08:12:53 PM PDT 24 |
Jul 15 08:25:08 PM PDT 24 |
4731830000 ps |
| T948 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1756068086 |
|
|
Jul 15 08:11:16 PM PDT 24 |
Jul 15 08:14:36 PM PDT 24 |
2431387501 ps |
| T273 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2343200539 |
|
|
Jul 15 08:11:07 PM PDT 24 |
Jul 15 09:28:30 PM PDT 24 |
15119511955 ps |
| T949 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2806012898 |
|
|
Jul 15 08:02:01 PM PDT 24 |
Jul 15 08:09:50 PM PDT 24 |
4250650998 ps |
| T235 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2199607931 |
|
|
Jul 15 08:22:49 PM PDT 24 |
Jul 15 09:00:53 PM PDT 24 |
13348135540 ps |
| T950 |
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1108061000 |
|
|
Jul 15 08:27:50 PM PDT 24 |
Jul 15 09:18:57 PM PDT 24 |
12947783516 ps |
| T692 |
/workspace/coverage/default/0.chip_sw_edn_kat.483770504 |
|
|
Jul 15 08:06:55 PM PDT 24 |
Jul 15 08:20:49 PM PDT 24 |
3145330600 ps |
| T136 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.168511970 |
|
|
Jul 15 08:05:51 PM PDT 24 |
Jul 15 08:19:42 PM PDT 24 |
8242202400 ps |
| T951 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.542743142 |
|
|
Jul 15 08:10:34 PM PDT 24 |
Jul 15 09:35:02 PM PDT 24 |
15653968719 ps |
| T952 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1155131929 |
|
|
Jul 15 08:04:58 PM PDT 24 |
Jul 15 08:16:43 PM PDT 24 |
3702258114 ps |
| T953 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.1091884300 |
|
|
Jul 15 08:24:25 PM PDT 24 |
Jul 15 08:27:59 PM PDT 24 |
2568084848 ps |
| T738 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.563842980 |
|
|
Jul 15 08:29:51 PM PDT 24 |
Jul 15 08:35:49 PM PDT 24 |
4532206200 ps |
| T253 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3651099260 |
|
|
Jul 15 08:33:47 PM PDT 24 |
Jul 15 08:43:44 PM PDT 24 |
5615036818 ps |
| T363 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.1123850070 |
|
|
Jul 15 08:03:15 PM PDT 24 |
Jul 15 08:15:49 PM PDT 24 |
6641651776 ps |
| T954 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1404480503 |
|
|
Jul 15 08:18:21 PM PDT 24 |
Jul 15 08:26:07 PM PDT 24 |
7454833370 ps |
| T955 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.799125267 |
|
|
Jul 15 08:24:54 PM PDT 24 |
Jul 15 08:28:50 PM PDT 24 |
2861409560 ps |
| T956 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3527362811 |
|
|
Jul 15 08:04:51 PM PDT 24 |
Jul 15 08:09:19 PM PDT 24 |
2520434150 ps |
| T805 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.911748369 |
|
|
Jul 15 08:32:15 PM PDT 24 |
Jul 15 08:39:47 PM PDT 24 |
3452431400 ps |
| T274 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3405635901 |
|
|
Jul 15 08:27:57 PM PDT 24 |
Jul 15 09:19:30 PM PDT 24 |
14736165759 ps |
| T957 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.842263349 |
|
|
Jul 15 08:21:19 PM PDT 24 |
Jul 15 08:26:50 PM PDT 24 |
2704537860 ps |
| T832 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3361009061 |
|
|
Jul 15 08:29:02 PM PDT 24 |
Jul 15 08:33:55 PM PDT 24 |
3636739840 ps |
| T263 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.567943393 |
|
|
Jul 15 08:05:00 PM PDT 24 |
Jul 15 08:35:09 PM PDT 24 |
11010784701 ps |
| T958 |
/workspace/coverage/default/1.chip_sw_aes_entropy.2575855487 |
|
|
Jul 15 08:09:55 PM PDT 24 |
Jul 15 08:14:02 PM PDT 24 |
3121390782 ps |
| T275 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.200608691 |
|
|
Jul 15 08:09:35 PM PDT 24 |
Jul 15 09:28:20 PM PDT 24 |
22543452096 ps |
| T793 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.770395558 |
|
|
Jul 15 08:30:38 PM PDT 24 |
Jul 15 08:40:56 PM PDT 24 |
6392434280 ps |
| T216 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3229533572 |
|
|
Jul 15 08:08:24 PM PDT 24 |
Jul 15 09:12:45 PM PDT 24 |
20656521014 ps |
| T959 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2530697527 |
|
|
Jul 15 08:25:11 PM PDT 24 |
Jul 15 08:36:53 PM PDT 24 |
4531893121 ps |
| T960 |
/workspace/coverage/default/0.chip_sw_example_concurrency.471939183 |
|
|
Jul 15 08:02:29 PM PDT 24 |
Jul 15 08:07:21 PM PDT 24 |
3682512632 ps |
| T114 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3863825834 |
|
|
Jul 15 08:23:03 PM PDT 24 |
Jul 15 08:32:26 PM PDT 24 |
4377377037 ps |
| T69 |
/workspace/coverage/default/4.chip_tap_straps_rma.2270973335 |
|
|
Jul 15 08:26:00 PM PDT 24 |
Jul 15 08:30:59 PM PDT 24 |
3820703126 ps |
| T961 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3951260734 |
|
|
Jul 15 08:06:47 PM PDT 24 |
Jul 15 08:17:22 PM PDT 24 |
4991024950 ps |
| T32 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.4201878408 |
|
|
Jul 15 08:01:59 PM PDT 24 |
Jul 15 08:48:35 PM PDT 24 |
11821013998 ps |
| T242 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.43838069 |
|
|
Jul 15 08:18:45 PM PDT 24 |
Jul 15 08:25:39 PM PDT 24 |
5436898275 ps |
| T276 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.1242034818 |
|
|
Jul 15 08:02:20 PM PDT 24 |
Jul 15 08:15:50 PM PDT 24 |
4757662218 ps |
| T277 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.1164392759 |
|
|
Jul 15 08:05:11 PM PDT 24 |
Jul 15 08:26:19 PM PDT 24 |
5146486318 ps |
| T7 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.4159715568 |
|
|
Jul 15 08:05:30 PM PDT 24 |
Jul 15 08:11:51 PM PDT 24 |
4308623030 ps |
| T278 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3450137373 |
|
|
Jul 15 08:29:16 PM PDT 24 |
Jul 15 08:39:49 PM PDT 24 |
4374569552 ps |
| T279 |
/workspace/coverage/default/2.chip_sw_example_rom.3436757072 |
|
|
Jul 15 08:17:07 PM PDT 24 |
Jul 15 08:19:42 PM PDT 24 |
2493822540 ps |
| T280 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3409332287 |
|
|
Jul 15 08:20:52 PM PDT 24 |
Jul 15 08:26:07 PM PDT 24 |
2944329848 ps |
| T281 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2514074903 |
|
|
Jul 15 08:03:04 PM PDT 24 |
Jul 15 08:25:21 PM PDT 24 |
9101173592 ps |
| T282 |
/workspace/coverage/default/2.chip_sw_kmac_idle.2180603270 |
|
|
Jul 15 08:23:39 PM PDT 24 |
Jul 15 08:27:14 PM PDT 24 |
2577552908 ps |
| T63 |
/workspace/coverage/default/1.chip_sw_alert_test.2024710974 |
|
|
Jul 15 08:09:35 PM PDT 24 |
Jul 15 08:14:39 PM PDT 24 |
2464977312 ps |
| T209 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2023747706 |
|
|
Jul 15 08:19:53 PM PDT 24 |
Jul 15 08:25:44 PM PDT 24 |
2967330224 ps |
| T446 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.4129205416 |
|
|
Jul 15 08:11:58 PM PDT 24 |
Jul 15 08:56:06 PM PDT 24 |
11617222947 ps |
| T447 |
/workspace/coverage/default/0.chip_sw_aes_enc.645747745 |
|
|
Jul 15 08:02:52 PM PDT 24 |
Jul 15 08:07:23 PM PDT 24 |
2778729612 ps |
| T962 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3697927849 |
|
|
Jul 15 08:13:07 PM PDT 24 |
Jul 15 08:19:40 PM PDT 24 |
4306011640 ps |
| T326 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.1068330887 |
|
|
Jul 15 08:06:00 PM PDT 24 |
Jul 15 08:35:18 PM PDT 24 |
7517770592 ps |
| T963 |
/workspace/coverage/default/1.chip_sw_aes_idle.3026147621 |
|
|
Jul 15 08:08:26 PM PDT 24 |
Jul 15 08:11:15 PM PDT 24 |
2702123000 ps |
| T765 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1695022898 |
|
|
Jul 15 08:34:08 PM PDT 24 |
Jul 15 08:40:20 PM PDT 24 |
4129148500 ps |
| T453 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2708753852 |
|
|
Jul 15 08:10:29 PM PDT 24 |
Jul 15 08:27:33 PM PDT 24 |
5952559382 ps |
| T964 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.112561589 |
|
|
Jul 15 08:25:26 PM PDT 24 |
Jul 15 08:34:49 PM PDT 24 |
6732083135 ps |
| T822 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.824949339 |
|
|
Jul 15 08:33:40 PM PDT 24 |
Jul 15 08:41:20 PM PDT 24 |
5800067520 ps |
| T757 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.457832282 |
|
|
Jul 15 08:32:59 PM PDT 24 |
Jul 15 08:41:53 PM PDT 24 |
4588754760 ps |
| T184 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3161627707 |
|
|
Jul 15 08:23:17 PM PDT 24 |
Jul 15 08:28:20 PM PDT 24 |
2913369784 ps |
| T965 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2760641804 |
|
|
Jul 15 08:12:11 PM PDT 24 |
Jul 15 09:53:19 PM PDT 24 |
24460570900 ps |
| T347 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1107207295 |
|
|
Jul 15 08:08:44 PM PDT 24 |
Jul 15 08:19:33 PM PDT 24 |
3756536310 ps |
| T966 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.1522717757 |
|
|
Jul 15 08:06:43 PM PDT 24 |
Jul 15 08:11:33 PM PDT 24 |
3413583050 ps |
| T967 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.4246434697 |
|
|
Jul 15 08:08:37 PM PDT 24 |
Jul 15 08:25:49 PM PDT 24 |
5986710776 ps |
| T16 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1319790537 |
|
|
Jul 15 08:14:40 PM PDT 24 |
Jul 15 08:43:24 PM PDT 24 |
24479594686 ps |
| T968 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2325591006 |
|
|
Jul 15 08:19:41 PM PDT 24 |
Jul 15 08:32:45 PM PDT 24 |
7132644107 ps |
| T969 |
/workspace/coverage/default/0.chip_tap_straps_prod.3615378987 |
|
|
Jul 15 08:04:27 PM PDT 24 |
Jul 15 08:07:18 PM PDT 24 |
2686603835 ps |
| T970 |
/workspace/coverage/default/2.rom_e2e_static_critical.2894817012 |
|
|
Jul 15 08:26:55 PM PDT 24 |
Jul 15 09:47:59 PM PDT 24 |
16707875804 ps |
| T79 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2442994432 |
|
|
Jul 15 08:33:36 PM PDT 24 |
Jul 15 08:39:46 PM PDT 24 |
3500300684 ps |
| T87 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.222428424 |
|
|
Jul 15 08:08:43 PM PDT 24 |
Jul 15 08:21:58 PM PDT 24 |
5461182820 ps |
| T88 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.3886698948 |
|
|
Jul 15 08:18:48 PM PDT 24 |
Jul 15 09:23:02 PM PDT 24 |
15529204528 ps |
| T89 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1491093889 |
|
|
Jul 15 08:04:16 PM PDT 24 |
Jul 15 08:16:03 PM PDT 24 |
5012429684 ps |
| T90 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.487266285 |
|
|
Jul 15 08:06:11 PM PDT 24 |
Jul 15 08:11:49 PM PDT 24 |
4701063200 ps |
| T91 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2982678992 |
|
|
Jul 15 08:26:11 PM PDT 24 |
Jul 15 08:40:15 PM PDT 24 |
6011024560 ps |
| T92 |
/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2142649400 |
|
|
Jul 15 08:11:03 PM PDT 24 |
Jul 15 08:20:57 PM PDT 24 |
4795126250 ps |
| T93 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.3282823173 |
|
|
Jul 15 08:13:55 PM PDT 24 |
Jul 15 08:26:56 PM PDT 24 |
4261311352 ps |
| T10 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2614384044 |
|
|
Jul 15 08:16:53 PM PDT 24 |
Jul 15 08:20:42 PM PDT 24 |
2719536270 ps |
| T94 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.2873618261 |
|
|
Jul 15 08:30:46 PM PDT 24 |
Jul 15 08:42:59 PM PDT 24 |
6110891636 ps |
| T434 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.4063228865 |
|
|
Jul 15 08:04:10 PM PDT 24 |
Jul 15 08:15:00 PM PDT 24 |
7282844362 ps |
| T201 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3613211057 |
|
|
Jul 15 08:17:28 PM PDT 24 |
Jul 15 08:25:51 PM PDT 24 |
4553305952 ps |
| T251 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3441731041 |
|
|
Jul 15 08:07:19 PM PDT 24 |
Jul 15 08:17:50 PM PDT 24 |
5044761728 ps |
| T151 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3810318289 |
|
|
Jul 15 08:04:51 PM PDT 24 |
Jul 15 09:01:11 PM PDT 24 |
16676485728 ps |
| T435 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1932105913 |
|
|
Jul 15 08:05:42 PM PDT 24 |
Jul 15 08:11:18 PM PDT 24 |
5155896600 ps |
| T436 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.819951075 |
|
|
Jul 15 08:17:34 PM PDT 24 |
Jul 15 08:29:49 PM PDT 24 |
3890422500 ps |
| T437 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1149731775 |
|
|
Jul 15 08:29:52 PM PDT 24 |
Jul 15 08:37:04 PM PDT 24 |
3895734432 ps |
| T70 |
/workspace/coverage/default/0.chip_tap_straps_rma.1857534461 |
|
|
Jul 15 08:06:01 PM PDT 24 |
Jul 15 08:15:40 PM PDT 24 |
5629594672 ps |
| T376 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3263052238 |
|
|
Jul 15 08:03:37 PM PDT 24 |
Jul 15 08:10:37 PM PDT 24 |
3274423520 ps |
| T373 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.2739767859 |
|
|
Jul 15 08:17:32 PM PDT 24 |
Jul 15 09:36:07 PM PDT 24 |
26745555864 ps |
| T50 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.3041926197 |
|
|
Jul 15 08:03:08 PM PDT 24 |
Jul 15 08:09:56 PM PDT 24 |
3727965948 ps |
| T971 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.690107016 |
|
|
Jul 15 08:23:09 PM PDT 24 |
Jul 15 08:40:45 PM PDT 24 |
7294563368 ps |
| T152 |
/workspace/coverage/default/1.rom_raw_unlock.3725989900 |
|
|
Jul 15 08:15:08 PM PDT 24 |
Jul 15 08:19:31 PM PDT 24 |
5612058723 ps |
| T972 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1115836586 |
|
|
Jul 15 08:27:34 PM PDT 24 |
Jul 15 08:54:21 PM PDT 24 |
8654588092 ps |
| T706 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.1988209773 |
|
|
Jul 15 08:23:53 PM PDT 24 |
Jul 15 08:25:43 PM PDT 24 |
1868055890 ps |
| T973 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3280556949 |
|
|
Jul 15 08:21:59 PM PDT 24 |
Jul 15 08:29:15 PM PDT 24 |
3596724572 ps |
| T974 |
/workspace/coverage/default/3.chip_tap_straps_dev.3534382206 |
|
|
Jul 15 08:25:18 PM PDT 24 |
Jul 15 08:30:01 PM PDT 24 |
2966854130 ps |
| T533 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2523739144 |
|
|
Jul 15 08:05:09 PM PDT 24 |
Jul 15 08:18:29 PM PDT 24 |
4486171568 ps |
| T80 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.2453354805 |
|
|
Jul 15 08:09:53 PM PDT 24 |
Jul 15 08:14:26 PM PDT 24 |
3632453539 ps |
| T356 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2533656969 |
|
|
Jul 15 08:04:38 PM PDT 24 |
Jul 15 08:15:35 PM PDT 24 |
4682273809 ps |
| T975 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1735909617 |
|
|
Jul 15 08:12:13 PM PDT 24 |
Jul 15 08:22:16 PM PDT 24 |
5196501834 ps |
| T976 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.423705848 |
|
|
Jul 15 08:27:47 PM PDT 24 |
Jul 15 08:39:26 PM PDT 24 |
4570225720 ps |
| T783 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.2058911568 |
|
|
Jul 15 08:30:49 PM PDT 24 |
Jul 15 08:42:52 PM PDT 24 |
4420099498 ps |
| T977 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1970035918 |
|
|
Jul 15 08:02:10 PM PDT 24 |
Jul 15 08:07:57 PM PDT 24 |
5367032582 ps |
| T978 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1885141293 |
|
|
Jul 15 08:06:28 PM PDT 24 |
Jul 15 08:56:27 PM PDT 24 |
31626443085 ps |
| T166 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2457989290 |
|
|
Jul 15 08:32:07 PM PDT 24 |
Jul 15 08:41:15 PM PDT 24 |
4789507904 ps |
| T979 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1850929213 |
|
|
Jul 15 08:13:09 PM PDT 24 |
Jul 15 08:26:35 PM PDT 24 |
5387673016 ps |
| T210 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1699794533 |
|
|
Jul 15 08:07:47 PM PDT 24 |
Jul 15 08:36:47 PM PDT 24 |
24842288404 ps |
| T775 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.1680620986 |
|
|
Jul 15 08:29:25 PM PDT 24 |
Jul 15 08:41:01 PM PDT 24 |
5567726988 ps |
| T95 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2148167611 |
|
|
Jul 15 08:07:46 PM PDT 24 |
Jul 15 08:34:20 PM PDT 24 |
22486516408 ps |
| T321 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1944631188 |
|
|
Jul 15 08:04:06 PM PDT 24 |
Jul 15 08:13:20 PM PDT 24 |
5025187580 ps |
| T11 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2146143691 |
|
|
Jul 15 08:05:48 PM PDT 24 |
Jul 15 08:37:37 PM PDT 24 |
20990956422 ps |
| T755 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.214400992 |
|
|
Jul 15 08:29:18 PM PDT 24 |
Jul 15 08:44:44 PM PDT 24 |
5118699068 ps |
| T760 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3604420177 |
|
|
Jul 15 08:31:16 PM PDT 24 |
Jul 15 08:38:51 PM PDT 24 |
4371982552 ps |
| T980 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.4158241525 |
|
|
Jul 15 08:21:16 PM PDT 24 |
Jul 15 08:25:00 PM PDT 24 |
3035092680 ps |
| T338 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3298757993 |
|
|
Jul 15 08:18:36 PM PDT 24 |
Jul 15 08:44:34 PM PDT 24 |
13075713256 ps |
| T96 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3367761786 |
|
|
Jul 15 08:23:44 PM PDT 24 |
Jul 15 08:51:23 PM PDT 24 |
22890514712 ps |
| T981 |
/workspace/coverage/default/1.chip_sw_kmac_idle.1199932854 |
|
|
Jul 15 08:11:01 PM PDT 24 |
Jul 15 08:14:13 PM PDT 24 |
2839111312 ps |
| T8 |
/workspace/coverage/default/1.chip_jtag_csr_rw.3597602260 |
|
|
Jul 15 08:04:56 PM PDT 24 |
Jul 15 08:25:31 PM PDT 24 |
13217753638 ps |
| T425 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2412698516 |
|
|
Jul 15 08:32:18 PM PDT 24 |
Jul 15 08:40:52 PM PDT 24 |
4856087922 ps |
| T426 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1601613469 |
|
|
Jul 15 08:28:18 PM PDT 24 |
Jul 15 08:35:43 PM PDT 24 |
6255537193 ps |
| T427 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.1021883746 |
|
|
Jul 15 08:30:12 PM PDT 24 |
Jul 15 08:43:07 PM PDT 24 |
4659779792 ps |
| T428 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.373667222 |
|
|
Jul 15 08:03:31 PM PDT 24 |
Jul 15 08:14:24 PM PDT 24 |
3874461672 ps |
| T429 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2297773803 |
|
|
Jul 15 08:14:47 PM PDT 24 |
Jul 15 09:25:29 PM PDT 24 |
14803469480 ps |
| T430 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1757341549 |
|
|
Jul 15 08:09:35 PM PDT 24 |
Jul 15 08:31:31 PM PDT 24 |
15740145272 ps |
| T431 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.4079716848 |
|
|
Jul 15 08:18:59 PM PDT 24 |
Jul 15 09:13:47 PM PDT 24 |
14234450461 ps |
| T432 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.2265164013 |
|
|
Jul 15 08:15:02 PM PDT 24 |
Jul 15 08:19:30 PM PDT 24 |
2654630784 ps |
| T433 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.854320080 |
|
|
Jul 15 08:30:33 PM PDT 24 |
Jul 15 08:37:37 PM PDT 24 |
3630471100 ps |
| T982 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.4261668616 |
|
|
Jul 15 08:04:01 PM PDT 24 |
Jul 15 08:14:49 PM PDT 24 |
5300307798 ps |
| T983 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2207847606 |
|
|
Jul 15 08:10:33 PM PDT 24 |
Jul 15 09:08:07 PM PDT 24 |
15304365248 ps |
| T167 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.273238780 |
|
|
Jul 15 08:04:02 PM PDT 24 |
Jul 15 08:13:33 PM PDT 24 |
4744061668 ps |
| T355 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3436250927 |
|
|
Jul 15 08:25:32 PM PDT 24 |
Jul 15 08:30:36 PM PDT 24 |
3071096267 ps |
| T984 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.699580331 |
|
|
Jul 15 08:11:16 PM PDT 24 |
Jul 15 08:15:44 PM PDT 24 |
2801885719 ps |
| T202 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2465745949 |
|
|
Jul 15 08:03:14 PM PDT 24 |
Jul 15 08:16:41 PM PDT 24 |
7833260899 ps |
| T256 |
/workspace/coverage/default/1.chip_jtag_mem_access.3404363797 |
|
|
Jul 15 08:05:02 PM PDT 24 |
Jul 15 08:33:02 PM PDT 24 |
14355184250 ps |
| T419 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1005918060 |
|
|
Jul 15 08:04:09 PM PDT 24 |
Jul 15 08:07:40 PM PDT 24 |
3152805344 ps |
| T985 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.4103966660 |
|
|
Jul 15 08:07:12 PM PDT 24 |
Jul 15 08:13:10 PM PDT 24 |
4714842744 ps |
| T986 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3825313342 |
|
|
Jul 15 08:27:26 PM PDT 24 |
Jul 15 08:50:30 PM PDT 24 |
7526666752 ps |
| T987 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2200273601 |
|
|
Jul 15 08:27:59 PM PDT 24 |
Jul 15 08:46:44 PM PDT 24 |
13576164156 ps |
| T988 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1945687238 |
|
|
Jul 15 08:22:27 PM PDT 24 |
Jul 15 08:31:16 PM PDT 24 |
8124225716 ps |
| T9 |
/workspace/coverage/default/2.chip_jtag_csr_rw.1672312029 |
|
|
Jul 15 08:15:05 PM PDT 24 |
Jul 15 08:56:56 PM PDT 24 |
20577481712 ps |
| T14 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1325876493 |
|
|
Jul 15 08:02:06 PM PDT 24 |
Jul 15 08:07:43 PM PDT 24 |
4511685828 ps |
| T366 |
/workspace/coverage/default/1.chip_sw_hmac_enc.3044667291 |
|
|
Jul 15 08:10:21 PM PDT 24 |
Jul 15 08:14:16 PM PDT 24 |
2834905104 ps |
| T359 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.3513588832 |
|
|
Jul 15 08:16:17 PM PDT 24 |
Jul 15 08:20:05 PM PDT 24 |
2655925110 ps |
| T989 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3152330699 |
|
|
Jul 15 08:18:41 PM PDT 24 |
Jul 15 08:28:50 PM PDT 24 |
8044035879 ps |
| T990 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.2470424738 |
|
|
Jul 15 08:20:13 PM PDT 24 |
Jul 15 08:42:57 PM PDT 24 |
5724903216 ps |
| T991 |
/workspace/coverage/default/0.chip_sw_aes_entropy.2665144373 |
|
|
Jul 15 08:09:58 PM PDT 24 |
Jul 15 08:15:02 PM PDT 24 |
2450959520 ps |
| T284 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1967231335 |
|
|
Jul 15 08:27:18 PM PDT 24 |
Jul 15 08:37:43 PM PDT 24 |
5503446408 ps |
| T992 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.180135090 |
|
|
Jul 15 08:05:56 PM PDT 24 |
Jul 15 08:26:12 PM PDT 24 |
6330481880 ps |
| T993 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3131938332 |
|
|
Jul 15 08:03:49 PM PDT 24 |
Jul 15 08:44:59 PM PDT 24 |
10678670864 ps |
| T994 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1922529264 |
|
|
Jul 15 08:29:25 PM PDT 24 |
Jul 15 08:35:54 PM PDT 24 |
3699933768 ps |
| T995 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1719991144 |
|
|
Jul 15 08:08:19 PM PDT 24 |
Jul 15 08:19:42 PM PDT 24 |
3761990872 ps |
| T996 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1802212896 |
|
|
Jul 15 08:33:50 PM PDT 24 |
Jul 15 08:45:04 PM PDT 24 |
4545320498 ps |
| T702 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1491080489 |
|
|
Jul 15 08:12:19 PM PDT 24 |
Jul 15 08:22:45 PM PDT 24 |
5361991068 ps |
| T997 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2947676641 |
|
|
Jul 15 08:03:16 PM PDT 24 |
Jul 15 08:09:04 PM PDT 24 |
4834543312 ps |
| T998 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3982203400 |
|
|
Jul 15 08:13:54 PM PDT 24 |
Jul 15 09:26:33 PM PDT 24 |
13667429562 ps |
| T438 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1856233318 |
|
|
Jul 15 08:13:51 PM PDT 24 |
Jul 15 08:36:24 PM PDT 24 |
20560672280 ps |
| T999 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1196555874 |
|
|
Jul 15 08:32:00 PM PDT 24 |
Jul 15 08:39:50 PM PDT 24 |
5538610620 ps |
| T704 |
/workspace/coverage/default/0.chip_tap_straps_dev.355200870 |
|
|
Jul 15 08:06:39 PM PDT 24 |
Jul 15 08:38:39 PM PDT 24 |
16158563988 ps |
| T1000 |
/workspace/coverage/default/1.rom_keymgr_functest.369751477 |
|
|
Jul 15 08:15:09 PM PDT 24 |
Jul 15 08:22:40 PM PDT 24 |
4992575654 ps |
| T1001 |
/workspace/coverage/default/1.chip_sw_flash_init.1349986898 |
|
|
Jul 15 08:06:49 PM PDT 24 |
Jul 15 08:35:00 PM PDT 24 |
19904311924 ps |
| T1002 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2591718094 |
|
|
Jul 15 08:21:31 PM PDT 24 |
Jul 15 08:33:34 PM PDT 24 |
3814209508 ps |
| T826 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.1646034217 |
|
|
Jul 15 08:30:39 PM PDT 24 |
Jul 15 08:40:14 PM PDT 24 |
5649561432 ps |
| T1003 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3806201801 |
|
|
Jul 15 08:03:39 PM PDT 24 |
Jul 15 09:10:57 PM PDT 24 |
19129152741 ps |
| T1004 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3568120187 |
|
|
Jul 15 08:06:42 PM PDT 24 |
Jul 15 08:53:08 PM PDT 24 |
13357861320 ps |
| T258 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.477333333 |
|
|
Jul 15 08:23:45 PM PDT 24 |
Jul 15 08:30:42 PM PDT 24 |
4291231716 ps |
| T715 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.1141472341 |
|
|
Jul 15 08:02:34 PM PDT 24 |
Jul 15 08:06:56 PM PDT 24 |
3191812616 ps |
| T729 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.3791034738 |
|
|
Jul 15 08:26:01 PM PDT 24 |
Jul 15 08:38:27 PM PDT 24 |
4803067240 ps |
| T1005 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.2000572859 |
|
|
Jul 15 08:08:22 PM PDT 24 |
Jul 15 08:13:10 PM PDT 24 |
2969678804 ps |
| T1006 |
/workspace/coverage/default/1.chip_tap_straps_prod.3043078921 |
|
|
Jul 15 08:11:39 PM PDT 24 |
Jul 15 08:20:26 PM PDT 24 |
5458529372 ps |
| T1007 |
/workspace/coverage/default/1.chip_sw_hmac_multistream.762650353 |
|
|
Jul 15 08:11:32 PM PDT 24 |
Jul 15 08:39:15 PM PDT 24 |
7638399370 ps |
| T236 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.904411012 |
|
|
Jul 15 08:11:00 PM PDT 24 |
Jul 15 08:29:10 PM PDT 24 |
7289229774 ps |
| T187 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.818259186 |
|
|
Jul 15 08:07:52 PM PDT 24 |
Jul 15 09:30:54 PM PDT 24 |
43596689820 ps |
| T176 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.541672342 |
|
|
Jul 15 08:04:30 PM PDT 24 |
Jul 15 08:07:20 PM PDT 24 |
3318510323 ps |
| T831 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.4128845201 |
|
|
Jul 15 08:33:37 PM PDT 24 |
Jul 15 08:42:09 PM PDT 24 |
5580762280 ps |
| T1008 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2600217690 |
|
|
Jul 15 08:24:20 PM PDT 24 |
Jul 15 08:33:34 PM PDT 24 |
4155312600 ps |
| T1009 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3118716102 |
|
|
Jul 15 08:17:22 PM PDT 24 |
Jul 15 09:48:05 PM PDT 24 |
47170272833 ps |
| T1010 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.242361039 |
|
|
Jul 15 08:27:01 PM PDT 24 |
Jul 15 08:29:48 PM PDT 24 |
2275254648 ps |
| T1011 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1993110701 |
|
|
Jul 15 08:31:00 PM PDT 24 |
Jul 15 08:36:24 PM PDT 24 |
3622654220 ps |
| T809 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2811506616 |
|
|
Jul 15 08:33:23 PM PDT 24 |
Jul 15 08:41:13 PM PDT 24 |
5078630522 ps |
| T1012 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1560888166 |
|
|
Jul 15 08:04:35 PM PDT 24 |
Jul 15 08:14:15 PM PDT 24 |
6639037175 ps |
| T1013 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.960563445 |
|
|
Jul 15 08:18:52 PM PDT 24 |
Jul 15 08:27:02 PM PDT 24 |
4358020320 ps |
| T1014 |
/workspace/coverage/default/1.chip_sw_example_concurrency.3424657764 |
|
|
Jul 15 08:10:03 PM PDT 24 |
Jul 15 08:13:29 PM PDT 24 |
2035103490 ps |
| T771 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3878054463 |
|
|
Jul 15 08:19:35 PM PDT 24 |
Jul 15 08:25:35 PM PDT 24 |
3504353040 ps |
| T534 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.220702345 |
|
|
Jul 15 08:11:29 PM PDT 24 |
Jul 15 08:27:28 PM PDT 24 |
5007460030 ps |
| T177 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2234425343 |
|
|
Jul 15 08:04:04 PM PDT 24 |
Jul 15 08:07:06 PM PDT 24 |
3349766444 ps |
| T153 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1274574720 |
|
|
Jul 15 08:04:11 PM PDT 24 |
Jul 15 10:49:59 PM PDT 24 |
59519870123 ps |
| T773 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.2798156078 |
|
|
Jul 15 08:30:44 PM PDT 24 |
Jul 15 08:41:16 PM PDT 24 |
6291446542 ps |
| T1015 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2133741131 |
|
|
Jul 15 08:08:31 PM PDT 24 |
Jul 15 09:44:10 PM PDT 24 |
47052970472 ps |
| T1016 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.1694499326 |
|
|
Jul 15 08:08:46 PM PDT 24 |
Jul 15 08:17:33 PM PDT 24 |
5361547440 ps |
| T219 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2773532639 |
|
|
Jul 15 08:05:04 PM PDT 24 |
Jul 15 08:34:00 PM PDT 24 |
7238693184 ps |
| T406 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3057420469 |
|
|
Jul 15 08:22:50 PM PDT 24 |
Jul 15 08:26:20 PM PDT 24 |
3034912052 ps |
| T1017 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1067153588 |
|
|
Jul 15 08:16:39 PM PDT 24 |
Jul 15 08:21:17 PM PDT 24 |
3016723940 ps |
| T795 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3266391851 |
|
|
Jul 15 08:34:04 PM PDT 24 |
Jul 15 08:39:52 PM PDT 24 |
4003044788 ps |
| T1018 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3923740374 |
|
|
Jul 15 08:28:15 PM PDT 24 |
Jul 15 09:09:02 PM PDT 24 |
12930264460 ps |
| T421 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3747035429 |
|
|
Jul 15 08:06:45 PM PDT 24 |
Jul 15 08:16:25 PM PDT 24 |
9374117587 ps |
| T1019 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.445672744 |
|
|
Jul 15 08:11:11 PM PDT 24 |
Jul 15 08:14:47 PM PDT 24 |
3085322818 ps |
| T1020 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2522571585 |
|
|
Jul 15 08:27:07 PM PDT 24 |
Jul 15 08:37:07 PM PDT 24 |
4229321916 ps |
| T707 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.907227935 |
|
|
Jul 15 08:02:16 PM PDT 24 |
Jul 15 08:04:23 PM PDT 24 |
2386467931 ps |
| T1021 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2417877445 |
|
|
Jul 15 08:04:44 PM PDT 24 |
Jul 15 08:10:50 PM PDT 24 |
6476100512 ps |
| T1022 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2475342271 |
|
|
Jul 15 08:25:49 PM PDT 24 |
Jul 15 08:36:19 PM PDT 24 |
4334628062 ps |
| T1023 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1889327599 |
|
|
Jul 15 08:22:45 PM PDT 24 |
Jul 15 08:28:16 PM PDT 24 |
3305616736 ps |
| T787 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3502996905 |
|
|
Jul 15 08:33:33 PM PDT 24 |
Jul 15 08:44:51 PM PDT 24 |
5755640968 ps |
| T1024 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.920428223 |
|
|
Jul 15 08:18:50 PM PDT 24 |
Jul 15 08:27:27 PM PDT 24 |
7275423691 ps |
| T1025 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2067124334 |
|
|
Jul 15 08:15:51 PM PDT 24 |
Jul 15 08:18:33 PM PDT 24 |
2399047917 ps |
| T398 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1559990067 |
|
|
Jul 15 08:10:50 PM PDT 24 |
Jul 15 08:13:40 PM PDT 24 |
2469116608 ps |
| T155 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.1025566026 |
|
|
Jul 15 08:05:38 PM PDT 24 |
Jul 15 08:16:16 PM PDT 24 |
3386685100 ps |
| T36 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3916724975 |
|
|
Jul 15 08:03:25 PM PDT 24 |
Jul 15 09:54:16 PM PDT 24 |
31299477536 ps |
| T243 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3151521507 |
|
|
Jul 15 08:22:53 PM PDT 24 |
Jul 15 08:58:03 PM PDT 24 |
27023223941 ps |
| T328 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.2864026707 |
|
|
Jul 15 08:32:31 PM PDT 24 |
Jul 15 08:40:36 PM PDT 24 |
5050675392 ps |
| T1026 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2195039559 |
|
|
Jul 15 08:22:02 PM PDT 24 |
Jul 15 08:30:46 PM PDT 24 |
4662119473 ps |
| T364 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1774505878 |
|
|
Jul 15 08:05:59 PM PDT 24 |
Jul 15 08:10:35 PM PDT 24 |
2258329348 ps |
| T1027 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3360901320 |
|
|
Jul 15 08:19:34 PM PDT 24 |
Jul 15 08:25:01 PM PDT 24 |
4685439320 ps |
| T823 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1001479237 |
|
|
Jul 15 08:28:56 PM PDT 24 |
Jul 15 08:34:11 PM PDT 24 |
3488954380 ps |
| T719 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.2143456950 |
|
|
Jul 15 08:15:43 PM PDT 24 |
Jul 15 08:19:57 PM PDT 24 |
3448150260 ps |
| T1028 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.174725313 |
|
|
Jul 15 08:03:38 PM PDT 24 |
Jul 15 08:07:48 PM PDT 24 |
2475323656 ps |
| T1029 |
/workspace/coverage/default/1.chip_sival_flash_info_access.2465722630 |
|
|
Jul 15 08:05:39 PM PDT 24 |
Jul 15 08:10:31 PM PDT 24 |
3086058504 ps |
| T1030 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.870609044 |
|
|
Jul 15 08:02:06 PM PDT 24 |
Jul 15 08:06:25 PM PDT 24 |
3148648217 ps |
| T1031 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.569429227 |
|
|
Jul 15 08:15:08 PM PDT 24 |
Jul 15 08:20:26 PM PDT 24 |
3005273209 ps |