| T1171 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1920256582 |
|
|
Jul 15 08:24:21 PM PDT 24 |
Jul 15 08:29:35 PM PDT 24 |
3396000285 ps |
| T168 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.2676212778 |
|
|
Jul 15 08:23:27 PM PDT 24 |
Jul 15 08:32:46 PM PDT 24 |
4391305960 ps |
| T689 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.890869352 |
|
|
Jul 15 08:03:31 PM PDT 24 |
Jul 15 08:12:49 PM PDT 24 |
2745712306 ps |
| T1172 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1617520592 |
|
|
Jul 15 08:32:38 PM PDT 24 |
Jul 15 08:42:38 PM PDT 24 |
5907079704 ps |
| T169 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.2954331328 |
|
|
Jul 15 08:11:43 PM PDT 24 |
Jul 15 08:22:40 PM PDT 24 |
6081896604 ps |
| T766 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.4274830236 |
|
|
Jul 15 08:32:52 PM PDT 24 |
Jul 15 08:39:46 PM PDT 24 |
3758674660 ps |
| T1173 |
/workspace/coverage/default/1.chip_sw_example_rom.3847369937 |
|
|
Jul 15 08:08:09 PM PDT 24 |
Jul 15 08:10:03 PM PDT 24 |
3157165640 ps |
| T1174 |
/workspace/coverage/default/0.chip_sw_aes_idle.2788624913 |
|
|
Jul 15 08:03:49 PM PDT 24 |
Jul 15 08:08:38 PM PDT 24 |
3275927530 ps |
| T1175 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3550405827 |
|
|
Jul 15 08:30:58 PM PDT 24 |
Jul 15 08:39:17 PM PDT 24 |
3562345550 ps |
| T1176 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.845445180 |
|
|
Jul 15 08:33:00 PM PDT 24 |
Jul 15 08:39:13 PM PDT 24 |
3674437758 ps |
| T808 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1405901866 |
|
|
Jul 15 08:29:46 PM PDT 24 |
Jul 15 08:36:34 PM PDT 24 |
3280342920 ps |
| T1177 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2562193536 |
|
|
Jul 15 08:10:33 PM PDT 24 |
Jul 15 09:14:00 PM PDT 24 |
14670884572 ps |
| T348 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2540703342 |
|
|
Jul 15 08:10:19 PM PDT 24 |
Jul 15 08:19:01 PM PDT 24 |
3064718796 ps |
| T1178 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.451769035 |
|
|
Jul 15 08:14:55 PM PDT 24 |
Jul 15 08:27:13 PM PDT 24 |
6513032870 ps |
| T1179 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1780580655 |
|
|
Jul 15 08:06:22 PM PDT 24 |
Jul 15 08:10:56 PM PDT 24 |
2856690661 ps |
| T52 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.1844296036 |
|
|
Jul 15 08:18:29 PM PDT 24 |
Jul 15 08:24:48 PM PDT 24 |
3634300219 ps |
| T1180 |
/workspace/coverage/default/2.chip_tap_straps_rma.3026812842 |
|
|
Jul 15 08:22:50 PM PDT 24 |
Jul 15 08:25:46 PM PDT 24 |
2510128159 ps |
| T12 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2353177984 |
|
|
Jul 15 08:13:02 PM PDT 24 |
Jul 15 08:22:31 PM PDT 24 |
4122025000 ps |
| T1181 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.374619560 |
|
|
Jul 15 08:21:58 PM PDT 24 |
Jul 15 08:28:08 PM PDT 24 |
5151300728 ps |
| T336 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.4134402620 |
|
|
Jul 15 08:03:50 PM PDT 24 |
Jul 15 08:17:34 PM PDT 24 |
4268139142 ps |
| T1182 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.18299234 |
|
|
Jul 15 08:24:32 PM PDT 24 |
Jul 15 08:33:42 PM PDT 24 |
7385140850 ps |
| T1183 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.924746626 |
|
|
Jul 15 08:15:26 PM PDT 24 |
Jul 15 10:06:00 PM PDT 24 |
23590340910 ps |
| T1184 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.812489479 |
|
|
Jul 15 08:20:14 PM PDT 24 |
Jul 15 08:38:16 PM PDT 24 |
5950464080 ps |
| T24 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3973528419 |
|
|
Jul 15 08:16:35 PM PDT 24 |
Jul 15 08:21:53 PM PDT 24 |
3644281073 ps |
| T341 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2243827610 |
|
|
Jul 15 08:07:25 PM PDT 24 |
Jul 15 08:30:55 PM PDT 24 |
5427104280 ps |
| T1185 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3373159500 |
|
|
Jul 15 08:10:43 PM PDT 24 |
Jul 15 08:17:53 PM PDT 24 |
3465933780 ps |
| T248 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3726450380 |
|
|
Jul 15 08:18:03 PM PDT 24 |
Jul 15 08:25:12 PM PDT 24 |
4954903880 ps |
| T1186 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2058066364 |
|
|
Jul 15 08:01:04 PM PDT 24 |
Jul 15 08:07:22 PM PDT 24 |
4485255640 ps |
| T1187 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4116375493 |
|
|
Jul 15 08:13:10 PM PDT 24 |
Jul 15 08:24:40 PM PDT 24 |
4867875578 ps |
| T1188 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2195284112 |
|
|
Jul 15 08:09:39 PM PDT 24 |
Jul 15 08:16:28 PM PDT 24 |
18543219356 ps |
| T1189 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.287528376 |
|
|
Jul 15 08:24:51 PM PDT 24 |
Jul 15 08:40:41 PM PDT 24 |
6415165576 ps |
| T1190 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.2797704463 |
|
|
Jul 15 08:02:25 PM PDT 24 |
Jul 15 08:06:52 PM PDT 24 |
2785896152 ps |
| T1191 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.3683843736 |
|
|
Jul 15 08:33:34 PM PDT 24 |
Jul 15 08:44:33 PM PDT 24 |
5804663480 ps |
| T1192 |
/workspace/coverage/default/2.chip_sival_flash_info_access.3887459814 |
|
|
Jul 15 08:18:31 PM PDT 24 |
Jul 15 08:24:55 PM PDT 24 |
3650708656 ps |
| T1193 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.207424445 |
|
|
Jul 15 08:19:39 PM PDT 24 |
Jul 15 08:24:10 PM PDT 24 |
2382551232 ps |
| T1194 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2518032260 |
|
|
Jul 15 08:21:40 PM PDT 24 |
Jul 15 08:27:27 PM PDT 24 |
2998560120 ps |
| T1195 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.825575901 |
|
|
Jul 15 08:05:16 PM PDT 24 |
Jul 15 08:50:39 PM PDT 24 |
31709126120 ps |
| T304 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2490292459 |
|
|
Jul 15 08:13:13 PM PDT 24 |
Jul 15 08:18:59 PM PDT 24 |
3191408946 ps |
| T1196 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.310490684 |
|
|
Jul 15 08:18:52 PM PDT 24 |
Jul 15 08:22:43 PM PDT 24 |
2373560860 ps |
| T1197 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3687828849 |
|
|
Jul 15 08:17:16 PM PDT 24 |
Jul 15 08:29:08 PM PDT 24 |
4768743782 ps |
| T1198 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.4145747991 |
|
|
Jul 15 08:23:06 PM PDT 24 |
Jul 15 08:34:43 PM PDT 24 |
5097992380 ps |
| T1199 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.2285973452 |
|
|
Jul 15 08:09:30 PM PDT 24 |
Jul 15 08:11:41 PM PDT 24 |
2540632251 ps |
| T668 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1775369975 |
|
|
Jul 15 08:03:40 PM PDT 24 |
Jul 15 08:14:25 PM PDT 24 |
5211017659 ps |
| T1200 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3017151339 |
|
|
Jul 15 08:11:40 PM PDT 24 |
Jul 15 08:46:40 PM PDT 24 |
24334284232 ps |
| T1201 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2571824550 |
|
|
Jul 15 08:28:58 PM PDT 24 |
Jul 15 09:34:10 PM PDT 24 |
15490374230 ps |
| T1202 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3900834082 |
|
|
Jul 15 08:14:53 PM PDT 24 |
Jul 15 09:26:24 PM PDT 24 |
13556175853 ps |
| T1203 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2308563572 |
|
|
Jul 15 08:17:57 PM PDT 24 |
Jul 15 08:56:28 PM PDT 24 |
25608296593 ps |
| T1204 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2212495717 |
|
|
Jul 15 08:15:24 PM PDT 24 |
Jul 15 08:36:06 PM PDT 24 |
5973641318 ps |
| T1205 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3192034559 |
|
|
Jul 15 08:25:58 PM PDT 24 |
Jul 15 08:32:10 PM PDT 24 |
5623782013 ps |
| T305 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.655405511 |
|
|
Jul 15 08:24:22 PM PDT 24 |
Jul 15 08:29:03 PM PDT 24 |
2628415985 ps |
| T834 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.84856167 |
|
|
Jul 15 08:29:11 PM PDT 24 |
Jul 15 08:39:17 PM PDT 24 |
5975662820 ps |
| T1206 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3917552328 |
|
|
Jul 15 08:04:34 PM PDT 24 |
Jul 15 08:29:23 PM PDT 24 |
6804935320 ps |
| T1207 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.825789725 |
|
|
Jul 15 08:10:34 PM PDT 24 |
Jul 15 08:19:40 PM PDT 24 |
8123905500 ps |
| T350 |
/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1147749696 |
|
|
Jul 15 08:06:17 PM PDT 24 |
Jul 15 08:12:45 PM PDT 24 |
4100378982 ps |
| T1208 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2216882198 |
|
|
Jul 15 08:28:27 PM PDT 24 |
Jul 15 08:38:46 PM PDT 24 |
3785111000 ps |
| T329 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3087571268 |
|
|
Jul 15 08:32:04 PM PDT 24 |
Jul 15 08:37:26 PM PDT 24 |
4110831088 ps |
| T330 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3524707521 |
|
|
Jul 15 08:32:36 PM PDT 24 |
Jul 15 08:42:34 PM PDT 24 |
4747086856 ps |
| T1209 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.4007263436 |
|
|
Jul 15 08:08:01 PM PDT 24 |
Jul 15 08:11:22 PM PDT 24 |
3037306960 ps |
| T82 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3778616948 |
|
|
Jul 15 08:22:46 PM PDT 24 |
Jul 15 08:44:58 PM PDT 24 |
12335917900 ps |
| T1210 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.485845309 |
|
|
Jul 15 08:31:32 PM PDT 24 |
Jul 15 08:41:26 PM PDT 24 |
5960571584 ps |
| T1211 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1121889325 |
|
|
Jul 15 08:20:54 PM PDT 24 |
Jul 15 08:31:02 PM PDT 24 |
5795649360 ps |
| T379 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.4194167186 |
|
|
Jul 15 08:30:03 PM PDT 24 |
Jul 15 08:39:50 PM PDT 24 |
5448042360 ps |
| T1212 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3702808666 |
|
|
Jul 15 08:18:25 PM PDT 24 |
Jul 15 08:28:55 PM PDT 24 |
5435128560 ps |
| T1213 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.2530268980 |
|
|
Jul 15 08:15:25 PM PDT 24 |
Jul 15 08:19:32 PM PDT 24 |
2929527890 ps |
| T1214 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.3780087296 |
|
|
Jul 15 08:30:46 PM PDT 24 |
Jul 15 09:47:08 PM PDT 24 |
15659036450 ps |
| T1215 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.4232537411 |
|
|
Jul 15 08:22:47 PM PDT 24 |
Jul 15 08:27:16 PM PDT 24 |
3450739482 ps |
| T1216 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.1189371454 |
|
|
Jul 15 08:18:27 PM PDT 24 |
Jul 15 09:33:18 PM PDT 24 |
15319179200 ps |
| T762 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.4214088358 |
|
|
Jul 15 08:31:23 PM PDT 24 |
Jul 15 08:42:22 PM PDT 24 |
5979804768 ps |
| T1217 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2303337260 |
|
|
Jul 15 08:13:30 PM PDT 24 |
Jul 15 08:29:40 PM PDT 24 |
13540085683 ps |
| T777 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.326015574 |
|
|
Jul 15 08:27:21 PM PDT 24 |
Jul 15 08:38:37 PM PDT 24 |
6622676168 ps |
| T1218 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1672797980 |
|
|
Jul 15 08:27:11 PM PDT 24 |
Jul 15 08:46:37 PM PDT 24 |
13851948233 ps |
| T314 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2865320122 |
|
|
Jul 15 08:12:16 PM PDT 24 |
Jul 15 08:32:45 PM PDT 24 |
7591188479 ps |
| T380 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.1045669752 |
|
|
Jul 15 08:35:19 PM PDT 24 |
Jul 15 08:45:57 PM PDT 24 |
5145159876 ps |
| T1219 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.222100465 |
|
|
Jul 15 08:14:17 PM PDT 24 |
Jul 15 08:34:09 PM PDT 24 |
10692449632 ps |
| T1220 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2645728992 |
|
|
Jul 15 08:16:33 PM PDT 24 |
Jul 15 08:21:39 PM PDT 24 |
3453463696 ps |
| T1221 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1270797697 |
|
|
Jul 15 08:17:57 PM PDT 24 |
Jul 15 09:44:43 PM PDT 24 |
46003820170 ps |
| T1222 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.580641997 |
|
|
Jul 15 08:20:40 PM PDT 24 |
Jul 15 08:35:37 PM PDT 24 |
8794396968 ps |
| T797 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2993264489 |
|
|
Jul 15 08:07:23 PM PDT 24 |
Jul 15 08:13:39 PM PDT 24 |
4108529392 ps |
| T1223 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1271841568 |
|
|
Jul 15 08:11:10 PM PDT 24 |
Jul 16 12:06:55 AM PDT 24 |
78095947010 ps |
| T1224 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.886663747 |
|
|
Jul 15 08:09:40 PM PDT 24 |
Jul 15 08:16:51 PM PDT 24 |
4306932175 ps |
| T1225 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1912151340 |
|
|
Jul 15 08:10:37 PM PDT 24 |
Jul 15 08:42:36 PM PDT 24 |
10339482978 ps |
| T1226 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.2750865668 |
|
|
Jul 15 08:04:48 PM PDT 24 |
Jul 15 11:16:31 PM PDT 24 |
63933724225 ps |
| T806 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2809445269 |
|
|
Jul 15 08:28:21 PM PDT 24 |
Jul 15 08:34:44 PM PDT 24 |
3316350664 ps |
| T1227 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2466940538 |
|
|
Jul 15 08:14:53 PM PDT 24 |
Jul 15 08:19:36 PM PDT 24 |
3149780214 ps |
| T1228 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.4002039296 |
|
|
Jul 15 08:09:46 PM PDT 24 |
Jul 15 08:20:49 PM PDT 24 |
3955736018 ps |
| T1229 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2385557479 |
|
|
Jul 15 08:10:42 PM PDT 24 |
Jul 15 08:14:58 PM PDT 24 |
3584702834 ps |
| T249 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2045065007 |
|
|
Jul 15 08:09:04 PM PDT 24 |
Jul 15 08:23:17 PM PDT 24 |
5830431424 ps |
| T131 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4014889980 |
|
|
Jul 15 08:05:22 PM PDT 24 |
Jul 15 08:14:40 PM PDT 24 |
5412045816 ps |
| T1230 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3914925702 |
|
|
Jul 15 08:28:35 PM PDT 24 |
Jul 15 08:58:49 PM PDT 24 |
8786810226 ps |
| T1231 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.2003550231 |
|
|
Jul 15 08:07:01 PM PDT 24 |
Jul 15 08:13:00 PM PDT 24 |
3393968320 ps |
| T1232 |
/workspace/coverage/default/1.rom_e2e_static_critical.3590216363 |
|
|
Jul 15 08:20:02 PM PDT 24 |
Jul 15 09:24:08 PM PDT 24 |
16744042318 ps |
| T1233 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.914747928 |
|
|
Jul 15 08:10:31 PM PDT 24 |
Jul 15 08:37:30 PM PDT 24 |
9853302864 ps |
| T1234 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1316886671 |
|
|
Jul 15 08:19:19 PM PDT 24 |
Jul 15 08:36:34 PM PDT 24 |
10029345897 ps |
| T1235 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3290750844 |
|
|
Jul 15 08:13:59 PM PDT 24 |
Jul 15 09:40:42 PM PDT 24 |
23017303040 ps |
| T1236 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3264338306 |
|
|
Jul 15 08:05:43 PM PDT 24 |
Jul 15 08:41:41 PM PDT 24 |
12729531751 ps |
| T815 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.1747851958 |
|
|
Jul 15 08:28:03 PM PDT 24 |
Jul 15 08:38:26 PM PDT 24 |
5100519010 ps |
| T360 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.2816440386 |
|
|
Jul 15 08:02:06 PM PDT 24 |
Jul 15 08:06:29 PM PDT 24 |
3345874000 ps |
| T1237 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2408713814 |
|
|
Jul 15 08:14:47 PM PDT 24 |
Jul 15 09:28:23 PM PDT 24 |
14724007920 ps |
| T1238 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3361965493 |
|
|
Jul 15 08:27:44 PM PDT 24 |
Jul 15 09:05:13 PM PDT 24 |
13452362260 ps |
| T1239 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2657441984 |
|
|
Jul 15 08:05:28 PM PDT 24 |
Jul 15 08:10:49 PM PDT 24 |
2704836920 ps |
| T337 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.85216032 |
|
|
Jul 15 08:22:11 PM PDT 24 |
Jul 15 08:43:28 PM PDT 24 |
5763840592 ps |
| T1240 |
/workspace/coverage/default/2.chip_sw_hmac_enc.736450744 |
|
|
Jul 15 08:20:10 PM PDT 24 |
Jul 15 08:26:19 PM PDT 24 |
2626604090 ps |
| T800 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.3214541266 |
|
|
Jul 15 08:28:41 PM PDT 24 |
Jul 15 08:38:49 PM PDT 24 |
4933990084 ps |
| T1241 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1034516547 |
|
|
Jul 15 08:08:48 PM PDT 24 |
Jul 15 08:17:25 PM PDT 24 |
5362349320 ps |
| T1242 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.604423008 |
|
|
Jul 15 08:20:39 PM PDT 24 |
Jul 15 08:42:53 PM PDT 24 |
9070569254 ps |
| T769 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4162153084 |
|
|
Jul 15 08:03:44 PM PDT 24 |
Jul 15 09:14:00 PM PDT 24 |
37674671703 ps |
| T1243 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2701754819 |
|
|
Jul 15 08:23:17 PM PDT 24 |
Jul 15 09:15:47 PM PDT 24 |
24676935076 ps |
| T1244 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1014845803 |
|
|
Jul 15 08:15:51 PM PDT 24 |
Jul 15 08:18:59 PM PDT 24 |
2125208496 ps |
| T1245 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.188885513 |
|
|
Jul 15 08:12:00 PM PDT 24 |
Jul 15 08:17:20 PM PDT 24 |
2954095634 ps |
| T156 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.2059719367 |
|
|
Jul 15 08:12:00 PM PDT 24 |
Jul 15 08:21:06 PM PDT 24 |
3920475628 ps |
| T770 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3732274918 |
|
|
Jul 15 08:03:47 PM PDT 24 |
Jul 15 11:34:49 PM PDT 24 |
256588585180 ps |
| T1246 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3126162960 |
|
|
Jul 15 08:14:16 PM PDT 24 |
Jul 15 08:45:42 PM PDT 24 |
9185976568 ps |
| T1247 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3738063424 |
|
|
Jul 15 08:05:05 PM PDT 24 |
Jul 15 08:24:47 PM PDT 24 |
7589378300 ps |
| T1248 |
/workspace/coverage/default/1.chip_sw_example_flash.3626928582 |
|
|
Jul 15 08:04:59 PM PDT 24 |
Jul 15 08:07:59 PM PDT 24 |
2989347874 ps |
| T1249 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.1159308317 |
|
|
Jul 15 08:04:36 PM PDT 24 |
Jul 15 08:11:22 PM PDT 24 |
5629252590 ps |
| T1250 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1023920153 |
|
|
Jul 15 08:23:33 PM PDT 24 |
Jul 15 08:32:12 PM PDT 24 |
7290050918 ps |
| T204 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3660645405 |
|
|
Jul 15 08:09:07 PM PDT 24 |
Jul 15 08:19:17 PM PDT 24 |
5070318111 ps |
| T1251 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.574545611 |
|
|
Jul 15 08:29:13 PM PDT 24 |
Jul 15 08:38:51 PM PDT 24 |
3562375900 ps |
| T74 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.3471546589 |
|
|
Jul 15 08:04:24 PM PDT 24 |
Jul 15 08:08:57 PM PDT 24 |
2440615560 ps |
| T64 |
/workspace/coverage/default/0.chip_sw_alert_test.2166034080 |
|
|
Jul 15 08:05:57 PM PDT 24 |
Jul 15 08:13:48 PM PDT 24 |
3413086650 ps |
| T369 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.2923450103 |
|
|
Jul 15 08:10:01 PM PDT 24 |
Jul 15 08:14:32 PM PDT 24 |
3131466816 ps |
| T333 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2659945025 |
|
|
Jul 15 08:17:34 PM PDT 24 |
Jul 15 08:27:45 PM PDT 24 |
4297565914 ps |
| T1252 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.4047592249 |
|
|
Jul 15 08:30:22 PM PDT 24 |
Jul 15 08:38:21 PM PDT 24 |
4073503272 ps |
| T137 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.326145235 |
|
|
Jul 15 08:25:27 PM PDT 24 |
Jul 15 08:40:36 PM PDT 24 |
8949119994 ps |
| T1253 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2639882155 |
|
|
Jul 15 08:13:59 PM PDT 24 |
Jul 15 09:08:50 PM PDT 24 |
11940380500 ps |
| T1254 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.383596148 |
|
|
Jul 15 08:35:30 PM PDT 24 |
Jul 15 08:45:15 PM PDT 24 |
4146270920 ps |
| T342 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.4183377718 |
|
|
Jul 15 08:14:54 PM PDT 24 |
Jul 15 08:41:36 PM PDT 24 |
7577708704 ps |
| T1255 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1565656565 |
|
|
Jul 15 08:08:43 PM PDT 24 |
Jul 15 08:46:19 PM PDT 24 |
29392665120 ps |
| T1256 |
/workspace/coverage/default/0.chip_sw_power_idle_load.631480343 |
|
|
Jul 15 08:08:16 PM PDT 24 |
Jul 15 08:21:34 PM PDT 24 |
5098941652 ps |
| T65 |
/workspace/coverage/default/2.chip_sw_alert_test.2726248188 |
|
|
Jul 15 08:21:54 PM PDT 24 |
Jul 15 08:26:46 PM PDT 24 |
3365539552 ps |
| T1257 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2768535262 |
|
|
Jul 15 08:11:44 PM PDT 24 |
Jul 15 08:49:08 PM PDT 24 |
8568276584 ps |
| T163 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.4274418328 |
|
|
Jul 15 08:07:45 PM PDT 24 |
Jul 15 08:09:40 PM PDT 24 |
1961252185 ps |
| T306 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2289638414 |
|
|
Jul 15 08:14:14 PM PDT 24 |
Jul 15 08:19:42 PM PDT 24 |
2398431275 ps |
| T1258 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1647293028 |
|
|
Jul 15 08:10:58 PM PDT 24 |
Jul 15 08:17:06 PM PDT 24 |
2768777142 ps |
| T1259 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.866160671 |
|
|
Jul 15 08:17:42 PM PDT 24 |
Jul 15 08:33:43 PM PDT 24 |
5997812865 ps |
| T1260 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.4032825009 |
|
|
Jul 15 08:27:30 PM PDT 24 |
Jul 15 08:35:01 PM PDT 24 |
3952054184 ps |
| T1261 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2657526280 |
|
|
Jul 15 08:10:39 PM PDT 24 |
Jul 15 09:14:33 PM PDT 24 |
15527649840 ps |
| T1262 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.3215836400 |
|
|
Jul 15 08:03:06 PM PDT 24 |
Jul 15 08:07:19 PM PDT 24 |
3191730578 ps |
| T807 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.929007891 |
|
|
Jul 15 08:30:37 PM PDT 24 |
Jul 15 08:37:44 PM PDT 24 |
3380189000 ps |
| T1263 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2536315494 |
|
|
Jul 15 08:03:51 PM PDT 24 |
Jul 15 08:16:40 PM PDT 24 |
4015774764 ps |
| T445 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2634894970 |
|
|
Jul 15 08:22:26 PM PDT 24 |
Jul 15 08:31:48 PM PDT 24 |
5281649512 ps |
| T367 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.716584838 |
|
|
Jul 15 08:06:29 PM PDT 24 |
Jul 15 08:20:39 PM PDT 24 |
4706668700 ps |
| T1264 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.2206161920 |
|
|
Jul 15 08:29:36 PM PDT 24 |
Jul 15 08:42:07 PM PDT 24 |
5219497350 ps |
| T1265 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.446234898 |
|
|
Jul 15 08:11:57 PM PDT 24 |
Jul 15 08:44:10 PM PDT 24 |
9264464950 ps |
| T1266 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.181895694 |
|
|
Jul 15 08:14:35 PM PDT 24 |
Jul 15 08:39:38 PM PDT 24 |
11263875990 ps |
| T1267 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1044145873 |
|
|
Jul 15 08:18:13 PM PDT 24 |
Jul 15 08:41:37 PM PDT 24 |
10851312463 ps |
| T1268 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2157847544 |
|
|
Jul 15 08:02:39 PM PDT 24 |
Jul 15 08:14:54 PM PDT 24 |
4005644396 ps |
| T811 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.823906552 |
|
|
Jul 15 08:31:06 PM PDT 24 |
Jul 15 08:37:34 PM PDT 24 |
3792423824 ps |
| T1269 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2045408766 |
|
|
Jul 15 08:04:42 PM PDT 24 |
Jul 15 08:12:31 PM PDT 24 |
3671830160 ps |
| T357 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.669282319 |
|
|
Jul 15 08:10:14 PM PDT 24 |
Jul 15 08:24:45 PM PDT 24 |
5352337992 ps |
| T1270 |
/workspace/coverage/default/0.chip_sival_flash_info_access.622908286 |
|
|
Jul 15 08:01:00 PM PDT 24 |
Jul 15 08:04:22 PM PDT 24 |
2365408600 ps |
| T1271 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2152078501 |
|
|
Jul 15 08:02:29 PM PDT 24 |
Jul 15 08:10:21 PM PDT 24 |
7151319798 ps |
| T1272 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1132673559 |
|
|
Jul 15 08:05:15 PM PDT 24 |
Jul 15 08:20:10 PM PDT 24 |
7539393400 ps |
| T1273 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.190690504 |
|
|
Jul 15 08:21:42 PM PDT 24 |
Jul 15 08:28:20 PM PDT 24 |
3316508427 ps |
| T1274 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.906204040 |
|
|
Jul 15 08:02:39 PM PDT 24 |
Jul 15 08:04:29 PM PDT 24 |
2558268082 ps |
| T1275 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1141047786 |
|
|
Jul 15 08:08:09 PM PDT 24 |
Jul 15 08:20:47 PM PDT 24 |
5270709210 ps |
| T1276 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.476639152 |
|
|
Jul 15 08:06:00 PM PDT 24 |
Jul 15 08:12:09 PM PDT 24 |
3446097028 ps |
| T1277 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3041590301 |
|
|
Jul 15 08:04:45 PM PDT 24 |
Jul 15 08:26:25 PM PDT 24 |
7054829509 ps |
| T1278 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1918764947 |
|
|
Jul 15 08:13:52 PM PDT 24 |
Jul 15 08:24:49 PM PDT 24 |
4978738985 ps |
| T1279 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.2168596031 |
|
|
Jul 15 08:20:51 PM PDT 24 |
Jul 15 08:42:35 PM PDT 24 |
6842587416 ps |
| T1280 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2596667722 |
|
|
Jul 15 08:24:19 PM PDT 24 |
Jul 15 08:35:06 PM PDT 24 |
4143992680 ps |
| T1281 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2885967183 |
|
|
Jul 15 08:03:09 PM PDT 24 |
Jul 15 08:35:28 PM PDT 24 |
13156385896 ps |
| T1282 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.1092986344 |
|
|
Jul 15 08:30:25 PM PDT 24 |
Jul 15 08:39:41 PM PDT 24 |
4818228632 ps |
| T764 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.554475813 |
|
|
Jul 15 08:30:53 PM PDT 24 |
Jul 15 08:36:44 PM PDT 24 |
3871851160 ps |
| T1283 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2647491869 |
|
|
Jul 15 08:13:53 PM PDT 24 |
Jul 15 08:22:54 PM PDT 24 |
5285426248 ps |
| T784 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.208243654 |
|
|
Jul 15 08:28:58 PM PDT 24 |
Jul 15 08:38:20 PM PDT 24 |
4534514288 ps |
| T1284 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1965327511 |
|
|
Jul 15 08:21:06 PM PDT 24 |
Jul 15 09:11:57 PM PDT 24 |
18818642029 ps |
| T1285 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3008435760 |
|
|
Jul 15 08:11:52 PM PDT 24 |
Jul 15 08:32:38 PM PDT 24 |
10852757778 ps |
| T1286 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.868045152 |
|
|
Jul 15 08:09:31 PM PDT 24 |
Jul 15 08:11:57 PM PDT 24 |
2384415920 ps |
| T1287 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3421223896 |
|
|
Jul 15 08:17:52 PM PDT 24 |
Jul 15 08:44:03 PM PDT 24 |
6936281452 ps |
| T1288 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1667656786 |
|
|
Jul 15 08:18:27 PM PDT 24 |
Jul 15 08:27:29 PM PDT 24 |
3156631410 ps |
| T1289 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.377367025 |
|
|
Jul 15 08:12:55 PM PDT 24 |
Jul 15 08:24:40 PM PDT 24 |
4490581328 ps |
| T47 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1950343306 |
|
|
Jul 15 08:19:31 PM PDT 24 |
Jul 15 08:30:14 PM PDT 24 |
6475040000 ps |
| T1290 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2518012179 |
|
|
Jul 15 08:27:46 PM PDT 24 |
Jul 15 08:49:24 PM PDT 24 |
8534527168 ps |
| T1291 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.4289402212 |
|
|
Jul 15 08:08:49 PM PDT 24 |
Jul 15 08:27:11 PM PDT 24 |
8877889746 ps |
| T690 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.1778260229 |
|
|
Jul 15 08:12:14 PM PDT 24 |
Jul 15 08:22:52 PM PDT 24 |
2696852620 ps |
| T1292 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3075322163 |
|
|
Jul 15 08:18:54 PM PDT 24 |
Jul 15 08:25:39 PM PDT 24 |
3579042520 ps |
| T1293 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.1135758547 |
|
|
Jul 15 08:31:42 PM PDT 24 |
Jul 15 08:42:02 PM PDT 24 |
4742579668 ps |
| T1294 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3750052263 |
|
|
Jul 15 08:07:21 PM PDT 24 |
Jul 15 08:22:46 PM PDT 24 |
5293230664 ps |
| T1295 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.433028225 |
|
|
Jul 15 08:05:59 PM PDT 24 |
Jul 15 08:16:44 PM PDT 24 |
4118079692 ps |
| T802 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1673918112 |
|
|
Jul 15 08:34:10 PM PDT 24 |
Jul 15 08:41:58 PM PDT 24 |
3919108960 ps |
| T1296 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.235775209 |
|
|
Jul 15 08:08:03 PM PDT 24 |
Jul 15 08:13:28 PM PDT 24 |
2685697916 ps |
| T1297 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1888117491 |
|
|
Jul 15 08:04:02 PM PDT 24 |
Jul 15 08:13:44 PM PDT 24 |
4297160310 ps |
| T1298 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2582677622 |
|
|
Jul 15 08:34:42 PM PDT 24 |
Jul 15 08:44:05 PM PDT 24 |
4893498952 ps |
| T1299 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1789019399 |
|
|
Jul 15 08:04:16 PM PDT 24 |
Jul 15 08:08:33 PM PDT 24 |
3464067150 ps |
| T1300 |
/workspace/coverage/default/2.chip_sw_aes_entropy.2787913580 |
|
|
Jul 15 08:20:50 PM PDT 24 |
Jul 15 08:27:45 PM PDT 24 |
3249708904 ps |
| T778 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.318961282 |
|
|
Jul 15 08:30:50 PM PDT 24 |
Jul 15 08:41:53 PM PDT 24 |
5500102994 ps |
| T48 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3057621320 |
|
|
Jul 15 08:02:24 PM PDT 24 |
Jul 15 08:11:58 PM PDT 24 |
5836158592 ps |
| T1301 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3765687572 |
|
|
Jul 15 08:05:59 PM PDT 24 |
Jul 15 08:33:19 PM PDT 24 |
9224942752 ps |
| T1302 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2195994701 |
|
|
Jul 15 08:03:00 PM PDT 24 |
Jul 15 08:11:56 PM PDT 24 |
4152823011 ps |
| T1303 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2996379539 |
|
|
Jul 15 08:09:40 PM PDT 24 |
Jul 15 08:13:43 PM PDT 24 |
2576981256 ps |
| T1304 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2609197009 |
|
|
Jul 15 08:10:10 PM PDT 24 |
Jul 15 08:13:47 PM PDT 24 |
2119737526 ps |
| T368 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3538569437 |
|
|
Jul 15 08:18:33 PM PDT 24 |
Jul 15 08:32:24 PM PDT 24 |
4737895762 ps |
| T1305 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3715984263 |
|
|
Jul 15 08:23:21 PM PDT 24 |
Jul 15 08:57:01 PM PDT 24 |
25151187560 ps |
| T812 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.739816482 |
|
|
Jul 15 08:28:03 PM PDT 24 |
Jul 15 08:41:24 PM PDT 24 |
6410326978 ps |
| T1306 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3943396048 |
|
|
Jul 15 08:17:30 PM PDT 24 |
Jul 15 08:28:27 PM PDT 24 |
4657808552 ps |
| T1307 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1474606480 |
|
|
Jul 15 08:31:14 PM PDT 24 |
Jul 15 09:46:47 PM PDT 24 |
15536426280 ps |
| T833 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.3534226130 |
|
|
Jul 15 08:31:52 PM PDT 24 |
Jul 15 08:43:44 PM PDT 24 |
6205553728 ps |
| T821 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.3484142426 |
|
|
Jul 15 08:29:31 PM PDT 24 |
Jul 15 08:39:03 PM PDT 24 |
5948976964 ps |
| T1308 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2495015917 |
|
|
Jul 15 08:12:19 PM PDT 24 |
Jul 15 09:33:32 PM PDT 24 |
21245216200 ps |
| T1309 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.567688862 |
|
|
Jul 15 08:04:49 PM PDT 24 |
Jul 15 08:26:33 PM PDT 24 |
12018039899 ps |
| T1310 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.259972447 |
|
|
Jul 15 08:11:23 PM PDT 24 |
Jul 15 08:39:06 PM PDT 24 |
8815304941 ps |
| T1311 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.863147972 |
|
|
Jul 15 08:04:17 PM PDT 24 |
Jul 15 08:15:02 PM PDT 24 |
6033407720 ps |
| T1312 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.79236626 |
|
|
Jul 15 08:00:34 PM PDT 24 |
Jul 15 08:04:13 PM PDT 24 |
2509550080 ps |
| T1313 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.1487161430 |
|
|
Jul 15 08:13:13 PM PDT 24 |
Jul 15 08:22:07 PM PDT 24 |
6933252840 ps |
| T1314 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.452477906 |
|
|
Jul 15 08:15:59 PM PDT 24 |
Jul 15 08:27:35 PM PDT 24 |
5913769500 ps |
| T1315 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1204289929 |
|
|
Jul 15 08:03:34 PM PDT 24 |
Jul 15 08:18:30 PM PDT 24 |
7534593270 ps |
| T1316 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2804440848 |
|
|
Jul 15 08:04:03 PM PDT 24 |
Jul 15 08:12:23 PM PDT 24 |
4019347176 ps |
| T1317 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.3159697477 |
|
|
Jul 15 08:07:46 PM PDT 24 |
Jul 15 08:15:27 PM PDT 24 |
6117785048 ps |
| T298 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.908405211 |
|
|
Jul 15 08:29:12 PM PDT 24 |
Jul 15 08:34:45 PM PDT 24 |
3756104886 ps |
| T375 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2903412285 |
|
|
Jul 15 08:13:00 PM PDT 24 |
Jul 15 08:18:53 PM PDT 24 |
5126876936 ps |
| T1318 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3081545743 |
|
|
Jul 15 08:09:52 PM PDT 24 |
Jul 15 09:08:46 PM PDT 24 |
17446828312 ps |
| T1319 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.808531856 |
|
|
Jul 15 08:26:19 PM PDT 24 |
Jul 15 08:47:41 PM PDT 24 |
9240463005 ps |
| T1320 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.3120885658 |
|
|
Jul 15 08:02:28 PM PDT 24 |
Jul 15 08:14:21 PM PDT 24 |
4634152680 ps |
| T1321 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.861487669 |
|
|
Jul 15 08:13:49 PM PDT 24 |
Jul 15 08:32:33 PM PDT 24 |
6831928776 ps |
| T1322 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.2663799877 |
|
|
Jul 15 08:25:48 PM PDT 24 |
Jul 15 08:37:50 PM PDT 24 |
6095230344 ps |
| T894 |
/workspace/coverage/default/0.chip_jtag_mem_access.1196176860 |
|
|
Jul 15 07:55:51 PM PDT 24 |
Jul 15 08:19:19 PM PDT 24 |
13529990187 ps |
| T1323 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.1433108680 |
|
|
Jul 15 08:10:14 PM PDT 24 |
Jul 15 08:16:17 PM PDT 24 |
3027830400 ps |
| T1324 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.1159643902 |
|
|
Jul 15 08:24:44 PM PDT 24 |
Jul 15 08:48:18 PM PDT 24 |
6845398092 ps |
| T1325 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.561353873 |
|
|
Jul 15 08:06:21 PM PDT 24 |
Jul 15 08:23:22 PM PDT 24 |
5879551780 ps |
| T1326 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2515122636 |
|
|
Jul 15 08:18:43 PM PDT 24 |
Jul 15 08:24:10 PM PDT 24 |
3730972540 ps |
| T1327 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2389719125 |
|
|
Jul 15 08:30:10 PM PDT 24 |
Jul 15 08:35:25 PM PDT 24 |
3034893800 ps |
| T1328 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.2219824868 |
|
|
Jul 15 08:08:42 PM PDT 24 |
Jul 15 08:12:21 PM PDT 24 |
2539311050 ps |
| T1329 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.3122453087 |
|
|
Jul 15 08:12:27 PM PDT 24 |
Jul 15 08:19:21 PM PDT 24 |
3311094041 ps |
| T1330 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2417300661 |
|
|
Jul 15 08:20:57 PM PDT 24 |
Jul 15 08:49:21 PM PDT 24 |
8371040480 ps |
| T1331 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.3475701244 |
|
|
Jul 15 08:24:50 PM PDT 24 |
Jul 15 08:39:00 PM PDT 24 |
8263854320 ps |
| T718 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1356465159 |
|
|
Jul 15 08:03:13 PM PDT 24 |
Jul 15 08:09:08 PM PDT 24 |
3018308800 ps |
| T46 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.54273244 |
|
|
Jul 15 08:17:52 PM PDT 24 |
Jul 15 08:23:09 PM PDT 24 |
3007558014 ps |
| T139 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2142984396 |
|
|
Jul 15 08:10:28 PM PDT 24 |
Jul 15 08:24:14 PM PDT 24 |
6173595172 ps |
| T1332 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.4110568276 |
|
|
Jul 15 08:28:10 PM PDT 24 |
Jul 15 08:40:58 PM PDT 24 |
5295534296 ps |
| T1333 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.3503107015 |
|
|
Jul 15 08:02:58 PM PDT 24 |
Jul 15 08:09:09 PM PDT 24 |
3643674695 ps |
| T141 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3859851807 |
|
|
Jul 15 08:20:41 PM PDT 24 |
Jul 15 08:37:20 PM PDT 24 |
5130151590 ps |
| T1334 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1051581315 |
|
|
Jul 15 08:05:51 PM PDT 24 |
Jul 15 08:12:26 PM PDT 24 |
4042328080 ps |
| T1335 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3849929046 |
|
|
Jul 15 08:20:35 PM PDT 24 |
Jul 15 08:44:38 PM PDT 24 |
6694390190 ps |
| T1336 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.28305922 |
|
|
Jul 15 08:27:23 PM PDT 24 |
Jul 15 08:38:27 PM PDT 24 |
4721656000 ps |
| T1337 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3925275427 |
|
|
Jul 15 08:19:44 PM PDT 24 |
Jul 15 09:25:29 PM PDT 24 |
14488081104 ps |
| T1338 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3209244246 |
|
|
Jul 15 08:09:05 PM PDT 24 |
Jul 15 08:17:50 PM PDT 24 |
5932621360 ps |
| T830 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3284369004 |
|
|
Jul 15 08:33:10 PM PDT 24 |
Jul 15 08:42:17 PM PDT 24 |
4789069300 ps |
| T1339 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.4052879653 |
|
|
Jul 15 08:09:42 PM PDT 24 |
Jul 15 08:19:17 PM PDT 24 |
3889666686 ps |
| T1340 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2214597304 |
|
|
Jul 15 08:06:46 PM PDT 24 |
Jul 15 08:15:29 PM PDT 24 |
4317227778 ps |
| T1341 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1281193374 |
|
|
Jul 15 08:26:43 PM PDT 24 |
Jul 15 08:37:22 PM PDT 24 |
6846800644 ps |
| T49 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1584957103 |
|
|
Jul 15 08:08:52 PM PDT 24 |
Jul 15 08:16:00 PM PDT 24 |
6295960426 ps |
| T1342 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1159515799 |
|
|
Jul 15 08:10:01 PM PDT 24 |
Jul 15 09:02:43 PM PDT 24 |
11603442744 ps |
| T1343 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1129818248 |
|
|
Jul 15 08:05:38 PM PDT 24 |
Jul 15 08:08:32 PM PDT 24 |
2708756304 ps |
| T399 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1640337093 |
|
|
Jul 15 08:06:22 PM PDT 24 |
Jul 15 08:17:48 PM PDT 24 |
4952687006 ps |
| T1344 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3286210921 |
|
|
Jul 15 08:19:04 PM PDT 24 |
Jul 15 08:23:45 PM PDT 24 |
2506685325 ps |
| T358 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2765648915 |
|
|
Jul 15 08:03:22 PM PDT 24 |
Jul 15 08:16:20 PM PDT 24 |
4945836744 ps |
| T1345 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3836387247 |
|
|
Jul 15 08:23:03 PM PDT 24 |
Jul 15 08:34:27 PM PDT 24 |
4427148296 ps |
| T1346 |
/workspace/coverage/default/1.chip_sw_aes_enc.225552494 |
|
|
Jul 15 08:09:43 PM PDT 24 |
Jul 15 08:15:47 PM PDT 24 |
2983602120 ps |
| T1347 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.486868443 |
|
|
Jul 15 08:19:41 PM PDT 24 |
Jul 15 08:28:34 PM PDT 24 |
18927772296 ps |