| T225 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3849418374 |
|
|
Jul 16 08:46:11 PM PDT 24 |
Jul 16 09:23:29 PM PDT 24 |
10588028080 ps |
| T300 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.2426614975 |
|
|
Jul 16 08:40:24 PM PDT 24 |
Jul 16 09:09:03 PM PDT 24 |
8718416520 ps |
| T85 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.707933913 |
|
|
Jul 16 08:34:05 PM PDT 24 |
Jul 16 08:56:03 PM PDT 24 |
9407222550 ps |
| T301 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.1709267945 |
|
|
Jul 16 08:36:09 PM PDT 24 |
Jul 16 08:44:29 PM PDT 24 |
3296422818 ps |
| T146 |
/workspace/coverage/default/0.rom_raw_unlock.3488736249 |
|
|
Jul 16 08:33:31 PM PDT 24 |
Jul 16 08:38:28 PM PDT 24 |
5356693223 ps |
| T342 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.1256466853 |
|
|
Jul 16 08:31:14 PM PDT 24 |
Jul 16 08:35:11 PM PDT 24 |
2541181192 ps |
| T311 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.2394889772 |
|
|
Jul 16 08:36:57 PM PDT 24 |
Jul 16 08:59:25 PM PDT 24 |
6127901356 ps |
| T181 |
/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3803753238 |
|
|
Jul 16 08:51:53 PM PDT 24 |
Jul 16 08:59:46 PM PDT 24 |
5048842836 ps |
| T921 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2753342076 |
|
|
Jul 16 08:41:58 PM PDT 24 |
Jul 16 09:06:44 PM PDT 24 |
7838559160 ps |
| T252 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3984398786 |
|
|
Jul 16 08:29:44 PM PDT 24 |
Jul 16 08:38:42 PM PDT 24 |
4338299656 ps |
| T922 |
/workspace/coverage/default/1.rom_e2e_smoke.1856128662 |
|
|
Jul 16 08:44:30 PM PDT 24 |
Jul 16 09:49:58 PM PDT 24 |
15243707940 ps |
| T923 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.4122746493 |
|
|
Jul 16 08:50:31 PM PDT 24 |
Jul 16 08:56:42 PM PDT 24 |
4877854244 ps |
| T388 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.4027926968 |
|
|
Jul 16 08:37:56 PM PDT 24 |
Jul 16 08:41:59 PM PDT 24 |
2457501440 ps |
| T270 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.2335403531 |
|
|
Jul 16 08:41:13 PM PDT 24 |
Jul 16 08:53:06 PM PDT 24 |
4872529936 ps |
| T356 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.4159856538 |
|
|
Jul 16 08:55:06 PM PDT 24 |
Jul 16 09:05:48 PM PDT 24 |
6434918468 ps |
| T310 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.224931000 |
|
|
Jul 16 08:33:52 PM PDT 24 |
Jul 16 09:03:54 PM PDT 24 |
8876944968 ps |
| T175 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1489633459 |
|
|
Jul 16 08:26:55 PM PDT 24 |
Jul 16 08:39:49 PM PDT 24 |
7560432077 ps |
| T924 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2977504795 |
|
|
Jul 16 08:28:31 PM PDT 24 |
Jul 16 08:41:39 PM PDT 24 |
3887940668 ps |
| T315 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.777547628 |
|
|
Jul 16 08:28:27 PM PDT 24 |
Jul 16 08:40:22 PM PDT 24 |
4387374440 ps |
| T662 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.4020111082 |
|
|
Jul 16 08:47:44 PM PDT 24 |
Jul 16 08:58:08 PM PDT 24 |
5862242398 ps |
| T153 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3375994284 |
|
|
Jul 16 08:33:42 PM PDT 24 |
Jul 16 08:37:12 PM PDT 24 |
2350910793 ps |
| T925 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.2825031198 |
|
|
Jul 16 08:42:33 PM PDT 24 |
Jul 16 09:41:36 PM PDT 24 |
15486006224 ps |
| T734 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.499711686 |
|
|
Jul 16 08:58:13 PM PDT 24 |
Jul 16 09:05:03 PM PDT 24 |
3699396420 ps |
| T926 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.581390773 |
|
|
Jul 16 08:35:02 PM PDT 24 |
Jul 16 08:49:15 PM PDT 24 |
5757054868 ps |
| T764 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.317366626 |
|
|
Jul 16 08:59:30 PM PDT 24 |
Jul 16 09:06:15 PM PDT 24 |
3435751798 ps |
| T927 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.981152120 |
|
|
Jul 16 08:33:05 PM PDT 24 |
Jul 16 08:39:24 PM PDT 24 |
3108007288 ps |
| T703 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1154061986 |
|
|
Jul 16 08:55:40 PM PDT 24 |
Jul 16 09:01:53 PM PDT 24 |
3520601628 ps |
| T35 |
/workspace/coverage/default/2.chip_sw_gpio.909195841 |
|
|
Jul 16 08:44:17 PM PDT 24 |
Jul 16 08:54:01 PM PDT 24 |
4335787366 ps |
| T782 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2326710262 |
|
|
Jul 16 08:57:26 PM PDT 24 |
Jul 16 09:03:41 PM PDT 24 |
3461294904 ps |
| T131 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4108408154 |
|
|
Jul 16 08:51:00 PM PDT 24 |
Jul 16 09:01:58 PM PDT 24 |
4218779708 ps |
| T928 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2984703131 |
|
|
Jul 16 08:56:56 PM PDT 24 |
Jul 16 09:25:24 PM PDT 24 |
7836050384 ps |
| T929 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1931483341 |
|
|
Jul 16 08:37:40 PM PDT 24 |
Jul 16 08:49:46 PM PDT 24 |
4423632292 ps |
| T738 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.281624966 |
|
|
Jul 16 09:00:30 PM PDT 24 |
Jul 16 09:09:16 PM PDT 24 |
4687402720 ps |
| T811 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.203935645 |
|
|
Jul 16 08:57:30 PM PDT 24 |
Jul 16 09:03:27 PM PDT 24 |
3282486344 ps |
| T354 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.566585546 |
|
|
Jul 16 08:57:33 PM PDT 24 |
Jul 16 09:05:34 PM PDT 24 |
5005258460 ps |
| T233 |
/workspace/coverage/default/0.chip_sw_flash_init.3202449035 |
|
|
Jul 16 08:25:59 PM PDT 24 |
Jul 16 09:03:24 PM PDT 24 |
20949578840 ps |
| T392 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3018181877 |
|
|
Jul 16 08:36:52 PM PDT 24 |
Jul 16 08:55:45 PM PDT 24 |
9141083572 ps |
| T235 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1149855272 |
|
|
Jul 16 08:33:56 PM PDT 24 |
Jul 16 09:57:55 PM PDT 24 |
47138396160 ps |
| T930 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.272645664 |
|
|
Jul 16 08:39:57 PM PDT 24 |
Jul 16 08:50:52 PM PDT 24 |
5342455732 ps |
| T7 |
/workspace/coverage/default/2.chip_jtag_csr_rw.2996199254 |
|
|
Jul 16 08:39:50 PM PDT 24 |
Jul 16 09:18:11 PM PDT 24 |
22297225113 ps |
| T407 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.1491341322 |
|
|
Jul 16 08:57:27 PM PDT 24 |
Jul 16 09:06:42 PM PDT 24 |
6035067600 ps |
| T408 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.4005215711 |
|
|
Jul 16 08:28:17 PM PDT 24 |
Jul 16 08:37:49 PM PDT 24 |
3421453736 ps |
| T340 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.4128852566 |
|
|
Jul 16 08:41:43 PM PDT 24 |
Jul 16 09:08:43 PM PDT 24 |
8272979895 ps |
| T247 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.1407518772 |
|
|
Jul 16 08:31:33 PM PDT 24 |
Jul 16 08:36:35 PM PDT 24 |
2521077802 ps |
| T409 |
/workspace/coverage/default/1.chip_sw_hmac_oneshot.1047950168 |
|
|
Jul 16 08:37:52 PM PDT 24 |
Jul 16 08:43:29 PM PDT 24 |
2951054640 ps |
| T324 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.302988546 |
|
|
Jul 16 08:35:25 PM PDT 24 |
Jul 16 08:49:16 PM PDT 24 |
4917676352 ps |
| T410 |
/workspace/coverage/default/1.chip_sw_example_rom.3694200321 |
|
|
Jul 16 08:32:25 PM PDT 24 |
Jul 16 08:34:19 PM PDT 24 |
2390144264 ps |
| T411 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2763841061 |
|
|
Jul 16 08:56:22 PM PDT 24 |
Jul 16 09:02:36 PM PDT 24 |
3962986680 ps |
| T412 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3404195414 |
|
|
Jul 16 08:36:43 PM PDT 24 |
Jul 16 08:56:59 PM PDT 24 |
7732998766 ps |
| T199 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2432923179 |
|
|
Jul 16 08:32:15 PM PDT 24 |
Jul 17 12:12:27 AM PDT 24 |
77231431328 ps |
| T86 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.535451589 |
|
|
Jul 16 08:32:05 PM PDT 24 |
Jul 16 08:57:58 PM PDT 24 |
12793947960 ps |
| T746 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.178811382 |
|
|
Jul 16 08:56:09 PM PDT 24 |
Jul 16 09:06:01 PM PDT 24 |
5831121532 ps |
| T236 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1540916505 |
|
|
Jul 16 08:26:13 PM PDT 24 |
Jul 16 08:34:51 PM PDT 24 |
5561452440 ps |
| T341 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3596737173 |
|
|
Jul 16 08:32:55 PM PDT 24 |
Jul 16 08:44:42 PM PDT 24 |
4644375880 ps |
| T931 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3982639954 |
|
|
Jul 16 08:43:56 PM PDT 24 |
Jul 16 08:51:54 PM PDT 24 |
7126480304 ps |
| T932 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3214459194 |
|
|
Jul 16 08:46:29 PM PDT 24 |
Jul 16 08:59:14 PM PDT 24 |
4791687280 ps |
| T419 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2648117273 |
|
|
Jul 16 08:52:01 PM PDT 24 |
Jul 16 09:01:48 PM PDT 24 |
5019582150 ps |
| T933 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.4098073331 |
|
|
Jul 16 08:40:09 PM PDT 24 |
Jul 16 08:52:30 PM PDT 24 |
9673907572 ps |
| T801 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1385464658 |
|
|
Jul 16 08:58:22 PM PDT 24 |
Jul 16 09:06:00 PM PDT 24 |
4321874376 ps |
| T934 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3849191715 |
|
|
Jul 16 08:26:49 PM PDT 24 |
Jul 16 08:33:14 PM PDT 24 |
4364905592 ps |
| T935 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.2853960540 |
|
|
Jul 16 08:28:34 PM PDT 24 |
Jul 16 08:48:52 PM PDT 24 |
4847939772 ps |
| T737 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2652333725 |
|
|
Jul 16 09:03:00 PM PDT 24 |
Jul 16 09:09:40 PM PDT 24 |
3951355020 ps |
| T510 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3799808047 |
|
|
Jul 16 08:44:13 PM PDT 24 |
Jul 16 08:57:28 PM PDT 24 |
5128877272 ps |
| T156 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2963203847 |
|
|
Jul 16 08:29:47 PM PDT 24 |
Jul 16 08:42:29 PM PDT 24 |
5112937500 ps |
| T201 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1465073834 |
|
|
Jul 16 08:44:38 PM PDT 24 |
Jul 16 08:49:30 PM PDT 24 |
2378928203 ps |
| T936 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2909049658 |
|
|
Jul 16 08:40:08 PM PDT 24 |
Jul 16 08:50:00 PM PDT 24 |
4173848068 ps |
| T795 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.3069687778 |
|
|
Jul 16 09:03:04 PM PDT 24 |
Jul 16 09:13:48 PM PDT 24 |
4634495560 ps |
| T937 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1784149462 |
|
|
Jul 16 08:48:13 PM PDT 24 |
Jul 16 09:29:43 PM PDT 24 |
10780819279 ps |
| T357 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2242376493 |
|
|
Jul 16 09:00:47 PM PDT 24 |
Jul 16 09:13:09 PM PDT 24 |
4138988560 ps |
| T253 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.1980797431 |
|
|
Jul 16 08:36:26 PM PDT 24 |
Jul 16 09:10:49 PM PDT 24 |
10555152874 ps |
| T725 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2767760704 |
|
|
Jul 16 09:00:33 PM PDT 24 |
Jul 16 09:10:42 PM PDT 24 |
5489744940 ps |
| T136 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3555374004 |
|
|
Jul 16 08:28:12 PM PDT 24 |
Jul 16 08:35:03 PM PDT 24 |
5938570528 ps |
| T122 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.196509285 |
|
|
Jul 16 08:47:15 PM PDT 24 |
Jul 16 08:56:28 PM PDT 24 |
6337579526 ps |
| T63 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2292276480 |
|
|
Jul 16 08:27:03 PM PDT 24 |
Jul 16 08:34:59 PM PDT 24 |
4011063928 ps |
| T739 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.900515315 |
|
|
Jul 16 08:57:23 PM PDT 24 |
Jul 16 09:06:52 PM PDT 24 |
4798665800 ps |
| T766 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.194623215 |
|
|
Jul 16 09:00:22 PM PDT 24 |
Jul 16 09:07:11 PM PDT 24 |
3327679946 ps |
| T383 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.2784012784 |
|
|
Jul 16 08:36:59 PM PDT 24 |
Jul 16 08:46:17 PM PDT 24 |
3313781270 ps |
| T938 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.2746648965 |
|
|
Jul 16 08:27:14 PM PDT 24 |
Jul 16 08:38:35 PM PDT 24 |
5731428040 ps |
| T784 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.4255460620 |
|
|
Jul 16 08:57:24 PM PDT 24 |
Jul 16 09:06:30 PM PDT 24 |
4981506552 ps |
| T939 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1201349198 |
|
|
Jul 16 08:45:20 PM PDT 24 |
Jul 16 08:56:44 PM PDT 24 |
7934760496 ps |
| T391 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.3296740589 |
|
|
Jul 16 08:27:33 PM PDT 24 |
Jul 16 08:31:22 PM PDT 24 |
2936389824 ps |
| T940 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.1926071061 |
|
|
Jul 16 08:41:38 PM PDT 24 |
Jul 16 08:45:07 PM PDT 24 |
3259117128 ps |
| T941 |
/workspace/coverage/default/0.rom_e2e_self_hash.4255989846 |
|
|
Jul 16 08:34:07 PM PDT 24 |
Jul 16 10:15:59 PM PDT 24 |
25748205768 ps |
| T723 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.703805439 |
|
|
Jul 16 08:58:08 PM PDT 24 |
Jul 16 09:06:37 PM PDT 24 |
3758329088 ps |
| T787 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.3122194164 |
|
|
Jul 16 08:55:52 PM PDT 24 |
Jul 16 09:05:14 PM PDT 24 |
6248841400 ps |
| T663 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2919306607 |
|
|
Jul 16 08:38:02 PM PDT 24 |
Jul 16 08:46:20 PM PDT 24 |
5259788867 ps |
| T679 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3483471344 |
|
|
Jul 16 08:33:18 PM PDT 24 |
Jul 16 08:54:07 PM PDT 24 |
7867649400 ps |
| T942 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1053662264 |
|
|
Jul 16 08:55:23 PM PDT 24 |
Jul 16 09:03:31 PM PDT 24 |
4720263193 ps |
| T943 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3667729312 |
|
|
Jul 16 08:47:56 PM PDT 24 |
Jul 16 08:59:55 PM PDT 24 |
9301482328 ps |
| T944 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1217497123 |
|
|
Jul 16 08:31:20 PM PDT 24 |
Jul 16 10:01:34 PM PDT 24 |
45704107144 ps |
| T731 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3892186828 |
|
|
Jul 16 08:59:09 PM PDT 24 |
Jul 16 09:11:31 PM PDT 24 |
5315699942 ps |
| T680 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2627879400 |
|
|
Jul 16 08:38:45 PM PDT 24 |
Jul 16 08:49:33 PM PDT 24 |
4787840520 ps |
| T385 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2450086437 |
|
|
Jul 16 08:37:47 PM PDT 24 |
Jul 16 10:30:29 PM PDT 24 |
24237427960 ps |
| T137 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.682061512 |
|
|
Jul 16 08:43:30 PM PDT 24 |
Jul 16 08:53:58 PM PDT 24 |
8274259192 ps |
| T945 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3035069769 |
|
|
Jul 16 08:36:54 PM PDT 24 |
Jul 16 08:43:49 PM PDT 24 |
3485506680 ps |
| T946 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.2886473364 |
|
|
Jul 16 08:28:40 PM PDT 24 |
Jul 16 08:53:02 PM PDT 24 |
9133970704 ps |
| T947 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.1168847366 |
|
|
Jul 16 08:51:45 PM PDT 24 |
Jul 16 08:56:11 PM PDT 24 |
3226975800 ps |
| T43 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1571638118 |
|
|
Jul 16 08:31:40 PM PDT 24 |
Jul 16 08:35:42 PM PDT 24 |
2348044920 ps |
| T308 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.24712671 |
|
|
Jul 16 08:37:14 PM PDT 24 |
Jul 16 08:49:20 PM PDT 24 |
5297814556 ps |
| T49 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.3455792429 |
|
|
Jul 16 08:33:09 PM PDT 24 |
Jul 16 08:38:49 PM PDT 24 |
3588506273 ps |
| T948 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.3271508781 |
|
|
Jul 16 08:36:18 PM PDT 24 |
Jul 16 08:43:09 PM PDT 24 |
3198848490 ps |
| T716 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.253433478 |
|
|
Jul 16 08:57:42 PM PDT 24 |
Jul 16 09:07:51 PM PDT 24 |
5014979958 ps |
| T949 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.523691265 |
|
|
Jul 16 08:45:57 PM PDT 24 |
Jul 16 09:47:00 PM PDT 24 |
14471539608 ps |
| T747 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1900221720 |
|
|
Jul 16 08:56:21 PM PDT 24 |
Jul 16 09:02:25 PM PDT 24 |
3625239904 ps |
| T724 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3343598061 |
|
|
Jul 16 08:57:08 PM PDT 24 |
Jul 16 09:04:31 PM PDT 24 |
4091304456 ps |
| T950 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3856903945 |
|
|
Jul 16 08:49:31 PM PDT 24 |
Jul 16 09:00:02 PM PDT 24 |
5272225668 ps |
| T951 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3617349022 |
|
|
Jul 16 08:55:07 PM PDT 24 |
Jul 16 09:05:56 PM PDT 24 |
6233782579 ps |
| T952 |
/workspace/coverage/default/1.chip_sw_aes_enc.2865567370 |
|
|
Jul 16 08:40:10 PM PDT 24 |
Jul 16 08:46:18 PM PDT 24 |
3095063092 ps |
| T953 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.708194418 |
|
|
Jul 16 08:35:32 PM PDT 24 |
Jul 16 08:39:49 PM PDT 24 |
2775186092 ps |
| T954 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.2508140103 |
|
|
Jul 16 08:34:02 PM PDT 24 |
Jul 16 09:10:29 PM PDT 24 |
25885878121 ps |
| T955 |
/workspace/coverage/default/3.chip_tap_straps_prod.804895705 |
|
|
Jul 16 08:50:06 PM PDT 24 |
Jul 16 08:52:40 PM PDT 24 |
1913776150 ps |
| T956 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.1891094869 |
|
|
Jul 16 08:40:34 PM PDT 24 |
Jul 16 08:45:54 PM PDT 24 |
3088671080 ps |
| T957 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.1887717441 |
|
|
Jul 16 08:28:02 PM PDT 24 |
Jul 16 08:50:27 PM PDT 24 |
5763362406 ps |
| T320 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.2503227186 |
|
|
Jul 16 08:47:06 PM PDT 24 |
Jul 16 09:12:44 PM PDT 24 |
6228083198 ps |
| T958 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.1360010965 |
|
|
Jul 16 08:39:22 PM PDT 24 |
Jul 16 08:47:40 PM PDT 24 |
3710771760 ps |
| T433 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.559586867 |
|
|
Jul 16 08:35:33 PM PDT 24 |
Jul 16 08:56:45 PM PDT 24 |
7600572942 ps |
| T959 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3049284318 |
|
|
Jul 16 08:55:40 PM PDT 24 |
Jul 16 09:15:55 PM PDT 24 |
7899609250 ps |
| T960 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2061369545 |
|
|
Jul 16 08:50:44 PM PDT 24 |
Jul 16 09:31:23 PM PDT 24 |
13209589184 ps |
| T61 |
/workspace/coverage/default/2.chip_sw_alert_test.2441343974 |
|
|
Jul 16 08:44:52 PM PDT 24 |
Jul 16 08:50:54 PM PDT 24 |
3753188400 ps |
| T770 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.646269119 |
|
|
Jul 16 08:56:09 PM PDT 24 |
Jul 16 09:05:44 PM PDT 24 |
4127270830 ps |
| T169 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2144433557 |
|
|
Jul 16 08:26:26 PM PDT 24 |
Jul 16 08:28:48 PM PDT 24 |
2586960667 ps |
| T961 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.921097990 |
|
|
Jul 16 08:28:02 PM PDT 24 |
Jul 16 08:42:02 PM PDT 24 |
7895422025 ps |
| T806 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1995223328 |
|
|
Jul 16 08:58:16 PM PDT 24 |
Jul 16 09:04:29 PM PDT 24 |
3588212368 ps |
| T785 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1138377793 |
|
|
Jul 16 08:55:53 PM PDT 24 |
Jul 16 09:02:25 PM PDT 24 |
3501345050 ps |
| T180 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.899520784 |
|
|
Jul 16 08:26:41 PM PDT 24 |
Jul 16 09:48:38 PM PDT 24 |
44061683881 ps |
| T962 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.148929014 |
|
|
Jul 16 08:29:11 PM PDT 24 |
Jul 16 08:35:06 PM PDT 24 |
3200954342 ps |
| T14 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2887609003 |
|
|
Jul 16 08:36:43 PM PDT 24 |
Jul 16 08:44:31 PM PDT 24 |
6837142840 ps |
| T963 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.2683083900 |
|
|
Jul 16 08:34:10 PM PDT 24 |
Jul 16 08:50:37 PM PDT 24 |
5735041404 ps |
| T134 |
/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2427408193 |
|
|
Jul 16 08:38:03 PM PDT 24 |
Jul 16 09:15:34 PM PDT 24 |
17373953962 ps |
| T964 |
/workspace/coverage/default/0.chip_sival_flash_info_access.3022778471 |
|
|
Jul 16 08:26:41 PM PDT 24 |
Jul 16 08:31:59 PM PDT 24 |
2775565384 ps |
| T965 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1362824420 |
|
|
Jul 16 08:29:54 PM PDT 24 |
Jul 16 08:35:50 PM PDT 24 |
3366969712 ps |
| T135 |
/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.672764388 |
|
|
Jul 16 08:48:20 PM PDT 24 |
Jul 16 09:23:47 PM PDT 24 |
17918576716 ps |
| T966 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.292609696 |
|
|
Jul 16 08:49:47 PM PDT 24 |
Jul 16 08:56:35 PM PDT 24 |
7764718808 ps |
| T967 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.811786083 |
|
|
Jul 16 08:28:04 PM PDT 24 |
Jul 16 08:49:31 PM PDT 24 |
8976031040 ps |
| T968 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2651966948 |
|
|
Jul 16 08:34:29 PM PDT 24 |
Jul 16 08:49:04 PM PDT 24 |
7481227240 ps |
| T722 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.3928620154 |
|
|
Jul 16 08:56:39 PM PDT 24 |
Jul 16 09:05:37 PM PDT 24 |
4669944304 ps |
| T32 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.2567906019 |
|
|
Jul 16 08:26:22 PM PDT 24 |
Jul 16 09:39:23 PM PDT 24 |
18172188216 ps |
| T234 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.944796526 |
|
|
Jul 16 08:27:15 PM PDT 24 |
Jul 16 09:56:27 PM PDT 24 |
46813039952 ps |
| T969 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.936481724 |
|
|
Jul 16 08:27:45 PM PDT 24 |
Jul 16 08:31:46 PM PDT 24 |
2873279008 ps |
| T809 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.3842744093 |
|
|
Jul 16 08:55:51 PM PDT 24 |
Jul 16 09:07:08 PM PDT 24 |
4950778358 ps |
| T8 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.1656540568 |
|
|
Jul 16 08:47:30 PM PDT 24 |
Jul 16 08:57:03 PM PDT 24 |
5082757160 ps |
| T345 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.2379807301 |
|
|
Jul 16 08:56:18 PM PDT 24 |
Jul 16 09:07:19 PM PDT 24 |
5038137872 ps |
| T182 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.4040755429 |
|
|
Jul 16 08:46:50 PM PDT 24 |
Jul 16 08:57:08 PM PDT 24 |
7103082232 ps |
| T358 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1398359560 |
|
|
Jul 16 08:31:17 PM PDT 24 |
Jul 16 08:36:21 PM PDT 24 |
3257071880 ps |
| T790 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.1178768677 |
|
|
Jul 16 08:57:37 PM PDT 24 |
Jul 16 09:10:34 PM PDT 24 |
5157255608 ps |
| T970 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.2635877196 |
|
|
Jul 16 08:33:37 PM PDT 24 |
Jul 16 08:43:56 PM PDT 24 |
7393490405 ps |
| T971 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.4169856269 |
|
|
Jul 16 08:48:38 PM PDT 24 |
Jul 16 08:54:27 PM PDT 24 |
3145483952 ps |
| T972 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.1177317536 |
|
|
Jul 16 08:51:17 PM PDT 24 |
Jul 16 08:55:53 PM PDT 24 |
2715880968 ps |
| T973 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3807487113 |
|
|
Jul 16 08:28:01 PM PDT 24 |
Jul 16 08:32:38 PM PDT 24 |
3694353480 ps |
| T9 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2133175780 |
|
|
Jul 16 08:28:26 PM PDT 24 |
Jul 16 08:36:05 PM PDT 24 |
5232511848 ps |
| T33 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.3005183708 |
|
|
Jul 16 08:25:56 PM PDT 24 |
Jul 16 09:01:21 PM PDT 24 |
8576798316 ps |
| T974 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.469116144 |
|
|
Jul 16 08:58:20 PM PDT 24 |
Jul 16 09:05:08 PM PDT 24 |
3630993826 ps |
| T975 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3915724014 |
|
|
Jul 16 08:41:57 PM PDT 24 |
Jul 16 08:52:07 PM PDT 24 |
4194966942 ps |
| T976 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2980954550 |
|
|
Jul 16 08:40:39 PM PDT 24 |
Jul 16 08:43:29 PM PDT 24 |
2670225684 ps |
| T977 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1529988827 |
|
|
Jul 16 08:31:12 PM PDT 24 |
Jul 16 08:55:56 PM PDT 24 |
9251818980 ps |
| T386 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.4215314495 |
|
|
Jul 16 08:37:42 PM PDT 24 |
Jul 16 10:12:49 PM PDT 24 |
24048727792 ps |
| T783 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3767037304 |
|
|
Jul 16 09:00:11 PM PDT 24 |
Jul 16 09:05:52 PM PDT 24 |
3188997040 ps |
| T269 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.551491046 |
|
|
Jul 16 08:34:13 PM PDT 24 |
Jul 16 08:36:01 PM PDT 24 |
2819249534 ps |
| T664 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3917794139 |
|
|
Jul 16 08:34:40 PM PDT 24 |
Jul 16 08:36:38 PM PDT 24 |
2088945613 ps |
| T978 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.996196549 |
|
|
Jul 16 08:35:41 PM PDT 24 |
Jul 16 08:46:40 PM PDT 24 |
4200815104 ps |
| T271 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2269809334 |
|
|
Jul 16 08:52:17 PM PDT 24 |
Jul 16 09:03:10 PM PDT 24 |
4620049000 ps |
| T979 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.4013989668 |
|
|
Jul 16 08:48:09 PM PDT 24 |
Jul 16 09:07:23 PM PDT 24 |
7573007904 ps |
| T980 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2693101150 |
|
|
Jul 16 08:39:09 PM PDT 24 |
Jul 16 08:58:17 PM PDT 24 |
6022142278 ps |
| T720 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3761026370 |
|
|
Jul 16 08:59:36 PM PDT 24 |
Jul 16 09:09:07 PM PDT 24 |
5519380154 ps |
| T981 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2465529732 |
|
|
Jul 16 08:34:26 PM PDT 24 |
Jul 16 08:55:04 PM PDT 24 |
8028444192 ps |
| T982 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.102752439 |
|
|
Jul 16 09:00:24 PM PDT 24 |
Jul 16 09:07:37 PM PDT 24 |
3867579232 ps |
| T749 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.766006653 |
|
|
Jul 16 08:40:32 PM PDT 24 |
Jul 16 08:53:30 PM PDT 24 |
5336681572 ps |
| T983 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.996979243 |
|
|
Jul 16 08:28:12 PM PDT 24 |
Jul 16 08:32:16 PM PDT 24 |
2856272304 ps |
| T984 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.4167280673 |
|
|
Jul 16 08:49:52 PM PDT 24 |
Jul 16 09:02:21 PM PDT 24 |
4295656920 ps |
| T985 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1694695309 |
|
|
Jul 16 08:34:13 PM PDT 24 |
Jul 16 08:44:34 PM PDT 24 |
6060019462 ps |
| T986 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3638264780 |
|
|
Jul 16 08:45:07 PM PDT 24 |
Jul 16 08:47:59 PM PDT 24 |
2591918380 ps |
| T735 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2641340657 |
|
|
Jul 16 08:58:35 PM PDT 24 |
Jul 16 09:06:11 PM PDT 24 |
3307719016 ps |
| T987 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.844846244 |
|
|
Jul 16 08:32:55 PM PDT 24 |
Jul 16 08:57:49 PM PDT 24 |
9064088400 ps |
| T240 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.448791658 |
|
|
Jul 16 08:56:07 PM PDT 24 |
Jul 16 09:04:34 PM PDT 24 |
4530963322 ps |
| T988 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1518560019 |
|
|
Jul 16 08:33:43 PM PDT 24 |
Jul 16 08:44:23 PM PDT 24 |
5655425964 ps |
| T989 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.1800398689 |
|
|
Jul 16 08:44:49 PM PDT 24 |
Jul 16 09:42:56 PM PDT 24 |
25113320580 ps |
| T990 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2640584818 |
|
|
Jul 16 08:45:00 PM PDT 24 |
Jul 16 08:48:41 PM PDT 24 |
2297619776 ps |
| T709 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2576633196 |
|
|
Jul 16 08:52:19 PM PDT 24 |
Jul 16 08:59:36 PM PDT 24 |
3825930444 ps |
| T991 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1930715095 |
|
|
Jul 16 08:30:59 PM PDT 24 |
Jul 16 08:43:58 PM PDT 24 |
4960003720 ps |
| T797 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.264860160 |
|
|
Jul 16 09:03:02 PM PDT 24 |
Jul 16 09:10:27 PM PDT 24 |
4072227888 ps |
| T760 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.558300983 |
|
|
Jul 16 08:59:10 PM PDT 24 |
Jul 16 09:11:49 PM PDT 24 |
4576577314 ps |
| T992 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2617829618 |
|
|
Jul 16 08:44:37 PM PDT 24 |
Jul 16 08:52:27 PM PDT 24 |
19489243354 ps |
| T346 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3369301612 |
|
|
Jul 16 08:31:28 PM PDT 24 |
Jul 16 08:37:14 PM PDT 24 |
3373511223 ps |
| T277 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.4140418469 |
|
|
Jul 16 08:46:36 PM PDT 24 |
Jul 16 08:57:17 PM PDT 24 |
3745734424 ps |
| T993 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2826026344 |
|
|
Jul 16 08:55:19 PM PDT 24 |
Jul 16 09:17:32 PM PDT 24 |
8887395076 ps |
| T170 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3483947059 |
|
|
Jul 16 08:35:33 PM PDT 24 |
Jul 16 08:38:13 PM PDT 24 |
2967412096 ps |
| T994 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.610283548 |
|
|
Jul 16 08:45:40 PM PDT 24 |
Jul 16 08:58:48 PM PDT 24 |
7754675974 ps |
| T754 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.2874148562 |
|
|
Jul 16 08:56:33 PM PDT 24 |
Jul 16 09:04:35 PM PDT 24 |
5039610188 ps |
| T995 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.618161272 |
|
|
Jul 16 08:34:16 PM PDT 24 |
Jul 16 10:13:23 PM PDT 24 |
23311894438 ps |
| T996 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.730201757 |
|
|
Jul 16 08:31:46 PM PDT 24 |
Jul 16 08:42:00 PM PDT 24 |
4455952434 ps |
| T150 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.361528432 |
|
|
Jul 16 08:34:55 PM PDT 24 |
Jul 16 08:42:33 PM PDT 24 |
3182701418 ps |
| T997 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3148285125 |
|
|
Jul 16 08:41:23 PM PDT 24 |
Jul 16 08:51:09 PM PDT 24 |
4417009162 ps |
| T31 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.4085029279 |
|
|
Jul 16 08:28:40 PM PDT 24 |
Jul 16 08:56:26 PM PDT 24 |
21300308436 ps |
| T998 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2671617594 |
|
|
Jul 16 08:35:25 PM PDT 24 |
Jul 16 09:43:44 PM PDT 24 |
14980498162 ps |
| T999 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2830955363 |
|
|
Jul 16 08:29:11 PM PDT 24 |
Jul 16 08:46:44 PM PDT 24 |
11264878208 ps |
| T733 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3948774874 |
|
|
Jul 16 08:59:38 PM PDT 24 |
Jul 16 09:04:16 PM PDT 24 |
3265897960 ps |
| T1000 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.722112655 |
|
|
Jul 16 08:54:17 PM PDT 24 |
Jul 16 09:07:20 PM PDT 24 |
9088891024 ps |
| T102 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3465856060 |
|
|
Jul 16 08:36:00 PM PDT 24 |
Jul 16 09:04:49 PM PDT 24 |
23715786368 ps |
| T196 |
/workspace/coverage/default/0.chip_jtag_csr_rw.10748028 |
|
|
Jul 16 08:20:59 PM PDT 24 |
Jul 16 08:39:58 PM PDT 24 |
11505082504 ps |
| T1001 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.966675240 |
|
|
Jul 16 08:43:25 PM PDT 24 |
Jul 16 08:52:29 PM PDT 24 |
4358265714 ps |
| T758 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.362575971 |
|
|
Jul 16 08:58:34 PM PDT 24 |
Jul 16 09:05:27 PM PDT 24 |
3964431112 ps |
| T762 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.39399326 |
|
|
Jul 16 09:00:00 PM PDT 24 |
Jul 16 09:12:09 PM PDT 24 |
6031624218 ps |
| T214 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.659874821 |
|
|
Jul 16 08:31:33 PM PDT 24 |
Jul 16 09:31:13 PM PDT 24 |
20808756611 ps |
| T1002 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2586094535 |
|
|
Jul 16 08:44:55 PM PDT 24 |
Jul 16 08:51:54 PM PDT 24 |
4498025880 ps |
| T36 |
/workspace/coverage/default/1.chip_sw_gpio.3604034983 |
|
|
Jul 16 08:31:47 PM PDT 24 |
Jul 16 08:40:31 PM PDT 24 |
4455523830 ps |
| T1003 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1762084111 |
|
|
Jul 16 08:32:47 PM PDT 24 |
Jul 16 10:11:20 PM PDT 24 |
50036765000 ps |
| T1004 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2512881785 |
|
|
Jul 16 08:51:25 PM PDT 24 |
Jul 16 09:00:26 PM PDT 24 |
5741006973 ps |
| T193 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2745427841 |
|
|
Jul 16 08:42:20 PM PDT 24 |
Jul 16 08:49:51 PM PDT 24 |
4493307629 ps |
| T1005 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1708797557 |
|
|
Jul 16 08:36:49 PM PDT 24 |
Jul 16 09:33:24 PM PDT 24 |
14670319240 ps |
| T778 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.4174435795 |
|
|
Jul 16 08:59:11 PM PDT 24 |
Jul 16 09:06:12 PM PDT 24 |
3490648780 ps |
| T362 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.2046180197 |
|
|
Jul 16 09:03:05 PM PDT 24 |
Jul 16 09:11:33 PM PDT 24 |
4597858520 ps |
| T371 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3159365674 |
|
|
Jul 16 08:37:20 PM PDT 24 |
Jul 16 08:48:02 PM PDT 24 |
6816242930 ps |
| T372 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2319489226 |
|
|
Jul 16 08:46:56 PM PDT 24 |
Jul 16 08:53:24 PM PDT 24 |
4913014035 ps |
| T373 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.1779149297 |
|
|
Jul 16 08:28:46 PM PDT 24 |
Jul 16 08:39:33 PM PDT 24 |
5371782064 ps |
| T374 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.3954446013 |
|
|
Jul 16 08:55:53 PM PDT 24 |
Jul 16 09:06:38 PM PDT 24 |
5955565812 ps |
| T375 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.20808928 |
|
|
Jul 16 08:44:31 PM PDT 24 |
Jul 16 08:48:23 PM PDT 24 |
3105628750 ps |
| T176 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2987388349 |
|
|
Jul 16 08:49:21 PM PDT 24 |
Jul 16 08:53:12 PM PDT 24 |
2477781441 ps |
| T376 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1621962692 |
|
|
Jul 16 08:27:01 PM PDT 24 |
Jul 16 08:31:38 PM PDT 24 |
2319354440 ps |
| T377 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.4116678116 |
|
|
Jul 16 08:42:36 PM PDT 24 |
Jul 16 09:00:06 PM PDT 24 |
5669804747 ps |
| T378 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.183836791 |
|
|
Jul 16 08:58:47 PM PDT 24 |
Jul 16 09:06:19 PM PDT 24 |
3966407810 ps |
| T1006 |
/workspace/coverage/default/0.chip_sw_edn_kat.541643346 |
|
|
Jul 16 08:32:49 PM PDT 24 |
Jul 16 08:44:28 PM PDT 24 |
3808771432 ps |
| T1007 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1790964883 |
|
|
Jul 16 08:29:11 PM PDT 24 |
Jul 16 09:26:46 PM PDT 24 |
18958109382 ps |
| T1008 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3952058353 |
|
|
Jul 16 08:29:50 PM PDT 24 |
Jul 16 08:35:12 PM PDT 24 |
3117307276 ps |
| T226 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.111740561 |
|
|
Jul 16 08:30:36 PM PDT 24 |
Jul 16 09:04:56 PM PDT 24 |
9686743904 ps |
| T367 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4035319270 |
|
|
Jul 16 08:37:47 PM PDT 24 |
Jul 16 08:47:51 PM PDT 24 |
5529488040 ps |
| T748 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2358642634 |
|
|
Jul 16 09:00:29 PM PDT 24 |
Jul 16 09:06:26 PM PDT 24 |
3820103360 ps |
| T1009 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2683418195 |
|
|
Jul 16 08:49:29 PM PDT 24 |
Jul 16 08:53:22 PM PDT 24 |
3352323972 ps |
| T1010 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.1701190976 |
|
|
Jul 16 08:40:03 PM PDT 24 |
Jul 16 08:43:43 PM PDT 24 |
2870762352 ps |
| T1011 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.2663742303 |
|
|
Jul 16 08:38:47 PM PDT 24 |
Jul 16 08:50:08 PM PDT 24 |
4560330548 ps |
| T1012 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3866197694 |
|
|
Jul 16 08:43:26 PM PDT 24 |
Jul 16 09:12:11 PM PDT 24 |
16076665178 ps |
| T1013 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.172040562 |
|
|
Jul 16 08:43:24 PM PDT 24 |
Jul 16 09:00:23 PM PDT 24 |
7887118954 ps |
| T317 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.65077485 |
|
|
Jul 16 08:32:30 PM PDT 24 |
Jul 16 09:06:44 PM PDT 24 |
13480178072 ps |
| T1014 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1567841541 |
|
|
Jul 16 08:56:51 PM PDT 24 |
Jul 16 09:16:16 PM PDT 24 |
9251434362 ps |
| T1015 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2001201712 |
|
|
Jul 16 08:43:21 PM PDT 24 |
Jul 16 09:03:07 PM PDT 24 |
5365907358 ps |
| T161 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.4172058054 |
|
|
Jul 16 08:46:56 PM PDT 24 |
Jul 16 08:54:34 PM PDT 24 |
4338906628 ps |
| T1016 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1695358235 |
|
|
Jul 16 08:32:55 PM PDT 24 |
Jul 16 08:37:02 PM PDT 24 |
2503147412 ps |
| T1017 |
/workspace/coverage/default/2.chip_sw_example_rom.2621904138 |
|
|
Jul 16 08:39:37 PM PDT 24 |
Jul 16 08:41:38 PM PDT 24 |
2474860872 ps |
| T1018 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3973601946 |
|
|
Jul 16 08:44:03 PM PDT 24 |
Jul 16 09:07:34 PM PDT 24 |
6893663376 ps |
| T736 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.4194706497 |
|
|
Jul 16 08:42:52 PM PDT 24 |
Jul 16 08:55:52 PM PDT 24 |
5012940000 ps |
| T241 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2395951084 |
|
|
Jul 16 08:29:18 PM PDT 24 |
Jul 16 08:38:09 PM PDT 24 |
6273430188 ps |
| T1019 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1354101584 |
|
|
Jul 16 08:40:12 PM PDT 24 |
Jul 16 09:45:12 PM PDT 24 |
16960097808 ps |
| T1020 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.597223816 |
|
|
Jul 16 09:01:09 PM PDT 24 |
Jul 16 09:07:21 PM PDT 24 |
4344058416 ps |
| T1021 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.4143475862 |
|
|
Jul 16 08:43:54 PM PDT 24 |
Jul 16 08:50:04 PM PDT 24 |
4185520469 ps |
| T1022 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3427514283 |
|
|
Jul 16 08:44:44 PM PDT 24 |
Jul 16 08:54:30 PM PDT 24 |
7501775272 ps |
| T1023 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1607077142 |
|
|
Jul 16 08:42:17 PM PDT 24 |
Jul 16 08:46:37 PM PDT 24 |
2745154108 ps |
| T1024 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.421097587 |
|
|
Jul 16 08:48:38 PM PDT 24 |
Jul 16 08:58:45 PM PDT 24 |
6970869100 ps |
| T44 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3466671149 |
|
|
Jul 16 08:44:16 PM PDT 24 |
Jul 16 08:50:02 PM PDT 24 |
3368657112 ps |
| T396 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.2076594036 |
|
|
Jul 16 08:45:52 PM PDT 24 |
Jul 16 08:50:59 PM PDT 24 |
2677883428 ps |
| T355 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.2376547950 |
|
|
Jul 16 08:57:59 PM PDT 24 |
Jul 16 09:08:15 PM PDT 24 |
4261279432 ps |
| T1025 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.3867724257 |
|
|
Jul 16 08:55:39 PM PDT 24 |
Jul 16 10:02:05 PM PDT 24 |
15499564051 ps |