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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.22 95.64 94.14 95.45 95.00 97.53 99.54


Total test records in report: 2933
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T696 /workspace/coverage/default/1.chip_sw_power_sleep_load.3443274319 Jul 16 08:38:15 PM PDT 24 Jul 16 08:45:03 PM PDT 24 4998321908 ps
T1170 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.311550793 Jul 16 08:46:39 PM PDT 24 Jul 16 08:50:29 PM PDT 24 3135790156 ps
T1171 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.720835945 Jul 16 08:31:18 PM PDT 24 Jul 16 09:06:16 PM PDT 24 10127200293 ps
T329 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1553923488 Jul 16 08:29:50 PM PDT 24 Jul 16 08:39:53 PM PDT 24 4826837824 ps
T1172 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3390313288 Jul 16 08:57:32 PM PDT 24 Jul 16 09:04:59 PM PDT 24 4080665038 ps
T683 /workspace/coverage/default/11.chip_sw_all_escalation_resets.2214051533 Jul 16 08:56:18 PM PDT 24 Jul 16 09:06:34 PM PDT 24 4231274130 ps
T1173 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1803712257 Jul 16 08:35:50 PM PDT 24 Jul 16 08:50:23 PM PDT 24 8986883640 ps
T1174 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3847417151 Jul 16 08:40:03 PM PDT 24 Jul 16 08:56:53 PM PDT 24 8139566758 ps
T338 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1820838224 Jul 16 08:44:09 PM PDT 24 Jul 16 08:58:12 PM PDT 24 4532605832 ps
T1175 /workspace/coverage/default/1.chip_sw_edn_sw_mode.146755747 Jul 16 08:34:09 PM PDT 24 Jul 16 09:10:24 PM PDT 24 10688125132 ps
T1176 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3024239540 Jul 16 08:36:46 PM PDT 24 Jul 16 09:41:26 PM PDT 24 14857903900 ps
T1177 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4037124970 Jul 16 08:46:54 PM PDT 24 Jul 16 09:00:47 PM PDT 24 4068625164 ps
T416 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1837652460 Jul 16 08:39:35 PM PDT 24 Jul 16 08:47:15 PM PDT 24 5007941480 ps
T316 /workspace/coverage/default/0.chip_plic_all_irqs_0.1474303307 Jul 16 08:28:49 PM PDT 24 Jul 16 08:50:15 PM PDT 24 5341363930 ps
T668 /workspace/coverage/default/1.rom_volatile_raw_unlock.1866900852 Jul 16 08:41:35 PM PDT 24 Jul 16 08:43:42 PM PDT 24 2775905613 ps
T1178 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.656500467 Jul 16 08:48:50 PM PDT 24 Jul 16 10:00:23 PM PDT 24 25042407200 ps
T13 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.4132969165 Jul 16 08:29:06 PM PDT 24 Jul 16 08:37:05 PM PDT 24 6620569340 ps
T1179 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3525272949 Jul 16 08:29:46 PM PDT 24 Jul 16 08:37:53 PM PDT 24 4438826590 ps
T1180 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.1378939290 Jul 16 08:34:12 PM PDT 24 Jul 16 08:38:58 PM PDT 24 3246566530 ps
T1181 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.408638772 Jul 16 08:50:04 PM PDT 24 Jul 16 09:19:03 PM PDT 24 8102572512 ps
T1182 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1444623182 Jul 16 08:33:57 PM PDT 24 Jul 16 08:55:03 PM PDT 24 5391195147 ps
T1183 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.4074453414 Jul 16 08:31:14 PM PDT 24 Jul 16 08:40:12 PM PDT 24 4115920732 ps
T1184 /workspace/coverage/default/2.chip_tap_straps_dev.1619997589 Jul 16 08:49:34 PM PDT 24 Jul 16 08:55:52 PM PDT 24 4185123804 ps
T283 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1145537771 Jul 16 08:33:30 PM PDT 24 Jul 16 08:42:00 PM PDT 24 3634539700 ps
T744 /workspace/coverage/default/73.chip_sw_all_escalation_resets.138027148 Jul 16 09:00:43 PM PDT 24 Jul 16 09:09:56 PM PDT 24 4586480688 ps
T1185 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1660600086 Jul 16 08:29:52 PM PDT 24 Jul 16 08:34:06 PM PDT 24 2875479065 ps
T772 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3810498131 Jul 16 08:58:57 PM PDT 24 Jul 16 09:06:31 PM PDT 24 4325305976 ps
T1186 /workspace/coverage/default/1.rom_keymgr_functest.1033399730 Jul 16 08:39:55 PM PDT 24 Jul 16 08:51:06 PM PDT 24 4712168834 ps
T1187 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3230481607 Jul 16 08:35:09 PM PDT 24 Jul 16 09:33:24 PM PDT 24 20429978257 ps
T1188 /workspace/coverage/default/0.chip_sw_hmac_oneshot.2028638015 Jul 16 08:30:14 PM PDT 24 Jul 16 08:36:04 PM PDT 24 3081446376 ps
T1189 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4143432111 Jul 16 08:36:32 PM PDT 24 Jul 16 08:47:19 PM PDT 24 4466974440 ps
T1190 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.319482923 Jul 16 08:36:30 PM PDT 24 Jul 16 08:46:25 PM PDT 24 8525998888 ps
T256 /workspace/coverage/default/58.chip_sw_all_escalation_resets.65976749 Jul 16 08:57:41 PM PDT 24 Jul 16 09:08:37 PM PDT 24 5208442742 ps
T297 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2321705932 Jul 16 08:29:44 PM PDT 24 Jul 16 08:33:40 PM PDT 24 2857780938 ps
T1191 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3874979609 Jul 16 08:33:36 PM PDT 24 Jul 16 08:37:28 PM PDT 24 2290464020 ps
T1192 /workspace/coverage/default/1.chip_sw_kmac_idle.859074555 Jul 16 08:37:54 PM PDT 24 Jul 16 08:42:35 PM PDT 24 2498259400 ps
T12 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.1636978129 Jul 16 08:34:01 PM PDT 24 Jul 16 08:39:08 PM PDT 24 3490205564 ps
T728 /workspace/coverage/default/20.chip_sw_all_escalation_resets.3665991245 Jul 16 08:56:18 PM PDT 24 Jul 16 09:05:26 PM PDT 24 4081892552 ps
T76 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.1653898552 Jul 16 08:29:27 PM PDT 24 Jul 16 10:29:30 PM PDT 24 32209161432 ps
T1193 /workspace/coverage/default/0.chip_sw_coremark.1728062700 Jul 16 08:36:09 PM PDT 24 Jul 17 12:32:45 AM PDT 24 72234279952 ps
T1194 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.389505814 Jul 16 08:46:37 PM PDT 24 Jul 16 09:01:32 PM PDT 24 5283542300 ps
T1195 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2411292071 Jul 16 08:46:19 PM PDT 24 Jul 16 09:41:41 PM PDT 24 14572663896 ps
T1196 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.4234155933 Jul 16 08:44:46 PM PDT 24 Jul 16 09:03:52 PM PDT 24 7186403992 ps
T1197 /workspace/coverage/default/0.rom_e2e_asm_init_prod.3617303288 Jul 16 08:32:59 PM PDT 24 Jul 16 09:37:13 PM PDT 24 15580012051 ps
T158 /workspace/coverage/default/90.chip_sw_all_escalation_resets.1675182610 Jul 16 08:58:57 PM PDT 24 Jul 16 09:10:36 PM PDT 24 6633411300 ps
T1198 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1419081523 Jul 16 08:29:44 PM PDT 24 Jul 16 08:42:10 PM PDT 24 8832989848 ps
T798 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2793914490 Jul 16 08:59:44 PM PDT 24 Jul 16 09:05:59 PM PDT 24 3602075030 ps
T1199 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3147027822 Jul 16 08:29:02 PM PDT 24 Jul 16 08:41:44 PM PDT 24 11772813118 ps
T1200 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2589624502 Jul 16 08:37:02 PM PDT 24 Jul 16 09:22:36 PM PDT 24 11930058083 ps
T1201 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3303133951 Jul 16 08:38:20 PM PDT 24 Jul 16 10:18:26 PM PDT 24 22687154392 ps
T194 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2687270472 Jul 16 08:28:02 PM PDT 24 Jul 16 08:37:10 PM PDT 24 4007404772 ps
T257 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.141708405 Jul 16 08:33:19 PM PDT 24 Jul 16 08:40:39 PM PDT 24 5414679884 ps
T775 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2101602588 Jul 16 08:59:03 PM PDT 24 Jul 16 09:03:54 PM PDT 24 3759093092 ps
T773 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2007700103 Jul 16 09:03:18 PM PDT 24 Jul 16 09:09:31 PM PDT 24 3766141512 ps
T1202 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.801085106 Jul 16 08:37:28 PM PDT 24 Jul 16 10:04:31 PM PDT 24 23695088775 ps
T421 /workspace/coverage/default/4.chip_sw_all_escalation_resets.3060567954 Jul 16 08:51:23 PM PDT 24 Jul 16 09:02:28 PM PDT 24 5501336582 ps
T399 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2524845240 Jul 16 08:37:09 PM PDT 24 Jul 16 09:06:30 PM PDT 24 23066881120 ps
T1203 /workspace/coverage/default/0.chip_sw_flash_crash_alert.3024077606 Jul 16 08:29:52 PM PDT 24 Jul 16 08:40:58 PM PDT 24 4595439336 ps
T719 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.87596624 Jul 16 09:01:27 PM PDT 24 Jul 16 09:08:02 PM PDT 24 3583548720 ps
T1204 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.106477412 Jul 16 08:45:12 PM PDT 24 Jul 16 09:48:44 PM PDT 24 15155354040 ps
T1205 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2837451856 Jul 16 08:31:08 PM PDT 24 Jul 16 08:35:08 PM PDT 24 2643024654 ps
T1206 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.1481288227 Jul 16 08:55:48 PM PDT 24 Jul 16 09:10:02 PM PDT 24 4960338680 ps
T697 /workspace/coverage/default/2.chip_sw_power_sleep_load.85549390 Jul 16 08:48:15 PM PDT 24 Jul 16 08:54:40 PM PDT 24 5088628928 ps
T1207 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3362299247 Jul 16 08:44:27 PM PDT 24 Jul 16 09:20:20 PM PDT 24 18709767331 ps
T1208 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2569433057 Jul 16 08:33:58 PM PDT 24 Jul 16 08:37:44 PM PDT 24 3048044836 ps
T1209 /workspace/coverage/default/2.rom_e2e_asm_init_prod.3294933304 Jul 16 08:53:02 PM PDT 24 Jul 16 09:48:47 PM PDT 24 15943285824 ps
T1210 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1893812865 Jul 16 08:35:00 PM PDT 24 Jul 16 08:55:04 PM PDT 24 13321483036 ps
T1211 /workspace/coverage/default/2.rom_e2e_smoke.3713100666 Jul 16 08:53:25 PM PDT 24 Jul 16 09:48:10 PM PDT 24 14976698776 ps
T335 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3000045326 Jul 16 08:30:27 PM PDT 24 Jul 16 08:38:00 PM PDT 24 4151941192 ps
T1212 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.27525428 Jul 16 08:50:40 PM PDT 24 Jul 16 09:01:35 PM PDT 24 3546645631 ps
T1213 /workspace/coverage/default/0.chip_sw_usbdev_dpi.2249888355 Jul 16 08:30:00 PM PDT 24 Jul 16 09:25:28 PM PDT 24 11531457484 ps
T413 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1849530493 Jul 16 08:30:53 PM PDT 24 Jul 16 08:40:45 PM PDT 24 7079746190 ps
T1214 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1327928218 Jul 16 08:46:43 PM PDT 24 Jul 16 09:11:36 PM PDT 24 12157560346 ps
T123 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.173410001 Jul 16 08:36:55 PM PDT 24 Jul 16 08:46:30 PM PDT 24 5456389472 ps
T327 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.921500834 Jul 16 08:41:04 PM PDT 24 Jul 16 08:51:36 PM PDT 24 4116654504 ps
T1215 /workspace/coverage/default/0.rom_e2e_shutdown_output.2203526319 Jul 16 08:34:29 PM PDT 24 Jul 16 09:43:02 PM PDT 24 28430935500 ps
T1216 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1355215893 Jul 16 08:30:04 PM PDT 24 Jul 16 09:00:20 PM PDT 24 13372664496 ps
T1217 /workspace/coverage/default/1.chip_sw_edn_auto_mode.1072456682 Jul 16 08:33:04 PM PDT 24 Jul 16 08:47:48 PM PDT 24 4286296892 ps
T1218 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3512346888 Jul 16 08:57:54 PM PDT 24 Jul 16 09:02:59 PM PDT 24 3126457384 ps
T364 /workspace/coverage/default/45.chip_sw_all_escalation_resets.3463492838 Jul 16 08:56:40 PM PDT 24 Jul 16 09:04:57 PM PDT 24 4464402930 ps
T1219 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2340399706 Jul 16 08:36:09 PM PDT 24 Jul 16 08:39:34 PM PDT 24 2565053046 ps
T1220 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2895462349 Jul 16 08:51:03 PM PDT 24 Jul 16 08:58:36 PM PDT 24 5252727955 ps
T808 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3968532217 Jul 16 09:00:00 PM PDT 24 Jul 16 09:06:48 PM PDT 24 3738204300 ps
T1221 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3724359763 Jul 16 08:32:22 PM PDT 24 Jul 16 08:37:24 PM PDT 24 2459374046 ps
T414 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2399507881 Jul 16 08:50:02 PM PDT 24 Jul 16 09:14:35 PM PDT 24 21473423990 ps
T1222 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2413761187 Jul 16 08:44:47 PM PDT 24 Jul 16 09:02:36 PM PDT 24 5887940760 ps
T1223 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3423524924 Jul 16 08:46:29 PM PDT 24 Jul 16 10:20:32 PM PDT 24 26017512974 ps
T1224 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1261268685 Jul 16 08:49:51 PM PDT 24 Jul 16 08:56:41 PM PDT 24 2663071000 ps
T1225 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3631938015 Jul 16 08:47:52 PM PDT 24 Jul 16 08:56:54 PM PDT 24 5603694728 ps
T1226 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2075406359 Jul 16 08:35:37 PM PDT 24 Jul 16 08:54:32 PM PDT 24 6934035880 ps
T1227 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1484219166 Jul 16 08:42:28 PM PDT 24 Jul 16 08:48:28 PM PDT 24 3646208060 ps
T1228 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.865032107 Jul 16 08:27:51 PM PDT 24 Jul 16 10:07:06 PM PDT 24 25613134104 ps
T1229 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1964662145 Jul 16 08:31:36 PM PDT 24 Jul 16 09:11:11 PM PDT 24 31427040234 ps
T1230 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2045682210 Jul 16 08:55:29 PM PDT 24 Jul 16 09:57:23 PM PDT 24 16156551000 ps
T1231 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.170547269 Jul 16 08:37:12 PM PDT 24 Jul 16 08:50:33 PM PDT 24 5418270813 ps
T1232 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.25821292 Jul 16 08:32:18 PM PDT 24 Jul 16 08:45:13 PM PDT 24 5683534047 ps
T1233 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1593775338 Jul 16 08:46:37 PM PDT 24 Jul 16 09:39:28 PM PDT 24 17042026880 ps
T1234 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2899464219 Jul 16 08:30:07 PM PDT 24 Jul 16 08:40:25 PM PDT 24 5553026784 ps
T1235 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3899769783 Jul 16 08:28:35 PM PDT 24 Jul 16 08:33:58 PM PDT 24 2808640882 ps
T1236 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2218623428 Jul 16 08:43:30 PM PDT 24 Jul 16 08:48:24 PM PDT 24 3067124858 ps
T1237 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.816139215 Jul 16 08:53:52 PM PDT 24 Jul 16 09:45:46 PM PDT 24 15260061690 ps
T1238 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2776989062 Jul 16 08:30:03 PM PDT 24 Jul 16 08:55:12 PM PDT 24 7990029324 ps
T767 /workspace/coverage/default/75.chip_sw_all_escalation_resets.910775976 Jul 16 09:00:00 PM PDT 24 Jul 16 09:09:16 PM PDT 24 5167292472 ps
T759 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2658745282 Jul 16 08:45:51 PM PDT 24 Jul 16 08:51:47 PM PDT 24 3274477320 ps
T1239 /workspace/coverage/default/0.rom_e2e_asm_init_dev.1351236005 Jul 16 08:45:23 PM PDT 24 Jul 16 10:05:14 PM PDT 24 15382592076 ps
T727 /workspace/coverage/default/6.chip_sw_all_escalation_resets.748893341 Jul 16 08:56:10 PM PDT 24 Jul 16 09:06:09 PM PDT 24 5344816926 ps
T1240 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.51414156 Jul 16 08:43:49 PM PDT 24 Jul 16 08:48:38 PM PDT 24 3511903932 ps
T1241 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1620555343 Jul 16 08:32:29 PM PDT 24 Jul 16 09:18:15 PM PDT 24 32436856440 ps
T1242 /workspace/coverage/default/1.chip_sw_uart_tx_rx.25353594 Jul 16 08:36:49 PM PDT 24 Jul 16 08:49:04 PM PDT 24 4640476466 ps
T1243 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1111426478 Jul 16 08:31:34 PM PDT 24 Jul 16 08:49:30 PM PDT 24 5694475928 ps
T1244 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4152576099 Jul 16 08:35:44 PM PDT 24 Jul 16 08:47:03 PM PDT 24 3854321486 ps
T1245 /workspace/coverage/default/2.chip_sw_kmac_idle.2751124587 Jul 16 08:45:51 PM PDT 24 Jul 16 08:50:01 PM PDT 24 2917110188 ps
T1246 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2073638228 Jul 16 08:31:41 PM PDT 24 Jul 16 08:42:57 PM PDT 24 6810133260 ps
T1247 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.839731938 Jul 16 08:44:02 PM PDT 24 Jul 16 08:49:12 PM PDT 24 3063206651 ps
T1248 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2880062425 Jul 16 08:48:46 PM PDT 24 Jul 16 08:57:49 PM PDT 24 3585673572 ps
T765 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.897431572 Jul 16 08:59:26 PM PDT 24 Jul 16 09:08:01 PM PDT 24 3271256440 ps
T1249 /workspace/coverage/default/2.chip_sw_aes_entropy.3659681481 Jul 16 08:52:00 PM PDT 24 Jul 16 08:56:40 PM PDT 24 2823164528 ps
T1250 /workspace/coverage/default/1.chip_sw_hmac_smoketest.564146119 Jul 16 08:39:57 PM PDT 24 Jul 16 08:45:42 PM PDT 24 3234817400 ps
T129 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2560807029 Jul 16 08:29:33 PM PDT 24 Jul 16 08:37:32 PM PDT 24 4449440738 ps
T1251 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2259053256 Jul 16 08:51:11 PM PDT 24 Jul 16 09:01:53 PM PDT 24 4168572708 ps
T1252 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1066863625 Jul 16 08:33:03 PM PDT 24 Jul 16 08:35:05 PM PDT 24 1854233400 ps
T1253 /workspace/coverage/default/1.rom_e2e_asm_init_prod.67551357 Jul 16 08:43:18 PM PDT 24 Jul 16 09:51:04 PM PDT 24 15345683218 ps
T1254 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2514685337 Jul 16 08:33:18 PM PDT 24 Jul 16 10:36:26 PM PDT 24 23102194524 ps
T1255 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2605729409 Jul 16 08:44:26 PM PDT 24 Jul 16 08:51:31 PM PDT 24 3569910200 ps
T1256 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2929512684 Jul 16 08:26:24 PM PDT 24 Jul 16 08:31:42 PM PDT 24 3146418940 ps
T381 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1907938722 Jul 16 08:32:10 PM PDT 24 Jul 16 08:44:06 PM PDT 24 4369684218 ps
T1257 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.630903146 Jul 16 08:51:01 PM PDT 24 Jul 16 09:02:49 PM PDT 24 3946828740 ps
T1258 /workspace/coverage/default/0.chip_sw_csrng_smoketest.2545233050 Jul 16 08:29:25 PM PDT 24 Jul 16 08:33:05 PM PDT 24 3068201872 ps
T124 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4284760906 Jul 16 08:31:10 PM PDT 24 Jul 16 08:39:42 PM PDT 24 5362718560 ps
T1259 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3540282057 Jul 16 08:28:42 PM PDT 24 Jul 16 08:35:41 PM PDT 24 3373919728 ps
T1260 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.2902589013 Jul 16 08:37:16 PM PDT 24 Jul 16 08:41:28 PM PDT 24 3009406719 ps
T1261 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2283884000 Jul 16 08:31:31 PM PDT 24 Jul 16 08:44:27 PM PDT 24 5050564300 ps
T258 /workspace/coverage/default/63.chip_sw_all_escalation_resets.2149628940 Jul 16 08:58:10 PM PDT 24 Jul 16 09:07:55 PM PDT 24 5517465960 ps
T1262 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.537276084 Jul 16 08:47:03 PM PDT 24 Jul 16 08:48:48 PM PDT 24 1957308170 ps
T1263 /workspace/coverage/default/1.chip_tap_straps_dev.2578389515 Jul 16 08:36:06 PM PDT 24 Jul 16 08:41:14 PM PDT 24 4494683402 ps
T1264 /workspace/coverage/default/0.chip_sw_example_manufacturer.2792243074 Jul 16 08:28:37 PM PDT 24 Jul 16 08:33:28 PM PDT 24 2516999280 ps
T1265 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.371348987 Jul 16 08:30:10 PM PDT 24 Jul 16 08:34:57 PM PDT 24 3050912051 ps
T757 /workspace/coverage/default/82.chip_sw_all_escalation_resets.1022015259 Jul 16 09:02:39 PM PDT 24 Jul 16 09:11:31 PM PDT 24 5791480300 ps
T229 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3504810075 Jul 16 08:46:26 PM PDT 24 Jul 16 09:42:15 PM PDT 24 12870888984 ps
T1266 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.4229889878 Jul 16 08:56:30 PM PDT 24 Jul 16 09:46:29 PM PDT 24 14308299139 ps
T1267 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3171457761 Jul 16 08:56:04 PM PDT 24 Jul 16 09:03:07 PM PDT 24 4053635304 ps
T1268 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.407294809 Jul 16 08:38:37 PM PDT 24 Jul 16 08:42:25 PM PDT 24 2660233229 ps
T1269 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3871274456 Jul 16 08:54:43 PM PDT 24 Jul 16 09:11:01 PM PDT 24 8516843833 ps
T1270 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2193631278 Jul 16 08:51:44 PM PDT 24 Jul 16 09:16:43 PM PDT 24 8164582364 ps
T1271 /workspace/coverage/default/2.chip_sw_hmac_enc.3292958407 Jul 16 08:46:46 PM PDT 24 Jul 16 08:51:37 PM PDT 24 3523797392 ps
T1272 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.970613186 Jul 16 08:55:14 PM PDT 24 Jul 16 09:02:18 PM PDT 24 3340514646 ps
T1273 /workspace/coverage/default/87.chip_sw_all_escalation_resets.2063905654 Jul 16 08:58:46 PM PDT 24 Jul 16 09:11:15 PM PDT 24 5870962820 ps
T810 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2038726551 Jul 16 08:56:59 PM PDT 24 Jul 16 09:03:16 PM PDT 24 4028263296 ps
T688 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.560486793 Jul 16 08:39:21 PM PDT 24 Jul 16 08:44:52 PM PDT 24 2652231306 ps
T729 /workspace/coverage/default/51.chip_sw_all_escalation_resets.2701735271 Jul 16 08:56:37 PM PDT 24 Jul 16 09:05:26 PM PDT 24 5137594570 ps
T1274 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.1389942785 Jul 16 08:51:19 PM PDT 24 Jul 16 09:04:06 PM PDT 24 5330205564 ps
T1275 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1805681259 Jul 16 08:27:56 PM PDT 24 Jul 16 08:34:39 PM PDT 24 3396210152 ps
T1276 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1778334282 Jul 16 08:30:23 PM PDT 24 Jul 16 08:41:37 PM PDT 24 5451100110 ps
T1277 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1671432930 Jul 16 08:30:33 PM PDT 24 Jul 16 08:42:05 PM PDT 24 5239191768 ps
T37 /workspace/coverage/default/0.chip_sw_gpio.1821184951 Jul 16 08:28:29 PM PDT 24 Jul 16 08:36:38 PM PDT 24 4029413150 ps
T1278 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2147627956 Jul 16 08:33:32 PM PDT 24 Jul 16 08:44:41 PM PDT 24 6581347868 ps
T1279 /workspace/coverage/default/0.rom_e2e_smoke.1094172322 Jul 16 08:35:09 PM PDT 24 Jul 16 09:32:22 PM PDT 24 15331170818 ps
T1280 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3408217596 Jul 16 08:29:58 PM PDT 24 Jul 17 12:41:00 AM PDT 24 78316183082 ps
T705 /workspace/coverage/default/1.rom_raw_unlock.1498011499 Jul 16 08:41:48 PM PDT 24 Jul 16 08:46:06 PM PDT 24 5285491085 ps
T1281 /workspace/coverage/default/1.chip_sw_flash_init.1236228484 Jul 16 08:32:51 PM PDT 24 Jul 16 09:13:34 PM PDT 24 26340748482 ps
T1282 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2217599648 Jul 16 08:52:13 PM PDT 24 Jul 16 10:09:33 PM PDT 24 20556452024 ps
T272 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1054691626 Jul 16 08:28:15 PM PDT 24 Jul 16 08:37:51 PM PDT 24 4843808340 ps
T1283 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.4125031461 Jul 16 08:45:12 PM PDT 24 Jul 16 08:48:18 PM PDT 24 2729511100 ps
T1284 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3112403311 Jul 16 08:30:24 PM PDT 24 Jul 16 08:35:52 PM PDT 24 3608635072 ps
T1285 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2424815082 Jul 16 08:28:02 PM PDT 24 Jul 16 08:46:42 PM PDT 24 11241884185 ps
T1286 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.790634610 Jul 16 08:28:09 PM PDT 24 Jul 16 08:36:38 PM PDT 24 4565284584 ps
T1287 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.799843398 Jul 16 08:38:44 PM PDT 24 Jul 16 08:48:30 PM PDT 24 4892110300 ps
T415 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.25765026 Jul 16 08:32:02 PM PDT 24 Jul 16 09:05:50 PM PDT 24 24400144232 ps
T1288 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3155307049 Jul 16 08:29:44 PM PDT 24 Jul 16 09:46:15 PM PDT 24 17036691400 ps
T1289 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.3323671479 Jul 16 08:47:15 PM PDT 24 Jul 16 08:50:26 PM PDT 24 1891735071 ps
T195 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2889673880 Jul 16 08:33:47 PM PDT 24 Jul 16 08:43:20 PM PDT 24 3601614869 ps
T1290 /workspace/coverage/default/2.chip_sw_example_concurrency.150264893 Jul 16 08:43:01 PM PDT 24 Jul 16 08:48:05 PM PDT 24 3217422146 ps
T62 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.2555548549 Jul 16 08:34:26 PM PDT 24 Jul 16 08:42:21 PM PDT 24 5812863588 ps
T1291 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2220700947 Jul 16 08:43:29 PM PDT 24 Jul 16 08:53:29 PM PDT 24 8105706712 ps
T1292 /workspace/coverage/default/19.chip_sw_all_escalation_resets.1646948647 Jul 16 08:57:34 PM PDT 24 Jul 16 09:07:33 PM PDT 24 5627040810 ps
T1293 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3446707618 Jul 16 08:52:15 PM PDT 24 Jul 16 09:01:22 PM PDT 24 4521563798 ps
T1294 /workspace/coverage/default/1.chip_sw_hmac_enc.3038048405 Jul 16 08:38:06 PM PDT 24 Jul 16 08:44:36 PM PDT 24 3320576490 ps
T1295 /workspace/coverage/default/1.chip_sw_aes_idle.854040517 Jul 16 08:35:04 PM PDT 24 Jul 16 08:40:23 PM PDT 24 2439724916 ps
T1296 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3636378737 Jul 16 08:34:38 PM PDT 24 Jul 16 08:42:28 PM PDT 24 7907167330 ps
T1297 /workspace/coverage/default/1.chip_sw_edn_kat.3361266003 Jul 16 08:38:05 PM PDT 24 Jul 16 08:48:54 PM PDT 24 3531195732 ps
T1298 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.22840021 Jul 16 08:47:34 PM PDT 24 Jul 16 09:20:24 PM PDT 24 13066693686 ps
T1299 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3113864970 Jul 16 08:29:22 PM PDT 24 Jul 16 08:34:50 PM PDT 24 3340960647 ps
T1300 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2837674219 Jul 16 08:34:07 PM PDT 24 Jul 16 08:41:35 PM PDT 24 4587946426 ps
T1301 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1865907733 Jul 16 08:31:31 PM PDT 24 Jul 16 08:41:14 PM PDT 24 5688494429 ps
T1302 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3147692810 Jul 16 08:57:48 PM PDT 24 Jul 16 09:05:08 PM PDT 24 3790255192 ps
T713 /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.3352837688 Jul 16 08:30:04 PM PDT 24 Jul 16 09:06:26 PM PDT 24 9987301282 ps
T1303 /workspace/coverage/default/2.rom_volatile_raw_unlock.2012176488 Jul 16 08:49:53 PM PDT 24 Jul 16 08:52:09 PM PDT 24 2486557079 ps
T93 /workspace/coverage/default/10.chip_sw_all_escalation_resets.700672844 Jul 16 08:55:19 PM PDT 24 Jul 16 09:08:45 PM PDT 24 5104468082 ps
T1304 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2588457293 Jul 16 08:36:59 PM PDT 24 Jul 16 09:59:28 PM PDT 24 19216159024 ps
T1305 /workspace/coverage/default/66.chip_sw_all_escalation_resets.1090316805 Jul 16 08:58:46 PM PDT 24 Jul 16 09:10:26 PM PDT 24 4469398256 ps
T1306 /workspace/coverage/default/1.rom_e2e_self_hash.2677732345 Jul 16 08:48:16 PM PDT 24 Jul 16 10:19:03 PM PDT 24 26278063176 ps
T1307 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.725099792 Jul 16 08:43:24 PM PDT 24 Jul 16 08:47:06 PM PDT 24 2809069940 ps
T1308 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3390463712 Jul 16 08:44:21 PM PDT 24 Jul 16 09:06:01 PM PDT 24 8167483336 ps
T1309 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1007520702 Jul 16 08:42:13 PM PDT 24 Jul 16 08:48:52 PM PDT 24 3232483646 ps
T1310 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.989972737 Jul 16 08:41:04 PM PDT 24 Jul 16 08:47:29 PM PDT 24 6132411354 ps
T1311 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2613752926 Jul 16 08:40:24 PM PDT 24 Jul 16 08:50:32 PM PDT 24 4973385276 ps
T244 /workspace/coverage/default/1.chip_sw_alert_test.2534415315 Jul 16 08:33:46 PM PDT 24 Jul 16 08:39:20 PM PDT 24 2998436032 ps
T1312 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2100124314 Jul 16 08:38:08 PM PDT 24 Jul 16 09:29:40 PM PDT 24 11082443800 ps
T1313 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1394268096 Jul 16 08:43:52 PM PDT 24 Jul 16 10:20:14 PM PDT 24 22877829245 ps
T155 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2942699458 Jul 16 08:28:09 PM PDT 24 Jul 16 08:30:03 PM PDT 24 2528670905 ps
T1314 /workspace/coverage/default/0.chip_sw_aes_idle.3209993080 Jul 16 08:29:19 PM PDT 24 Jul 16 08:33:37 PM PDT 24 2959676190 ps
T1315 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2642273155 Jul 16 08:59:25 PM PDT 24 Jul 16 09:06:40 PM PDT 24 4221469032 ps
T780 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1288511188 Jul 16 08:57:50 PM PDT 24 Jul 16 09:04:07 PM PDT 24 3632454968 ps
T1316 /workspace/coverage/default/3.chip_sw_uart_tx_rx.1416507533 Jul 16 08:51:13 PM PDT 24 Jul 16 09:00:35 PM PDT 24 4434449920 ps
T369 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4205471475 Jul 16 08:29:10 PM PDT 24 Jul 16 08:37:43 PM PDT 24 5098668276 ps
T1317 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.782841082 Jul 16 08:51:40 PM PDT 24 Jul 16 10:08:56 PM PDT 24 22479762388 ps
T1318 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1624845471 Jul 16 08:44:43 PM PDT 24 Jul 16 09:43:10 PM PDT 24 20576816550 ps
T303 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.952058756 Jul 16 08:36:13 PM PDT 24 Jul 16 08:53:43 PM PDT 24 9536150537 ps
T1319 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.104625600 Jul 16 08:29:49 PM PDT 24 Jul 16 08:41:22 PM PDT 24 7757267080 ps
T370 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1885570786 Jul 16 09:00:41 PM PDT 24 Jul 16 09:06:49 PM PDT 24 3592223400 ps
T259 /workspace/coverage/default/99.chip_sw_all_escalation_resets.2845378857 Jul 16 09:00:06 PM PDT 24 Jul 16 09:08:27 PM PDT 24 4869425264 ps
T1320 /workspace/coverage/default/0.rom_e2e_asm_init_rma.3996516618 Jul 16 08:37:24 PM PDT 24 Jul 16 09:43:00 PM PDT 24 15440230172 ps
T1321 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3169705766 Jul 16 08:29:37 PM PDT 24 Jul 16 08:31:29 PM PDT 24 2355828010 ps
T1322 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2632247462 Jul 16 08:36:59 PM PDT 24 Jul 16 10:11:56 PM PDT 24 49792473385 ps
T1323 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.57601684 Jul 16 08:55:31 PM PDT 24 Jul 16 09:02:58 PM PDT 24 3834310382 ps
T1324 /workspace/coverage/default/38.chip_sw_all_escalation_resets.1194847635 Jul 16 08:57:20 PM PDT 24 Jul 16 09:09:48 PM PDT 24 5601328938 ps
T1325 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1891305295 Jul 16 08:31:13 PM PDT 24 Jul 16 09:13:49 PM PDT 24 12624613022 ps
T1326 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.374394271 Jul 16 08:32:56 PM PDT 24 Jul 16 11:30:23 PM PDT 24 57930065096 ps
T1327 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1256307819 Jul 16 08:51:55 PM PDT 24 Jul 16 08:57:07 PM PDT 24 2780125578 ps
T1328 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.809799759 Jul 16 08:43:34 PM PDT 24 Jul 16 09:10:20 PM PDT 24 8669809320 ps
T1329 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3840779511 Jul 16 08:54:48 PM PDT 24 Jul 16 09:16:03 PM PDT 24 8845761224 ps
T1330 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.4171379152 Jul 16 08:36:48 PM PDT 24 Jul 16 09:59:40 PM PDT 24 18493887496 ps
T1331 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.4000849938 Jul 16 08:40:48 PM PDT 24 Jul 16 08:47:20 PM PDT 24 6212393856 ps
T1332 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3595268522 Jul 16 08:44:25 PM PDT 24 Jul 16 09:10:09 PM PDT 24 13516573847 ps
T1333 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.4080731095 Jul 16 08:31:29 PM PDT 24 Jul 16 08:42:07 PM PDT 24 4225848484 ps
T1334 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1019168540 Jul 16 08:31:22 PM PDT 24 Jul 16 08:46:45 PM PDT 24 5560730476 ps
T1335 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1383298539 Jul 16 08:33:22 PM PDT 24 Jul 16 08:38:34 PM PDT 24 3145827200 ps
T1336 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.448594480 Jul 16 08:36:58 PM PDT 24 Jul 16 09:36:23 PM PDT 24 14809718774 ps
T1337 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1543341576 Jul 16 08:27:29 PM PDT 24 Jul 16 08:31:08 PM PDT 24 2669565680 ps
T1338 /workspace/coverage/default/2.chip_sw_hmac_smoketest.4046727031 Jul 16 08:51:07 PM PDT 24 Jul 16 08:57:49 PM PDT 24 3404730970 ps
T348 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.81718027 Jul 16 08:35:37 PM PDT 24 Jul 16 08:39:59 PM PDT 24 3003476552 ps
T1339 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3689539913 Jul 16 08:49:51 PM PDT 24 Jul 16 08:54:58 PM PDT 24 2638826952 ps
T1340 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3824120796 Jul 16 08:56:19 PM PDT 24 Jul 16 09:01:15 PM PDT 24 3431077908 ps
T422 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.486977268 Jul 16 08:29:12 PM PDT 24 Jul 16 09:14:28 PM PDT 24 24234188340 ps
T45 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1477232779 Jul 16 08:27:41 PM PDT 24 Jul 16 08:32:55 PM PDT 24 2746177750 ps
T1341 /workspace/coverage/default/1.chip_sw_example_concurrency.1990012468 Jul 16 08:32:15 PM PDT 24 Jul 16 08:36:05 PM PDT 24 2670981440 ps
T1342 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.3335462996 Jul 16 08:35:43 PM PDT 24 Jul 16 09:43:31 PM PDT 24 14328818396 ps
T51 /workspace/coverage/default/0.chip_sw_spi_device_tpm.3227350005 Jul 16 08:28:07 PM PDT 24 Jul 16 08:35:27 PM PDT 24 3051960419 ps
T125 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.63471884 Jul 16 08:36:42 PM PDT 24 Jul 16 08:48:45 PM PDT 24 5422317720 ps
T1343 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.629645824 Jul 16 08:36:14 PM PDT 24 Jul 16 09:29:14 PM PDT 24 11239045579 ps
T1344 /workspace/coverage/default/2.rom_raw_unlock.469849122 Jul 16 08:49:42 PM PDT 24 Jul 16 08:54:16 PM PDT 24 4551443800 ps
T1345 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2632219444 Jul 16 08:33:07 PM PDT 24 Jul 16 08:53:16 PM PDT 24 10386705980 ps
T1346 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.863455142 Jul 16 08:36:40 PM PDT 24 Jul 16 08:44:46 PM PDT 24 3834810808 ps
T1347 /workspace/coverage/default/2.chip_sw_uart_smoketest.690043653 Jul 16 08:50:36 PM PDT 24 Jul 16 08:57:07 PM PDT 24 3425689832 ps
T1348 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3752666327 Jul 16 08:29:52 PM PDT 24 Jul 16 08:42:20 PM PDT 24 5079362120 ps
T1349 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3940590391 Jul 16 08:57:09 PM PDT 24 Jul 16 09:05:04 PM PDT 24 3659000056 ps
T179 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2140583191 Jul 16 08:31:51 PM PDT 24 Jul 16 09:51:24 PM PDT 24 43806471355 ps
T1350 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2976393929 Jul 16 08:52:40 PM PDT 24 Jul 16 08:57:27 PM PDT 24 2802414960 ps
T154 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1718283709 Jul 16 08:43:24 PM PDT 24 Jul 16 08:47:27 PM PDT 24 2889857020 ps
T1351 /workspace/coverage/default/4.chip_tap_straps_testunlock0.1021744722 Jul 16 08:50:42 PM PDT 24 Jul 16 08:52:48 PM PDT 24 2161569978 ps
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