Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_detector_cnt_th_3_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_detector_cnt_th_4_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_detector_cnt_th_5_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_detector_cnt_th_6_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_detector_cnt_th_7_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_wkup_cause_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T132,T133
1	0	Covered	T9,T132,T133
1	1	Covered	T383,T380,T381

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T132,T133
1	0	Covered	T383,T380,T381
1	1	Covered	T9,T132,T133

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1838078	200	0	0
SrcPulseCheck_M	152937160	200	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1838078	200	0	0
T9	2433	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T204	2523	0	0	0
T380	0	3	0	0
T381	0	4	0	0
T383	0	2	0	0
T384	0	1	0	0
T409	0	1	0	0
T419	0	1	0	0
T420	0	1	0	0
T434	522	0	0	0
T435	1083	0	0	0
T436	721	0	0	0
T437	1057	0	0	0
T438	345	0	0	0
T439	711	0	0	0
T440	321	0	0	0
T441	438	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152937160	200	0	0
T9	246799	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T204	272940	0	0	0
T380	0	3	0	0
T381	0	4	0	0
T383	0	2	0	0
T384	0	1	0	0
T409	0	1	0	0
T419	0	1	0	0
T420	0	1	0	0
T434	24207	0	0	0
T435	50727	0	0	0
T436	45379	0	0	0
T437	96959	0	0	0
T438	17071	0	0	0
T439	55174	0	0	0
T440	11059	0	0	0
T441	20534	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T132,T133
1	0	Covered	T9,T132,T133
1	1	Covered	T383,T380,T381

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T132,T133
1	0	Covered	T383,T380,T381
1	1	Covered	T9,T132,T133

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152937160	200	0	0
SrcPulseCheck_M	1838078	200	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152937160	200	0	0
T9	246799	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T204	272940	0	0	0
T380	0	3	0	0
T381	0	4	0	0
T383	0	2	0	0
T384	0	1	0	0
T409	0	1	0	0
T419	0	1	0	0
T420	0	1	0	0
T434	24207	0	0	0
T435	50727	0	0	0
T436	45379	0	0	0
T437	96959	0	0	0
T438	17071	0	0	0
T439	55174	0	0	0
T440	11059	0	0	0
T441	20534	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1838078	200	0	0
T9	2433	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T204	2523	0	0	0
T380	0	3	0	0
T381	0	4	0	0
T383	0	2	0	0
T384	0	1	0	0
T409	0	1	0	0
T419	0	1	0	0
T420	0	1	0	0
T434	522	0	0	0
T435	1083	0	0	0
T436	721	0	0	0
T437	1057	0	0	0
T438	345	0	0	0
T439	711	0	0	0
T440	321	0	0	0
T441	438	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T132,T133
1	0	Covered	T9,T132,T133
1	1	Covered	T383,T380,T381

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T132,T133
1	0	Covered	T383,T380,T381
1	1	Covered	T9,T132,T133

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1838078	252	0	0
SrcPulseCheck_M	152937160	252	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1838078	252	0	0
T9	2433	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T204	2523	0	0	0
T380	0	15	0	0
T381	0	13	0	0
T383	0	2	0	0
T384	0	1	0	0
T409	0	1	0	0
T419	0	1	0	0
T420	0	1	0	0
T434	522	0	0	0
T435	1083	0	0	0
T436	721	0	0	0
T437	1057	0	0	0
T438	345	0	0	0
T439	711	0	0	0
T440	321	0	0	0
T441	438	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152937160	252	0	0
T9	246799	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T204	272940	0	0	0
T380	0	15	0	0
T381	0	13	0	0
T383	0	2	0	0
T384	0	1	0	0
T409	0	1	0	0
T419	0	1	0	0
T420	0	1	0	0
T434	24207	0	0	0
T435	50727	0	0	0
T436	45379	0	0	0
T437	96959	0	0	0
T438	17071	0	0	0
T439	55174	0	0	0
T440	11059	0	0	0
T441	20534	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T132,T133
1	0	Covered	T9,T132,T133
1	1	Covered	T383,T380,T381

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T132,T133
1	0	Covered	T383,T380,T381
1	1	Covered	T9,T132,T133

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152937160	252	0	0
SrcPulseCheck_M	1838078	252	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152937160	252	0	0
T9	246799	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T204	272940	0	0	0
T380	0	15	0	0
T381	0	13	0	0
T383	0	2	0	0
T384	0	1	0	0
T409	0	1	0	0
T419	0	1	0	0
T420	0	1	0	0
T434	24207	0	0	0
T435	50727	0	0	0
T436	45379	0	0	0
T437	96959	0	0	0
T438	17071	0	0	0
T439	55174	0	0	0
T440	11059	0	0	0
T441	20534	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1838078	252	0	0
T9	2433	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T204	2523	0	0	0
T380	0	15	0	0
T381	0	13	0	0
T383	0	2	0	0
T384	0	1	0	0
T409	0	1	0	0
T419	0	1	0	0
T420	0	1	0	0
T434	522	0	0	0
T435	1083	0	0	0
T436	721	0	0	0
T437	1057	0	0	0
T438	345	0	0	0
T439	711	0	0	0
T440	321	0	0	0
T441	438	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T132,T133
1	0	Covered	T9,T132,T133
1	1	Covered	T383,T381,T487

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T132,T133
1	0	Covered	T383,T381,T487
1	1	Covered	T9,T132,T133

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1838078	216	0	0
SrcPulseCheck_M	152937160	216	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1838078	216	0	0
T9	2433	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T204	2523	0	0	0
T380	0	2	0	0
T381	0	16	0	0
T383	0	2	0	0
T384	0	1	0	0
T409	0	1	0	0
T419	0	1	0	0
T420	0	1	0	0
T434	522	0	0	0
T435	1083	0	0	0
T436	721	0	0	0
T437	1057	0	0	0
T438	345	0	0	0
T439	711	0	0	0
T440	321	0	0	0
T441	438	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152937160	216	0	0
T9	246799	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T204	272940	0	0	0
T380	0	2	0	0
T381	0	16	0	0
T383	0	2	0	0
T384	0	1	0	0
T409	0	1	0	0
T419	0	1	0	0
T420	0	1	0	0
T434	24207	0	0	0
T435	50727	0	0	0
T436	45379	0	0	0
T437	96959	0	0	0
T438	17071	0	0	0
T439	55174	0	0	0
T440	11059	0	0	0
T441	20534	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T132,T133
1	0	Covered	T9,T132,T133
1	1	Covered	T383,T381,T487

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T132,T133
1	0	Covered	T383,T381,T487
1	1	Covered	T9,T132,T133

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152937160	216	0	0
SrcPulseCheck_M	1838078	216	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152937160	216	0	0
T9	246799	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T204	272940	0	0	0
T380	0	2	0	0
T381	0	16	0	0
T383	0	2	0	0
T384	0	1	0	0
T409	0	1	0	0
T419	0	1	0	0
T420	0	1	0	0
T434	24207	0	0	0
T435	50727	0	0	0
T436	45379	0	0	0
T437	96959	0	0	0
T438	17071	0	0	0
T439	55174	0	0	0
T440	11059	0	0	0
T441	20534	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1838078	216	0	0
T9	2433	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T204	2523	0	0	0
T380	0	2	0	0
T381	0	16	0	0
T383	0	2	0	0
T384	0	1	0	0
T409	0	1	0	0
T419	0	1	0	0
T420	0	1	0	0
T434	522	0	0	0
T435	1083	0	0	0
T436	721	0	0	0
T437	1057	0	0	0
T438	345	0	0	0
T439	711	0	0	0
T440	321	0	0	0
T441	438	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T132,T133
1	0	Covered	T9,T132,T133
1	1	Covered	T383,T380,T381

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T132,T133
1	0	Covered	T383,T380,T381
1	1	Covered	T9,T132,T133

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1838078	241	0	0
SrcPulseCheck_M	152937160	241	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1838078	241	0	0
T9	2433	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T204	2523	0	0	0
T380	0	21	0	0
T381	0	17	0	0
T383	0	2	0	0
T384	0	1	0	0
T409	0	1	0	0
T419	0	1	0	0
T420	0	1	0	0
T434	522	0	0	0
T435	1083	0	0	0
T436	721	0	0	0
T437	1057	0	0	0
T438	345	0	0	0
T439	711	0	0	0
T440	321	0	0	0
T441	438	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152937160	241	0	0
T9	246799	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T204	272940	0	0	0
T380	0	21	0	0
T381	0	17	0	0
T383	0	2	0	0
T384	0	1	0	0
T409	0	1	0	0
T419	0	1	0	0
T420	0	1	0	0
T434	24207	0	0	0
T435	50727	0	0	0
T436	45379	0	0	0
T437	96959	0	0	0
T438	17071	0	0	0
T439	55174	0	0	0
T440	11059	0	0	0
T441	20534	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T132,T133
1	0	Covered	T9,T132,T133
1	1	Covered	T383,T380,T381

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T132,T133
1	0	Covered	T383,T380,T381
1	1	Covered	T9,T132,T133

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152937160	241	0	0
SrcPulseCheck_M	1838078	241	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152937160	241	0	0
T9	246799	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T204	272940	0	0	0
T380	0	21	0	0
T381	0	17	0	0
T383	0	2	0	0
T384	0	1	0	0
T409	0	1	0	0
T419	0	1	0	0
T420	0	1	0	0
T434	24207	0	0	0
T435	50727	0	0	0
T436	45379	0	0	0
T437	96959	0	0	0
T438	17071	0	0	0
T439	55174	0	0	0
T440	11059	0	0	0
T441	20534	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1838078	241	0	0
T9	2433	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T204	2523	0	0	0
T380	0	21	0	0
T381	0	17	0	0
T383	0	2	0	0
T384	0	1	0	0
T409	0	1	0	0
T419	0	1	0	0
T420	0	1	0	0
T434	522	0	0	0
T435	1083	0	0	0
T436	721	0	0	0
T437	1057	0	0	0
T438	345	0	0	0
T439	711	0	0	0
T440	321	0	0	0
T441	438	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T132,T133
1	0	Covered	T9,T132,T133
1	1	Covered	T383,T380,T381

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T132,T133
1	0	Covered	T383,T380,T381
1	1	Covered	T9,T132,T133

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1838078	207	0	0
SrcPulseCheck_M	152937160	207	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1838078	207	0	0
T9	2433	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T204	2523	0	0	0
T380	0	6	0	0
T381	0	23	0	0
T383	0	2	0	0
T384	0	1	0	0
T409	0	1	0	0
T419	0	1	0	0
T420	0	1	0	0
T434	522	0	0	0
T435	1083	0	0	0
T436	721	0	0	0
T437	1057	0	0	0
T438	345	0	0	0
T439	711	0	0	0
T440	321	0	0	0
T441	438	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152937160	207	0	0
T9	246799	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T204	272940	0	0	0
T380	0	6	0	0
T381	0	23	0	0
T383	0	2	0	0
T384	0	1	0	0
T409	0	1	0	0
T419	0	1	0	0
T420	0	1	0	0
T434	24207	0	0	0
T435	50727	0	0	0
T436	45379	0	0	0
T437	96959	0	0	0
T438	17071	0	0	0
T439	55174	0	0	0
T440	11059	0	0	0
T441	20534	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T132,T133
1	0	Covered	T9,T132,T133
1	1	Covered	T383,T380,T381

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T132,T133
1	0	Covered	T383,T380,T381
1	1	Covered	T9,T132,T133

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152937160	207	0	0
SrcPulseCheck_M	1838078	207	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152937160	207	0	0
T9	246799	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T204	272940	0	0	0
T380	0	6	0	0
T381	0	23	0	0
T383	0	2	0	0
T384	0	1	0	0
T409	0	1	0	0
T419	0	1	0	0
T420	0	1	0	0
T434	24207	0	0	0
T435	50727	0	0	0
T436	45379	0	0	0
T437	96959	0	0	0
T438	17071	0	0	0
T439	55174	0	0	0
T440	11059	0	0	0
T441	20534	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1838078	207	0	0
T9	2433	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T204	2523	0	0	0
T380	0	6	0	0
T381	0	23	0	0
T383	0	2	0	0
T384	0	1	0	0
T409	0	1	0	0
T419	0	1	0	0
T420	0	1	0	0
T434	522	0	0	0
T435	1083	0	0	0
T436	721	0	0	0
T437	1057	0	0	0
T438	345	0	0	0
T439	711	0	0	0
T440	321	0	0	0
T441	438	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1838078	252	0	0
SrcPulseCheck_M	152937160	255	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1838078	252	0	0
T1	5036	2	0	0
T3	0	2	0	0
T10	0	4	0	0
T12	0	3	0	0
T13	0	3	0	0
T14	0	4	0	0
T29	548	0	0	0
T67	715	0	0	0
T102	0	2	0	0
T103	0	2	0	0
T104	0	2	0	0
T105	493	0	0	0
T106	2874	0	0	0
T107	699	0	0	0
T108	5299	0	0	0
T109	806	0	0	0
T110	2813	0	0	0
T111	1217	0	0	0
T418	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152937160	255	0	0
T1	178783	2	0	0
T2	0	1	0	0
T3	0	2	0	0
T10	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T29	41214	0	0	0
T67	46847	0	0	0
T102	0	2	0	0
T103	0	2	0	0
T104	0	2	0	0
T105	22891	0	0	0
T106	322517	0	0	0
T107	53725	0	0	0
T108	620062	0	0	0
T109	42647	0	0	0
T110	309438	0	0	0
T111	102551	0	0	0
T418	0	2	0	0